DC Design Compiler 综合脚本命令及参考模板

Tcl与DesignCompiler（三）——DC综合的流程1、基本流程概述⾸先给三个图，⼀个图是⾼层次设计的流程图：下⾯是我对这张图的理解： ①设计之前，准备好库、HDL代码的思想、约束⽣成；然后根据设计思想⽤ RTL 源码详细地、完整地为设计建⽴模型、定义设计中寄存器结构和数⽬、定义设计中的组合电路功能、定义设计中寄存器时钟等等的设计规格和实现。

②完成 RTL 源码设计之后,应让设计开发与功能仿真并⾏进⾏: ·在设计开发阶段,我们使⽤ DC 来实现特定的设计⽬标(设计规则和优化约束),以及执⾏默认选项的初步综合. ·如果设计开发结果未能在 10%的偏差范围内满⾜时序⽬标,则需要修正 HDL 代码,然后重复设计开发和功能验证的过程. ·在功能仿真中,通过特定的⼯具来确定设计是否能按如所需的功能⼯作. ·如果设计未能满⾜功能要求, 我们必须修改设计代码以及重复设计开发和功能仿真. 继续设计开发和功能仿真直⾄设计功能正确及满⾜⼩于 10%偏差的时序⽬标. ③使⽤ DC 完成设计的综合并满⾜设计⽬标.这个过程包括三个步骤，即综合=转化+逻辑优化+映射，⾸先将 RTL 源代码转化为通⽤的布尔等式，然后设计的约束对电路进⾏逻辑综合和优化，使电路能满⾜设计的⽬标或者约束，最后使⽤⽬标⼯艺库的逻辑单元映射成门级⽹表，在将设计综合成门级⽹表之后,要验证此时的设计是否满⾜设计⽬标.如果不能满⾜设计⽬标,此时需要产⽣及分析报告确定问题及解决问题 ④当设计满⾜功能、时序以及其他的设计⽬标的时候,需要执⾏物理层设计最后分析物理层设计的性能，也就是使⽤DC的拓扑模式，加⼊floorplan的物理信息后进⾏综合分析设计的性能。

如果结果未能满⾜设计⽬标,应返回第三步.如果满⾜设计⽬标,则本部分设计周期完成. ⼀个图是DC在设计流程中的位置： 这个图将上⾯的流程图细化，着重与DC的部分，描述了使⽤DC进⾏逻辑综合时要做的事，同时，也是对前⾯的流程图解说的图形概述。

DC Design Compiler 综合脚本命令及参考模板Design Compiler 综合脚本常用命令和模板参照自己的设计，以及自己的工艺信息，适当修改下面的Constraints 和 Run Script 等的脚本，添加一些相关的约束语句，就可以运行了详细的命令请参照DC的官方User Guide等相关资料。

Invoking Design CompilerUnix% design_vision # Interactive GUI, WLM mode Unix%design_vision –topographical # Interactive GUI, Topographical mode Unix% dc_shell-t # Interactive shell, WLM mode Unix% dc_shell-t –topographical # Interactive shell, Topographical mode Unix% dc_shell-t –f RUN.tcl | tee –i my.log # Batch mode.synopsys_dc.setupset search_path “$search_path libs cons unmapped rtl”set synthetic_library dw_foundation.sldbset target_library 65nm.dbset link_library “* $target_library $synthetic_library IP.db”set symbol_library 65nm.sdbdefine_design_lib WORK –path ./workset_svf <my_filename.svf>set_vsdc <my_filename.vsdc>history keep 200set sh_enable_page_mode falseset cache_write .set cache_read $cache_writesuppress_message {LINT-28 LINT-32 LINT-33 UID-401} setalib_library_analysis_path [get_unix_variable HOME] alias h history alias rc “report_constraint -all_violators”TCL Commands and Constructsset PER 2.0 # Define a variable and its value echo $PER # Variable substitution , 2.0set MARG 0.95expr $PER * $MARG # expr: *, /, +, -, >, <, =, <=, >=set pci_ports [get_ports A] # Imbedded command set pci_ports[get_ports “Y??M Z*”] # Wildcardsecho “Effctv P = \ # Soft quotes , 1.9[expr $PERIOD * $MARGIN]”echo {Effctv P = \ # Hard quotes[expr $PERIOD * $MARGIN]} # , Effctv P = [expr $PER * $MARG] # Comment lineset COMMENT in_line; # In-line comment set MY_DESIGNS {B1.v ...B26.v} # foreach loop foreach DESIGN $MY_DESIGNS {read_verilog $DESIGN}for {set i 1} {$i < 27} {incr i} { # for loopread_verilog BLOCK_$i.v}Helpful UNIX-like DC-shell commandspwdcdlshistory!!!7!reportsh <UNIX_command>printenvget_unix_variable ARCHConstraintsreset_designset_max_area 0create_clock -period 2 –name Main_Clk [get_ports Clk1]create_clock –period 2.5 –waveform {2 3.5} [get_ports Clk2]create_clock –period 3.5 –name V_Clk; # VIRTUAL clockset_clock_uncertainty –setup 0.14 [get_clocks *]set_clock_uncertainty –setup 0.21 –from [get_clocks Main_Clk] –to [get_clocks Clk2] set_clock_latency –max 0.6 [get_clocks Main_Clk] set_clock_latency –source –max 0.3 [get_clocks Main_Clk]set_clock_transition 0.08 [get_clocks Main_Clk] set_input_delay -max 0.6-clock Main_Clk [all_inputs] set_input_delay –max 0.3 –clock Clk2 –clock_fall –add_delay [get_ports “B E”]set_input_delay -max 0.5 -clock –network_latency_included V_Clk [get_ports “A C F”]set_output_delay -max 0.8 -clock –source_latency_included Main_Clk [all_outputs]set_output_delay -max 1.1 -clock V_Clk [get_ports “OUT2 OUT7]set_max_capacitance 1.2 [all_inputs]set_load 0.080 [all_outputs]set_load [expr [load_of slow_proc/NAND2_3/A] * 4] [get_ports OUT3] set_load 0.12 [all_inputs]set_input_transition 0.12 [remove_from_collection[all_inputs][get_ports B]]set_driving_cell –lib_cell FD1 –pin Q [get_ports B]set_operating_conditions –max WCCOMset auto_wire_load_selection falseset_wire_load_model –name 1.6MGatesset_wire_load_mode enclosedset_wire_load_model –name 200KGates [get_designs “SUB1 SUB2”] set_wire_load_model –name 3.2MGates [get_ports IN_A]set_port_fanout_number 8 [get_ports IN_A] set_false_path -from[get_clocks Asynch_CLKA] -to [get_clocks Asynch_CLKB]set_multicycle_path –setup 4 –from –from A_reg -throughU_Mult/Out –to B_regset_multicycle_path –hold 3 –from –from A_reg -throughU_Mult/Out –to B_regset_isolate_ports –type inverter [all_outputs]set_ideal_network [get_ports reset* select*] set_ideal_network[get_pins FF_SET_reg/Q] set_ideal_network –no_propagate [get_nets CTRL] set_ideal_latency 1.4 [get_ports reset* select*]set_ideal_transition 0.5 [get_pins FF_SET_reg/Q] set_scan_configuration -style <multiplexed_flip_flop | clocked_scan | lssd | aux_clock_lssd> Checking and Removing Constraints and Directivesreport_clock; report_clock -skewreport_designreport_port –verbosereport_wire_loadreport_path_groupsreport_timing_requirements (–ignored) report_auto_ungroupreport_isolate_ports write_script –output <constraints.tcl>check_timingreset_path –from FF1_regremove_clockremove_clock_transition remove_clock_uncertainty remove_input_delay remove_output_delay remove_driving_cell remove_wire_load_modelSyntax CheckingUnix% dcprocheck constr_file.conPhysical Constraints – Topographical Modeset_aspect_ratioset_utilizationset_placement_areaset_rectilinear_outline set_port_sideset_port_locationset_cell_locationcreate_placement_keepoutMisc. Reports# Generate A library report fileread_db library_file.dblist_libsredirect –file reports/lib.rpt {report_lib <libname>}report_hierarchy [-noleaf]# Arithmetic implementation and# resource-sharing info report_resources# List area for all cells in the design report_cell [get_cells –hier *]Run Scriptread_verilog {A.v B.v TOP.v} orread_vhdl {A.vhd B.vhd TOP.vhd} orread_ddc MY_TOP.ddc oracs_read_hdl MY_TOP oranalyze –format verilog {A.v B.v TOP.v}elaborate MY_TOP –parameters “A_WIDTH=8, B_WIDTH=16”current_design MY_TOPlinkif {[check_design] ==0} {echo “Check Design Error”exit # Exits DC if a check-design error is encountered } # Continue if NO problems encounteredwrite –f ddc –hier –out unmappedd/TOP.ddcredirect –tee –file reports/precompile.rpt {source –echo -verbose TOP.con} redirect –append –tee –file reports/precompile.rpt{check_timing} source <Physical_Constraints_TCL_file> or # Source tcl constraints, if available, orextract_physical_constraints <DEF_file> # Extract and apply from an existing# DEF floorplan filegroup_path -name CLK1 -critical_range <10% of CLK1 Period> –weight 5group_path -name CLK2 -critical_range <10% of CLK2 Period> –weight 2group_path –name INPUTS –from [all_inputs]group_path –name OUTPUTS –to [all_outputs]group_path –name COMBO –from [all_inputs] –to [all_outputs]set_fix_multiple_port_nets –all –buffer_constants********************************************************* * ** Insert Expert, Ultra or ACS compile flow here * * **********************************************************check_designreport_constraint –all_violatorsreport_timing –delay –to –from –through –input_pins –max_paths \–nworst –nets –cap –sig –groupreport_areareport_qorset verilogout_no_tri truechange_names –rule verilog –hierwrite –f verilog –hier –out mapped/TOP.vwrite –f ddc –hier –out mapped/TOP.ddcwrite_sdc TOP.sdcwrite_scan_def –out TOP_scan.defwrite_physical_constraints –output TOP_PhysConstr.tcl exitObject Retrieval and Manipulation (Collection Commands)get_ports, get_pins, get_designsget_cells, get_nets, get_clocksget_nets –of_objects [get_pins FF1_reg/Q] get_libs <lib_name>get_lib_cells <lib_name/cell_names> get_lib_pins<lib_name/cell_name/pin_names> all_inputs, all_outputs, all_clocks,all_registers all_connectedall_fanin, all_fanoutall_ideal_netsset pci_ports [get_ports pci_*]echo $pci_ports # , _sel184query_objects $pci_ports # , {pci_1 pci_2 ...} get_object_name $pci_ports # , pci_1 pci_2 ...sizeof_collection $pci_ports # , 37set pci_ports [add_to_collection $pci_ports \[get_ports CTRL*]]set all_inputs_except_clk [remove_from_collection \[all_inputs] [get_ports CLK]]compare_collectionsindex_collectionsort_collectionforeach_in_collection my_cells [get_cells -hier * \-filter “is_hierarchical == true”] {echo “Instance [get_object_name $cell] is hierarchical”}# Filtering operators: ==, !=, >, <, >=, <=, =~, !~filter_collection [get_cells *] “ref_name =~ AN*”get_cells * -filter “dont_touch == true”get_clocks * -filter “period < 10”# List all cell attributes and redirect output to a fileredirect –file cell_attr \{list_attributes –application –class cell}# Grep the file for cell attributes starting with dont_UNIX% grep dont_ cell_attr | more# List the value of the attribute dont_touchget_attribute <cell_name> dont_touchUltra Compile Flow - Topographical or WLM ModeUltra + DesignWare and DFTC licenses available# In “topo” mode (dc_shell-t –topo) specify Milkyway reference and design libraries create_mw_lib –tech <technology_file> -mw_reference_library <mw_reference_libraries> \<mw_design_library_name>open_mw_lib <mw_design_library_name>set_tlu_plus_files -max_tluplus <max_tluplus_file> -tech2itf_map <mapping_file> set compile_auto_ungroup_delay_num_cells 99999999 set compile_auto_ungroup_count_leaf_cells trueset compile_auto_ungroup_override_wlm trueset_ungroup <top_level_and/or_pipelined_blocks> false# OPTIONAL: Disable unconditional auto-ungrouping# of DesignWare hierarchy (not usually recommended) setcompile_ultra_ungroup_dw false# If design contains pipelined sub-designs and the pipeline registers# are grouped together at the input or output, relax timingset_multicycle_path –setup <#_stages> -from U_Pipeline/R3_reg* –to U_Pipeline/R7_reg*# In “ topo” mode, if the floorplan is available, apply or extract the physical constraintssource <physical_constraints_file> ORextract_physical_constraints <DEF_file># OPTIONAL: Exclude specific cells/design from adaptive retiming (-retime) set_dont_retime <cells_or_designs> true# First compilecompile_ultra –scan –retime –timing|-area# The design hierarchy may have changed due to auto-ungrouping/-uniquifying reset_path -from U_Pipeline/R3_reg* -to U_Pipeline/R7_reg* # OPTIONAL: Maintain registered pipeline outputs if requiredset_dont_touch [get_cells U_Pipeline/R12_reg*] true# Optimize registers if pipeline violates timing; Skip if nopipeline issues: set_optimize_registers true –designMy_Pipeline_Subdesignoptimize_registers –only_attributed_designs# Continue if design is NOT meeting all constraints:# Apply more focus on violating critical paths, as necessarygroup_path –name <group_name> -from <path_start> -to <path_end> \ –critical range <10% of max delay goal> -weight 5# Select appropriate second compile# In “topo” mode in DC v2006.06, or any mode in DC v2007.03 or latercompile_ultra –scan –incremental# In “WLM” mode in DC v2006.06set_ultra_optimization truecompile –boundary –scan –map_effort high –incremental (-area_effort medium|low|none)# In “topo” mode prior to DC v2007.03: Write out updated physical constraintswrite_physical_constraints –output PhysConstr.tclDFT Flow – Expert or UltraDFTC license available# Prior to the first compile set the# scan cell styleset_scan_configuration –style ..# Perform the first test-ready compilecompile –boundary –map high –scan # ORcompile_ultra –timing -scan# Continue before the next compile:# Read in the scan specification filesource scan_spec.tcl# Check for DFT rule violationsdft_drc# Preview the scan chainspreview_dft# Insert and optimize scaninsert_dft****************************************************** * ** Execute additional Ultra/Expert optimization * * techniques, as needed * * *******************************************************# After the final compile check the DFT QoR# and write out the scan DEF filedft_drc –coverage_estimatewrite_scan_def -out <my_design.def>Some Scan Specification Commandsset_scan_state test_readyset_dft_configuration ...set_dft_signal ...set_scan_path ...set_scan_configuration ...create_test_protocolExpert Compile FlowNo Ultra license available; DFTC license available compile –boundary –scan –map_effort high# Continue if NOT meeting constraints# Note: -scan requires DFTC licensecompile –boundary –scan –map_effort high –incremental \(-area_effort medium|low|none)# Continue if NOT meeting constraints:# Increase max-delay priority if OK to postpone DRC fixingset_cost_priority –delay# Note: The design hierarchy may have changed due to auto-# uniquifying# Apply more focus on violating critical paths, as necessarygroup_path –name <group_name> -from <path_start> \-to <path_end> –critical range <10% of max delay goal> -weight 5 # Repartition if design is poorly partitioned group –design<NEW_DESIGN> -cell_name <U_NEW_CELL> \{U2 U7 ...}ungroup –start_level 2 U_NEW_CELLcompile –boundary –scan –map_effort high –incremental \(-area_effort medium|low|none)# Or, can ungroup all hierarchy in lieu of group/ungroup# commands with –ungroup_allcompile –boundary –scan –map_effort high –incremental \(-area_effort medium|low|none) –ungroup_all“Pseudo Ultra” Compile FlowUltra license available; No DesignWare license available set compile_auto_ungroup_delay_num_cells 99999999 setcompile_auto_ungroup_area_num_cells 99999999 setcompile_auto_ungroup_count_leaf_cells trueset compile_auto_ungroup_override_wlm trueset_ungroup <top_level_and/or_pipelined_blocks> false# OPTIONAL: Disable unconditional auto-ungrouping# of DesignWare hierarchy (not usually recommended) set compile_ultra_ungroup_dw false# If design contains pipelined sub-designs and the pipeline registers# are grouped together at the input or output, relax timing set_multicycle_path –setup <#_stages> \-from U_Pipeline/R3_reg* –to U_Pipeline/R7_reg*# Enable Ultra optimizations available for compileset_ultra_optimization –no_auto_dwlib trueset hlo_disable_datapath_optimization trueset compile_slack_driven_buffering truecompile –boundary –scan –map_effort high –auto_ungroup delay|area \ (-area_effort medium|low|none)# Note: The design hierarchy may have changed due to auto- # ungrouping and auto-uniquifyingreset_path -from U_Pipeline/R3_reg* -to U_Pipeline/R7_reg* # OPTIONAL: Maintain registered pipeline outputs if required set_dont_touch [get_cells U_Pipeline/R12_reg*] true # Optimize registers if pipeline violates timing; Skip if no pipeline issues:set_optimize_registers true –design My_Pipeline_Subdesign optimize_registers –only_attributed_designs# Continue if design is NOT meeting all constraints: compile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none)# Continue if NOT meeting all constraints:set_cost_priority –delay# Ungroup DesignWare components amid combinational logic ungroup <DesignWare_components># Apply more focus on violating critical paths, as necessary group_path –name <group_name> -from <path_start> -to <path_end> \ –critical range <10% of max delay goal> -weight 5 compile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none)。

Design Compiler 综合脚本常用命令和模板参照自己的设计，以及自己的工艺信息，适当修改下面的Constraints和Run Script 等的脚本，添加一些相关的约束语句，就可以运行了详细的命令请参照DC的官方User Guide等相关资料。

Invoking Design CompilerUnix% design_vision # Interactive GUI, WLM modeUnix% design_vision –topographical # Interactive GUI, Topographical modeUnix% dc_shell-t # Interactive shell, WLM modeUnix% dc_shell-t –topographical # Interactive shell, Topographical modeUnix% dc_shell-t –f RUN.tcl | tee –i my.log # Batch mode.synopsys_dc.setupset search_pa th “$search_path libs cons unmapped rtl”set synthetic_library dw_foundation.sldbset target_library 65nm.dbset link_library “* $target_library $synthetic_library IP.db”set symbol_library 65nm.sdbdefine_design_lib WORK –path ./workset_svf <my_filename.svf>set_vsdc <my_filename.vsdc>history keep 200set sh_enable_page_mode falseset cache_write .set cache_read $cache_writesuppress_message {LINT-28 LINT-32 LINT-33 UID-401}set alib_library_analysis_path [get_unix_variable HOME]alias h historyalias rc “report_constraint -all_violators”TCL Commands and Constructsset PER 2.0 # Define a variable and its valueecho $PER # Variable substitution → 2.0set MARG 0.95expr $PER * $MARG # expr: *, /, +, -, >, <, =, <=, >=set pci_ports [get_ports A] # Imbedded commandset pci_ports [get_ports “Y??M Z*”]# Wildcardsecho “Effctv P = \ # Soft quotes → 1.9[expr $PERIOD * $MARGIN]”echo {Effctv P = \ # Hard quotes[expr $PERIOD * $MARGIN]} # → Effctv P = [expr $PER * $MARG] # Comment lineset COMMENT in_line; # In-line commentset MY_DESIGNS {B1.v ... B26.v} # foreach loopforeach DESIGN $MY_DESIGNS {read_verilog $DESIGN}for {set i 1} {$i < 27} {incr i} { # for loopread_verilog BLOCK_$i.v}Helpful UNIX-like DC-shell commandspwdcdlshistory!!!7!reportsh <UNIX_command>printenvget_unix_variable ARCHConstraintsreset_designset_max_area 0create_clock -period 2 –name Main_Clk [get_ports Clk1]create_clock –period 2.5 –waveform {2 3.5} [get_ports Clk2]create_clock –period 3.5 –name V_Clk; # VIRTUAL clockset_clock_uncertainty –setup 0.14 [get_clocks *]set_clock_uncertainty –setup 0.21 –from [get_clocks Main_Clk] –to [get_clocks Clk2]set_clock_latency –max 0.6 [get_clocks Main_Clk]set_clock_latency –source –max 0.3 [get_clocks Main_Clk]set_clock_transition 0.08 [get_clocks Main_Clk]set_input_delay -max 0.6 -clock Main_Clk [all_inputs]set_input_delay –max 0.3 –clock Clk2 –clock_fall –add_delay [get_ports “B E”]set_input_delay -max 0.5 -clock –network_latency_included V_Clk [get_ports “A C F”]set_output_delay -max 0.8 -clock –source_latency_included Main_Clk [all_outputs]set_output_delay -max 1.1 -clock V_Clk [get_ports “OUT2 OUT7]set_max_capacitance 1.2 [all_inputs]set_load 0.080 [all_outputs]set_load [expr [load_of slow_proc/NAND2_3/A] * 4] [get_ports OUT3]set_load 0.12 [all_inputs]set_input_transition 0.12 [remove_from_collection [all_inputs][get_ports B]]set_driving_cell –lib_cell FD1 –pin Q [get_ports B]set_operating_conditions –max WCCOMset auto_wire_load_selection falseset_wire_load_model –name 1.6MGatesset_wire_load_mode enclosedset_wire_load_model –name 200KGates [get_designs “SUB1 SUB2”]set_wire_load_model –name 3.2MGates [get_ports IN_A]set_port_fanout_number 8 [get_ports IN_A]set_false_path -from [get_clocks Asynch_CLKA] -to [get_clocks Asynch_CLKB]set_multicycle_path –setup 4 –from –from A_reg -through U_Mult/Out –to B_regset_multicycle_path –hold 3 –from –from A_reg -through U_Mult/Out –to B_regset_isolate_ports –type inverter [all_outputs]set_ideal_network [get_ports reset* select*]set_ideal_network [get_pins FF_SET_reg/Q]set_ideal_network –no_propagate [get_nets CTRL]set_ideal_latency 1.4 [get_ports reset* select*]set_ideal_transition 0.5 [get_pins FF_SET_reg/Q]set_scan_configuration -style <multiplexed_flip_flop | clocked_scan | lssd | aux_clock_lssd>Checking and Removing Constraints and Directivesreport_clock; report_clock -skewreport_designreport_port –verbosereport_wire_loadreport_path_groupsreport_timing_requirements (–ignored)report_auto_ungroupreport_isolate_portswrite_script –output <constraints.tcl>check_timingreset_path –from FF1_regremove_clockremove_clock_transitionremove_clock_uncertaintyremove_input_delayremove_output_delayremove_driving_cellremove_wire_load_modelSyntax CheckingUnix% dcprocheck constr_file.conPhysical Constraints – Topographical Modeset_aspect_ratioset_utilizationset_placement_areaset_rectilinear_outlineset_port_sideset_port_locationset_cell_locationcreate_placement_keepoutMisc. Reports# Generate A library report fileread_db library_file.dblist_libsredirect –file reports/lib.rpt {report_lib <libname>} report_hierarchy [-noleaf]# Arithmetic implementation and# resource-sharing inforeport_resources# List area for all cells in the designreport_cell [get_cells –hier *]Run Scriptread_verilog {A.v B.v TOP.v} orread_vhdl {A.vhd B.vhd TOP.vhd} orread_ddc MY_TOP.ddc oracs_read_hdl MY_TOP oranalyze –format verilog {A.v B.v TOP.v}elaborate MY_TOP –parameters “A_WIDTH=8, B_WIDTH=16”current_design MY_TOPlinkif {[check_design] ==0} {echo “Check Design Error”exit # Exits DC if a check-design error is encountered} # Continue if NO problems encounteredwrite –f ddc –hier –out unmappedd/TOP.ddcredirect –tee –file reports/precompile.rpt {source –echo -verbose TOP.con}redirect –append –tee –file reports/precompile.rpt {check_timing}source <Physical_Constraints_TCL_file> or # Source tcl constraints, if available, or extract_physical_constraints <DEF_file> # Extract and apply from an existing # DEF floorplan filegroup_path -name CLK1 -critical_range <10% of CLK1 Period> –weight 5group_path -name CLK2 -critical_range <10% of CLK2 Period> –weight 2group_path –name INPUTS –from [all_inputs]group_path –name OUTPUTS –to [all_outputs]group_path –name COMBO –from [all_inputs] –to [all_outputs]set_fix_multiple_port_nets –all –buffer_constants********************************************************** ** Insert Expert, Ultra or ACS compile flow here ** **********************************************************check_designreport_constraint –all_violatorsreport_timing –delay –to –from –through –input_pins –max_paths \–nworst –nets –cap –sig –groupreport_areareport_qorset verilogout_no_tri truechange_names –rule verilog –hierwrite –f verilog –hier –out mapped/TOP.vwrite –f ddc –hier –out mapped/TOP.ddcwrite_sdc TOP.sdcwrite_scan_def –out TOP_scan.defwrite_physical_constraints –output TOP_PhysConstr.tcl exitObject Retrieval and Manipulation (Collection Commands) get_ports, get_pins, get_designsget_cells, get_nets, get_clocksget_nets –of_objects [get_pins FF1_reg/Q]get_libs <lib_name>get_lib_cells <lib_name/cell_names>get_lib_pins <lib_name/cell_name/pin_names>all_inputs, all_outputs, all_clocks, all_registersall_connectedall_fanin, all_fanoutall_ideal_netsset pci_ports [get_ports pci_*]echo $pci_ports # → _sel184 query_objects $pci_ports # → {pci_1 pci_2 ...} get_object_name $pci_ports # → pci_1 pci_2 ... sizeof_collection $pci_ports # → 37set pci_ports [add_to_collection $pci_ports \[get_ports CTRL*]]set all_inputs_except_clk [remove_from_collection \ [all_inputs] [get_ports CLK]]compare_collectionsindex_collectionsort_collectionforeach_in_collection my_cells [get_cells -hier * \ -filter “is_hierarchical == true”] {echo “Instance [get_object_name $cell] is hierarchical”}# Filtering operators: ==, !=, >, <, >=, <=, =~, !~filter_collection [get_cells *] “ref_name =~ AN*”get_cells * -filter “dont_touch == true”get_clocks * -filter “period < 10”# List all cell attributes and redirect output to a fileredirect –file cell_attr \{list_attributes –application –class cell}# Grep the file for cell attributes starting with dont_UNIX% grep dont_ cell_attr | more# List the value of the attribute dont_touchget_attribute <cell_name> dont_touchUltra Compile Flow - Topographical or WLM ModeUltra + DesignWare and DFTC licenses available# In “topo” mode (dc_shell-t –topo) specify Milkyway reference and design libraries create_mw_lib –tech <technology_file> -mw_reference_library <mw_reference_libraries> \<mw_design_library_name>open_mw_lib <mw_design_library_name>set_tlu_plus_files -max_tluplus <max_tluplus_file> -tech2itf_map <mapping_file>set compile_auto_ungroup_delay_num_cells 99999999set compile_auto_ungroup_count_leaf_cells trueset compile_auto_ungroup_override_wlm trueset_ungroup <top_level_and/or_pipelined_blocks> false# OPTIONAL: Disable unconditional auto-ungrouping# of DesignWare hierarchy (not usually recommended)set compile_ultra_ungroup_dw false# If design contains pipelined sub-designs and the pipeline registers# are grouped together at the input or output, relax timingset_multicycle_path –setup <#_stages> -from U_Pipeline/R3_reg* –to U_Pipeline/R7_reg* # In “ topo” mode, if the floorplan is available, apply or extract the physical constraints source <physical_constraints_file> ORextract_physical_constraints <DEF_file># OPTIONAL: Exclude specific cells/design from adaptive retiming (-retime)set_dont_retime <cells_or_designs> true# First compilecompile_ultra –scan –retime –timing|-area# The design hierarchy may have changed due to auto-ungrouping/-uniquifyingreset_path -from U_Pipeline/R3_reg* -to U_Pipeline/R7_reg*# OPTIONAL: Maintain registered pipeline outputs if requiredset_dont_touch [get_cells U_Pipeline/R12_reg*] true# Optimize registers if pipeline violates timing; Skip if no pipeline issues:set_optimize_registers true –design My_Pipeline_Subdesignoptimize_registers –only_attributed_designs# Continue if design is NOT meeting all constraints:# Apply more focus on violating critical paths, as necessarygroup_path –name <group_name> -from <path_start> -to <path_end> \–critical range <10% of max delay goal> -weight 5# Select appropriate second compile# In “topo” mode in DC v2006.06, or any mode in DC v2007.03 or latercompile_ultra –scan –incremental# In “WLM” mode in DC v2006.06set_ultra_optimization truecompile –boundary –scan –map_effort high –incremental (-area_effort medium|low|none) # In “topo” mode prior to DC v2007.03: Write out updated physical constraintswrite_physical_constraints –output PhysConstr.tclDFT Flow – Expert or UltraDFTC license available# Prior to the first compile set the# scan cell styleset_scan_configuration –style ..# Perform the first test-ready compilecompile –boundary –map high –scan # ORcompile_ultra –timing -scan# Continue before the next compile:# Read in the scan specification filesource scan_spec.tcl# Check for DFT rule violationsdft_drc# Preview the scan chainspreview_dft# Insert and optimize scaninsert_dft******************************************************* * * Execute additional Ultra/Expert optimization ** techniques, as needed ** * ******************************************************# After the final compile check the DFT QoR# and write out the scan DEF filedft_drc –coverage_estimatewrite_scan_def -out <my_design.def>Some Scan Specification Commandsset_scan_state test_readyset_dft_configuration ...set_dft_signal ...set_scan_path ...set_scan_configuration ...create_test_protocolExpert Compile FlowNo Ultra license available; DFTC license availablecompile –boundary –scan –map_effort high# Continue if NOT meeting constraints# Note: -scan requires DFTC licensecompile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none)# Continue if NOT meeting constraints:# Increase max-delay priority if OK to postpone DRC fixingset_cost_priority –delay# Note: The design hierarchy may have changed due to auto- # uniquifying# Apply more focus on violating critical paths, as necessary group_path –name <group_name> -from <path_start> \-to <path_end> –critical range <10% of max delay goal> -weight 5 # Repartition if design is poorly partitionedgroup –design <NEW_DESIGN> -cell_name <U_NEW_CELL> \{U2 U7 ...}ungroup –start_level 2 U_NEW_CELLcompile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none)# Or, can ungroup all hierarchy in lieu of group/ungroup# commands with –ungroup_allcompile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none) –ungroup_all“Pseudo Ultra” Compile FlowUltra license available; No DesignWare license availableset compile_auto_ungroup_delay_num_cells 99999999set compile_auto_ungroup_area_num_cells 99999999set compile_auto_ungroup_count_leaf_cells trueset compile_auto_ungroup_override_wlm trueset_ungroup <top_level_and/or_pipelined_blocks> false# OPTIONAL: Disable unconditional auto-ungrouping# of DesignWare hierarchy (not usually recommended)set compile_ultra_ungroup_dw false# If design contains pipelined sub-designs and the pipeline registers# are grouped together at the input or output, relax timingset_multicycle_path –setup <#_stages> \-from U_Pipeline/R3_reg* –to U_Pipeline/R7_reg*# Enable Ultra optimizations available for compileset_ultra_optimization –no_auto_dwlib trueset hlo_disable_datapath_optimization trueset compile_slack_driven_buffering truecompile –boundary –scan –map_effort high –auto_ungroup delay|area \ (-area_effort medium|low|none)# Note: The design hierarchy may have changed due to auto-# ungrouping and auto-uniquifyingreset_path -from U_Pipeline/R3_reg* -to U_Pipeline/R7_reg*# OPTIONAL: Maintain registered pipeline outputs if requiredset_dont_touch [get_cells U_Pipeline/R12_reg*] true# Optimize registers if pipeline violates timing; Skip if no pipeline issues:set_optimize_registers true –design My_Pipeline_Subdesignoptimize_registers –only_attributed_designs# Continue if design is NOT meeting all constraints:compile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none)# Continue if NOT meeting all constraints:set_cost_priority –delay# Ungroup DesignWare components amid combinational logicungroup <DesignWare_components># Apply more focus on violating critical paths, as necessarygroup_path –name <group_name> -from <path_start> -to <path_end> \–critical range <10% of max delay goal> -weight 5compile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none)。

Synopsys综合工具DesignCompiler（DC）Synopsys 综合工具Design Compiler（DC）简介一.约束的基本概念：约束就是对用户的设计中可度量的电路参数（如时序、面积以及电容等）进行声明。

没有约束，工具（本文为DC）就不能有效地优化电路，以满足要求。

当DC对设计进行优化时，使用了两类约束：1）设计规则约束（Design Rule Constraints，DRC）：此类约束是工具固有的，由工艺库（technology library）来定义。

此类约束是设计功能正确的必要条件，通过库应用于所有设计上。

当然，你可以将它们定义的更紧。

2）优化约束（Optimization Constraints）：它们是由用户定义的，前提是可实现的。

用户在使用DC时，可以通过命令行或编写约束文件（.scr）来定义约束。

下图给出DC 主要的DRC及优化约束，以及相关的DC命令（dc_shell接口命令）。

DRC：最大转换时间（Max Transition Time）：对于一条连线（net）来说，是其驱动pin逻辑值转化的最长时间。

最大扇出（Max Fanout）：对于驱动pin来讲。

最大/最小电容（Max/Min Capacitance）：用来控制连线的电容值。

器件退化（Cell Degradation）：某些工艺库包括器件退化表，它列举了某一器件可驱动的最大电容，是该器件输入pin最大转换时间的函数。

优化约束：时序约束：包括输入/输出延迟（Input/Output Delay）：同步路径最大/最小延迟（Minimum/Maximum Delay）：异步路径最大面积（门数）：最小孔隙度（Min porosity）：可布线性二．约束报告约束报告提供了设计规则和优化约束的信息。

可采用如下命令产生相应报告：report_constraintreport_portreport_clockreport_attributereport_timing_requirements用户可通过输出相应报告，来分析设计是否满足了约束。

Design Compiler（DC）使用1.建立逻辑综合环境，熟悉DC命令建立逻辑综合环境的命令是：new_dc [文件名]，例如new_dc mydesign，就是在当前目录下新建一个名为mydesign的DC综合环境。

环境如图1 环境实例所示。

图1 环境实例在mydesign目录下，Readme文件给了我们怎么使用工具的提示；filelist.tcl文件是给出需要综合代码的路径和文件名。

在synopsys.sdc文件中我们设置设计约束和设置工作环境，比如建立时钟，设置输入延时和输出延时等等。

在top.tcl文件中设置顶层模块名，设置库文件名，以及读入设置好的clock和输入、输出约束的文件，以及分析并报告结果。

.synopsys_dc.setup文件是DC工具的设置文件。

2.以加法器Adder_Array为例说明具体使用步骤。

Adder_Array共有5个设计文件，分别为顶层模块Adder_Array.v，状态机模块FSM.v，数据通过模块Data_Path.v，加法器模块adder_21.v，减法器模块Add_Sub_21.v。

Adder_Array 综合的步骤如下：（1）Adder_Array的设计文件添加到filelist.tcl中。

如图2 文件列表图2 文件列表（2）在top.tcl中将顶层模块设置为Adder_Array。

如图3修改顶层模块名图3 修改顶层模块名（3）修改synopsys.sdc实现以下设计约束：时钟周期1.2ns，input_delay设置为0.5ns，output_delay设置为0.5ns。

如果使用者想增加其他的设计约束可以在此文件中增添。

（4）进入刚才建好的综合环境，在终端中执行run命令，调用Design Compiler执行逻辑综合。

打开终端：cd [建好的环境路径]，进入后输入run，即可。

（5）等逻辑综合执行完毕后，查看123.log，对其中的error和warning进行确认，如果有问题修改设计或综合脚本后重新综合，直至没有问题。

Synopsys Design Compiler使用一、介绍：美国Synopsys公司发布的“Design Compiler”软件，简称“DC”，是一种逻辑合成工具。

通过改进电路延迟时间的计算方法，缩小了逻辑合成时的时序与布局完成后的最终时序之间的偏差。

DC得到全球60多个半导体厂商、380多个工艺库的支持。

据最新Dataquest的统计，Synopsys的逻辑综合工具占据91%的市场份额。

DC是十二年来工业界标准的逻辑综合工具，也是Synopsys最核心的产品。

它使IC设计者在最短的时间内最佳的利用硅片完成设计。

它根据设计描述和约束条件并针对特定的工艺库自动综合出一个优化的门级电路。

它可以接受多种输入格式，如硬件描述语言、原理图和网表等，并产生多种性能报告，在缩短设计时间的同时提高设计性能。

二、要求：由于实训没有硬性要求VHDL文件，本人挑选了已经预先做好的洗衣机时控电路，利用Synopsys Design Compiler工具，进行优化分析，通过这一过程熟悉软件的使用。

三、过程：设置优化运行库，鉴于老师在练习手册上面提供的例子，我们使用库LSI-10K，因此在打开VHDL文件前，需要作以下设置Setup->Defaults，填入以下信息。

在File->read打开要分析优化的VHDL文件，这里我选择一个洗衣机时控电路NewWasher.vhd 如下所示（分别为不同层次的视图：顶层、器件、门级电路）在Tools->Design Optimization中设置好兼顾平衡的约束条件（左图），确定编译后，产生了右边经过优化的门级电路图。

接下来，把优化过的图形转换为VHDL文件和DB文件输出，另存到指定位置File->Save As如右图，生成了新的DB文件和vhd文件。

接下来，是要设定CLK的周期，根据分析、优化、编译出来的Slack Time 松弛数值和Area面积数值，选取最合适的平衡点。

数字逻辑综合DC脚本⽰例及解释#script for Design Compiler# Language : TCL# Usage :# 1) make sure the lib in the current directory# 2) if you have the file .synopsys_dc.setup,# set synopsys_dc_setup_file 1,# if not, set synopsys_dc_setup_file 0# 3) change Step 3 : Variables to what you want# Especially : top module name, clock name,# reset name, all files name, and period# 4) typing dc_shell-t -f run_72.tcl | tee -i run.log##========================================================set synopsys_dc_setup_file 0#-----------------------------------------------------# Step 1 :# Setting Up path and library：# If you have edited the file .synopsys_dc.setup, then you can skip over this step#-----------------------------------------------------if { $synopsys_dc_setup_file == 0} {set search_path [list /home/chanshi/dc/library/smic /home/chanshi/dc/rfid/source /home/chanshi/dc/script]set target_library {typical.db}#set target_library {CSM35OS142_typ.db};# if you want use typical library,change to typical.db#set link_library [list {*} ram_interp_typical_syn.db ram_458_typical_syn.db typical.db]set link_library [list {*} $target_library]}#set symbol_library {csm18ic.sdb csm18io.sdb}#set synthetic_library {dw_foundation.sldb};# Design Wareset command_log_file "command.log"#-----------------------------------------------------# Step 2 :# Compile Swithes#-----------------------------------------------------#set verilogout_no_tri true ;# if inout used, tri net will be used#通过将三态（tri）逻辑声明成线⽹（wire）来确保⽹表中不会出现三态逻辑，因为⼀些布线⼯具很难读取包含tri、tran源语、assign语句的⽹表，对于“inout”类型的port,DC产⽣tri wire 语句和tran 源语，对于tri，还会产⽣assign语句set test_default_scan_style multiplexed_flip_flop#设置扫描链的类型，还可以通过set_scan_configuration -style来设置set link_force_case case_insensitive#设置link命令是否区分⼤⼩写，默认是check_reference,就是根据产⽣reference的模块格式来判断是否⼤⼩写敏感，如果是vhdl格式就是不敏感，如果是verilog就敏感define_name_rules VLSI_NET -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type net -max_length 256define_name_rules VLSI_CELL -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type cell -max_length 256define_name_rules VLSI_PORT -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type port -max_length 256define_name_rules TAN_RULE -allowed "a-zA-Z0-9_" -first_restricted "0-9_\[]" -max_length 256 -map {{{"*cell*", "mycell"}, {"*-return", "myreturn"}}};set hdlin_check_no_latch "true"#设置如果推断出锁存器，是否报warning，默认是false，即不报。

Design Compiler 使用简要说明Design Compiler可以针对层次化的组合电路或者时序电路的速度、面积和可布性进行优化。

按照所定义的电路的测量特征所要达到的目标，Design Compiler综合一个电路并将其放入目标库中，这样可以生成适用于你的计算机辅助设计工程（CAE）工具的原理图或网表。

综合的过程如下图：•读入设计及其子设计。

•设置顶层的设计特性参数•设置实际时序和面积目标参数•执行check_design验证设计，识别并且更正错误•进行Design Compiler优化在db、verilog、vhdl文件夹下设计内容都是一样的，只是形式不一样。

Db文件夹：ALARM_BLOCK.db ALARM_COUNTER.db ALARM_SM.dbALARM_STATE_MACHINE.db COMPARATOR.dbHOURS_FILTER.db MUX.db TIME_BLOCK.dbTIME_COUNTER.dbTIME_STATE_MACHINE.db CONVERTOR.pla CONVERTOR_CKT.db TOP.dbVerilog文件夹：ALARM_BLOCK.v ALARM_COUNTER.v ALARM_SM.vALARM_STATE_MACHINE.v COMPARATOR.vHOURS_FILTER.v MUX.vTIME_BLOCK.vTIME_COUNTER.vTIME_STATE_MACHINE.v CONVERTOR.pla CONVERTOR_CKT.v TOP.vVhdl文件夹：ALARM_BLOCK.vhd ALARM_BLOCK.vhd ALARM_SM.vhdALARM_STATE_MACHINE.vhd COMPARATOR.vhdHOURS_FILTER.vhd MUX.vhd TIME_BLOCK.vhdTIME_COUNTER.vhdTIME_STATE_MACHINE.vhd CONVERTOR.pla CONVERTOR_CKT.vhd TOP.vhd设置path参数将 Synopsys_installroot/arch/syn/bin加到.cshrc文件中。

DC学习----第一章基本概念作者：未知时间：2010-08-15 15:02:50 来自：网络转载1.1 启动文件启动文件用来指定综合工具所需要的一些初始化信息。

DC使用名为“.synopsys_dc.setup”的启动文件，启动时，DC会以下述顺序搜索并装载相应目录下的启动文件：1)、DC的安装目录；2)、用户的home目录；3)、当前启动目录。

注意：后装载的启动文件中的设置将覆盖先装载的启动文件中的相同设置。

下面是一个DC启动文件的实例，它包含了几乎所有重要的设置，下文将结合该实例解释启动文件中各项设置的具体含义。

例1-1（一个DC启动文件）：search_path= search_path + {“.”, synopsys_root + “/dw/sim_ver” }search_path= search_path + { “~/risc32/synthesis/libraries” }target_library={ tcb773stc.db }synthetic_library={dw_foundation.sldb}link_library = { “*”, dw_foundation.sldb, tcb773stc.db }symbol_library = { tcb773s.sdb }synlib_wait_for_design_license = {"DesignWare-Foundation"}alias rt “report_timing”designer= XXXXXcompany= “ASIC Lab, Fudan Univ.”search_path指定了综合工具的搜索路径。

target_library为综合的目标库，它一般是由生产线提供的工艺相关的库。

synthetic_library是综合库，它包含了一些可综合的与工艺无关的IP。

dw_foundation.sldb是Synopsys提供的名为Design Ware的综合库，它包含了基本的算术运算逻辑、控制逻辑、可综合存储器等IP，在综合是调用这些IP有助于提高电路性能和减少综合时间。