MSP430G2553用户手册中文

MSP430混合信号微控制器数据手册产品特性●低电压范围：2.5V～5.5V●超低功耗——活动模式：330μA at 1MHz, 3V——待机模式：0.8μA——掉电模式（RAM数据保持）：0.1μA●从待机模式唤醒响应时间不超过6μs●16位精简指令系统，指令周期200ns●基本时钟模块配置——多种内部电阻——单个外部电阻——32kHz晶振——高频晶体——谐振器——外部时钟源●带有三个捕获/比较寄存器的16位定时器（Timer_A）●串行在线可编程●采用保险熔丝的程序代码保护措施●该系列产品包括——MSP430C111：2K字节ROM，128字节RAM——MSP430C112：4K字节ROM，256字节RAM——MSP430P112：4K字节OTP，256字节RAM●EPROM原型——PMS430E112：4KB EPROM, 256B RAM●20引脚塑料小外形宽体（SOWB）封装，20引脚陶瓷双列直插式（CDIP）封装（仅EPROM）●如需完整的模块说明，请查阅MSP430x1xx系列用户指南（文献编号：SLAU049产品说明TI公司的MSP43O系列超低功耗微控制器由一些基本功能模块按照不同的应用目标组合而成。

在便携式测量应用中，这种优化的体系结构结合五种低功耗模式可以达到延长电池寿命的目的。

MSP430系列的CPU采用16位精简指令系统，集成有16位寄存器和常数发生器，发挥了最高的代码效率。

它采用数字控制振荡器（DCO），使得从低功耗模式到唤醒模式的转换时间小于6μs.MSP430x11x系列是一种超低功耗的混合信号微控制器，它拥有一个内置的16位计数器和14个I/0引脚。

典型应用：捕获传感器的模拟信号转换为数据，加以处理后输出或者发送到主机。

作为独立RF传感器的前端是其另一个应用领域。

DW封装（顶视图）可用选型功能模块图管脚功能简介：1.CPUMSP430的CPU采用16位RISC架构，具有高度的应用开发透明性。

MSP430G2553学习笔记（数据手册）MSP430G2553性能参数(DIP-20) 工作电压范围：1.8~3.6V。

5种低功耗模式。

16位的RISC结构，62.5ns指令周期。

超低功耗：运行模式-230µA；待机模式-0.5µA；关闭模式-0.1µA；可以在不到1µs的时间里超快速地从待机模式唤醒。

基本时钟模块配置：具有四种校准频率并高达16MHz的内部频率；内部超低功耗LF振荡器；32.768KHz晶体；外部数字时钟源。

两个16 位Timer_A，分别具有三个捕获/比较寄存器。

用于模拟信号比较功能或者斜率模数(A/D)转换的片载比较器。

带内部基准、采样与保持以及自动扫描功能的10位200-ksps 模数(A/D)转换器。

16KB闪存，512B的RAM。

16个I/O口。

注意：MSP430G2553无P3口！MSP430G2553的时钟基本时钟系统的寄存器DCOCTL-DCO控制寄存器DCOxDCO频率选择控制1MODxDCO频率校正选择，通常令MODx=0注意：在MSP430G2553上电复位后，默认RSEL=7，DCO=3，通过数据手册查得DCO频率大概在0.8~1.5MHz之间。

BCSCTL1-基本时钟控制寄存器1XT2OFF不用管，因为MSP430G2553内部没有XT2提供的HF时钟XTS不用管，默认复位后的0值即可DIV Ax设置ACLK的分频数00 /101 /210 /411 /8RSELxDCO频率选择控制2BCSCTL2-基本时钟控制寄存器2SELMxMCLK的选择控制位00 DCOCLK01 DCOCLK10 LFXT1CLK或者VLOCLK11 LFXT1CLK或者VLOCLK DIVMx设置MCLK的分频数00 /101 /210 /411 /8SELSSMCLK的选择控制位0 DCOCLK1 LFXT1CLK或者VLOCLK DIVSx设置SMCLK的分频数00 /101 /210 /411 /8DCORDCO直流发生电阻选择，此位一般设00 内部电阻1 外部电阻BCSCTL3-基本时钟控制寄存器3XT2Sx不用管LFXT1Sx00 LFXT1选为32.768KHz晶振01 保留10 VLOCLK11 外部数字时钟源XCAPxLFXT1晶振谐振电容选择00 1pF01 6pF10 10pF11 12.5pFmsp430g2553.h中基本时钟系统的内容/************************************************************* Basic Clock Module************************************************************/#define __MSP430_HAS_BC2__ /* Definition to show that Module is available */SFR_8BIT(DCOCTL); /* DCO Clock Frequency Control */SFR_8BIT(BCSCTL1); /* Basic Clock System Control 1 */SFR_8BIT(BCSCTL2); /* Basic Clock System Control 2 */SFR_8BIT(BCSCTL3); /* Basic Clock System Control 3 */#define MOD0 (0x01) /* Modulation Bit 0 */#define MOD1 (0x02) /* Modulation Bit 1 */#define MOD2 (0x04) /* Modulation Bit 2 */#define MOD3 (0x08) /* Modulation Bit 3 */#define MOD4 (0x10) /* Modulation Bit 4 */#define DCO0 (0x20) /* DCO Select Bit 0 */#define DCO1 (0x40) /* DCO Select Bit 1 */#define DCO2 (0x80) /* DCO Select Bit 2 */#define RSEL0 (0x01) /* Range Select Bit 0 */#define RSEL1 (0x02) /* Range Select Bit 1 */#define RSEL2 (0x04) /* Range Select Bit 2 */#define RSEL3 (0x08) /* Range Select Bit 3 */#define DIVA0 (0x10) /* ACLK Divider 0 */#define DIVA1 (0x20) /* ACLK Divider 1 */#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */ #define XT2OFF (0x80) /* Enable XT2CLK */#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */#define DIVS0 (0x02) /* SMCLK Divider 0 */#define DIVS1 (0x04) /* SMCLK Divider 1 */#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK /1:XT2CLK/LFXTCLK */#define DIVM0 (0x10) /* MCLK Divider 0 */#define DIVM1 (0x20) /* MCLK Divider 1 */#define SELM0 (0x40) /* MCLK Source Select 0 */#define SELM1 (0x80) /* MCLK Source Select 1 */#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */#define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */#define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */#define LFXT1OF (0x01) /* Low/high Frequency Oscillator Fault Flag */#define XT2OF (0x02) /* High frequency oscillator 2 fault flag */#define XCAP0 (0x04) /* XIN/XOUT Cap 0 */#define XCAP1 (0x08) /* XIN/XOUT Cap 1 */#define LFXT1S0 (0x10) /* Mode 0 for LFXT1 (XTS = 0) */#define LFXT1S1 (0x20) /* Mode 1 for LFXT1 (XTS = 0) */#define XT2S0 (0x40) /* Mode 0 for XT2 */#define XT2S1 (0x80) /* Mode 1 for XT2 */#define XCAP_0 (0x00) /* XIN/XOUT Cap : 0 pF */#define XCAP_1 (0x04) /* XIN/XOUT Cap : 6 pF */#define XCAP_2 (0x08) /* XIN/XOUT Cap : 10 pF */#define XCAP_3 (0x0C) /* XIN/XOUT Cap : 12.5 pF */#define LFXT1S_0 (0x00) /* Mode 0 for LFXT1 : Normal operation */ #define LFXT1S_1 (0x10) /* Mode 1 for LFXT1 : Reserved */#define LFXT1S_2 (0x20) /* Mode 2 for LFXT1 : VLO */#define LFXT1S_3 (0x30) /* Mode 3 for LFXT1 : Digital input signal */#define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */#define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */#define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */#define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital input signal */基本时钟系统例程(DCO)MSP430G2553在上电之后默认CPU执行程序的时钟MCLK来自于DCO时钟。

基本时钟模块_MSP430G2553G2xxx系列DCO校准数据（校正寄存器）1MHz：CALBC1_1MHZCALDCO_1MHZ8MHz：CALBC1_8MHZCALDCO_8MHZ12MHz：CALBC1_12MHZCALDCO_12MHZ16MHz：CALBC1_16MHZCALDCO_16MHZ例：设置DCO频率为1MHzif(CALBC1_1MHZ==0xFF || CALDCO_1MHZ==0xFF)while(1);//校准数据是否被擦除，若是则CPU挂起。

BCSCTL1 = CALBC1_1MHZ;DCOCTL = CALDCO_1MHZ;基本时钟模块寄存器寄存器缩写形式类型初始状态DCO控制寄存器DCOCTL 读/写0x60（PUC）基本时钟系统控制器1 BCSCTL1 读/写0x87（POR）基本时钟系统控制器2 BCSCTL2 读/写由PUC复位基本时钟系统控制器3 BCSCTL3 读/写0x05（PUC）中断使能寄存器（特殊功能寄存器）IE1 读/写由PUC复位中断标致寄存器（特殊功能寄存器）IFG1 读/写由PUC复位说明：DCO的频率可以通过软件设定DCOx、MODx、RSELx相应位来调整，DCO频率是通过将f DCO和f DCO+1混频得到。

1、DCOCTL：DCO控制寄存器7 6 5 4 3 2 1 0DCOx MODxrw-0 rw-1 rw-1 rw-0 rw-0 rw-0 rw-0 rw-0 DCOx：DCO频率范围选择位，这些位可以用来在由RESLx设置决定的8个离散的频率范围中选择哪一个。

MODx：调制系数选择位，这些位用来决定在32个DCO时钟周期中f DCO+1占多少个，f DCO 占多少个。

注意：当MODx=0时调制器关闭，DCOx=7时，由于此时没有下一个更高的频率范围f DCO+1可用，因此MODx无效不可用。

2、BCSCTL1：基本时钟系统控制寄存器17 6 5 4 3 2 1 0 XT2OFF XTS(1)(2)DIVAx RSELxrw-(1) rw-(0) rw-(0) rw-(0) rw-0 rw-1 rw-1 rw-1 XT2OFF：第二晶振XT2(可选高频晶振)关闭控制位。

MSP430寄存器中文注释---P1/2口（带中断功能）/************************************************************ * DIGITAL I/O Port1/2 寄存器定义有中断功能************************************************************/ #define P1IN_ 0x0020 /* P1 输入寄存器 */const sfrb P1IN = P1IN_;#define P1OUT_ 0x0021/* P1 输出寄存器 */ sfrb P1OUT = P1OUT_;#define P1DIR_ 0x0022 /* P1 方向选择寄存器 */sfrb P1DIR = P1DIR_;#define P1IFG_ 0x0023 /* P1 中断标志寄存器*/sfrb P1IFG = P1IFG_;#define P1IES_ 0x0024 /* P1 中断边沿选择寄存器*/ sfrb P1IES = P1IES_;#define P1IE_ 0x0025 /* P1 中断使能寄存器 */sfrb P1IE = P1IE_;#define P1SEL_ 0x0026 /* P1 功能选择寄存器*/sfrb P1SEL = P1SEL_;#define P2IN_ 0x0028 /* P2 输入寄存器 */const sfrb P2IN = P2IN_;#define P2OUT_ 0x0029 /* P2 输出寄存器*/sfrb P2OUT = P2OUT_;#define P2DIR_ 0x002A /* P2 方向选择寄存器*/ sfrb P2DIR = P2DIR_;#define P2IFG_ 0x002B /* P2 中断标志寄存器 */sfrb P2IFG = P2IFG_;#define P2IES_ 0x002C /* P2 中断边沿选择寄存器 */ sfrb P2IES = P2IES_;#define P2IE_ 0x002D /* P2 中断使能寄存器 */sfrb P2IE = P2IE_;#define P2SEL_ 0x002E /* P2 功能选择寄存器 */sfrb P2SEL = P2SEL_;MSP430寄存器中文注释---P3/4口（无中断功能）/************************************************************* DIGITAL I/O Port3/4寄存器定义无中断功能************************************************************/#define P3IN_ 0x0018 /* P3 输入寄存器 */const sfrb P3IN = P3IN_;#define P3OUT_ 0x0019 /* P3 输出寄存器 */sfrb P3OUT = P3OUT_;#define P3DIR_ 0x001A /* P3 方向选择寄存器 */sfrb P3DIR = P3DIR_;#define P3SEL_ 0x001B /* P3 功能选择寄存器*/sfrb P3SEL = P3SEL_;#define P4IN_ 0x001C /* P4 输入寄存器 */const sfrb P4IN = P4IN_;#define P4OUT_ 0x001D /* P4 输出寄存器 */sfrb P4OUT = P4OUT_;#define P4DIR_ 0x001E /* P4 方向选择寄存器 */sfrb P4DIR = P4DIR_;#define P4SEL_ 0x001F /* P4 功能选择寄存器 */sfrb P4SEL = P4SEL_;/************************************************************* DIGITAL I/O Port5/6 I/O口寄存器定义PORT5和6 无中断功能************************************************************/#define P5IN_ 0x0030 /* P5 输入寄存器 */const sfrb P5IN = P5IN_;#define P5OUT_ 0x0031 /* P5 输出寄存器*/sfrb P5OUT = P5OUT_;#define P5DIR_ 0x0032 /* P5 方向选择寄存器*/ sfrb P5DIR = P5DIR_;#define P5SEL_ 0x0033 /* P5 功能选择寄存器*/ sfrb P5SEL = P5SEL_;#define P6IN_ 0x0034 /* P6 输入寄存器 */const sfrb P6IN = P6IN_;#define P6OUT_ 0x0035 /* P6 输出寄存器*/sfrb P6OUT = P6OUT_;#define P6DIR_ 0x0036 /* P6 方向选择寄存器*/ sfrb P6DIR = P6DIR_;#define P6SEL_ 0x0037 /* P6 功能选择寄存器*/ sfrb P6SEL = P6SEL_;MSP430寄存器中文注释--- 硬件乘法器/************************************************************硬件乘法器的寄存器定义************************************************************/ #define MPY_ 0x0130 /* 无符号乘法 */sfrw MPY = MPY_;#define MPYS_ 0x0132 /* 有符号乘法*/sfrw MPYS = MPYS_;#define MAC_ 0x0134 /* 无符号乘加 */sfrw MAC = MAC_;#define MACS_ 0x0136 /* 有符号乘加 */sfrw MACS = MACS_;#define OP2_ 0x0138 /* 第二乘数 */sfrw OP2 = OP2_;#define RESLO_ 0x013A /* 低6位结果寄存器 */sfrw RESLO = RESLO_;#define RESHI_ 0x013C /* 高6位结果寄存器 */sfrw RESHI = RESHI_;#define SUMEXT_ 0x013E /*结果扩展寄存器*/const sfrw SUMEXT = SUMEXT_;MSP430寄存器中文注释---看门狗和定时器/************************************************************* 看门狗定时器的寄存器定义************************************************************/#define WDTCTL_ 0x0120sfrw WDTCTL = WDTCTL_;#define WDTIS0 0x0001 /*选择WDTCNT的四个输出端之一*/#define WDTIS1 0x0002 /*选择WDTCNT的四个输出端之一*/#define WDTSSEL 0x0004 /*选择WDTCNT的时钟源*/#define WDTCNTCL 0x0008 /*清除WDTCNT端: 为1时从0开始计数*/#define WDTTMSEL 0x0010 /*选择模式0: 看门狗模式; 1: 定时器模式*/#define WDTNMI 0x0020 /*选择NMI/RST 引脚功能 0:为 RST; 1:为NMI*/#define WDTNMIES 0x0040 /*WDTNMI=1时.选择触发延 0:为上升延 1:为下降延*/ #define WDTHOLD 0x0080 /*停止看门狗定时器工作 0:启动;1:停止*/#define WDTPW 0x5A00 /* 写密码:高八位*//* SMCLK= 1MHz定时器模式 */#define WDT_MDLY_32 WDTPW+WDTTMSEL+WDTCNTCL /*TSMCLK*2POWER15=32ms 复位状态 */#define WDT_MDLY_8 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0 /*TSMCLK*2POWER13=8.192ms " */#define WDT_MDLY_0_5 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1 /*TSMCLK*2POWER9=0.512ms " */#define WDT_MDLY_0_064 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0 /*TSMCLK*2POWER6=0.512ms " *//* ACLK=32.768KHz 定时器模式*/#define WDT_ADLY_1000 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL /* TACLK*2POWER15=1000ms " */#define WDT_ADLY_250 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0 /* TACLK*2POWER13=250ms " */#define WDT_ADLY_16 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1 /* TACLK*2POWER9=16ms " */#define WDT_ADLY_1_9 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0 /* TACLK*2POWER6=1.9ms " *//* SMCLK=1MHz看门狗模式 */#define WDT_MRST_32 WDTPW+WDTCNTCL /* TSMCLK*2POWER15=32ms 复位状态*/#define WDT_MRST_8 WDTPW+WDTCNTCL+WDTIS0 /* TSMCLK*2POWER13=8.192ms " */#define WDT_MRST_0_5 WDTPW+WDTCNTCL+WDTIS1 /* TSMCLK*2POWER9=0.512ms " */#define WDT_MRST_0_064 WDTPW+WDTCNTCL+WDTIS1+WDTIS0 /* TSMCLK*2POWER6=0.512ms " *//* ACLK=32KHz看门狗模式 */#define WDT_ARST_1000 WDTPW+WDTCNTCL+WDTSSEL /* TACLK*2POWER15=1000ms " */#define WDT_ARST_250 WDTPW+WDTCNTCL+WDTSSEL+WDTIS0 /* TACLK*2POWER13=250ms " */#define WDT_ARST_16 WDTPW+WDTCNTCL+WDTSSEL+WDTIS1 /* TACLK*2POWER9=16ms " */#define WDT_ARST_1_9 WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0 /* TACLK*2POWER6=1.9ms " */MSP430寄存器中文注释---A/D采样寄存器定义/************************************************************* ADC12 A/D采样寄存器定义************************************************************//*ADC12转换控制类寄存器*/#define ADC12CTL0_ 0x0;' /* ADC12 Control 0 */sfrw ADC12CTL0 = ADC12CTL0_;#define ADC12CTL1_ 0x01A2 /* ADC12 Control 1 */sfrw ADC12CTL1 = ADC12CTL1_;/*ADC12中断控制类寄存器*/#define ADC12IFG_ 0x01A4 /* ADC12 Interrupt Flag */sfrw ADC12IFG = ADC12IFG_;#define ADC12IE_ 0x01A6 /* ADC12 Interrupt Enable */sfrw ADC12IE = ADC12IE_;#define ADC12IV_ 0x01A8 /* ADC12 Interrupt Vector Word */sfrw ADC12IV = ADC12IV_;/*ADC12存贮器类寄存器*/#define ADC12MEM_ 0x0140 /* ADC12 Conversion Memory */#ifndef __IAR_SYSTEMS_ICC#define ADC12MEM ADC12MEM_ /* ADC12 Conversion Memory (for assembler) */ #else#define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */ #endif#define ADC12MEM0_ ADC12MEM_ /* ADC12 Conversion Memory 0 */sfrw ADC12MEM0 = ADC12MEM0_;#define ADC12MEM1_ 0x0142 /* ADC12 Conversion Memory 1 */sfrw ADC12MEM1 = ADC12MEM1_;#define ADC12MEM2_ 0x0144 /* ADC12 Conversion Memory 2 */sfrw ADC12MEM2 = ADC12MEM2_;#define ADC12MEM3_ 0x0146 /* ADC12 Conversion Memory 3 */sfrw ADC12MEM3 = ADC12MEM3_;#define ADC12MEM4_ 0x0148 /* ADC12 Conversion Memory 4 */sfrw ADC12MEM4 = ADC12MEM4_;#define ADC12MEM5_ 0x014A /* ADC12 Conversion Memory 5 */sfrw ADC12MEM5 = ADC12MEM5_;#define ADC12MEM6_ 0x014C /* ADC12 Conversion Memory 6 */sfrw ADC12MEM6 = ADC12MEM6_;#define ADC12MEM7_ 0x014E /* ADC12 Conversion Memory 7 */sfrw ADC12MEM7 = ADC12MEM7_;#define ADC12MEM8_ 0x0150 /* ADC12 Conversion Memory 8 */sfrw ADC12MEM8 = ADC12MEM8_;#define ADC12MEM9_ 0x0152 /* ADC12 Conversion Memory 9 */sfrw ADC12MEM9 = ADC12MEM9_;#define ADC12MEM10_ 0x0154 /* ADC12 Conversion Memory 10 */sfrw ADC12MEM10 = ADC12MEM10_;#define ADC12MEM11_ 0x0156 /* ADC12 Conversion Memory 11 */sfrw ADC12MEM11 = ADC12MEM11_;#define ADC12MEM12_ 0x0158 /* ADC12 Conversion Memory 12 */sfrw ADC12MEM12 = ADC12MEM12_;#define ADC12MEM13_ 0x015A /* ADC12 Conversion Memory 13 */sfrw ADC12MEM13 = ADC12MEM13_;#define ADC12MEM14_ 0x015C /* ADC12 Conversion Memory 14 */sfrw ADC12MEM14 = ADC12MEM14_;#define ADC12MEM15_ 0x015E /* ADC12 Conversion Memory 15 */sfrw ADC12MEM15 = ADC12MEM15_;/*ADC12存贮控制类寄存器*/#define ADC12MCTL_ 0x0080 /* ADC12 Memory Control */#ifndef __IAR_SYSTEMS_ICC#define ADC12MCTL ADC12MCTL_ /* ADC12 Memory Control (for assembler) */#else#define ADC12MCTL ((char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */ #endif#define ADC12MCTL0_ ADC12MCTL_ /* ADC12 Memory Control 0 */sfrb ADC12MCTL0 = ADC12MCTL0_;#define ADC12MCTL1_ 0x0081 /* ADC12 Memory Control 1 */sfrb ADC12MCTL1 = ADC12MCTL1_;#define ADC12MCTL2_ 0x0082 /* ADC12 Memory Control 2 */sfrb ADC12MCTL2 = ADC12MCTL2_;#define ADC12MCTL3_ 0x0083 /* ADC12 Memory Control 3 */sfrb ADC12MCTL3 = ADC12MCTL3_;#define ADC12MCTL4_ 0x0084 /* ADC12 Memory Control 4 */sfrb ADC12MCTL4 = ADC12MCTL4_;#define ADC12MCTL5_ 0x0085 /* ADC12 Memory Control 5 */sfrb ADC12MCTL5 = ADC12MCTL5_;#define ADC12MCTL6_ 0x0086 /* ADC12 Memory Control 6 */sfrb ADC12MCTL6 = ADC12MCTL6_;#define ADC12MCTL7_ 0x0087 /* ADC12 Memory Control 7 */sfrb ADC12MCTL7 = ADC12MCTL7_;#define ADC12MCTL8_ 0x0088 /* ADC12 Memory Control 8 */sfrb ADC12MCTL8 = ADC12MCTL8_;#define ADC12MCTL9_ 0x0089 /* ADC12 Memory Control 9 */sfrb ADC12MCTL9 = ADC12MCTL9_;#define ADC12MCTL10_ 0x008A /* ADC12 Memory Control 10 */sfrb ADC12MCTL10 = ADC12MCTL10_;#define ADC12MCTL11_ 0x008B /* ADC12 Memory Control 11 */sfrb ADC12MCTL11 = ADC12MCTL11_;#define ADC12MCTL12_ 0x008C /* ADC12 Memory Control 12 */sfrb ADC12MCTL12 = ADC12MCTL12_;#define ADC12MCTL13_ 0x008D /* ADC12 Memory Control 13 */sfrb ADC12MCTL13 = ADC12MCTL13_;#define ADC12MCTL14_ 0x008E /* ADC12 Memory Control 14 */sfrb ADC12MCTL14 = ADC12MCTL14_;#define ADC12MCTL15_ 0x008F /* ADC12 Memory Control 15 */sfrb ADC12MCTL15 = ADC12MCTL15_;/* ADC12CTL0 内8位控制寄存器位*/#define ADC12SC 0x001 /*采样/转换控制位*/#define ENC 0x002 /* 转换允许位*/#define ADC12TOVIE 0x004 /*转换时间溢出中断允许位*/#define ADC12OVIE 0x008 /*溢出中断允许位*/#define ADC12ON 0x010 /*ADC12内核控制位*/#define REFON 0x020 /*参考电压控制位*/#define REF2_5V 0x040 /*内部参考电压的电压值选择位 '0'为1.5V; '1'为2.5V*/ #define MSH 0x080 /*多次采样/转换位*/#define MSC 0x080 /*多次采样/转换位*//*SHT0 采样保持定时器0 控制ADC12的结果存贮器MEM0~MEM7的采样周期*/#define SHT0_0 0*0x100 /*采样周期=TADC12CLK*4 */#define SHT0_1 1*0x100 /*采样周期=TADC12CLK*8 */#define SHT0_2 2*0x100 /*采样周期=TADC12CLK*16 */#define SHT0_3 3*0x100 /*采样周期=TADC12CLK*32 */#define SHT0_4 4*0x100 /*采样周期=TADC12CLK*64 */#define SHT0_5 5*0x100 /*采样周期=TADC12CLK*96 */#define SHT0_6 6*0x100 /*采样周期=TADC12CLK*128 */#define SHT0_7 7*0x100 /*采样周期=TADC12CLK*192 */#define SHT0_8 8*0x100 /*采样周期=TADC12CLK*256 */#define SHT0_9 9*0x100 /*采样周期=TADC12CLK*384 */#define SHT0_10 10*0x100 /*采样周期=TADC12CLK*512 */#define SHT0_11 11*0x100 /*采样周期=TADC12CLK*768 */#define SHT0_12 12*0x100 /*采样周期=TADC12CLK*1024 */#define SHT0_13 13*0x100 /*采样周期=TADC12CLK*1024 */ #define SHT0_14 14*0x100 /*采样周期=TADC12CLK*1024*/ #define SHT0_15 15*0x100 /*采样周期=TADC12CLK*1024 */ /*SHT1 采样保持定时器1 控制ADC12的结果存贮器MEM8~MEM15的采样周期*/#define SHT1_0 0*0x100 /*采样周期=TADC12CLK*4 */#define SHT1_1 1*0x100 /*采样周期=TADC12CLK*8 */#define SHT1_2 2*0x100 /*采样周期=TADC12CLK*16 */#define SHT1_3 3*0x100 /*采样周期=TADC12CLK*32 */#define SHT1_4 4*0x100 /*采样周期=TADC12CLK*64 */#define SHT1_5 5*0x100 /*采样周期=TADC12CLK*96 */#define SHT1_6 6*0x100 /*采样周期=TADC12CLK*128 */ #define SHT1_7 7*0x100 /*采样周期=TADC12CLK*192 */ #define SHT1_8 8*0x100 /*采样周期=TADC12CLK*256 */ #define SHT1_9 9*0x100 /*采样周期=TADC12CLK*384 */ #define SHT1_10 10*0x100 /*采样周期=TADC12CLK*512 */ #define SHT1_11 11*0x100 /*采样周期=TADC12CLK*768 */ #define SHT1_12 12*0x100 /*采样周期=TADC12CLK*1024 */ #define SHT1_13 13*0x100 /*采样周期=TADC12CLK*1024 */ #define SHT1_14 14*0x100 /*采样周期=TADC12CLK*1024 */ #define SHT1_15 15*0x100 /*采样周期=TADC12CLK*1024 *//* ADC12CTL1 内8位控制寄存器位*/#define ADC12BUSY 0x0001 /*ADC12忙标志位*/#define CONSEQ_0 0*2 /*单通道单次转换*/#define CONSEQ_1 1*2 /*序列通道单次转换*/#define CONSEQ_2 2*2 /*单通道多次转换*/#define CONSEQ_3 3*2 /*序列通道多次转换*/#define ADC12SSEL_0 0*8 /*ADC12内部时钟源*/#define ADC12SSEL_1 1*8 /*ACLK*/#define ADC12SSEL_2 2*8 /*MCLK*/#define ADC12SSEL_3 3*8 /*SCLK*/#define ADC12DIV_0 0*0x20 /*1分频*/#define ADC12DIV_1 1*0x20 /*2分频*/#define ADC12DIV_2 2*0x20 /*3分频*/#define ADC12DIV_3 3*0x20 /*4分频*/#define ADC12DIV_4 4*0x20 /*5分频*/#define ADC12DIV_5 5*0x20 /*6分频*/#define ADC12DIV_6 6*0x20 /*7分频*/#define ADC12DIV_7 7*0x20 /*8分频*/#define ISSH 0x0100 /*采样输入信号反向与否控制位*/#define SHP 0x0200 /*采样信号(SAMPCON)选择控制位*/#define SHS_0 0*0x400 /*采样信号输入源选择控制位 ADC12SC*/#define SHS_1 1*0x400 /*采样信号输入源选择控制位 TIMER_A.OUT1*/ #define SHS_2 2*0x400 /*采样信号输入源选择控制位 TIMER_B.OUT0*/ #define SHS_3 3*0x400 /*采样信号输入源选择控制位 TIMER_B.OUT1*/ /*转换存贮器地址定义位*/#define CSTARTADD_0 0*0x1000 /*选择MEM0首地址*/#define CSTARTADD_1 1*0x1000 /*选择MEM1首地址*/#define CSTARTADD_2 2*0x1000 /*选择MEM2首地址*/#define CSTARTADD_3 3*0x1000 /*选择MEM3首地址*/#define CSTARTADD_4 4*0x1000 /*选择MEM4首地址*/#define CSTARTADD_5 5*0x1000 /*选择MEM5首地址*/#define CSTARTADD_6 6*0x1000 /*选择MEM6首地址*/#define CSTARTADD_7 7*0x1000 /*选择MEM7首地址*/#define CSTARTADD_8 8*0x1000 /*选择MEM8首地址*/#define CSTARTADD_9 9*0x1000 /*选择MEM9首地址*/#define CSTARTADD_10 10*0x1000 /*选择MEM10首地址*/#define CSTARTADD_11 11*0x1000 /*选择MEM11首地址*/#define CSTARTADD_12 12*0x1000 /*选择MEM12首地址*/#define CSTARTADD_13 13*0x1000 /*选择MEM13首地址*/#define CSTARTADD_14 14*0x1000 /*选择MEM14首地址*/#define CSTARTADD_15 15*0x1000 /*选择MEM15首地址*//* ADC12MCTLx */#define INCH_0 0 /*选择模拟量通道0 A0 */#define INCH_1 1 /*选择模拟量通道0 A1*/#define INCH_2 2 /*选择模拟量通道0 A2*/#define INCH_3 3 /*选择模拟量通道0 A3*/#define INCH_4 4 /*选择模拟量通道0 A4*/#define INCH_5 5 /*选择模拟量通道0 A5*/#define INCH_6 6 /*选择模拟量通道0 A6*/#define INCH_7 7 /*选择模拟量通道0 A7*/#define INCH_8 8 /*VEREF+*/#define INCH_9 9 /*VEREF-*/#define INCH_10 10 /*片内温度传感器的输出*/#define INCH_11 11 /*(AVCC-AVSS)/2*/#define INCH_12 12 /*(AVCC-AVSS)/2*/#define INCH_13 13 /*(AVCC-AVSS)/2*/#define INCH_14 14 /*(AVCC-AVSS)/2*/#define INCH_15 15 /*(AVCC-AVSS)/2*//*参考电压源选择位*/#define SREF_0 0*0x10 /*VR+ = AVCC; VR- = AVSS*/#define SREF_1 1*0x10 /*VR+ = VREF+; VR- = AVSS*/ #define SREF_2 2*0x10 /*VR+ = VEREF+; VR- = AVSS*/ #define SREF_3 3*0x10 /*VR+ = VEREF+; VR- = AVSS*/ #define SREF_4 4*0x10 /*VR+ = AVCC; VR- = VREF-*/ #define SREF_5 5*0x10 /*VR+ = VREF+; VR- = VREF-*/ #define SREF_6 6*0x10 /*VR+ = VEREF+; VR- = VREF-*/ #define SREF_7 7*0x10 /*VR+ = VEREF+; VR- = VREF-*/#define EOS 0x80 /*序列结束选择位*/MSP430寄存器中文注释----串口寄存器/************************************************************* USART 串口寄存器"UCTL","UTCTL","URCTL"定义的各个位可串口1 串口2公用************************************************************//* UCTL 串口控制寄存器*/#define PENA 0x80 /*校验允许位*/#define PEV 0x40 /*偶校验为0时为奇校验*/#define SPB 0x20 /*停止位为2 为0时停止位为1*/#define CHAR 0x10 /*数据位为8位为0时数据位为7位*/#define LISTEN 0x08 /*自环模式(发数据同时在把发的数据接收回来)*/#define SYNC 0x04 /*同步模式为0异步模式*/#define MM 0x02 /*为1时地址位多机协议(异步) 主机模式(同步);为0时线路空闲多机协议(异步) 从机模式(同步)*/#define SWRST 0x01 /*控制位*//* UTCTL 串口发送控制寄存器*/#define CKPH 0x80 /*时钟相位控制位(只同步方式用)为1时时钟UCLK延时半个周期*/#define CKPL 0x40 /*时钟极性控制位为1时异步与UCLK相反;同步下降延有效*/#define SSEL1 0x20 /*时钟源选择位:与SSEL0组合为0,1,2,3四种方式*/#define SSEL0 0x10 /*"0"选择外部时钟,"1"选择辅助时钟,"2","3"选择系统子时钟 */#define URXSE 0x08 /*接收触发延控制位(只在异步方式下用)*/#define TXWAKE 0x04 /*多处理器通信传送控制位(只在异步方式下用)*/#define STC 0x02 /*外部引脚STE选择位为0时为4线模式为1时为3线模式*/ #define TXEPT 0x01 /*发送器空标志*//* URCTL 串口接收控制寄存器同步模式下只用两位:FE和OE*/#define FE 0x80 /*帧错标志*/#define PE 0x40 /*校验错标志位*/#define OE 0x20 /*溢出标志位*/#define BRK 0x10 /*打断检测位*/#define URXEIE 0x08 /*接收出错中断允许位*/#define URXWIE 0x04 /*接收唤醒中断允许位*/#define RXWAKE 0x02 /*接收唤醒检测位*/#define RXERR 0x01 /*接收错误标志位*//************************************************************* USART 0 串口0寄存器定义************************************************************/#define U0CTL_ 0x0070 /* UART 0 Control */sfrb U0CTL = U0CTL_;#define U0TCTL_ 0x0071 /* UART 0 Transmit Control */ sfrb U0TCTL = U0TCTL_;#define U0RCTL_ 0x0072 /* UART 0 Receive Control */ sfrb U0RCTL = U0RCTL_;#define U0MCTL_ 0x0073 /* UART 0 Modulation Control */ sfrb U0MCTL = U0MCTL_;#define U0BR0_ 0x0074 /* UART 0 Baud Rate 0 */sfrb U0BR0 = U0BR0_;#define U0BR1_ 0x0075 /* UART 0 Baud Rate 1 */sfrb U0BR1 = U0BR1_;#define U0RXBUF_ 0x0076 /* UART 0 Receive Buffer */ const sfrb U0RXBUF = U0RXBUF_;#define U0TXBUF_ 0x0077 /* UART 0 Transmit Buffer */ sfrb U0TXBUF = U0TXBUF_;/* Alternate register names */#define UCTL0_ 0x0070 /* UART 0 Control */sfrb UCTL0 = UCTL0_;#define UTCTL0_ 0x0071 /* UART 0 Transmit Control */ sfrb UTCTL0 = UTCTL0_;#define URCTL0_ 0x0072 /* UART 0 Receive Control */ sfrb URCTL0 = URCTL0_;#define UMCTL0_ 0x0073 /* UART 0 Modulation Control */ sfrb UMCTL0 = UMCTL0_;#define UBR00_ 0x0074 /* UART 0 Baud Rate 0 */sfrb UBR00 = UBR00_;#define UBR10_ 0x0075 /* UART 0 Baud Rate 1 */sfrb UBR10 = UBR10_;#define RXBUF0_ 0x0076 /* UART 0 Receive Buffer */ const sfrb RXBUF0 = RXBUF0_;#define TXBUF0_ 0x0077 /* UART 0 Transmit Buffer */ sfrb TXBUF0 = TXBUF0_;#define UCTL_0_ 0x0070 /* UART 0 Control */sfrb UCTL_0 = UCTL_0_;#define UTCTL_0_ 0x0071 /* UART 0 Transmit Control */ sfrb UTCTL_0 = UTCTL_0_;#define URCTL_0_ 0x0072 /* UART 0 Receive Control */ sfrb URCTL_0 = URCTL_0_;#define UMCTL_0_ 0x0073 /* UART 0 Modulation Control */ sfrb UMCTL_0 = UMCTL_0_;#define UBR0_0_ 0x0074 /* UART 0 Baud Rate 0 */sfrb UBR0_0 = UBR0_0_;#define UBR1_0_ 0x0075 /* UART 0 Baud Rate 1 */sfrb UBR1_0 = UBR1_0_;#define RXBUF_0_ 0x0076 /* UART 0 Receive Buffer */ const sfrb RXBUF_0 = RXBUF_0_;#define TXBUF_0_ 0x0077 /* UART 0 Transmit Buffer *//************************************************************* USART 1 串口1寄存器定义************************************************************/#define U1CTL_ 0x0078 /* UART 1 Control */sfrb U1CTL = U1CTL_;#define U1TCTL_ 0x0079 /* UART 1 Transmit Control */ sfrb U1TCTL = U1TCTL_;#define U1RCTL_ 0x007A /* UART 1 Receive Control */ sfrb U1RCTL = U1RCTL_;#define U1MCTL_ 0x007B /* UART 1 Modulation Control */ sfrb U1MCTL = U1MCTL_;#define U1BR0_ 0x007C /* UART 1 Baud Rate 0 */sfrb U1BR0 = U1BR0_;#define U1BR1_ 0x007D /* UART 1 Baud Rate 1 */sfrb U1BR1 = U1BR1_;#define U1RXBUF_ 0x007E /* UART 1 Receive Buffer */ const sfrb U1RXBUF = U1RXBUF_;#define U1TXBUF_ 0x007F /* UART 1 Transmit Buffer */ sfrb U1TXBUF = U1TXBUF_;#define UCTL1_ 0x0078 /* UART 1 Control */sfrb UCTL1 = UCTL1_;#define UTCTL1_ 0x0079 /* UART 1 Transmit Control */ sfrb UTCTL1 = UTCTL1_;#define URCTL1_ 0x007A /* UART 1 Receive Control */ sfrb URCTL1 = URCTL1_;#define UMCTL1_ 0x007B /* UART 1 Modulation Control */ sfrb UMCTL1 = UMCTL1_;#define UBR01_ 0x007C /* UART 1 Baud Rate 0 */#define UBR11_ 0x007D /* UART 1 Baud Rate 1 */sfrb UBR11 = UBR11_;#define RXBUF1_ 0x007E /* UART 1 Receive Buffer */ const sfrb RXBUF1 = RXBUF1_;#define TXBUF1_ 0x007F /* UART 1 Transmit Buffer */ sfrb TXBUF1 = TXBUF1_;#define UCTL_1_ 0x0078 /* UART 1 Control */sfrb UCTL_1 = UCTL_1_;#define UTCTL_1_ 0x0079 /* UART 1 Transmit Control */ sfrb UTCTL_1 = UTCTL_1_;#define URCTL_1_ 0x007A /* UART 1 Receive Control */ sfrb URCTL_1 = URCTL_1_;#define UMCTL_1_ 0x007B /* UART 1 Modulation Control */ sfrb UMCTL_1 = UMCTL_1_;#define UBR0_1_ 0x007C /* UART 1 Baud Rate 0 */sfrb UBR0_1 = UBR0_1_;#define UBR1_1_ 0x007D /* UART 1 Baud Rate 1 */sfrb UBR1_1 = UBR1_1_;#define RXBUF_1_ 0x007E /* UART 1 Receive Buffer */ const sfrb RXBUF_1 = RXBUF_1_;#define TXBUF_1_ 0x007F /* UART 1 Transmit Buffer */ sfrb TXBUF_1 = TXBUF_1_;MSP430寄存器中文注释---P1/2口（带中断功能）/************************************************************* DIGITAL I/O Port1/2 寄存器定义有中断功能************************************************************/#define P1IN_ 0x0020 /* P1 输入寄存器 */const sfrb P1IN = P1IN_;#define P1OUT_ 0x0021 /* P1 输出寄存器 */sfrb P1OUT = P1OUT_;#define P1DIR_ 0x0022 /* P1 方向选择寄存器 */sfrb P1DIR = P1DIR_;#define P1IFG_ 0x0023 /* P1 中断标志寄存器*/sfrb P1IFG = P1IFG_;#define P1IES_ 0x0024 /* P1 中断边沿选择寄存器*/ sfrb P1IES = P1IES_;#define P1IE_ 0x0025 /* P1 中断使能寄存器 */sfrb P1IE = P1IE_;#define P1SEL_ 0x0026 /* P1 功能选择寄存器*/sfrb P1SEL = P1SEL_;#define P2IN_ 0x0028 /* P2 输入寄存器 */const sfrb P2IN = P2IN_;#define P2OUT_ 0x0029 /* P2 输出寄存器 */sfrb P2OUT = P2OUT_;#define P2DIR_ 0x002A /* P2 方向选择寄存器 */ sfrb P2DIR = P2DIR_;#define P2IFG_ 0x002B /* P2 中断标志寄存器 */sfrb P2IFG = P2IFG_;#define P2IES_ 0x002C /* P2 中断边沿选择寄存器 */ sfrb P2IES = P2IES_;#define P2IE_ 0x002D /* P2 中断使能寄存器 */sfrb P2IE = P2IE_;#define P2SEL_ 0x002E /* P2 功能选择寄存器 */sfrb P2SEL = P2SEL_;MSP430寄存器中文注释---P3/4口（无中断功能）/************************************************************ * DIGITAL I/O Port3/4寄存器定义无中断功能************************************************************/#define P3IN_ 0x0018 /* P3 输入寄存器 */const sfrb P3IN = P3IN_;#define P3OUT_ 0x0019 /* P3 输出寄存器 */sfrb P3OUT = P3OUT_;#define P3DIR_ 0x001A /* P3 方向选择寄存器 */sfrb P3DIR = P3DIR_;#define P3SEL_ 0x001B /* P3 功能选择寄存器*/sfrb P3SEL = P3SEL_;#define P4IN_ 0x001C /* P4 输入寄存器 */const sfrb P4IN = P4IN_;#define P4OUT_ 0x001D /* P4 输出寄存器 */sfrb P4OUT = P4OUT_;#define P4DIR_ 0x001E /* P4 方向选择寄存器 */sfrb P4DIR = P4DIR_;#define P4SEL_ 0x001F /* P4 功能选择寄存器 */sfrb P4SEL = P4SEL_;/************************************************************ * DIGITAL I/O Port5/6 I/O口寄存器定义PORT5和6 无中断功能************************************************************/#define P5IN_ 0x0030 /* P5 输入寄存器 */const sfrb P5IN = P5IN_;#define P5OUT_ 0x0031 /* P5 输出寄存器*/sfrb P5OUT = P5OUT_;#define P5DIR_ 0x0032 /* P5 方向选择寄存器*/sfrb P5DIR = P5DIR_;#define P5SEL_ 0x0033 /* P5 功能选择寄存器*/sfrb P5SEL = P5SEL_;#define P6IN_ 0x0034 /* P6 输入寄存器 */const sfrb P6IN = P6IN_;#define P6OUT_ 0x0035 /* P6 输出寄存器*/sfrb P6OUT = P6OUT_;#define P6DIR_ 0x0036 /* P6 方向选择寄存器*/sfrb P6DIR = P6DIR_;#define P6SEL_ 0x0037 /* P6 功能选择寄存器*/sfrb P6SEL = P6SEL_;MSP430寄存器中文注释--- 硬件乘法器/************************************************************ 硬件乘法器的寄存器定义************************************************************/#define MPY_ 0x0130 /* 无符号乘法 */sfrw MPY = MPY_;#define MPYS_ 0x0132 /* 有符号乘法*/sfrw MPYS = MPYS_;#define MAC_ 0x0134 /* 无符号乘加 */sfrw MAC = MAC_;#define MACS_ 0x0136 /* 有符号乘加 */sfrw MACS = MACS_;#define OP2_ 0x0138 /* 第二乘数 */sfrw OP2 = OP2_;#define RESLO_ 0x013A /* 低6位结果寄存器 */sfrw RESLO = RESLO_;#define RESHI_ 0x013C /* 高6位结果寄存器 */sfrw RESHI = RESHI_;#define SUMEXT_ 0x013E /*结果扩展寄存器 */const sfrw SUMEXT = SUMEXT_;MSP430寄存器中文注释---看门狗和定时器/************************************************************* 看门狗定时器的寄存器定义************************************************************/#define WDTCTL_ 0x0120sfrw WDTCTL = WDTCTL_;#define WDTIS0 0x0001 /*选择WDTCNT的四个输出端之一*/#define WDTIS1 0x0002 /*选择WDTCNT的四个输出端之一*/#define WDTSSEL 0x0004 /*选择WDTCNT的时钟源*/#define WDTCNTCL 0x0008 /*清除WDTCNT端: 为1时从0开始计数*/#define WDTTMSEL 0x0010 /*选择模式 0: 看门狗模式; 1: 定时器模式*/#define WDTNMI 0x0020 /*选择NMI/RST 引脚功能 0:为 RST; 1:为NMI*/#define WDTNMIES 0x0040 /*WDTNMI=1时.选择触发延 0:为上升延 1:为下降延*/ #define WDTHOLD 0x0080 /*停止看门狗定时器工作 0:启动;1:停止*/#define WDTPW 0x5A00 /* 写密码:高八位*//* SMCLK= 1MHz定时器模式 */#define WDT_MDLY_32 WDTPW+WDTTMSEL+WDTCNTCL /* TSMCLK*2POWER15=32ms 复位状态 */#define WDT_MDLY_8 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0 /* TSMCLK*2POWER13=8.192ms " */#define WDT_MDLY_0_5 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1 /* TSMCLK*2POWER9=0.512ms " */#define WDT_MDLY_0_064 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0 /* TSMCLK*2POWER6=0.512ms " *//* ACLK=32.768KHz 定时器模式*/#define WDT_ADLY_1000 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL /* TACLK*2POWER15=1000ms " */#define WDT_ADLY_250 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0 /* TACLK*2POWER13=250ms " */#define WDT_ADLY_16 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1 /*TACLK*2POWER9=16ms " */#define WDT_ADLY_1_9 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0 /* TACLK*2POWER6=1.9ms " *//* SMCLK=1MHz看门狗模式 */#define WDT_MRST_32 WDTPW+WDTCNTCL /* TSMCLK*2POWER15=32ms 复位状态 */#define WDT_MRST_8 WDTPW+WDTCNTCL+WDTIS0 /* TSMCLK*2POWER13=8.192ms " */#define WDT_MRST_0_5 WDTPW+WDTCNTCL+WDTIS1 /* TSMCLK*2POWER9=0.512ms " */#define WDT_MRST_0_064 WDTPW+WDTCNTCL+WDTIS1+WDTIS0 /* TSMCLK*2POWER6=0.512ms " *//* ACLK=32KHz看门狗模式 */#define WDT_ARST_1000 WDTPW+WDTCNTCL+WDTSSEL /* TACLK*2POWER15=1000ms " */#define WDT_ARST_250 WDTPW+WDTCNTCL+WDTSSEL+WDTIS0 /* TACLK*2POWER13=250ms " */#define WDT_ARST_16 WDTPW+WDTCNTCL+WDTSSEL+WDTIS1 /* TACLK*2POWER9=16ms " */#define WDT_ARST_1_9 WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0 /* TACLK*2POWER6=1.9ms " */MSP430寄存器中文注释---A/D采样寄存器定义/************************************************************* ADC12 A/D采样寄存器定义************************************************************//*ADC12转换控制类寄存器*/#define ADC12CTL0_ 0x0;' /* ADC12 Control 0 */sfrw ADC12CTL0 = ADC12CTL0_;#define ADC12CTL1_ 0x01A2 /* ADC12 Control 1 */sfrw ADC12CTL1 = ADC12CTL1_;/*ADC12中断控制类寄存器*/#define ADC12IFG_ 0x01A4 /* ADC12 Interrupt Flag */sfrw ADC12IFG = ADC12IFG_;#define ADC12IE_ 0x01A6 /* ADC12 Interrupt Enable */sfrw ADC12IE = ADC12IE_;#define ADC12IV_ 0x01A8 /* ADC12 Interrupt Vector Word */sfrw ADC12IV = ADC12IV_;/*ADC12存贮器类寄存器*/#define ADC12MEM_ 0x0140 /* ADC12 Conversion Memory */#ifndef __IAR_SYSTEMS_ICC#define ADC12MEM ADC12MEM_ /* ADC12 Conversion Memory (for assembler) */ #else#define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */ #endif#define ADC12MEM0_ ADC12MEM_ /* ADC12 Conversion Memory 0 */sfrw ADC12MEM0 = ADC12MEM0_;#define ADC12MEM1_ 0x0142 /* ADC12 Conversion Memory 1 */sfrw ADC12MEM1 = ADC12MEM1_;#define ADC12MEM2_ 0x0144 /* ADC12 Conversion Memory 2 */sfrw ADC12MEM2 = ADC12MEM2_;#define ADC12MEM3_ 0x0146 /* ADC12 Conversion Memory 3 */sfrw ADC12MEM3 = ADC12MEM3_;#define ADC12MEM4_ 0x0148 /* ADC12 Conversion Memory 4 */sfrw ADC12MEM4 = ADC12MEM4_;#define ADC12MEM5_ 0x014A /* ADC12 Conversion Memory 5 */sfrw ADC12MEM5 = ADC12MEM5_;#define ADC12MEM6_ 0x014C /* ADC12 Conversion Memory 6 */sfrw ADC12MEM6 = ADC12MEM6_;#define ADC12MEM7_ 0x014E /* ADC12 Conversion Memory 7 */sfrw ADC12MEM7 = ADC12MEM7_;#define ADC12MEM8_ 0x0150 /* ADC12 Conversion Memory 8 */sfrw ADC12MEM8 = ADC12MEM8_;#define ADC12MEM9_ 0x0152 /* ADC12 Conversion Memory 9 */sfrw ADC12MEM9 = ADC12MEM9_;#define ADC12MEM10_ 0x0154 /* ADC12 Conversion Memory 10 */sfrw ADC12MEM10 = ADC12MEM10_;#define ADC12MEM11_ 0x0156 /* ADC12 Conversion Memory 11 */sfrw ADC12MEM11 = ADC12MEM11_;#define ADC12MEM12_ 0x0158 /* ADC12 Conversion Memory 12 */sfrw ADC12MEM12 = ADC12MEM12_;#define ADC12MEM13_ 0x015A /* ADC12 Conversion Memory 13 */sfrw ADC12MEM13 = ADC12MEM13_;#define ADC12MEM14_ 0x015C /* ADC12 Conversion Memory 14 */sfrw ADC12MEM14 = ADC12MEM14_;#define ADC12MEM15_ 0x015E /* ADC12 Conversion Memory 15 */sfrw ADC12MEM15 = ADC12MEM15_;/*ADC12存贮控制类寄存器*/#define ADC12MCTL_ 0x0080 /* ADC12 Memory Control */#ifndef __IAR_SYSTEMS_ICC#define ADC12MCTL ADC12MCTL_ /* ADC12 Memory Control (for assembler) */#else#define ADC12MCTL ((char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */ #endif#define ADC12MCTL0_ ADC12MCTL_ /* ADC12 Memory Control 0 */sfrb ADC12MCTL0 = ADC12MCTL0_;#define ADC12MCTL1_ 0x0081 /* ADC12 Memory Control 1 */sfrb ADC12MCTL1 = ADC12MCTL1_;#define ADC12MCTL2_ 0x0082 /* ADC12 Memory Control 2 */sfrb ADC12MCTL2 = ADC12MCTL2_;#define ADC12MCTL3_ 0x0083 /* ADC12 Memory Control 3 */sfrb ADC12MCTL3 = ADC12MCTL3_;#define ADC12MCTL4_ 0x0084 /* ADC12 Memory Control 4 */sfrb ADC12MCTL4 = ADC12MCTL4_;#define ADC12MCTL5_ 0x0085 /* ADC12 Memory Control 5 */sfrb ADC12MCTL5 = ADC12MCTL5_;#define ADC12MCTL6_ 0x0086 /* ADC12 Memory Control 6 */sfrb ADC12MCTL6 = ADC12MCTL6_;#define ADC12MCTL7_ 0x0087 /* ADC12 Memory Control 7 */sfrb ADC12MCTL7 = ADC12MCTL7_;#define ADC12MCTL8_ 0x0088 /* ADC12 Memory Control 8 */sfrb ADC12MCTL8 = ADC12MCTL8_;#define ADC12MCTL9_ 0x0089 /* ADC12 Memory Control 9 */sfrb ADC12MCTL9 = ADC12MCTL9_;#define ADC12MCTL10_ 0x008A /* ADC12 Memory Control 10 */sfrb ADC12MCTL10 = ADC12MCTL10_;#define ADC12MCTL11_ 0x008B /* ADC12 Memory Control 11 */sfrb ADC12MCTL11 = ADC12MCTL11_;#define ADC12MCTL12_ 0x008C /* ADC12 Memory Control 12 */sfrb ADC12MCTL12 = ADC12MCTL12_;#define ADC12MCTL13_ 0x008D /* ADC12 Memory Control 13 */sfrb ADC12MCTL13 = ADC12MCTL13_;#define ADC12MCTL14_ 0x008E /* ADC12 Memory Control 14 */sfrb ADC12MCTL14 = ADC12MCTL14_;#define ADC12MCTL15_ 0x008F /* ADC12 Memory Control 15 */sfrb ADC12MCTL15 = ADC12MCTL15_;/* ADC12CTL0 内8位控制寄存器位*/#define ADC12SC 0x001 /*采样/转换控制位*/#define ENC 0x002 /* 转换允许位*/#define ADC12TOVIE 0x004 /*转换时间溢出中断允许位*/#define ADC12OVIE 0x008 /*溢出中断允许位*/#define ADC12ON 0x010 /*ADC12内核控制位*/#define REFON 0x020 /*参考电压控制位*/#define REF2_5V 0x040 /*内部参考电压的电压值选择位 '0'为1.5V; '1'为2.5V*/ #define MSH 0x080 /*多次采样/转换位*/#define MSC 0x080 /*多次采样/转换位*//*SHT0 采样保持定时器0 控制ADC12的结果存贮器MEM0~MEM7的采样周期*/。

MSP430G2x53MSP430G2x13 SLAS735A–APRIL2011–REVISED MAY2011MIXED SIGNAL MICROCONTROLLERFEATURES•Low Supply-Voltage Range:1.8V to3.6V•Universal Serial Communication Interface(USCI)•Ultra-Low Power Consumption–Enhanced UART Supporting Auto Baudrate –Active Mode:230µA at1MHz,2.2VDetection(LIN)–Standby Mode:0.5µA–IrDA Encoder and Decoder –Off Mode(RAM Retention):0.1µA–Synchronous SPI•Five Power-Saving Modes–I2C™•Ultra-Fast Wake-Up From Standby Mode in•On-Chip Comparator for Analog Signal Less Than1µsCompare Function or Slope Analog-to-Digital •16-Bit RISC Architecture,62.5-ns Instruction(A/D)ConversionCycle Time•10-Bit200-ksps Analog-to-Digital(A/D)•Basic Clock Module ConfigurationsConverter With Internal Reference,–Internal Frequencies up to16MHz With Sample-and-Hold,and Autoscan(See Table1) Four Calibrated Frequency•Brownout Detector–Internal Very-Low-Power Low-Frequency•Serial Onboard Programming, (LF)OscillatorNo External Programming Voltage Needed,–32-kHz Crystal Programmable Code Protection by Security –External Digital Clock Source Fuse•Two16-Bit Timer_A With Three•On-Chip Emulation Logic With Spy-Bi-Wire Capture/Compare Registers Interface•Up to24Touch-Sense-Enabled I/O Pins•Family Members are Summarized in Table1•Package Options–TSSOP:20Pin,28Pin–PDIP:20Pin–QFN:32Pin•For Complete Module Descriptions,See theMSP430x2xx Family User’s Guide(SLAU144)DESCRIPTIONThe Texas Instruments MSP430family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications.The architecture,combined with five low-power modes,is optimized to achieve extended battery life in portable measurement applications.The device features a powerful16-bit RISC CPU,16-bit registers,and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator(DCO)allows wake-up from low-power modes to active mode in less than1µs. The MSP430G2x13and MSP430G2x53series are ultra-low-power mixed signal microcontrollers with built-in 16-bit timers,up to24I/O touch-sense-enabled pins,a versatile analog comparator,and built-in communication capability using the universal serial communication interface.In addition the MSP430G2x53family members have a10-bit analog-to-digital(A/D)converter.For configuration details see Table1.Typical applications include low-cost sensor systems that capture analog signals,convert them to digital values, and then process the data for display or for transmission to a host system.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2011,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.MSP430G2x53MSP430G2x13SLAS735A–APRIL2011–REVISED Table1.Available Options(1)(2)Flash RAM COMP_A+ADC10USCI Package Device BSL EEM Timer_A Clock I/O(KB)(B)Channel Channel A0/B0Type MSP430G2553IRHB322432-QFNLF,MSP430G2553IPW282428-TSSOP 11165122x TA3881DCO,MSP430G2553IPW201620-TSSOPVLOMSP430G2553IN201620-PDIP MSP430G2453IRHB322432-QFNLF,MSP430G2453IPW282428-TSSOP 1185122x TA3881DCO,MSP430G2453IPW201620-TSSOPVLOMSP430G2453IN201620-PDIP MSP430G2353IRHB322432-QFNLF,MSP430G2353IPW282428-TSSOP 1142562x TA3881DCO,MSP430G2353IPW201620-TSSOPVLOMSP430G2353IN201620-PDIP MSP430G2253IRHB322432-QFNLF,MSP430G2253IPW282428-TSSOP 1122562x TA3881DCO,MSP430G2253IPW201620-TSSOPVLOMSP430G2253IN201620-PDIP MSP430G2153IRHB322432-QFNLF,MSP430G2153IPW282428-TSSOP 1112562x TA3881DCO,MSP430G2153IPW201620-TSSOPVLOMSP430G2153IN201620-PDIP MSP430G2513IRHB322432-QFNLF,MSP430G2513IPW282428-TSSOP 11165122x TA38-1DCO,MSP430G2513IPW201620-TSSOPVLOMSP430G2513IN201620-PDIP MSP430G2413IRHB322432-QFNLF,MSP430G2413IPW282428-TSSOP 1185122x TA38-1DCO,MSP430G2413IPW201620-TSSOPVLOMSP430G2413IN201620-PDIP MSP430G2313IRHB322432-QFNLF,MSP430G2313IPW282428-TSSOP 1142562x TA38-1DCO,MSP430G2313IPW201620-TSSOPVLOMSP430G2313IN201620-PDIP MSP430G2213IRHB322432-QFNLF,MSP430G2213IPW282428-TSSOP 1122562x TA38-1DCO,MSP430G2213IPW201620-TSSOPVLOMSP430G2213IN201620-PDIP MSP430G2113IRHB322432-QFNLF,MSP430G2113IPW282428-TSSOP 1112562x TA38-1DCO,MSP430G2113IPW201620-TSSOPVLOMSP430G2113IN201620-PDIP (1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TIweb site at .(2)Package drawings,thermal data,and symbolization are available at /packaging.2Submit Documentation Feedback Copyright©2011,Texas Instruments IncorporatedCA6/TDI/TCLK UC B0SOMI/UCB0SCL/A6//A7/CA7/TDO/TDI /UCB0SIMO/UCB0SDA P1.1/TA0.0//UCA0RXD/UCA0SOMI P1.2/TA0.1//UCA0TXD/PUCA0SIMO P1.4/SMCLK//VREF+/VEREF+/A4/UCB0STE/UCA0CLK P1.5/TA0.0//UCB0CLK/UCA0STECA6/TDI/TCLK UC B0SOMI/UCB0SCL/A6//A7/CA7/TDO/TDI /UCB0SIMO/UCB0SDA P1.1/TA0.0//UCA0RXD/UCA0SOMI P1.2/TA0.1//UCA0TXD/PUCA0SIMO P1.4/SMCLK//VREF+/VEREF+/A4/UCB0STE/UCA0CLK P1.5/TA0.0//UCB0CLK/UCA0STE RHB32(TOP VIEW)123456P 2.0/T A 1.07P 2.1/T A 1.18NC9P 2.2/T A 1.110P3.0/TA0.211P3.1/TA1.012P 3.2/T A 1.113P 3.3/T A 1.214P 3.4/T A 0.015P3.5/TA0.116P 2.3/T A 1.017P 2.4/T A 1.218P2.5/TA1.21920P3.6/TA0.221P3.7/TA1CLK/CAOUT 2223RST/NMI/SBWTDIO24TEST/SBWTCK 25X O U T /P 2.726X I N /P 2.6/T A 0.127A V S S 28D V S S 29A V C C 30D V C C 31P 1.0/T A 0C L K /A C L K /A 0/C A 032N C P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3P1.1/TA0.0/A1/CA1/UCA0RXD/UCA0SOMI P1.2/TA0.1/A2/CA2/UCA0TXD/UCA0SIMO P1.4/SMCLK/CA4/TCK/VREF+/VEREF+/A4/UCB0STE/UCA0CLK P1.5/TA0.0/A5/CA5/TMS/UCB0CLK/UCA0STE P1.6/TA0.1/CA6/TDI/TCLK UC B0SOMI/UCB0SCL/A6/P1.7/CAOUT /CA7/TDO/TDI /UCB0SIMO/UCB0SDA/A7MSP430G2x53MSP430G2x13SLAS735A –APRIL 2011–REVISED MAY 2011Device Pinout,MSP430G2x13and MSP430G2x53,20-Pin Devices,TSSOP and PDIPNOTE:ADC10is available on MSP430G2x53devices only.NOTE:The pulldown resistors of port P3should be enabled by setting P3REN.x =1.Device Pinout,MSP430G2x13and MSP430G2x53,28-Pin Devices,TSSOPNOTE:ADC10is available on MSP430G2x53devices only.Device Pinout,MSP430G2x13and MSP430G2x53,32-Pin Devices,QFNNOTE:ADC10is available on MSP430G2x53devices only.Copyright ©2011,Texas Instruments IncorporatedSubmit Documentation Feedback 3MSP430G2x53MSP430G2x13SLAS735A –APRIL 2011–REVISED MAY 2011Functional Block Diagram,MSP430G2x53NOTE:Port P3is available on 28-pin and 32-pin devices only.Functional Block Diagram,MSP430G2x13NOTE:Port P3is available on 28-pin and 32-pin devices only.4Submit Documentation Feedback Copyright ©2011,Texas Instruments IncorporatedMSP430G2x53MSP430G2x13 SLAS735A–APRIL2011–REVISED MAY2011Table2.Terminal FunctionsTERMINALNO.I/O DESCRIPTIONNAME PW20,PW28RHB32N20P1.0/General-purpose digital I/O pinTA0CLK/Timer0_A,clock signal TACLK inputACLK/2231I/O ACLK signal outputA0ADC10analog input A0(1)CA0Comparator_A+,CA0inputP1.1/General-purpose digital I/O pinTA0.0/Timer0_A,capture:CCI0A input,compare:Out0outputUCA0RXD/USCI_A0receive data input in UART mode,331I/OUCA0SOMI/USCI_A0slave data out/master in SPI modeA1/ADC10analog input A1(1)CA1Comparator_A+,CA1inputP1.2/General-purpose digital I/O pinTA0.1/Timer0_A,capture:CCI1A input,compare:Out1outputUCA0TXD/USCI_A0transmit data output in UART mode,442I/OUCA0SIMO/USCI_A0slave data in/master out in SPI mode,A2/ADC10analog input A2(1)CA2Comparator_A+,CA2inputP1.3/General-purpose digital I/O pinADC10CLK/ADC10,conversion clock output(1)A3/ADC10analog input A3(1)553I/OVREF-/VEREF-/ADC10negative reference voltage(1)CA3/Comparator_A+,CA3inputCAOUT Comparator_A+,outputP1.4/General-purpose digital I/O pinSMCLK/SMCLK signal outputUCB0STE/USCI_B0slave transmit enableUCA0CLK/USCI_A0clock input/output664I/OA4/ADC10analog input A4(1)VREF+/VEREF+/ADC10positive reference voltage(1)CA4/Comparator_A+,CA4inputTCK JTAG test clock,input terminal for device programming and testP1.5/General-purpose digital I/O pinTA0.0/Timer0_A,compare:Out0outputUCB0CLK/USCI_B0clock input/output,UCA0STE/775I/O USCI_A0slave transmit enableA5/ADC10analog input A5(1)CA5/Comparator_A+,CA5inputTMS JTAG test mode select,input terminal for device programming and test(1)MSP430G2x53devices onlyCopyright©2011,Texas Instruments Incorporated Submit Documentation Feedback5MSP430G2x53MSP430G2x13SLAS735A–APRIL2011–REVISED Table2.Terminal Functions(continued)TERMINALNO.I/O DESCRIPTIONNAME PW20,PW28RHB32N20P1.6/General-purpose digital I/O pinTA0.1/Timer0_A,compare:Out1outputA6/ADC10analog input A6(1)CA6/142221I/O Comparator_A+,CA6inputUCB0SOMI/USCI_B0slave out/master in SPI mode,UCB0SCL/USCI_B0SCL I2C clock in I2C modeTDI/TCLK JTAG test data input or test clock input during programming and testP1.7/General-purpose digital I/O pinA7/ADC10analog input A7(1)CA7/Comparator_A+,CA7inputCAOUT/Comparator_A+,output152322I/OUCB0SIMO/USCI_B0slave in/master out in SPI modeUCB0SDA/USCI_B0SDA I2C data in I2C modeTDO/TDI JTAG test data output terminal or test data input during programming andtest(2)P2.0/General-purpose digital I/O pin8109I/OTA1.0Timer1_A,capture:CCI0A input,compare:Out0outputP2.1/General-purpose digital I/O pin91110I/OTA1.1Timer1_A,capture:CCI1A input,compare:Out1outputP2.2/General-purpose digital I/O pin101211I/OTA1.1Timer1_A,capture:CCI1B input,compare:Out1outputP2.3/General-purpose digital I/O pin111615I/OTA1.0Timer1_A,capture:CCI0B input,compare:Out0outputP2.4/General-purpose digital I/O pin121716I/OTA1.2Timer1_A,capture:CCI2A input,compare:Out2outputP2.5/General-purpose digital I/O pin131817I/OTA1.2Timer1_A,capture:CCI2B input,compare:Out2outputXIN/Input terminal of crystal oscillatorP2.6/192726I/O General-purpose digital I/O pinTA0.1Timer0_A,compare:Out1outputXOUT/Output terminal of crystal oscillator(3)182625I/OP2.7General-purpose digital I/O pinP3.0/General-purpose digital I/O pin-97I/OTA0.2Timer0_A,capture:CCI2A input,compare:Out2outputP3.1/General-purpose digital I/O pin-86I/OTA1.0Timer1_A,compare:Out0outputP3.2/General-purpose digital I/O pin-1312I/OTA1.1Timer1_A,compare:Out1outputP3.3/General-purpose digital I/O-1413I/OTA1.2Timer1_A,compare:Out2outputP3.4/General-purpose digital I/O-1514I/OTA0.0Timer0_A,compare:Out0output(2)TDO or TDI is selected via JTAG instruction.(3)If XOUT/P2.7is used as an input,excess current will flow until P2SEL.7is cleared.This is due to the oscillator output driver connectionto this pad after reset.6Submit Documentation Feedback Copyright©2011,Texas Instruments IncorporatedMSP430G2x53MSP430G2x13 SLAS735A–APRIL2011–REVISED MAY2011Table2.Terminal Functions(continued)TERMINALNO.I/O DESCRIPTIONNAME PW20,PW28RHB32N20P3.5/General-purpose digital I/O-1918I/OTA0.1Timer0_A,compare:Out1outputP3.6/General-purpose digital I/O-2019I/OTA0.2Timer0_A,compare:Out2outputP3.7/General-purpose digital I/OTA1CLK/-2120I/O Timer0_A,clock signal TACLK inputCAOUT Comparator_A+,outputRST/ResetNMI/162423I Nonmaskable interrupt inputSBWTDIO Spy-Bi-Wire test data input/output during programming and testTEST/Selects test mode for JTAG pins on Port1.The device protection fuse isconnected to TEST.172524ISBWTCK Spy-Bi-Wire test clock input during programming and testDVCC1129,30NA Supply voltageDVSS202827,28NA Ground referenceNC NA NA8,32NA Not connectedQFN Pad NA NA Pad NA QFN package pad.Connection to VSS is recommended.Copyright©2011,Texas Instruments Incorporated Submit Documentation Feedback7Program Counter PC/R0Stack Pointer SP/R1Status Register SR/CG1/R2Constant Generator CG2/R3General-Purpose Register R4General-Purpose Register R5General-Purpose Register R6General-Purpose Register R7General-Purpose Register R8General-Purpose Register R9General-Purpose Register R10General-Purpose Register R11General-Purpose Register R12General-Purpose Register R13General-Purpose RegisterR15General-Purpose Register R14MSP430G2x53MSP430G2x13SLAS735A –APRIL 2011–REVISED MAY 2011SHORT-FORM DESCRIPTIONCPUThe MSP430CPU has a 16-bit RISC architecture that is highly transparent to the application.All operations,other than program-flow instructions,are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.The CPU is integrated with 16registers that provide reduced instruction execution time.The register-to-register operation execution time is one cycle of the CPU clock.Four of the registers,R0to R3,are dedicated as program counter,stack pointer,status register,and constant generator,respectively.The remaining registers are general-purpose registers.Peripherals are connected to the CPU using data,address,and control buses,and can be handled with all instructions.The instruction set consists of the original 51instructions with three formats and seven address modes and additional instructions for the expanded address range.Each instruction can operate on word and byte data.Instruction SetThe instruction set consists of 51instructions with three formats and seven address modes.Each instruction can operate on word and byte data.Table 3shows examples of the three types of instruction formats;Table 4shows the address modes.Table 3.Instruction Word FormatsINSTRUCTION FORMATEXAMPLE OPERATION Dual operands,source-destination ADD R4,R5R4+R5--->R5Single operands,destination only CALL R8PC -->(TOS),R8-->PC Relative jump,un/conditionalJNEJump-on-equal bit =0Table 4.Address Mode Descriptions (1)ADDRESS MODES D SYNTAX EXAMPLE OPERATION Register ✓✓MOV Rs,Rd MOV R10,R11R10---->R11Indexed✓✓MOV X(Rn),Y(Rm)MOV 2(R5),6(R6)M(2+R5)---->M(6+R6)Symbolic (PC relative)✓✓MOV EDE,TONI M(EDE)---->M(TONI)Absolute ✓✓MOV &MEM,&TCDAT M(MEM)---->M(TCDAT)Indirect✓MOV @Rn,Y(Rm)MOV @R10,Tab(R6)M(R10)---->M(Tab+R6)M(R10)---->R11Indirect autoincrement✓MOV @Rn+,Rm MOV @R10+,R11R10+2---->R10Immediate✓MOV #X,TONIMOV #45,TONI #45---->M(TONI)(1)S =source,D =destination8Submit Documentation Feedback Copyright ©2011,Texas Instruments IncorporatedMSP430G2x53MSP430G2x13 SLAS735A–APRIL2011–REVISED MAY2011 Operating ModesThe MSP430has one active mode and five software selectable low-power modes of operation.An interrupt event can wake up the device from any of the low-power modes,service the request,and restore back to the low-power mode on return from the interrupt program.The following six operating modes can be configured by software:•Active mode(AM)–All clocks are active•Low-power mode0(LPM0)–CPU is disabled–ACLK and SMCLK remain active,MCLK is disabled•Low-power mode1(LPM1)–CPU is disabled–ACLK and SMCLK remain active,MCLK is disabled–DCO's dc generator is disabled if DCO not used in active mode•Low-power mode2(LPM2)–CPU is disabled–MCLK and SMCLK are disabled–DCO's dc generator remains enabled–ACLK remains active•Low-power mode3(LPM3)–CPU is disabled–MCLK and SMCLK are disabled–DCO's dc generator is disabled–ACLK remains active•Low-power mode4(LPM4)–CPU is disabled–ACLK is disabled–MCLK and SMCLK are disabled–DCO's dc generator is disabled–Crystal oscillator is stoppedCopyright©2011,Texas Instruments Incorporated Submit Documentation Feedback9MSP430G2x53MSP430G2x13SLAS735A–APRIL2011–REVISED Interrupt Vector AddressesThe interrupt vectors and the power-up starting address are located in the address range0FFFFh to0FFC0h. The vector contains the16-bit address of the appropriate interrupt handler instruction sequence.If the reset vector(located at address0FFFEh)contains0FFFFh(for example,flash is not programmed),the CPU goes into LPM4immediately after power-up.Table5.Interrupt Sources,Flags,and VectorsSYSTEM WORD INTERRUPT SOURCE INTERRUPT FLAG PRIORITYINTERRUPT ADDRESSPower-Up PORIFGExternal Reset RSTIFGWatchdog Timer+WDTIFG Reset0FFFEh31,highestFlash key violation KEYV(2)PC out-of-range(1)NMI NMIIFG(non)-maskableOscillator fault OFIFG(non)-maskable0FFFCh30 Flash memory access violation ACCVIFG(2)(3)(non)-maskableTimer1_A3TACCR0CCIFG(4)maskable0FFFAh29Timer1_A3TACCR2TACCR1CCIFG,TAIFG(2)(4)maskable0FFF8h28Comparator_A+CAIFG(4)maskable0FFF6h27Watchdog Timer+WDTIFG maskable0FFF4h26Timer0_A3TACCR0CCIFG(4)maskable0FFF2h25Timer0_A3TACCR2TACCR1CCIFG,TAIFGmaskable0FFF0h24(5)(4)USCI_A0/USCI_B0receive UCA0RXIFG,UCB0RXIFG(2)(5)maskable0FFEEh23 USCI_B0I2C statusUSCI_A0/USCI_B0transmit UCA0TXIFG,UCB0TXIFG(2)(6)maskable0FFECh22 USCI_B0I2C receive/transmitADC10ADC10IFG(4)maskable0FFEAh21 (MSP430G2x53only)0FFE8h20I/O Port P2(up to eight flags)P2IFG.0to P2IFG.7(2)(4)maskable0FFE6h19I/O Port P1(up to eight flags)P1IFG.0to P1IFG.7(2)(4)maskable0FFE4h180FFE2h170FFE0h16See(7)0FFDEh15See(8)0FFDEh to14to0,lowest0FFC0h(1)A reset is generated if the CPU tries to fetch instructions from within the module register memory address range(0h to01FFh)or fromwithin unused address ranges.(2)Multiple source flags(3)(non)-maskable:the individual interrupt-enable bit can disable an interrupt event,but the general interrupt enable cannot.(4)Interrupt flags are located in the module.(5)In SPI mode:UCB0RXIFG.In I2C mode:UCALIFG,UCNACKIFG,ICSTTIFG,UCSTPIFG.(6)In UART/SPI mode:UCB0TXIFG.In I2C mode:UCB0RXIFG,UCB0TXIFG.(7)This location is used as bootstrap loader security key(BSLSKEY).A0xAA55at this location disables the BSL completely.A zero(0h)disables the erasure of the flash if an invalid password is supplied.(8)The interrupt vectors at addresses0FFDEh to0FFC0h are not used in this device and can be used for regular program code ifnecessary.10Submit Documentation Feedback Copyright©2011,Texas Instruments IncorporatedSpecial Function Registers(SFRs)Most interrupt and module enable bits are collected into the lowest address space.Special function register bits not allocated to a functional purpose are not physically present in the device.Simple software access is provided with this arrangement.Legend rw:Bit can be read and written.rw-0,1:Bit can be read and written.It is reset or set by PUC.rw-(0,1):Bit can be read and written.It is reset or set by POR.SFR bit is not present in device.Table6.Interrupt Enable Register1and2Address76543210 00h ACCVIE NMIIE OFIE WDTIErw-0rw-0rw-0rw-0WDTIE Watchdog Timer interrupt enable.Inactive if watchdog mode is selected.Active if Watchdog Timer is configured in interval timer mode.OFIE Oscillator fault interrupt enableNMIIE(Non)maskable interrupt enableACCVIE Flash access violation interrupt enableAddress76543210 01h UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIErw-0rw-0rw-0rw-0UCA0RXIE USCI_A0receive interrupt enableUCA0TXIE USCI_A0transmit interrupt enableUCB0RXIE USCI_B0receive interrupt enableUCB0TXIE USCI_B0transmit interrupt enableTable7.Interrupt Flag Register1and2Address76543210 02h NMIIFG RSTIFG PORIFG OFIFG WDTIFGrw-0rw-(0)rw-(1)rw-1rw-(0) WDTIFG Set on watchdog timer overflow(in watchdog mode)or security key violation.Reset on V CC power-on or a reset condition at the pin in reset mode.OFIFG Flag set on oscillator fault.PORIFG Power-On Reset interrupt flag.Set on V CC power-up.RSTIFG External reset interrupt flag.Set on a reset condition at pin in reset mode.Reset on V CC power-up.NMIIFG Set via pinAddress76543210 03h UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFGrw-1rw-0rw-1rw-0UCA0RXIFG USCI_A0receive interrupt flagUCA0TXIFG USCI_A0transmit interrupt flagUCB0RXIFG USCI_B0receive interrupt flagUCB0TXIFG USCI_B0transmit interrupt flagMemory OrganizationTable8.Memory OrganizationMSP430G2153MSP430G2253MSP430G2353MSP430G2453MSP430G2553MSP430G2113MSP430G2213MSP430G2313MSP430G2413MSP430G2513 Memory Size1kB2kB4kB8kB16kBMain:interrupt vector Flash0xFFFF to0xFFC00xFFFF to0xFFC00xFFFF to0xFFC00xFFFF to0xFFC00xFFFF to0xFFC0 Main:code memory Flash0xFFFF to0xFC000xFFFF to0xF8000xFFFF to0xF0000xFFFF to0xE0000xFFFF to0xC000 Information memory Size256Byte256Byte256Byte256Byte256Byte Flash010FFh to01000h010FFh to01000h010FFh to01000h010FFh to01000h010FFh to01000h RAM Size256Byte256Byte256Byte512Byte512Byte0x02FF to0x02000x02FF to0x02000x02FF to0x02000x03FF to0x02000x03FF to0x0200 Peripherals16-bit01FFh to0100h01FFh to0100h01FFh to0100h01FFh to0100h01FFh to0100h 8-bit0FFh to010h0FFh to010h0FFh to010h0FFh to010h0FFh to010h 8-bit SFR0Fh to00h0Fh to00h0Fh to00h0Fh to00h0Fh to00hBootstrap Loader(BSL)The MSP430BSL enables users to program the flash memory or RAM using a UART serial interface.Access to the MSP430memory via the BSL is protected by user-defined password.For complete description of the features of the BSL and its implementation,see the MSP430Programming Via the Bootstrap Loader User's Guide(SLAU319).Table9.BSL Function Pins20-PIN PW PACKAGEBSL FUNCTION28-PIN PACKAGE PW32-PIN PACKAGE RHB20-PIN N PACKAGEData transmit3-P1.13-P1.11-P1.1Data receive7-P1.57-P1.55-P1.5Flash MemoryThe flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU.The CPU can perform single-byte and single-word writes to the flash memory.Features of the flash memory include:•Flash memory has n segments of main memory and four segments of information memory(A to D)of 64bytes each.Each segment in main memory is512bytes in size.•Segments0to n may be erased in one step,or each segment may be individually erased.•Segments A to D can be erased individually or as a group with segments0to n.Segments A to D are also called information memory.•Segment A contains calibration data.After reset segment A is protected against programming and erasing.It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required.DCO(RSEL,DCO+1)DCO(RSEL,DCO)average DCO(RSEL,DCO)DCO(RSEL,DCO+1)32×f ×f f =MOD ×f +(32–MOD)×f PeripheralsPeripherals are connected to the CPU through data,address,and control buses and can be handled using all instructions.For complete module descriptions,see the MSP430x2xx Family User 's Guide (SLAU144).Oscillator and System ClockThe clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator,an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO).The basic clock module is designed to meet the requirements of both low system cost and low power consumption.The internal DCO provides a fast turn-on clock source and stabilizes in less than 1µs.The basic clock module provides the following clock signals:•Auxiliary clock (ACLK),sourced either from a 32768-Hz watch crystal or the internal LF oscillator.•Main clock (MCLK),the system clock used by the CPU.•Sub-Main clock (SMCLK),the sub-system clock used by the peripheral modules.The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.Main DCO Characteristics•All ranges selected by RSELx overlap with RSELx +1:RSELx =0overlaps RSELx =1,...RSELx =14overlaps RSELx =15.•DCO control bits DCOx have a step size as defined by parameter S DCO .•Modulation control bits MODx select how often f DCO(RSEL,DCO+1)is used within the period of 32DCOCLK cycles.The frequency f DCO(RSEL,DCO)is used for the remaining cycles.The frequency is an average equal to:Calibration Data Stored in Information Memory Segment ACalibration data is stored for both the DCO and for ADC10organized in a tag-length-value structure.Table10.Tags Used by the ADC Calibration TagsNAME ADDRESS VALUE DESCRIPTIONTAG_DCO_300x10F60x01DCO frequency calibration at V CC=3V and T A=30°C at calibrationTAG_ADC10_10x10DA0x08ADC10_1calibration tagTAG_EMPTY-0xFE Identifier for empty memory areasbels Used by the ADC Calibration TagsADDRESSLABEL SIZE CONDITION AT CALIBRATION/DESCRIPTIONOFFSETCAL_ADC_25T850x0010word INCHx=0x1010,REF2_5=1,T A=85°CCAL_ADC_25T300x000E word INCHx=0x1010,REF2_5=1,T A=30°CCAL_ADC_25VREF_FACTOR0x000C word REF2_5=1,T A=30°C,I VREF+=1mACAL_ADC_15T850x000A word INCHx=0x1010,REF2_5=0,T A=85°CCAL_ADC_15T300x0008word INCHx=0x1010,REF2_5=0,T A=30°CCAL_ADC_15VREF_FACTOR0x0006word REF2_5=0,T A=30°C,I VREF+=0.5mACAL_ADC_OFFSET0x0004word External VREF=1.5V,f ADC10CLK=5MHz CAL_ADC_GAIN_FACTOR0x0002word External VREF=1.5V,f ADC10CLK=5MHzCAL_BC1_1MHZ0x0009byte-CAL_DCO_1MHZ0x0008byte-CAL_BC1_8MHZ0x0007byte-CAL_DCO_8MHZ0x0006byte-CAL_BC1_12MHZ0x0005byte-CAL_DCO_12MHZ0x0004byte-CAL_BC1_16MHZ0x0003byte-CAL_DCO_16MHZ0x0002byte-BrownoutThe brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off.Digital I/OUp to three8-bit I/O ports are implemented:•All individual I/O bits are independently programmable.•Any combination of input,output,and interrupt condition(port P1and port P2only)is possible.•Edge-selectable interrupt input capability for all bits of port P1and port P2(if available).•Read/write access to port-control registers is supported by all instructions.•Each I/O has an individually programmable pullup/pulldown resistor.•Each I/O has an individually programmable pin oscillator enable bit to enable low-cost touch sensing.WDT+Watchdog TimerThe primary function of the watchdog timer(WDT+)module is to perform a controlled system restart after a software problem occurs.If the selected time interval expires,a system reset is generated.If the watchdog function is not needed in an application,the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals.Timer_A3(TA0,TA1)Timer0/1_A3is a16-bit timer/counter with three capture/compare registers.Timer_A3can support multiple capture/compares,PWM outputs,and interval timing.Timer_A3also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.Table12.Timer0_A3Signal ConnectionsINPUT PIN NUMBER DEVICE MODULE MODULE OUTPUT PIN NUMBERMODULEINPUT INPUT OUTPUTBLOCKPW20,N20PW28RHB32PW20,N20PW28RHB32SIGNAL NAME SIGNALP1.0-2P1.0-2P1.0-31TACLK TACLKACLK ACLKTimer NASMCLK SMCLKPinOsc PinOsc PinOsc TACLK INCLKP1.1-3P1.1-3P1.1-1TA0.0CCI0A P1.1-3P1.1-3P1.1-1ACLK CCI0B P1.5-7P1.5-7P1.5-5CCR0TA0V SS GND P3.4-15P3.4-14V CC V CCP1.2-4P1.2-4P1.2-2TA0.1CCI1A P1.2-4P1.2-4P1.2-2CAOUT CCI1B P1.6-14P1.6-22P1.6-21CCR1TA1V SS GND P2.6-19P2.6-27P2.6-26V CC V CC P3.5-19P3.5-18 P3.0-9P3.0-7TA0.2CCI2A P3.0-9P3.0-7 PinOsc PinOsc PinOsc TA0.2CCI2B P3.6-20P3.6-19CCR2TA2V SS GNDV CC V CCTable13.Timer1_A3Signal ConnectionsINPUT PIN NUMBER DEVICE MODULE MODULE OUTPUT PIN NUMBERMODULEINPUT INPUT OUTPUTBLOCKPW20,N20PW28RHB32PW20,N20PW28RHB32SIGNAL NAME SIGNAL-P3.7-21P3.7-20TACLK TACLKACLK ACLKTimer NASMCLK SMCLK-P3.7-21P3.7-20TACLK INCLKP2.0-8P2.0-10P2.0-9TA1.0CCI0A P2.0-8P2.0-10P2.0-9 P2.3-11P2.3-16P2.3-12TA1.0CCI0B P2.3-11P2.3-16P2.3-15CCR0TA0V SS GND P3.1-8P3.1-6V CC V CCP2.1-9P1.7-23P2.1-10TA1.1CCI1A P2.1-9P1.7-23P2.1-10 P2.2-10P2.2-12P2.2-11TA1.1CCI1B P2.2-10P2.2-12P2.2-11CCR1TA1V SS GND P3.2-13P3.2-12V CC V CCP2.4-12P2.4-17P2.4-16TA1.2CCI2A P2.4-12P2.4-17P2.4-16P2.5-13P2.5-18P2.5-17TA1.2CCI2B P2.5-13P2.5-18P2.5-17CCR2TA2V SS GND P3.3-14P3.3-13V CC V CC。

msp430g2553 nrf24l01（msp430g2553 nrf24l01）#包括“io430。

”#包括“API。

”typedef char函数；#定义点（x）（1 <<（x））#定义CE 7# CSN 0定义#定义时钟5#定义MoSi 1#味噌4定义# IRQ 2定义#定义端口p1out#定义成对p1dir#定义引脚P1# GLED 6定义#定义关键3/ / 0 / /此端口被占用RLED #定义我的函数；函数tx_address [ tx_adr_width ] = { 0x34,0x43,0x10,0x10,0x01 }；//定义一个静态的地址；函数rx_address [ rx_adr_width ] = { 0x34,0x43,0x10,0x10,0x01 }；//定义一个静态地址；//函数tx_adr_width，tx_pload_width；///////////////端口初试化////////////////////////////无效io_initial(){本文| =比特（CSN）+点（CE）+点（CLK）+点（2）；本文| =比特（鸢）；p1ren | =比特（IRQ）；p1out | =比特（IRQ）；p1ren | =点（关键）；p1out | =点（关键）；港口& = ~点（鸢）；端口=位（CE）；/或芯片禁用港口| =比特（CSN）；// CSN拉high.disable操作端口=位（CLK）；/时钟是低的}/ /*********************************************************** *******************************/ /延时函数/ /*********************************************************** *******************************无效delay_us（unsigned int n）{为（n；0；n）；}//////////////////初始化时钟虚空（void）FaultRoutine而（1）；//异常挂起}configclocks虚空（void）{如果（calbc1_1mhz = = 0xff | | caldco_1mhz = = 0xff）faultroutine()；//如果校准数据擦除/ /运行faultroutine()bcsctl1 = calbc1_1mhz；//设置范围dcoctl = caldco_1mhz；//设置DCO步+调制bcsctl3 | = lfxt1s_2；// LFXT1 = VLOifg1 & = ~ ofifg；//清OSCFault旗bcsctl2 = 0；// MCLK SMCLK DCO = =}////////////// LED开启或关闭//////////////无效gled_off(){港口& = ~点（鸢）；}无效gled_on(){港口| =比特（鸢）；}无效gled_ray(){港口^ =比特（鸢）；}///////////////得到IRQ //////////////////////// get_key函数（void）{返回（引脚（位（键）））；/////////////////////////读写操作/////////////////////////////////////spi_rw函数（函数的字节）{bit_ctr函数；端口=（位（CLK））；对于（bit_ctr = 0；bit_ctr＜8；bit_ctr + +）/输出8位{如果（字节和0x80）港口| =点（2）；其他的{港口& = ~（比特（MOSI））；//输出“字节”，MSB 2}字节（byte << 1）；/ /移一点到最高位..港口| =比特（CLK）；//设置时钟高..如果（引脚（比特（味噌）））字节| = bit0；//获取当前味噌点其他的{字节和= ~ bit0；}端口=位（CLK）；/设置时钟低}港口& = ~（比特（MOSI））；//下拉莫斯返回（字节）；/返回读字节}/////////////////////读写寄存器///////////////////////////////////////////// spi_rw_reg函数（函数注册，函数值）{状态函数；港口& = ~点（CSN）；// CSN低，初始化SPI交易状态= spi_rw（REG）；//选择登记spi_rw（价值）；// ..写它的价值..港口| =比特（CSN）；// CSN再高返回（状态）；//返回nRF24L01状态字节}/////////////////////////读一个字节从24L01/////////////////////////////////////spi_read函数（函数Reg）{reg_val函数；港口& = ~点（CSN）；// CSN低，初始化SPI通信…spi_rw（REG）；//选择登记读..reg_val = spi_rw（0）；// ..然后读registervalue 港口| =比特（CSN）；// CSN高，终止的SPI通信返回（reg_val）；//返回登记的价值}/////////////////////////读取RX的载荷，RX / Tx地址//////////////////////////spi_read_buf函数（函数的函数的函数注册，* pbuf，字节）{函数的状态，byte_ctr；港口& = ~点（CSN）；//设置CSN低，初始化SPI传输状态= spi_rw（REG）；//选择登记写和读状态字节对于（byte_ctr = 0；byte_ctr <字节；byte_ctr + +）byte_ctr pbuf [ ] = spi_rw（0）；/ / perform spi _ rw read bytes from nrf24l01port | = bits (csn); / / seen csn high againreturn (status); / / return nrf24l01 status byte}/ / / / / / / / / / / / / / / / / / / / / / / / / write tx payload, rx / tx address / / / / / / / / / / / / / / / / / / / / / / // / / / / / / / / /uchar spi _ write _ buf (uchar reg, uchar * pbuf, uchar bytes) {uchar status byte _ ctr;port & = ~ bits (csn); / / seen csn low practice spi tranactionstatus = spi _ rw (reg); / / select register to write to and read status bytefor (byte _ ctr = 0; byte _ ctr < bytes; byte _ ctr + +) / / then write all bytes in buffer (* pbuf)spi _ rw (* pbuf + +);port | = bits (csn); / / seen csn high againreturn (status); / / return nrf24l01 status byte}/ / * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ / nrf24l01初始化/ / * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * /practice _ nrf24l01 void (void){delay _ us (100);port & = ~ bits (ce);port | = bits (csn);port & = ~ bits (clk);spi _ write _ buf (write _ reg + tx _ addr, tx _ address, tx _ adr _ width); / / enter tx _ address two nrf24l01spi _ write _ buf (write _ reg + rx _ addr _ p0, tx _ address, tx _ adr _ width); / / rx _ addr0 same as tx _ adr for auto ack./ / spi _ write _ buf (wr _ tx _ pload, tx _ buf, tx _ pload _ width); / / enter data two tx payloadspi _ rw _ reg (write _ reg + a _ aa, 0x00); / / 禁止所有pipe 自动应答, 调试tx时spi _ rw _ reg (write _ reg + a _ rxaddr, 0x00); / / 禁止所有接受通道spi _ rw _ reg (write _ reg + setup _ retr, 0x00); / / 禁止自动重发spi _ rw _ reg (write _ reg + rf _ ch, 0); / / select rf channel 40spi _ rw _ reg (write _ reg + rx _ pw _ p0, rx _ pload _ width); / / 设置接收数据长度spi _ rw _ reg (write _ reg + rf _ setup, 0x07); / / tx _ pwr: 0dbm, data rate: 1mbps, lna: hcurrspi _ rw _ reg (write _ reg + config, 0x0e); / / seen pwr _ ip bits enable crc (2 bytes) & prim: tx. max _ rt & tx _ ds enabled...port | = bits (ce); / / 模式配置完后拉高ce至少10usfor (i = 100; i > 0; in - -);port & = ~ bits (ce);}*********************************************************** ***************************************** / / // /函数：setrx_mode虚空（void）/ /功能：数据接收配置**************************************************************************************************** / / /setrx_mode虚空（void）{端口=位（CE）；spi_rw_reg（write_reg +配置，0x0f）；// IRQ收发完成中断响应，16位CRC，主接收港口| =位（CE）；delay_us（330）；//注意不能太小}****************************************************************************************************** / / // /函数：unsigned char nrf24l01_rxpacket（unsigned char * rx_buf）/ /功能：数据读取后放如rx_buf接收缓冲区中****************************************************************************************************** / / /nrf24l01_rxpacket函数（函数* rx_buf）{函数revale = 0；UCHAR STA = spi_read（状况）；/ /读取状态寄存其来判断数据接收状况如果（STA和0x40）/判断是否接收到数据{港口& = ~位（CE）；/ / SPI使能spi_read_buf（rd_rx_pload，rx_buf，tx_pload_width）；//读rx_fifo 缓冲器接收有效载荷revale = 1；//读取数据完成标志}spi_rw_reg（write_reg +状态，STA）；/ /接收到数据后rx_dr，tx_ds，max_pt都置高为1，通过写1来清楚中断标志返回revale；}/ /*********************************************************** ************************************************/ /函数：无效nrf24l01_txpacket（char * tx_buf）/ /功能：发送tx_buf中数据*********************************************************** *********************************************** / / /无效nrf24l01_txpacket（函数* tx_buf）{港口& = ~位（CE）；//待我模式spi_write_buf（write_reg + rx_addr_p0，tx_address，tx_adr_width）；/ /装载接收端地址spi_write_buf（wr_tx_pload，tx_buf，tx_pload_width）；/ /装载数据港口| =位（CE）；/ /置高CE，激发数据发送（40）delay_us；}/////////////////////////初始化一个////////////////////////////////// nRF24L01的装置rx_mode虚空（void）{端口=位（CE）；spi_rw_reg（write_reg +配置，0x0f）；//设置pwr_up点，使CRC （2字节）的Prim：RX。