PRICE LIST TST&STAUBLI COMPARE

price list中文翻译
price list中文翻译：价格清单。

常见释义
[词典] 价格清单;
[例句]We are seeking portland cement please sent price list.
我们正寻求波特兰水泥，请寄来价格清单。

名词price list:
a listing of prices for different goods or services
例句：
The price list wakened Mom from her dreams of owning a house in the suburb. 报价单使母亲意识到不可能在郊区买房子了。

In reply to your inquiry, we have sent you our latest price list.
为答复你方的询价，我们寄去了最新的价格单。

The company reissued its catalogue with a new price list.
这个公司重新发行了带有新价格表的商品目录。

Airmail revised price list but full range sample within fortnight.
航空寄上订正价格表，全套样品两周内寄出。

报关单练习1 根据以下所列资料填制出口货物报关单一份。

深圳市电子进出口有限公司与SUNLIT TRADE GMBH PEUTESTRASSE 6A-75589，HAMBURG,GERMANY所签第SSAB01-0032合同项下商品情况如下:CAR SPEAKER PY-1009A 6720 PAIRS 560CTNS USD3.30/PAIRPY-6960A 1705 PAIRS 341CTNS USD17.10/PAIR__________________________TOTAL USD51331.502004年11月28日，深圳市电子进出口有限公司收到了一份STATE BANK OF GERMANY，HAMBURG，GERMANY于2004年11月26日开来的信用证，购买汽车喇叭,信用证号码为GSN118488LY,金额为USD51331.50，CIF BREMEN条件，该公司立即与深圳市翔达电声器材厂联系，并签了合同EL2001-321，商品的有关情况如下：汽车喇叭 PY-1009A 6720对 RMB25.00/对 RMB168,000.00PY-6960A 1705对 RMB136.00/对 RMB231,880.00__________________________TOTAL RMB 399,880.00货备好后，深圳市电子进出口有限公司于2004年12月9日向深圳蛇口海关申报出口，将货装上了船名为深圳海，航次661的海轮运送出海，B/L NO.：SSAB01-001，NW：5.065MT，GW：5.966MT，唛头N/M，2×20’FCL：SZWY7891012/7891013，核销单编号：448899662，海关计量单位：对/个，运费为USD3000.00，保费率为0.69%。

商品编码为8518.2100。

练习2 根据下列资料，填制出口货物报关单一份1) THE SELLER: DALIAN HAITIAN GARMENT CO.,LTD.中韩合资大连海天服装有限公司（2115930064）2) THE BUYER: WAN DO APPAREL CO.LTD, 550-17, YANGCHUN-GU, SEOUL, KOREA3) PORT OF LOADING: DALIAN CHINA, FINAL DESTINATION: INCHON KOREA, CARRIER:DAIN/431E4) TERMS OF PAYMENT: DOCUMENTS AGAINST ACCEPTANCE5) NO.S OF PACKAGES DESCRIPTION QTY/UNIT UNIT PRICE AMOUNTFOB DALIAN CHINA260CTNS LADY’S JUMPER 1,300PCS @$11.00 USD14,300.00MAN’S JUMPER 1,300PCS @$11.00 USD14,300.00 TOTAL:USD28,600.006) B/L NO.: DAINE 431227, INVOICE NO.: HT01A087) NW: 2600KGS, GW: 3380KGS, 1×40’CONTAINER NO.: EASU9608490.8) 该公司在来料加工合同9911113项下出口男、女羽绒短上衣，分列手册（编号B09009301018）第2、3项，外汇核销单编号：215157263，计量单位：件/千克。

NiceLabel 2017 Segmentation, Positioning and PricingKen Moir –VP MarketingMiso Duplancic –Product Management Team Leader 28.6.2016Introducing Next Generation TechnologyAgenda 33•Design & Print•Design & Controlled Print•Managed Design & Controlled Print Positioning & Pricing2Segmentation & Progression 1Product & Licensing RestructureProduct & Licensing RestructureIntroducing NiceLabel 2017Why?•Introduce next generation technology•100% new designers, application builder, desktop print and web printing •Promote best practices and print productivity•Simplification•Products•PricingLicensing RestructurePrinter based licensing (variable pricing):•Simplicity•Promotes best practices and print productivity •Continuous revenue and upsell opportunity •FairPrinter as a “seat”:•Works for all modules•Industry standardSegmentation & ProgressionPositioning & PricingPositioning:DesignersWho is it for?Small or medium sized businesses with few users, few label variations or low volume printing requirementsDesigner ExpressDesigner ProUsers (seats) 1 user1 user, 3,5,10 printer seats Databases or File External data: MS Excel & Text files.All capabilities including MS Access, SQL Server and Oracle Dynamic Data (Variables)Basic counter / Basic variables / No functions All counters & serialization / All variables / All functions Dynamic ObjectsNoneVariable graphics,relative positioning, fit-to-boxOperator Printing Form All-in-one fixed form All-in-one adaptable formWhat need does it solve?Design and print professional labels without IT helpPricing: Designers -$ / €Product Number of users /Number of printers List priceworkstationsDesigner Express1unlimited295 Designer Pro1unlimited595 Designer Pro 3unlimited3895 Designer Pro 5unlimited5 1.395 Designer Pro 10*unlimited10 2.195 Designer Pro 5 Add-On unlimited5 1.095* = Call for more users –but you should be using LMS and web printing!The product we recommend in this segmentPositioning:Desktop SolutionsPowerFormsPowerForms SuiteUsers (seats) 1 user 3,5,10 printer seats Application builder PowerForms PowerFormsIntegrationNoneAutomation Easy & .NET SDKWhat need does it solve?Streamline printing to control labor costs, eliminate errors & improve productivityWho is it for?Small or medium sized businesses where:Operators print labels, accuracy is critical and productivity is importantNo need to adhere to quality management system (QMS) or regulatory requirementsPricing: Desktop Solutions* = Call for more printers –but you should be using LMS and web printing!The product we recommend in this segmentProductNumber of users / workstationsNumber of printersList pricePowerForms 1unlimited995PowerForms Suite 3unlimited31.295PowerForms Suite 5unlimited 5 1.995PowerForms Suite 10*unlimited 10 2.995PowerForms Suite 5 Add-Onunlimited51.495Positioning: LMSSKULMS ProLMS EnterpriseIntegration Automation Pro Automation Enterprise Web PrintingPowerForms Web PowerForms Web Document ManagementControl Center ProControl Center EnterpriseWhat need does it solve?Standardize your entire labeling process to meet quality control or regulatory requirements and improve efficiencyWho is it for? 5 to 5 thousand users SME to enterprise with QMS or Regulatory requirements (ISO 9001, EU or FDA GMPs)More LMS Detail•Who is it for?•Medium sized business & enterprise with QMS or Regulatory requirements such as ISO 9001, EU GMPs or FDA GMPs.•What need does it solve?•Standardize your entire labeling process to meet quality control or regulatory requirements and improve efficiencySKU LMS Pro LMS EnterpriseIntegrationAutomation Pro •Multi-core processing •HTTP trigger & action (REST)•Advanced XML filter•Central printer setting•Execute SQL (CRUD)•Bi-directional feedback •Store and recall templatesAutomation Enterprise plus:•SAP ABAP package•Failover & load balancing•Web services•PDF and previews•Advanced workflows & error handling Web Printing PowerForms Web•Centralized control •Infinitely scalable•Integrate with web apps.•Self service printer setup PowerForms Web•SameDocument Management Control Center Pro•Role based access control •Central document storage •Device management & alerts Control Center Enterprise plus:•Version control •Approval workflows•Quality Assurance ToolsPricing: LMS -$ / €Product# of users /workstations# of printers List Price LMS Pro 5unlimited5 3.495 LMS Pro 10unlimited10 5.995 LMS Pro 20*unlimited209.995 LMS Enterprise 5unlimited57.495 LMS Enterprise 10unlimited1012.995 LMS Enterprise 20*unlimited2021.995 LMS Enterprise 50**unlimited5043.995 LMS Enterprise 100**unlimited10065.995* = Call for more printers** = Full price list productSummaryBefore SimplificationDesigner Express DesignerStandard Designer ProDesigner ProPrint-OnlyPowerForms Desktop PowerFormsRuntimePowerFormsMulti-User3x AutomationEasy3x AutomationBundle Desktop SuiteDesktop SuiteRuntimeDesktop SuiteMulti-User3x AutomationPro AutomationEnterpriseControl CenterProControl CenterEnterprisePowerFormsWebSynchronizationAdd-On After SimplificationQ & A21。

亚马逊 MWS 配送出库货件 API 部分参考（2010 年 10 月 1 日版）内容亚马逊 MWS 配送出库货件 API 部分参考（2010 年 10 月 1 日版） (4)您应了解的“配送出库货件 API”部分的相关内容 (5)GetFulfillmentPreview (6)描述 (6)请求参数 (6)响应元素 (7)示例 (7)相关主题 (10)CreateFulfillmentOrder (11)描述 (11)请求参数 (11)响应元素 (12)示例 (12)相关主题 (14)GetFulfillmentOrder (15)描述 (15)请求参数 (15)响应元素 (15)示例 (15)相关主题 (18)ListAllFulfillmentOrders (19)描述 (19)请求参数 (19)响应元素 (19)示例 (19)相关主题 (21)ListAllFulfillmentOrdersByNextToken (22)描述 (22)请求参数 (22)响应元素 (22)示例 (22)相关主题 (24)GetPackageTrackingDetails (25)描述 (25)请求参数 (25)响应元素 (25)示例 (26)相关主题 (28)CancelFulfillmentOrder (29)描述 (29)请求参数 (29)响应元素 (29)示例 (29)相关主题 (30)GetServiceStatus (31)描述 (31)请求参数 (31)响应元素 (31)示例 (31)相关主题 (32)出库数据类型 (33)Address (33)CODSettings (34)CreateFulfillmentOrderItem (36)Currency (37)Fee (37)FulfillmentOrder (38)FulfillmentOrderItem (41)FulfillmentPreview (42)FulfillmentPreviewItem (43)FulfillmentPreviewShipment (44)FulfillmentShipment (45)FulfillmentShipmentItem (46)FulfillmentShipmentPackage (47)GetFulfillmentPreviewItem (48)TrackingAddress (48)TrackingEvent (49)UnfulfillablePreviewItem (50)Weight (51)客户端库更新 (52)亚马逊 MWS 配送出库货件 API 部分参考（2010 年 10 月 1 日版）版权 2011-2014 , Inc. or its affiliates。

Instance Type and TransmissionOriginal received from SWIFTPriority: NormalMessage output Reference: 1656 150707RZBASGSGAXXX5520068255 Correspondent Input Reference: 1656 150707HSBCHKHHGHKH0321891433 Message HeaderSwift Output: FIN 700 Issue of a Documentary Credit（跟单信用证）发报行（开证行）：香港上海汇丰银行有限公司（各香港办事处及总部）收报银行（通知行）：奥地利奥合国际银行股份有限公司新加坡分行MUR：GHF58000HV2E（电报用户参考编号）Message Text（报文正文）27：Sequence of Total 电文页次1页1/140A：Form of Documentary Credit 跟单信用证形式IRREVOCABLE 不可撤销跟单信用证20：Documentary Credit Number 信用证号码YDCTST52051331C：Date of Issue 开证日15070740E：Applicable Rules 适用规则UCP LATEST VERSION 信用证统一惯例最新版本31D：Date and Place of Expiry 到期日期与地点150915SINGAPORE 15-09-15在新加坡到期50：Applicant 信用证开证申请人POSCO ASIA CO LTD 浦亚实业有限公司ROOM 5508 CENTRAL PLAZA 中环广场5508室18 HARBOUR ROAD 港湾道18号WANCHAI HONG KONG 香港湾仔59：Beneficiary-Name & Address 信用证的受益人-名称及地址BRIGHT RUBY RESOURCES PTE LIMITED163 PENANG ROAD 02-03 WINSLAND HOUSE 2SINGAPORE 23846332B：Currency Code, A mount 信用证结算的货币和金额Currency: USD 货币：美元Amount: #67.680,00# 金额：67.680,0039A：Percentage Credit Amt Tolerance 信用证金额上下浮动允许的最大范围10/10 上下浮动最大为10%41D：Available With…By…- Name & Address 指定的有关银行及信用证兑付的方式ANY HSBC GROUP OFFICE OR ANY BANKBY NEGOTIATION任何汇丰集团办事处或任何银行议付（有追索权）42C：Drafts at …汇票付款期限SIGHT FOR INVOICE V ALUE OF GOODS 即期，汇票金额为发票金额42D：Drawee - Name & Address 信用证汇票的付款人ISSUING BANK 开证行43P：Partial Shipments （分装条款）表示该信用证的货物是否可以分批装运ALLOWED 允许43T：Transshipment （转运条款）表示该信用证是直接到达，还是通过转运到达NOT ALLOWED 不允许44E：Port of Loading/Airport of Dep. 装运港或启运机场ANY PORT OF CHINA 中国的任何港口44F：Port of Discharge/Airport of Dest. 卸货港或目的机场HOCHIMINH CITY PORT, VIETNAM 越南胡志明市港口44C：Latest Date of Shipment （最后装船工期）装船的最迟的日期15-08-3145A：Description of Goods &/or Services （货物描述）货物的情况、价格条款CFR FO HOCHIMINH CITY PORT, VIETNAM卖家负担成本加运费，买方负担卸货费，越南胡志明市港口HOT ROLLED ALLOY STEEL 热轧合金钢GRADE: SS400-B IN ACCORDANCE WITH JIS G3101-2010材质：SS400-B，依照日标JIS G3101-2010BORON CONTENT: 0.0008 PERCENT MINIMUM硼含量：不低于0.0008%MANUFACTURER:RIZHAO STEEL WIRE CO., LTD制造商：日照钢铁棒线厂COUNTRY OF ORIGIN: CHINA原产地：中国UNIT PRICE: USD 376.00/MT单价：376.00美元/吨SIZE(MM) QUANTITY(MT)尺寸重量8.0mm×2000mm×C 60吨10.0mm×2000mm×C 60吨12.0mm×2000mm×C 60吨TOTAL: 180MT (+/- 10PCT TOLERANCE)总计：180吨（+/-10%溢短装）OTHER DETAILS AS PER CONTRACT NO.: BRR-150618V-231WJ其它细节参照编号为BRR-150618V-231WJ的合同46A：Documents Required （单据要求）各种单据的要求1、SIGNED COMMERCIAL INVOICE IN DUPLICATE1、已签署的商业发票一式两份2、FULL SET OF ORIGINAL OF CLEAN ON BOARD BILLS OF LADINGCONSIGNED TO POSCO VIETNAM PROCESSING CENTER CO.,LTD.ADD: ROAD N2, NHON TRACH V IDZ, DONG NAI, VIETNAMTEL: 84-61-3569-350，FAX：84-61-3569-3562、全套正本已装船清洁提单，收货人为浦项制铁越南加工中心有限公司地址：N2路，任泽V工业区，东奈，越南电话：84-61-3569-350，传真：84-61-3569-356注明运费已付并通知浦项制铁越南加工中心有限公司，地址：N2路，任泽V工业区，东奈，越南，电话：84-61-3569-350，传真：84-61-3569-3563、SIGNED PACKING LIST SHOWING QUANTITY/NET AND GROSSWEIGHT IN TWO ORIGINAL3、签署的装箱单在两个正本上都要显示重量/净重和毛重4、BENEFICIARY’S CERTIFICATE STATING THAT ORIGINALASEAN-CHINA FREE TRADE PREFERENTIAL TARIFFCERTIFICATE OF ORIGIN(FORM E) IN 1 ORIGINAL AND MILLTEST CERTIFICATE IN 1 ORIGINAL AND 1 COPY HA VE BEENSENT BY DHL EXPRESS DIRECTLY TO APPLICANT DIRECTLYWITHIN 7 WORKING DAYS AFTER SHIPMENT DATE.4、受益人出具证明：原中国东盟自由贸易区优惠关税1份正本原产地证（中国-东盟），1份正本质检书和1份复印件应该在装运期后7个工作日内由国际航空快递直接发给信用证开证申请人47A：Additional Conditions 特别条款+10 PERCENT MORE OR LESS IN TOTAL QUANTITY AND TOTALAMOUNT ARE ACCEPTABLE BUT NO RESTRCTION ON THETOLERANCE OF INDIVIDUAL SIZE+10%的总重量和总金额的浮动是可以接受的，但是没有限制单个产品的尺寸公差+CHARTER PARTY B/L ACCEPTABLE+租船提单可以接受UNLESS OTHERWISE STIPULATED, THIRD PARTY DOCUMENTSEXCEPT DRAFT(S) AND COMMERCIAL INVOICE(S) AREACCEPTABLE+除非另作说明，第三方单据除了汇票和商业发票以外是可以接受的+ UNLESS OTHERWISE DC STIPULATED, B/L MUST NOT SHOW UNIT PRICE, V ALUE OF GOOD,THIS DC NUMBER AND DATE, INVOICENUMBER AND DATE AND CONTRACT NO.+除非跟单信用证另作说明，提单不能显示单价，商品金额，本信用证号码和日期，发票号码和日期以及合同号+DOCUMENTS PRESENTED WITH MISSPELLING OR TYPINGERRORS THAT DO NOT AFFECT THE MEANING OF A WORD ORSENTENCE IN WHICH THEY OCCUR, DO NOT MAKE A DOCUMENTDISCREPANT, UNLESS SUCH ERRORS RELATE TO PRICE, QUANTITY, QUALITY, SIZE AND DELIVERY TERMS, AND SO AFFECT THEMEANING.+提交的单据有拼写或打字错误，不影响他们所在字词或句子的意思，则不构成文件不符点，除非这些错误与价格、数量、质量、尺寸和交货期有关，以至于影响条款意思+ALL CHARGES OUTSIDE HONG KONG ARE FOR ACCOUNT OF BENEFICIARY.+香港之外的所有费用由受益人承担+A HKD150.00 OR EQUIV ALENT WILL BE DEDUCTED FROM THE PROCEEDS FOR EACH PRESENTATION OF DOCUMENTS UNDER THIS DOCUMENTARY CREDIT WHICH ARE OF V ALUE LESS THAN USD10, 000.00 OR EQUIV ALENT+每次在该跟单信用证下的交单金额低于10000美金或者等值时，350港币或等值将被从收益中被扣除+NOTWITHSTANDING ANY INSTRUCTIONS TO THE CONTRARY, THESE CHARGES ARE FOR THE ACCOUNT OF BENEFICIARY除非有任何相反的指示，否则这些费用由受益人承担+A HKD 620 OR EQUIV ALENT PLUS ALL RELATIVE CABLE CHARGES WILL BE DEDUCTED FROM THE REIMBURSEMENT CLAIM FOR EACH PRESENTATION OF DISCREPANT DOCUMENTS UNDER THIS DOCUMENTARY CREDIT+每次在该跟单信用证下，620港币或等值加上所有相关的电报费用将从提交的不符点单据的索偿金额中扣除NOTWITHSTANDING ANY INSTRUCTIONS TO THE CONTRARY, THESE CHARGES SHALL BE FOR THE ACCOUNT OF BENEFICIARY 除非有任何相反的指示，否则这些费用由受益人承担+IF DC IS OVERDRAWN AND SUCH A DISCREPANCY IS ACCEPTED BY APPLICANT AND DC ISSUING BANK, DC OVERDRAWN COMMISSION AT 1/4 PCT (MIN. HKD500 OR EQUIV ALENT) ARE FOR ACCOUNT OF BENEFICIARY AND WILL BE DEDUCTED FROM THE PROCEEDS AT TIME OF REIMBURSEMENT.+如果跟单信用证超额，而这个不符点被申请人以及信用证开证行所接受，那么跟单信用证超额费费率1-4%（最低500港币或等值），将由受益人承担，其费用将在索偿时从收益中扣除。

英语专业高级英语2课后翻译1. However intricate the ways in which animals communicate with each other, they do not indulge in anything that deserves the same of conversation.无论动物之间的交流有多么复杂，它们都称不上聊天。

2. Argument may often be a part of it, but the purpose of the argument is not to convince. There is no wining in conversation.争吵可能经常是它的一部分，但争吵的目的并不是要说服他人。

聊天中没有输赢之分。

3. Perhaps it is because of my upbringing in English pubs that I think bar conversation has a charm of its own.或许是我自小常去英国酒吧的缘故，我认为酒吧聊天拥有自己独特的魅力4. I do not remember what made one of our companions say it —— she clearly had not come into the bar to say it, it was not sth. that was pressing on her mind —— but her remark fell quite naturally into the talk我不记得是什么使我们的一个伙伴提前了这个话题——她显然不是特意来酒吧说这件事的，那也不是什么她非说不可的事——但她十分自然的在聊天中说出了这句话5.There is always resistance in the lower classes to any attempt by an upper class to lay down rules for "English as it should be spoken ".每当上流社会想给“规范英语”制定一些规则时，总会遭到下层社会的抵制。

6117AS–ATARM–20-Oct-04Features•Incorporates the ARM7TDMI ® ARM ® Thumb ® Processor–High-performance 32-bit RISC Architecture –High-density 16-bit Instruction Set –Leader in MIPS/Watt–Embedded ICE In-circuit Emulation, Debug Communication Channel Support •256 Kbytes of Internal High-speed Flash, Organized in 1024 Pages of 256 Bytes –Single Cycle Access at Up to 30 MHz in Worst Case Conditions–Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed–Page Programming Time: 4 ms, Including Page Auto-erase, Full Erase Time: 10 ms –10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit–Fast Flash Programming Interface for High Volume Production•64 Kbytes of Internal High-speed SRAM, Single-cycle Access at Maximum Speed •Memory Controller (MC)–Embedded Flash Controller, Abort Status and Misalignment Detection •Reset Controller (RSTC)–Based on Power-on Reset and Low-power Factory-calibrated Brownout Detector –Provides External Reset Signal Shaping and Reset Source Status •Clock Generator (CKGR)–Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL •Power Management Controller (PMC)–Software Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode–Three Programmable External Clock Signals •Advanced Interrupt Controller (AIC)–Individually Maskable, Eight-level Priority, Vectored Interrupt Sources–Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected•Debug Unit (DBGU)–2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention •Periodic Interval Timer (PIT)–20-bit Programmable Counter plus 12-bit Interval Counter •Windowed Watchdog (WDT)–12-bit key-protected Programmable Counter–Provides Reset or Interrupt Signals to the System–Counter May Be Stopped While the Processor is in Debug State or in Idle Mode •Real-time Timer (RTT)–32-bit Free-running Counter with Alarm –Runs Off the Internal RC Oscillator•One Parallel Input/Output Controller (PIOA)–Thirty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os –Input Change Interrupt Capability on Each I/O Line–Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output •Eleven Peripheral Data Controller (PDC) Channels•One USB 2.0 Full Speed (12 Mbits per second) Device Port–On-chip Transceiver, 328-byte Configurable Integrated FIFOs •One Synchronous Serial Controller (SSC)–Independent Clock and Frame Sync Signals for Each Receiver and Transmitter –I²S Analog Interface Support, Time Division Multiplex Support–High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer •Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)–Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation–Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support –Full Modem Line Support on USART1•One Master/Slave Serial Peripheral Interface (SPI)–8- to 16-bit Programmable Data Length, Four External Peripheral Chip SelectsAT91 ARM ® Thumb ®-based Microcontrollers AT91SAM7S256Summary PreliminaryNote: This is a summary document. A complete document is not available at this time. For more information, please contact your local Atmel sales office.2AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04•One Three-channel 16-bit Timer/Counter (TC)–Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel –Double PWM Generation, Capture/Waveform Mode, Up/Down Capability •One Four-channel 16-bit PWM Controller (PWMC)•One Two-wire Interface (TWI)–Master Mode Support Only, All Two-wire Atmel EEPROMs Supported•One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os •IEEE 1149.1 JTAG Boundary Scan on All Digital Pins•5V-tolerant I/Os, including Four High-current Drive I/O lines, Up to 16 mA Each •Power Supplies–Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components –3.3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply –1.8V VDDCORE Core Power Supply with Brownout Detector•Fully Static Operation: Up to 55 MHz at 1.65V and 85°C Worst Case Conditions •Available in a 64-lead LQFP PackageDescriptionAtmel’s AT91SAM7S256 is a member of a series of low pincount Flash microcontrollers based on the 32-bit ARM RISC processor. It features a 256 Kbyte high-speed Flash and a 64 Kbyte SRAM, a large set of peripherals, including a USB 2.0 device, and a com-plete set of system functions minimizing the number of external components. The device is an ideal migration path for 8-bit microcontroller users looking for additional per-formance and extended memory.The embedded Flash memory can be programmed in-system via the JTAG-ICE inter-face or via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserves its confidentiality.The AT91SAM7S256 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator.The AT91SAM7S256 is a general-purpose microcontroller. Its integrated USB Device port makes it an ideal device for peripheral applications requiring connectivity to a PC or cellular phone. Its aggressive price point and high level of integration pushes its scope of use far into the cost-sensitive, high-volume consumer market.3AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Block DiagramFigure 1. AT91SAM7S256 Block DiagramTDI TDO TMS TCK NRSTFIQIRQ0-IRQ1PCK0-PCK2PMCPeripheral BridgePeripheral Data ControllerAICPLL RCOSCSRAM64 KbytesARM7TDMI ProcessorICEJT AG SCANJTAGSELPIOAUSART0SSCTimer CounterRXD0TXD0SCK0RTS0CTS0NPCS0NPCS1NPCS2NPCS3MISO MOSI SPCK Flash256 KbytesReset ControllerDRXD DTXDTF TK TD RD RK RF TCLK0TCLK1TCLK2TIOA0TIOB0TIOA1TIOB1TIOA2TIOB2Memory Controller Abort StatusAddress Decoder Misalignment DetectionP I OP I OAPBPOREmbedded Flash ControllerAD0AD1AD2AD3ADTRGPLLRC 11 ChannelsPDCPDC USART1RXD1TXD1SCK1RTS1CTS1DCD1DSR1DTR1RI1PDCPDC PDCPDC SPIPDCADCADVREFPDCPDCTC0TC1TC2TWD TWCKTWIOSC XIN XOUTVDDIN PWMCPWM0PWM1PWM2PWM31.8 V Voltage RegulatorUSB DeviceFIFODDM DDPT r a n s c e i v e rGNDVDDOUT BOD VDDCOREVDDCOREAD4AD5AD6AD7VDDFLASHFast Flash Programming InterfaceERASEP I OPGMD0-PGMD15PGMNCMDPGMEN0-PGMEN1PGMRDY PGMNVALID PGMNOE PGMCKPGMM0-PGMM3VDDIOTST DBGUPDCPDCP I OPIT WDT RTTSystem ControllerVDDCORE4AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Signal DescriptionTable 1. Signal Description ListSignal NameFunctionTypeActive LevelCommentsPowerVDDIN Voltage Regulator Power Supply Input Power 3.0V to 3.6V VDDOUT Voltage Regulator Output Power 1.85V nominal VDDFLASH Flash Power Supply Power 3.0V to 3.6V VDDIO I/O Lines Power Supply Power 3.0V to 3.6V VDDCORE Core Power Supply Power 1.65V to 1.95V VDDPLL PLL Power 1.65V to 1.95VGNDGroundGroundClocks, Oscillators and PLLsXIN Main Oscillator Input Input XOUT Main Oscillator Output Output PLLRC PLL FilterInput PCK0 - PCK2Programmable Clock OutputOutputICE and JTAGTCK Test Clock Input No pull-up resistor TDI Test Data In Input No pull-up resistor TDO Test Data Out Output TMS Test Mode Select Input No pull-up resistor JT AGSELJTAG SelectionInputPull-down resistor Flash MemoryERASEFlash and NVM Configuration Bits Erase CommandInputHighPull-down resistorReset/TestNRST Microcontroller Reset I/O LowPull-Up resistor TSTTest Mode SelectInputPull-down resistorDebug UnitDRXD Debug Receive Data Input DTXDDebug Transmit DataOutput AICIRQ0 - IRQ1External Interrupt Inputs Input FIQFast Interrupt InputInput5AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04PIOP A0 - P A31Parallel IO Controller AI/OPulled-up input at resetUSB Device PortDDM USB Device Port Data - Analog DDPUSB Device Port Data +Analog USARTSCK0 - SCK1Serial Clock I/O TXD0 - TXD1Transmit Data I/O RXD0 - RXD1 Receive Data Input RTS0 - RTS1Request To Send Output CTS0 - CTS1Clear To Send Input DCD1Data Carrier Detect Input DTR1Data Terminal Ready Output DSR1Data Set Ready Input RI1Ring IndicatorInputSynchronous Serial ControllerTD Transmit Data Output RD Receive Data Input TK Transmit Clock I/O RK Receive Clock I/O TF Transmit Frame Sync I/O RFReceive Frame SyncI/O Timer/CounterTCLK0 - TCLK2External Clock Inputs Input TIOA0 - TIOA2I/O Line A I/O TIOB0 - TIOB2I/O Line BI/O PWM ControllerPWM0 - PWM3PWM ChannelsOutput SPIMISO Master In Slave Out I/O MOSI Master Out Slave In I/O SPCK SPI Serial ClockI/O NPCS0SPI Peripheral Chip Select 0I/O Low NPCS1-NPCS3SPI Peripheral Chip Select 1 to 3OutputLowTable 1. Signal Description List (Continued)Signal NameFunctionTypeActive LevelComments6AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Two-Wire InterfaceTWD Two-wire Serial Data I/O TWCKTwo-wire Serial ClockI/OAnalog-to-Digital ConverterAD0-AD3Analog Inputs Analog Digital pulled-up inputs at reset AD4-AD7Analog Inputs Analog Analog InputsADTRG ADC Trigger Input ADVREFADC ReferenceAnalogFast Flash Programming InterfacePGMEN0-PGMEN1Programming Enabling Input PGMM0-PGMM3Programming Mode Input PGMD0-PGMD15Programming Data I/O PGMRDY Programming Ready Output High PGMNVALID Data Direction Output Low PGMNOE Programming Read Input LowPGMCK Programming Clock Input PGMNCMDProgramming CommandInputLow Table 1. Signal Description List (Continued)Signal NameFunctionTypeActive LevelComments7AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Package and PinoutThe AT91SAM7S256 is available in a 64-lead LQFP package.64-lead LQFP Mechanical OverviewFigure 2 shows the orientation of the 64-lead LQFP package. A detailed mechanicaldescription is given in the section Mechanical Characteristics of the full datasheet.Figure 2. 64-lead LQFP Package Pinout (Top View)Pinout334948321716164Table 2. AT91SAM7S256 Pinout in 64-lead LQFP Package1ADVREF 17GND 33TDI 49TDO 2GND 18VDDIO 34P A6/PGMNOE 50JTAGSEL 3AD419P A16/PGMD435P A5/PGMRDY 51TMS 4AD520P A15/PGMD336P A4/PGMNCMD 52P A315AD621P A14/PGMD237P A27/PGMD1553TCK 6AD722P A13/PGMD138P A2854VDDCORE 7VDDIN 23P A24/PGMD1239NRST 55ERASE 8VDDOUT 24VDDCORE 40TST 56DDM 9P A17/PGMD5/AD025P A25/PGMD1341P A2957DDP 10P A18/PGMD6/AD126P A26/PGMD1442P A3058VDDIO 11P A21/PGMD927P A12/PGMD043P A359VDDFLASH12VDDCORE 28P A11/PGMM344P A260GND 13P A19/PGMD7/AD229P A10/PGMM245VDDIO 61XOUT 14P A22/PGMD1030P A9/PGMM146GND 62XIN/PGMCK 15P A23/PGMD1131P A8/PGMM047P A1/PGMEN163PLLRC 16P A20/PGMD8/AD332P A7/PGMNVALID48P A0/PGMEN064VDDPLL8AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Power ConsiderationsPower SuppliesThe AT91SAM7S256 has six types of power supply pins and integrates a voltage regu-lator, allowing the device to be supplied with only one voltage. The six power supply pin types are:•VDDIN pin. It powers the voltage regulator; voltage ranges from 3.0V to 3.6V , 3.3V nominal. If the voltage regulator is not used, VDDIN should be connected to GND.•VDDOUT pin. It is the output of the 1.8V voltage regulator.•VDDIO pin. It powers the I/O lines and the USB transceivers; dual voltage range is supported. Ranges from 3.0V to 3.6V , 3.3V nominal.•VDDFLASH pin. It powers a part of the Flash and is required for the Flash to operate correctly; voltage ranges from 3.0V to 3.6V, 3.3V nominal.•VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V , 1.8V typical. It can be connected to the VDDOUT pin with decouplingcapacitor. VDDCORE is required for the device, including its embedded Flash, to operate correctly.•VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the VDDOUT pin.No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be connected as shortly as possible to the system ground plane.Power ConsumptionThe AT91SAM7S256 has a static current of less than 60 µA on VDDCORE at 25°C,including the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 20 µA static current.The dynamic power consumption on VDDCORE is less than 50 mA at full speed when running out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not exceed 10 mA.Voltage RegulatorThe AT91SAM7S256 embeds a voltage regulator that is managed by the System Controller.In Normal Mode, the voltage regulator consumes less than 100 µA static current and draws 100 mA of output current.The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 20 µA static current and draws 1 mA of output current.Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or 1 nF) NPO capacitor must be connected between VDDOUT and GND as close to the chip as possible. One external 2.2 µF (or 3.3 µF) X7R capacitor must be connected between VDDOUT and GND.Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R.9AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Typical Powering SchematicsThe AT91SAM7S256 supports a 3.3V single supply mode. The internal regulator input connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 3 shows the power schematics to be used for USB bus-powered systems.Figure 3. 3.3V System Single Power Supply SchematicPower Source ranges from 4.5V (USB)to 18V3.3VVDDINVoltage RegulatorVDDOUTVDDIODC/DC ConverterVDDCOREVDDFLASHVDDPLL10AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04I/O Lines ConsiderationsJTAG Port PinsTMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not.TMS, TDI and TCK do not integrate a pull-up resistor.TDO is an output, driven at up to VDDIO, and has no pull-up resistor.The pin JTAGSEL is used to select the JTAG boundary scan when asserted at a high level. The pin JTAGSEL integrates a permanent pull-down resistor of about 15 k Ω to GND, so that it can be left unconnected for normal operations.Test PinThe pin TST is used for manufacturing test or fast programming mode of the AT91SAM7S256 when asserted high. The pin TST integrates a permanent pull-down resistor of about 15 k Ω to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, the pin TST and the pins PA0 and PA1 should be tied high.Driving the pin TST at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.Reset PinThe pin NRST is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low exter-nally to reset the microcontroller. There is no constraint on the length of the reset pulse,and the reset controller can guarantee a minimum pulse length. This allows connection of a simple push-button on the pin NRST as system user reset, and the use of the signal NRST to reset all the components of the system.The pin NRST integrates a permanent pull-up resistor to VDDIO .ERASE PinThe pin ERASE is used to re-initialize the Flash content and some of its NVM bits. It integrates a permanent pull-down resistor of about 15 k Ω to GND, so that it can be left unconnected for normal operations.PIO Controller A LinesAll the I/O lines PA0 to PA31 are 5V-tolerant and all integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers.5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be driven with a voltage of up to 5.5V. However, driving an I/O line with a voltage over VDDIO while the programmable pull-up resistor is enabled can lead to unpredictable results. Care should be taken, in particular at reset, as all the I/O lines default to input with pull-up resistor enabled at reset.I/O Line Drive LevelsThe PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently.The remaining I/O lines (PA4 to PA31) can draw only 8 mA.However, the total current drawn by all the I/O lines cannot exceed 150 mA.11AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Processor and ArchitectureARM7TDMI Processor•RISC processor based on ARMv4T Von Neumann architecture –Runs at up to 55 MHz, providing 0.9 MIPS/MHz •Two instruction sets–ARM ® high-performance 32-bit instruction set –Thumb ® high code density 16-bit instruction set •Three-stage pipeline architecture–Instruction Fetch (F)–Instruction Decode (D)–Execute (E)Debug and Test Features •Integrated embedded in-circuit emulator –Two watchpoint units–Test access port accessible through a JTAG protocol –Debug communication channel•Debug Unit –Two-pinUART –Debug communication channel interrupt handling –Chip ID Register•IEEE1149.1 JTAG Boundary-scan on all digital pinsMemory Controller•Bus Arbiter –Handles requests from the ARM7TDMI and the Peripheral Data Controller •Address decoder provides selection signals for –Three internal 1 Mbyte memory areas –One 256 Mbyte embedded peripheral area•Abort Status Registers –Source, Type and all parameters of the access leading to an abort are saved –Facilitates debug by detection of bad pointers •Misalignment Detector –Alignment checking of all data accesses –Abort generation in case of misalignment•Remap Command –Remaps the SRAM in place of the embedded non-volatile memory –Allows handling of dynamic exception vectors•Embedded Flash Controller –Embedded Flash interface, up to three programmable wait states–Prefetch buffer, bufferizing and anticipating the 16-bit requests, reducing the required wait states–Key-protected program, erase and lock/unlock sequencer –Single command for erasing, programming and locking operations –Interrupt generation in case of forbidden operation12AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Peripheral Data Controller•Handles data transfer between peripherals and memories •Eleven channels –Two for each USART –Two for the Debug Unit–Two for the Serial Synchronous Controller –Two for the Serial Peripheral Interface –One for the Analog-to-digital Converter•Low bus arbitration overhead –One Master Clock cycle needed for a transfer from memory to peripheral –Two Master Clock cycles needed for a transfer from peripheral to memory•Next Pointer management for reducing interrupt latency requirements13AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Memory•256 Kbytes of Flash Memory –1024 pages of 256 bytes–Fast access time, 30 MHz single-cycle access in Worst Case conditions –Page programming time: 4 ms, including page auto-erase –Page programming without auto-erase: 2 ms –Full chip erase time: 10 ms–10,000 write cycles, 10-year data retention capability –16 lock bits, each protecting 16 sectors of 64 pages –Protection Mode to secure contents of the Flash •64 Kbytes of Fast SRAM–Single-cycle access at full speedMemory MappingInternal SRAMThe AT91SAM7S256 embeds a high-speed 64-Kbyte SRAM bank. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x00200000. After Remap, the SRAM also becomes available at address 0x0.Internal FlashThe AT91SAM7S256 features one bank of 256 Kbytes of Flash. At any time, the Flash is mapped to address 0x0010 0000. It is also accessible at address 0x0 after the reset and before the Remap Command.Figure 4. Internal Memory Mapping256M BytesFlash Before Remap SRAM After Remap Undefined Areas(Abort)0x000F FFFF0x001F FFFF0x002F FFFF 0x0FFF FFFF1 M Bytes1 M Bytes1 M Bytes253 M BytesInternal FlashInternal SRAM0x0000 00000x0010 00000x0020 00000x0030 000014AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Embedded FlashFlash OverviewThe Flash of the AT91SAM7S256 is organized in 1024 pages of 256 bytes. The 262,144bytes are organized in 32-bit words.The Flash contains a 256-byte write buffer, accessible through a 32-bit interface.The Flash benefits from the integration of a power reset cell and from the brownout detector. This prevents code corruption during power supply changes, even in the worst conditions.Embedded Flash ControllerThe Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped within the Memory Controller on the APB. The User Interface allows:•programming of the access parameters of the Flash (number of wait states, timings, etc.)•starting commands such as full erase, page erase, page program, NVM bit set, NVM bit clear, etc.•getting the end status of the last command •getting error status•programming interrupts on the end of the last commands or on errorsThe Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that opti-mizes 16-bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode.Lock RegionsThe Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S256contains 16 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes.If a locked-regions erase or program command occurs, the command is aborted and the EFC trigs an interrupt.The 16 NVM bits are software programmable through the EFC User Interface. The com-mand "Set Lock Bit" enables the protection. The command "Clear Lock Bit" unlocks the lock region.Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.Security Bit FeatureThe AT91SAM7S256 features a security bit, based on a specific NVM-Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.This security bit can only be enabled, through the Command "Set Security Bit" of the EFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full flash erase is performed. When the security bit is deac-tivated, all accesses to the flash are permitted.It is important to note that the assertion of the ERASE pin should always be longer than 50 ms.As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is safer to connect it directly to GND for the final application.15AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Non-volatile Brownout Detector ControlTwo general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain in their state.These two GPNVM bits can be cleared or set respectively through the commands "Clear General-purpose NVM Bit" and "Set General-purpose NVM Bit" of the EFC User Interface.•GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables the BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus disables the brownout detector by default.•The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1 enables the brownout reset when a brownout is detected, Clearing the GPNVM Bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by default.Calibration BitsEight NVM bits are used to calibrate the brownout detector and the voltage regulator.These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.Fast Flash Programming InterfaceThe Fast Flash Programming Interface allows programming the device through either aserial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard industrial programmers.The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high.The Flash of the AT91SAM7S256 is organized in 1024 pages of 256 bytes. It reads as 65,536 32-bit words.The Flash contains a 256-byte write buffer, accessible through a 32-bit interface.16AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04System ControllerThe System Controller manages all vital blocks of the microcontroller: interrupts, clocks,power, time, debug and reset.Figure 5. System Controller Block DiagramNRSTSLCKAdvanced Interrupt ControllerReal-Time Timer Periodic Interval Timer Reset ControllerP A0-P A31periph_nreset System ControllerWatchdog Timerwdt_fault WDRPROCPIO ControllerPORBODRCOSCgpnvm[0]calenPower Management ControllerOSCPLLXIN XOUTPLLRC MAINCKPLLCKpit_irqMCK proc_nresetwdt_irq periph_irq{2]periph_nreset periph_clk[2..14]PCK MCKpmc_irqUDPCK nirqnfiq rtt_irqEmbedded Peripheralsperiph_clk[2]pck[0-2]in out enableARM7TDMISLCKSLCK irq0-irq1fiq irq0-irq1fiqperiph_irq[4..14]periph_irq[2..14]intintperiph_nresetperiph_clk[4..14]Embedded Flashflash_poejtag_nresetflash_poe gpnvm[0..1]flash_wrdis flash_wrdis proc_nresetperiph_nreset dbgu_txddbgu_rxdpit_irq rtt_irq dbgu_irq pmc_irq rstc_irqwdt_irq rstc_irqSLCKgpnvm[1]Boundary Scan TAP Controllerjtag_nresetice_nreset debugPCK debug idledebugMemory ControllerMCK proc_nresetbod_rst_enproc_nreset periph_nreset periph_nresetidleDebug Unitdbgu_irq MCKdbgu_rxd periph_nresetforce_ntrst dbgu_txdUSB DevicePortUDPCK periph_nreset periph_clk[11]periph_irq[11]usb_suspendusb_suspendVoltage RegulatorstandbyVoltage Regulator Mode Controllersecurity_bitcalice_nreset force_ntrstcal。