Verilog HDL-chapter4

Behavior description Early in the design process, describe the hardware algorithm behavior from the algorithm's point of view, describing external behavior of the circuit , called behavioral description
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4.2.2 Blocks statement
Block classify
Sequential block : begin end Parallel block: fork join nested blocks Named blocks
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4.2.1 Process statement
EX2： No Sensitive control table in always process
module clock_gen( clock); output clock; reg clock; // The clock variable initialization at time 0 initial clock = 1’b0; // The value of the clock flipped once each half-cycle always #10 clock = ~clock; initial #1000 $finish; endmodule
end indicator of block statement
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4.2 Process statement and blocks statement
Process statement：initial vs. always Event control sensitive list：only within always blocks to activate the execution of procedural block Block statement：begin-end vs. forkjoin Block name：optional Local variable declaration：optional
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4.1 Basic frame of behavior modeling When modeling a circuit by behavioral description, one should know：
1.Behavior of the circuit. If the circuit contain various behaviors, divide them. 2.Timing control (a) what the circuit should do when time reaches certain point (b) what the circuit should do when certain condition meets 。
Process statement @(Event control sensitive list)
start indicator of block statement：block name local variables declaration
procedural assignments or advanced programming statements (if-else, for ) ……
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4.2.1 Process statement
EX4：always process——Asynchronous clear, reset
module dff_asyn(q, d, clear, preset, clock); output q; input d, clear, preset, clock; reg q; always @(posedge clock or negedge clear or negedge preset) begin if (!clear) q = 0; else if (!preset) q=1; else q = d; //procedural assignment end endmodule //synthesizable
Verilog HDL
Fu Fangfa fff1984292@
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Chapter 4 Behavioral Modeling
4.1 Basic frame of behavior modeling 4.2 Process statement and blocks statement 4.3 Process assignment statement 4.4 Senior program statement 4.5 example
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描述一个具有相同相位的双时钟产生模 块，时钟周期分别是200延时单位和100 延时单位，占空比50%。
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module clock_gen (phi1, phi2); output phi1, phi2; reg phi1, phi2; initial begin phi1 = 0; phi2 = 0; end always #100 phi1 = ~phi1; always @ (posedge phi1) begin phi2 = 1; #50 phi2 = 0; #50 phi2 = 1; #50 phi2 = 0; end endmodule
模块定义 端口说明 模块 数据类型声明 描述体 结束行 过程块 1 过程块 2 ……. ……. 块语句 高级程序语句
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过程语句 （initial/always）
过程赋值语句
4.2 Process statement and blocks statement
Format of procedural block
Frame of module behavior description
EX： positive edge-sensitive D flip-flop module dff_pos(data,clk,q);//module definition input data,clk; //port declaration output q; // port declaration reg q; // Data Type Declaration always @(posedge clk) q<=data;// behavior description endmodule //
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4.1 Basic frame of behavior modeling
A module contains one or more procedural blocks executed concurrently Behavior of a procedural block depends on procedural statement（initial vs. always）and block statement（begin-end vs. fork-join） Within the block statement, there are
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4.2.1 Process statement
conclusion
In a module,there may be multiple initial and/or always blocks，which are independent of each other and executed concurrently Difference between initial and always block：
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4.1 Basic frame of behavior modeling
Circuit Description Style


Behavior description：focus on the Abstract description of the module behavior function structure description：Focus on detailed description of the internal structure of module implemented


For multiple block codes, each block starts to execute concurrently at time 0. Initial block executes only once, but always block may execute repeatedly. Always blocks generally include trigger condition, without trigger condition an always block is executed forever. However, Initial include no trigger condition.


Procedural assignment：blocking vs. nonblocking Advanced programming statements: if-else、case、 while、wait……
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4.1 Basic frame of behavior modeling
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4.2.1 Process statement