E233中文资料

DESCRIPTIONThe M37733MHLXXXHP is a single-chip microcomputer using the 7700 Family core. This single-chip microcomputer has a CPU and a bus interface unit. The CPU is a 16-bit parallel processor that can be an 8-bit parallel processor, and the bus interface unit enhances the memory access efficiency to execute instructions fast. This microcomputer also includes a 32 kHz oscillation circuit, in addition to the ROM, RAM, multiple-function timers, serial I/O, A-D converter, and so on.Its strong points are the low power dissipation, the low supply voltage, and the small package.FEATURESq Number of basic instructions (103)q Memory size ROM ................................................. 124 KbytesRAM ................................................ 3968 bytes q Instruction execution timeThe fastest instruction at 12 MHz frequency ...................... 333 ns q Single power supply ...................................................... 2.7–5.5 V q Low power dissipation (At 3 V supply voltage, 12 MHz frequency)............................................ 9 mW (Typ.)q Interrupts ............................................................ 19 types, 7 levels q Multiple-function 16-bit timer ................................................. 5 + 3 q Serial I/O (UART or clock synchronous) . (3)q10-bit A-D converter .............................................. 8-channel inputs q12-bit watchdog timerq Programmable input/output(ports P0, P1, P2, P3, P4, P5, P6, P7, P8) (68)q Clock generating circuit ........................................ 2 circuits built-in q Small package......................80-pin plastic molded fine-pitch QFP(80P6D-A;0.5 mm lead pitch) APPLICATIONControl devices for general commercial equipment such as office automation, office equipment, personal information equipment, and so on.Control devices for general industrial equipment such as communication equipment, and so on.FUNCTIONS OF M37733MHLXXXHPMemory sizeInput/Output ports Multi-function timersInterruptsClock generating circuit Power dissipation Parameter FunctionsNumber of basic instructions103Instruction execution time333 ns (the fastest instruction at external clock 12 MHz frequency) ROM124 KbytesRAM3968 bytesP0 – P2, P4 – P88-bit ! 8P34-bit ! 1TA0, TA1, TA2, TA3, TA416-bit ! 5TB0, TB1, TB216-bit ! 3Serial I/O(UART or clock synchronous serial I/O) ! 3A-D converter10-bit ! 1 (8 channels)Watchdog timer12-bit ! 13 external types, 16 internal typesEach interrupt can be set to the priority level (0 – 7.)2 circuits built-in (externally connected to a ceramic resonator or aquartz-crystal oscillator)Supply voltage 2.7 – 5.5 V9 mW (at 3 V supply voltage, external clock 12 MHz frequency)22.5 mW (at 5 V supply voltage, external clock 12 MHz frequency)Input/Output voltage 5 VOutput current 5 mAMemory expansion Maximum 16 MbytesOperating temperature range–40 to 85 °CDevice structure CMOS high-performance silicon gate processPackage80-pin plastic molded fine-pitch QFP (80P6D-A;0.5 mm lead pitch) Input/Output characteristicPIN DESCRIPTIONX IN Clock input Input X OUTClock output Output PinName Input/Output FunctionsVcc,Power source Apply 2.7 – 5.5 V to Vcc and 0 V to Vss.Vss CNVssCNVss input Input This pin controls the processor mode. Connect to Vss for the single-chip mode and the memory expansion mode, and to Vcc for the microprocessor mode.RESETReset input Input When “L” level is applied to this pin, the microcomputer enters the reset state.These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartz-crystal oscillator between X IN and X OUT . When an external clock is used, the clock source should be connected to the X IN pin, and the X OUT pin should be left open.EEnable output Output This pin functions as the enable signal output pin which indicates the access status in the internal bus. When output level of E signal is “L”, data/instruction read or data write is performed.BYTE External data InputIn the memory expansion mode or the microprocessor mode, this pin determines whether the bus widthexternal data bus has an 8-bit width or a 16-bit width. The data bus has a 16-bit width when “L”selection input signal is input and an 8-bit width when “H” signal is input.AVcc,Analog power Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss.AVss source input V REF Reference Input This is reference voltage input pin for the A-D converter.voltage input P00 – P07I/O port P0I/OIn the single-chip mode, port P0 becomes an 8-bit I/O port. An I/O direction register is available so that each pin can be programmed for input or output. These ports are in the input mode when reset.In the memory expansion mode or the microprocessor mode, these pins output address (A 0 – A 7).P10 – P17I/O port P1I/OIn the single-chip mode, these pins have the same functions as port P0. When the BYTE pin is set to “L” in the memory expansion mode or the microprocessor mode and external data bus has a 16-bit width, high-order data (D 8 – D 15) is input/output or an address (A 8 – A 15) is output. When the BYTE pin is “H” and an external data bus has an 8-bit width, only address (A 8 – A 15) is output.P20 – P27I/O port P2I/O In the single-chip mode, these pins have the same functions as port P0. In the memory expansion mode or the microprocessor mode, low-order data (D 0 – D 7) is input/output or an address (A 16 – A 23) is output.P30 – P33I/O port P3I/O In the single-chip mode, these pins have the same function as port P0. In the memory expansion mode or the microprocessor mode, R/W , BHE , ALE, and HLDA signals are output.P40 – P47I/O port P4I/OIn the single-chip mode, these pins have the same functions as port P0. In the memory expansion mode or the microprocessor mode, P40, P41, and P42 become HOLD and RDY input pins, and a clock φ 1 output pin, respectively. Functions of the other pins are the same as in the single-chip mode. However, in the memory expansion mode, P42 can be selected as an I/O port.P50 – P57I/O port P5I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timers A0 to A3 and input pins for key input interrupt input (KI 0 – KI 3).P60 – P67I/O port P6I/O In addition to having the same functions as port P0 in the single-chip mode, these pins alsofunction as I/O pins for timer A4, input pins for external interrupt input (INT 0 – INT 2) and input pins for timers B0 to B2. P67 also functions as sub-clock φ SUB output pin.P70 – P77I/O port P7I/OIn addition to having the same functions as port P0 in the single-chip mode, these pins function as input pins for A-D converter. P72 to P75 also function as I/O pins for UART2. Additionally, P76and P77 have the function as the output pin (X COUT ) and the input pin (X CIN ) of the sub-clock(32 kHz) oscillation circuit, respectively. When P76 and P77 are used as the X COUT and X CIN pins,connect a resonator or an oscillator between the both.P80 – P87I/O port P8I/OIn addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for UART 0 and UART 1.SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERN o t i c e :T S o me p a r a m e t r i BASIC FUNCTION BLOCKSThe M37733MHLXXXHP has the same functions as theM37733MHBXXXFP except for the package and the reset circuit.Refer to the section on the M37733MHBXXXFP.RESET CIRCUIT_____The microcomputer is released from the reset state when the RESET pin is returned to “H” level after holding it at “L” level with the power source voltage at 2.7 – 5.5 V. Program execution starts at the address formed by setting address A 23 – A 16 to 0016, A 15 – A 8 to the contents of address FFFF 16, and A 7 – A 0 to the contents of address FFFE 16.Figure 3 shows an example of a reset circuit. When the stabilized clock is input from the external to the main-clock oscillation circuit,the reset input voltage must be 0.55 V or less when the power source voltage reaches 2.7 V. When a resonator/oscillator is connected to the main-clock oscillation circuit, change the reset input voltage from “L” to “H” after the main-clock oscillation is fully stabilized.The status of the internal registers during reset is the same as the M37733MHBXXXFP’s.ADDRESSING MODESThe M37733MHLXXXHP has 28 powerful addressing modes. Refer to the “7700 Family Software Manual” for the details.MACHINE INSTRUCTION LISTThe M37733MHLXXXHP has 103 machine instructions. Refer to the “7700 Family Software Manual” for the details.DATA REQUIRED FOR MASK ROM ORDERINGPlease send the following data for mask orders.(1) M37733MHLXXXHP mask ROM order confirmation form (2) 80P6D, 80P6Q mark specification form (3) ROM data (EPROM 3 sets)N o t i c e :T S o me p a r a m e t r i SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERSymbolParameter ConditionsRatings Unit Vcc Power source voltage–0.3 to +7V AVcc Analog power source voltage–0.3 to +7V V I _____Input voltage RESET , CNVss, BYTE–0.3 to +12V Input voltage P00 – P07, P10 – P17, P20 – P27,P30 – P33, P40 – P47, P50 – P57,P60 – P67, P70 – P77, P80 – P87,V REF , X INOutput voltage P00 – P07, P10 – P17, P20 – P27,P30 – P33, P40 – P47, P50 – P57,P60 – P67, P70 – P77, P80 – P87,_X OUT , EP d Power dissipation Ta = 25 °C 200mW T opr Operating temperature –40 to +85°C T stgStorage temperature–65 to +150°CV IV O Limits Min.Typ.Max.f(X IN ) : Operating2.7 5.5f(X IN ) : Stopped, f(X CIN ) = 32.768 kHz2.75.5AVcc Analog power source voltage Vcc V Vss Power source voltage0V AVss Analog power source voltageVHigh-level input voltage P00 – P07, P30 – P33, P40 – P47, P50 – P57, P60 – P67,_____P70 – P77, P80 – P87, X IN , RESET , CNVss, BYTE, X CIN (Note 3)High-level input voltage P10 – P17, P20 – P27 (in single-chip mode)High-level input voltage P10 – P17, P20 – P27(in memory expansion mode and microprocessor mode)Low-level input voltage P00 – P07, P30 – P33, P40 – P47, P50 – P57, P60 – P67,_____P70 – P77, P80 – P87, X IN , RESET , CNVss, BYTE, X CIN (Note 3)Low-level input voltage P10 – P17, P20 – P27 (in single-chip mode)Low-level input voltage P10 – P17, P20 – P27(in memory expansion mode and microprocessor mode)High-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33,P40 – P47, P50 – P57, P60 – P67, P70 – P77,P80 – P87High-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77,P80 – P87Low-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33,P40 – P43, P54 – P57, P60 – P67, P70 – P77,P80 – P87Low-level peak output current P44 – P47, P50 – P53Low-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33,P40 – P43, P54 – P57, P60 – P67, P70 – P77,P80 – P87I OL(avg)Low-level average output current P44 – P47, P50 – P5312mA f(X IN )Main-clock oscillation frequency (Note 4)12MHz f(X CIN)Sub-clock oscillation frequency32.76850kHzABSOLUTE MAXIMUM RATINGS–0.3 to Vcc + 0.3V–0.3 to Vcc + 0.3V Unit Symbol ParameterRECOMMENDED OPERATING CONDITIONS (Vcc = 5 V ± 10%, Ta = –40 to +85 °C, unless otherwise noted)V Vcc Power source voltageNotes 1.Average output current is the average value of a 100 ms interval.2.The sum of I OL(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less,the sum of I OH(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less,the sum of I OL(peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and the sum of I OH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less.3.Limits V IH and V IL for X CIN are applied when the sub clock external input selection bit = “1”.4.The maximum value of f(X IN ) = 6 MHz when the main clock division selection bit = “1”.0.8 Vcc 0.8 Vcc 0.5 Vcc000Vcc Vcc Vcc 0.2Vcc 0.2Vcc 0.16Vcc –10–510165V V V V V V mAmAmA mA mA V IH V IH V IH V IL V IL V IL I OH(peak)I OH(avg)I OL(peak)I OL(peak)I OL(avg)High-level output voltage P00 – P07, P10 – P17, P20 – P27, P33,P40 – P47, P50 – P57, P60 – P67, P70 – P77,P80 – P87High-level output voltage P00 – P07, P10 – P17, P20 – P27, P33High-level output voltage P30 – P32High-level output voltage ELow-level output voltage P00 – P07, P10 – P17, P20 – P27, P33,P40 – P43, P54 – P57, P60 – P67, P70 – P77,P80 – P87Low-level output voltage P44 – P47, P50 – P53Low-level output voltage P00 – P07, P10 – P17, P20 – P27, P33Low-level output voltage P30 – P32Low-level output voltage EHysteresis HOLD , RDY , TA0IN – TA4IN , TB0IN – TB2IN ,INT 0 – INT 2, AD TRG , CTS 0, CTS 1, CTS 2, CLK 0,CLK 1, CLK 2, KI 0 – KI 3Hysteresis RESET Hysteresis X INHysteresis X CIN (When external clock is input)High-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33,P40 – P47, P50 – P57, P60 – P67, P70 – P77,P80 – P87, X IN , RESET , CNVss, BYTELow-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33,P40 – P47, P50 – P53, P60, P61, P65 – P67,P70 – P77, P80 – P87, X IN , RESET , CNVss, BYTEUnit ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, f(X IN ) = 12 MHz, unless otherwise noted)Symbol ParameterTest conditions32.54.7V V OH V OH –0.5–0.18V OH3.14.82.63.44.82.6V OH V OL V VV V 20.51.81.5V V OL 0.451.90.430.41.60.40.4V VV0.40.10.20.10.10.060.10.06V CC = 5 V, I OH = –10 mA V CC = 3 V, I OH = –1 mAV CC = 5 V, I OH = –400 µA V CC = 5 V, I OH = –10 mA V CC = 5 V, I OH = –400 µA V CC = 3 V, I OH = –1 mA V CC = 5 V, I OH = –10 mA V CC = 5 V, I OH = –400 µA V CC = 3 V, I OH = –1 mA V CC = 5 V, I OL = 10 mA V CC = 3 V, I OL = 1 mA V CC = 5 V, I OL = 16 mA V CC = 3 V, I OL = 10 mA V CC = 5 V, I OL = 2 mA V CC = 5 V, I OL = 10 mA V CC = 5 V, I OL = 2 mA V CC = 3 V, I OL = 1 mA V CC = 5 V, I OL = 10 mA V CC = 5 V, I OL = 2 mA V CC = 3 V, I OL = 1 mA V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 VV CC = 5 V, V I = 5 V V CC = 3 V, V I = 3 V V CC = 5 V, V I = 0 V V CC = 3 V, V I = 0 VV I = 0 V,without a pull-up transistor V I = 0 V,with a pull-up transistorWhen clock is stopped.10.70.50.40.40.260.40.26V CC = 5 V V CC = 3 V V CC = 5 VV CC = 3 V –0.25–0.08254–5–4–5–4–1.0 –0.35V V V V µAµAµAmA VV OL V OLV OL V T+ – V T–V T+ – V T–V T+ – V T–V T+ – V T–I IHI ILI ILV RAM Low-level input current P54 – P57, P62 – P64RAM hold voltage Limits Min.Typ.Max.V CC = 5 V,f(X IN ) = 12 MHz (square waveform),(f(f 2) = 6 MHz),f(X CIN ) = 32.768 kHz,in operating (Note 1)V CC = 3 V,f(X IN ) = 12 MHz (square waveform),(f(f 2) = 6 MHz),f(X CIN ) = 32.768 kHz,in operating (Note 1)V CC = 3 V,f(X IN ) = 12 MHz (square waveform),(f(f 2) = 0.75 MHz),f(X CIN ) : Stopped,in operatingV CC = 3 V,f(X IN ) = 12 MHz (square waveform),f(X CIN ) = 32.768 kHz,when a WIT instruction is executed (Note 2)V CC = 3 V,f(X IN ) : Stopped,f(X CIN ) = 32.768 kHz,in operating (Note 3)V CC = 3 V,f(X IN ) : Stopped,f(X CIN ) = 32.768 kHz,when a WIT instruction is executed (Note 4)Ta = 25 °C,when clock is stopped Ta = 85 °C,when clock is stoppedmAmAmAµAµAµAµA µAMax.960.812606120Limits Typ.4.530.46303UnitMin.Test conditionsSymbolParameterELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, unless otherwise noted)When single-chip mode, output pins are open, andother pins are V SS .Power source currentI CCLimits Min.Typ.Max. —ResolutionV REF = V CC 10Bits —Absolute accuracy V REF = V CC ± 3LSB R LADDER Ladder resistance V REF = V CC1025k Ωt CONV Conversion time 19.6µs V REF Reference voltage 2.7V CC V V IAAnalog input voltageV REFVSymbol ParameterTest conditionsUnit A–D CONVERTER CHARACTERISTICS(V CC = AV CC = 5 V, V SS = AV SS = 0 V, Ta = –40 to +85 °C, f(X IN ) = 12 MHz, unless otherwise noted (Note))Note. This applies when the main clock division selection bit = “0” and f(f 2) = 6 MHz.Notes 1. This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stopbit = “1”.2. This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”.3. This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock.4. This applies when the X COUT drivability selection bit = “0” and the system clock stop bit at wait state = “1”.Limits Min.Max.t c External clock input cycle time (Note 1)83ns t w(H)External clock input high-level pulse width (Note 2)33ns t w(L)External clock input low-level pulse width (Note 2)33ns t r External clock rise time 15ns t fExternal clock fall time15nsLimits Min.Max.t su(D–E)Data input setup time 50ns t su(RDY– φ1)RDY input setup time 80ns t su(HOLD– φ1)HOLD input setup time 80ns t h(E–D)Data input hold time 0ns t h( φ1–RDY)RDY input hold time 0ns t h( φ1–HOLD)HOLD input hold timensTIMING REQUIREMENTS (V CC = 2.7 – 5.5 V, V SS = 0 V, Ta = –40 to +85 °C, f(X IN ) = 12 MHz, unless otherwise noted (Note 1))Notes 1. This applies when the main clock division selection bit = “0” and f(f 2) = 6 MH Z .2. Input signal’s rise/fall time must be 100 ns or less, unless otherwise noted.External clock inputUnit Symbol ParameterNotes 1. When the main clock division selection bit = “1”, the minimum value of t c = 166 ns.2. When the main clock division selection bit = “1”, values of t w(H) / t c and t w(L) / t c must be set to values from 0.45 through 0.55.Unit Symbol ParameterMemory expansion mode and microprocessor modeSingle-chip modeUnit Symbol ParameterLimits Min.Max.t su(P0D–E)Port P0 input setup time 200ns t su(P1D–E)Port P1 input setup time 200ns t su(P2D–E)Port P2 input setup time 200ns t su(P3D–E)Port P3 input setup time 200ns t su(P4D–E)Port P4 input setup time 200ns t su(P5D–E)Port P5 input setup time 200ns t su(P6D–E)Port P6 input setup time 200ns t su(P7D–E)Port P7 input setup time 200ns t su(P8D–E)Port P8 input setup time 200ns t h(E–P0D)Port P0 input hold time 0ns t h(E–P1D)Port P1 input hold time 0ns t h(E–P2D)Port P2 input hold time 0ns t h(E–P3D)Port P3 input hold time 0ns t h(E–P4D)Port P4 input hold time 0ns t h(E–P5D)Port P5 input hold time 0ns t h(E–P6D)Port P6 input hold time 0ns t h(E–P7D)Port P7 input hold time 0ns t h(E–P8D)Port P8 input hold timensLimits Min.Max.t c(TA)TAi IN input cycle time250ns t w(TAH)TAi IN input high-level pulse width 125ns t w(TAL)TAi IN input low-level pulse width125nsUnit Symbol ParameterTimer A input (Count input in event counter mode)Limits Min.Max.t c(TA)TAi IN input cycle time (Note)666ns t w(TAH)TAi IN input high-level pulse width (Note)333ns t w(TAL)TAi IN input low-level pulse width (Note)333nsUnit Symbol ParameterTimer A input (Gating input in timer mode)Limits Min.Max.t c(TA)TAi IN input cycle time (Note)666ns t w(TAH)TAi IN input high-level pulse width 166ns t w(TAL)TAi IN input low-level pulse width166nsUnit Symbol ParameterTimer A input (External trigger input in one-shot pulse mode)Limits Min.Max.t w(TAH)TAi IN input high-level pulse width 166ns t w(TAL)TAi IN input low-level pulse width166nsUnit Symbol ParameterTimer A input (External trigger input in pulse width modulation mode)Limits Min.Max.t c(UP)TAi OUT input cycle time3333ns t w(UPH)TAi OUT input high-level pulse width 1666ns t w(UPL)TAi OUT input low-level pulse width 1666ns t su(UP–T IN )TAi OUT input setup time 666ns t h(T IN –UP)TAi OUT input hold time666nsUnit Symbol ParameterTimer A input (Up-down input in event counter mode)Limits Min.Max.t c(TA) TAj IN input cycle time 2000ns t su(TAj IN –TAj OUT ) TAj IN input setup time 500ns t su(TAj OUT –TAj IN ) TAj OUT input setup time500nsUnit SymbolParameterTimer A input (Two-phase pulse input in event counter mode)Note. Limits change depending on f(X IN ). Refer to “DATA FORMULAS”.Note. Limits change depending on f(X IN ). Refer to “DATA FORMULAS”.Limits Min.Max.t c(CK)CLK i input cycle time333ns t w(CKH)CLK i input high-level pulse width 166ns t w(CKL)CLK i input low-level pulse width 166ns t d(C–Q)T X D i output delay time 100ns t h(C–Q)T X D i hold time0ns t su(D–C)R X D i input setup time 65ns t h(C–D)R X D i input hold time75nsLimits Min.Max.t c(TB)TBi IN input cycle time (one edge count)250ns t w(TBH)TBi IN input high-level pulse width (one edge count)125ns t w(TBL)TBi IN input low-level pulse width (one edge count)125ns t c(TB)TBi IN input cycle time (both edges count)500ns t w(TBH)TBi IN input high-level pulse width (both edges count)250ns t w(TBL)TBi IN input low-level pulse width (both edges count)250nsUnit Symbol ParameterTimer B input (Count input in event counter mode)Limits Min.Max.t c(TB)TBi IN input cycle time (Note)666ns t w(TBH)TBi IN input high-level pulse width (Note)333ns t w(TBL)TBi IN input low-level pulse width (Note)333nsUnit Symbol ParameterTimer B input (Pulse period measurement mode)Limits Min.Max.t c(TB)TBi IN input cycle time (Note)666ns t w(TBH)TBi IN input high-level pulse width (Note)333ns t w(TBL)TBi IN input low-level pulse width (Note)333nsUnit Symbol ParameterTimer B input (Pulse width measurement mode)Unit Symbol ParameterA-D trigger inputUnit Symbol ParameterSerial I/OUnit Symbol ParameterLimits Min.Max.t w(INH)INT i input high-level pulse width 250ns t w(INL)INT i input low-level pulse width 250ns t w(KIL)KI i input low-level pulse width250nsLimits Min.Max.t c(AD)AD TRG input cycle time (minimum allowable trigger)1333ns t w(ADL)AD TRG input low-level pulse width166nsNote. Limits change depending on f(X IN ). Refer to “DATA FORMULAS”.Note. Limits change depending on f(X IN ). Refer to “DATA FORMULAS”.External interrupt INT i input, key input interrupt KI i inputDATA FORMULASTimer A input (Gating input in timer mode)8 ! 1092 • f(f 2)4 ! 1092 • f(f 2)4 ! 1092 • f(f 2)LimitsMin. Max.Symbol ParameterUnit t c(TA)TAi IN input cycle timet w(TAH)TAi IN input high-level pulse width t w (TAL )TAi IN input low-level pulse widthns ns ns8 ! 1092 • f(f 2)Timer A input (External trigger input in one-shot pulse mode)LimitsMin.Max.Symbol ParameterUnit t c(TA)TAi IN input cycle timensTimer B input (In pulse period measurement mode or pulse width measurement mode)Limits Min.Max.Symbol ParameterUnit ns ns nst c(TB)TBi IN input cycle timet w(TBH)TBi IN input high-level pulse width t w(TBL)TBi IN input low-level pulse width8 ! 1092 • f(f 2)4 ! 1092 • f(f 2)4 ! 1092 • f(f 2)Note. f(f 2) represents the clock f 2 frequency.For the relation to the main clock and sub clock, refer to Table 9 in data sheet “M37733MHBXXXFP”.SWITCHING CHARACTERISTICS(V CC = 2.7 – 5.5 V, V SS = 0 V, Ta = –40 to +85°C, f(X IN) = 12 MHz, unless otherwise noted (Note))2Fig. 2 Measuring circuit for ports P0 – P8 and φ 1Memory expansion mode and microprocessor modeCC SS IN2.No wait : Wait bit = “1”.Wait 1 : The external memory area is accessed with wait bit = “0” and wait selection bit = “1”.Wait 0 : The external memory area is accessed with wait bit = “0” and wait selection bit = “0”.Address output delay timeAddress output delay timeAddress hold timeALE pulse widthAddress output set up timeAddress hold timeALE output delay timeData output delay time Data hold timeE pulse widthFloating start delay time Floating release delay timeNo wait Wait 1Wait 0Memory expansion mode and microprocessor modeBus timing data formulas (V CC = 2.7 – 5.5 V, V SS = 0 V, Ta = –40 to +85 °C, f(X IN ) = 12 MHz (Max., Note), unless otherwise noted)90101 ! 1092 · f(f 2)3 ! 1092 · f(f 2)1 ! 1092 · f(f 2)3 ! 1092 · f(f 2)1 ! 1092 · f(f 2)1 ! 1092 · f(f 2)2 ! 1092 · f(f 2)1 ! 1092 · f(f 2)2 ! 1092 · f(f 2)ns ns ns ns ns ns ns ns ns ns No wait Wait 1Wait 0No wait Wait 1Wait 0No wait Wait 1Wait 0No wait Wait 1Wait 0No wait Wait 1Wait 0No wait Wait 1Wait 0No wait Wait 1Wait 01 ! 1092 · f(f 2)ns ns nsns ns ns 941 ! 1092 · f(f 2)1 ! 1092 · f(f 2)2 ! 1092 · f(f 2)4 ! 1092 · f(f 2)ns ns 1 ! 1092 · f(f 2)1 ! 1092 · f(f 2)3 ! 1092 · f(f 2)1 ! 1092 · f(f 2)3 ! 1092 · f(f 2)1 ! 1092 · f(f 2)1 ! 1092 · f(f 2)– 63– 68– 63– 88– 43– 43– 43– 73– 73– 43– 43– 43– 35– 35– 30– 63– 68– 63– 68– 50– 50Unit SymbolParameterLimitsWait modeMin.Max.t d(An–E)t d(A–E)t h(E–An)t w(ALE)t su(A–ALE)t h(ALE–A)t d(ALE–E)t d(E–DQ)t h(E–DQ)t w(EL)t pxz(E–DZ)t pzx(E–DZ)No wait Wait 1Wait 0BHE output delay timeR/W output delay timet d(BHE–E)t d(R/W–E)t h(E–BHE)t h(E–R/W)t d(E– φ 1)φ 1 output delay timeR/W hold timeBHE hold time030ns ns ns ns ns ns nsnsNotes 1.This applies when the main-clock division selection bit = “0”.2.f(f 2) represents the clock f 2 frequency.For the relation to the main clock and sub clock, refer to Table 9 in data sheet “M37733MHBXXXFP”.TIMING DIAGRAMt w(H)t d(E–P0Q)t d(E–P2Q)t d(E–P3Q)t d(E–P4Q)t d(E–P5Q)t d(E–P6Q)t d(E–P7Q)t d(E–P8Q)Port P0 outputPort P0 inputPort P1 outputPort P1 inputPort P2 outputPort P2 inputPort P3 outputPort P3 inputEX INPort P4 outputPort P4 inputPort P5 outputPort P5 inputPort P6 outputPort P6 inputPort P7 outputPort P7 inputPort P8 outputPort P8 inputt su(P0D–E)t h(E–P0D)t d(E–P1Q)t r t f t w(L)t ct su(P1D–E)t h(E–P1D)t su(P2D–E)t h(E–P2D)t su(P3D–E)t h(E–P3D)t su(P4D–E)t h(E–P4D)t su(P5D–E)t h(E–P5D)t su(P6D–E)t h(E–P6D)t su(P7D–E)t h(E–P7D)t su(P8D–E)t h(E–P8D)TAi IN input TAi OUT inputt c(TA)t w(TAH)t w(TAL)t c(UP)t w(UPH)t w(UPL)t h(T IN–UP)t su(UP–T IN) TAi OUT input(Up-down input)TAi IN input(when count by falling)TAi IN input(when count by rising)In event count modeTAj IN input TAj OUT inputt c(TA)t su(TAj IN–TAj OUT)t su(TAj IN–TAj OUT)t su(TAj OUT–TAj IN)t su(TAj OUT–TAj IN)In event counter mode(When two-phase pulse input is selected)t c(TB)t w(TBH)t w(TBL) TBi IN inputt c(AD)t w(ADL)t c(CK)t w(CKH)t w(CKL)t w(INL) t w(KNL)t d(C–Q)t SU(D–C)t h(C–D) t w(INH)AD TRG inputCLK iTxD iRxD iINTi inputKli inputt h(C–Q)。

2002.1 2.25错误代码表CMMC-1、1S、3、3S、5、6UC100、200、300错误关联信息用户自定义错误UC100错误关联信息1•用户自定义 错误发生用户自定义错误， UC100面板上的LED 指示灯将显示 P 、E 、C 、U 或是A 。

同时，J/S BOX 的START 指示灯闪烁。

2.其它错误J/S BOX 的R.STOP 指示灯闪烁。

错误排除后，指示灯熄灭。

3.状态指示灯LED （数据处理装置 通信电路板内）正常状态- 错误状态-- ----绿LED 指示灯点亮 ---绿LED 指示灯熄灭4.接触信号测头与工件接触，或是没有正常恢复时J/S BOX 的TS 的指示灯闪烁。

5.UC100错误发生时在 MAIN100的电路板上仅显示错误码的后一位。

术语解释1)ADC ------------ ――模/数转换器2) RT ------- ——转台3) DPRAM ------- 双端口 RAM4) IE命令 --------- -—立即执行命令5) S/B 单元一- -—信号发声器单兀6) J/S ------ 操纵杆7)特有关订制品8) CMMC --------- ------- CNC三坐标测量机用控制装置9) IT -------- - 索引表错误编号意义E000 类 ----------------- Reserved r E100类 ------------------ 通信相关E200 类 ---------------- 订制品（其它）> RecoverableE300类 ----------------- 标准/扫描（其它）E400类 ------------------ 标准（其它）：E500 类 ----------------- 标准（其它）Un recoverable E600类 ------------------ 初始化（其它）E700类 ------------------ 通信（其它）[E800 类------------------ 标准（其它）° Fatal errorE900类 ------------------ 标准（其它）error error#100 REC ERROR#200 REC ERROR#300 REC ERROR#400 REC ERROR编号 内容原因 解决方法行程末端浮动功能的设备种类) 【解决方法】请在从末端起多于 4mm 的内侧进行锁定。

ZH感谢您购买Yamaha 数字键盘！为了充分利用本乐器高级而又方便的功能，我们建议您仔细阅读本说明书。

也建议您将本说明书放置于安全便捷的地方，以便将来随时参阅。

使用本乐器之前，务必阅读第4–5页上的注意事项。

使用说明书电子琴2PSR-E233/YPT-230使用说明书3PSR-E233/YPT-230使用说明书注意事项请在操作使用前，首先仔细阅读下述内容* 请将本说明书存放在安全的地方，以便将来随时参阅。

警告为了避免因触电、短路、损伤、火灾或其它危险可能导致的严重受伤甚至死亡，请务必遵守下列基本注意事项。

这些注意事项包括但不限于下列情况：•请勿将电源线放在热源如加热器或散热器附近，不要过分弯折或损伤电源线，不要在其上加压重物，不要将其放在可能被踩踏引起绊倒或可能被碾压的地方。

•只能使用本乐器所规定的额定电压。

所要求的电压被印在本乐器的铭牌上。

•只能使用规定的适配器（第42页）。

使用不适当的适配器可能会损坏乐器或使乐器过热。

•定期检查电插头，擦除插头上积起来的脏物或灰尘。

•本乐器不含任何用户可自行修理的零件。

请勿打开本乐器或试图拆卸其内部零件或进行任何方式的改造。

若出现异常，请立即停止使用，并请有资质的Y amaha维修人员进行检修。

•请勿让本乐器淋雨或在水附近及潮湿环境中使用，或将盛有液体的容器（如花瓶、瓶子或玻璃杯）放在其上，否则可能会导致液体溅入任何开口。

如果任何液体如水渗入本器，请立即切断电源并从AC电源插座拔下电源线。

然后请有资质的Y amaha维修人员对设备进行检修。

•切勿用湿手插拔电源线插头。

•请勿在乐器上放置燃烧着的物体，比如蜡烛。

燃烧的物体可能会倾倒并引发火灾。

•请务必同时更换所有电池。

请勿混用新旧电池。

•请勿混用不同类型的电池，如将碱性电池与锰电池混用、混用不同厂家的电池或同一厂家不同类型的电池，否则可能会导致过热、火灾或电解液泄漏。

•切勿玩弄或拆卸电池。

•请勿在火中处理电池。

3B Series 4 Channel Backplane3B03Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 Fax: 781.326.8703© 2005 Analog Devices, Inc. All rights reserved.FEATURESMix and Match 3B Series I/O Module Capability Factory Mutual (FM) Approved CE Certified+1500 V peak Channel/Channel and Input/Output Isolation -25o C to +85o C Temperature Range LEDs indicate when power is appliedReplaceable AC Line Fuse in Protective Housing Versatile Mounting OptionsAPPLICATIONSIndustrial Signal Conditioning Industrial Signal Isolation Industrial Signal FilteringPRODUCT OVERVIEWTo address diverse applications, the 3B Subsystem Seriesincludes a family of backplanes which provide a complete signal conditioning solution. The 3B03 is designed for 4 channels to offer users the flexibility to match the size of a system to specific applications. All backplanes are provided with #6-32 x 1-inch screws and standoffs for mounting. Several mounting options are available, including rack, surface and NEMA enclosure. All 3B Series modules feature a universal pin out and can be easily tailored to fit the user’s application. Each backplane can accommodate any 3B Series module in a “Mix and Match”arrangement.Modules are “Hot Swappable”; power does not have to be removed when inserting or removing any module on the backplane.All backplanes provide a four screw terminal for each individual channel’s input field connections. These connections satisfy all transducer inputs and provide transducer excitation when necessary.FUNCTIONAL BLOCK DIAGRAMFigure 1 3B03 Functional Block DiagramA cold junction temperature sensor is also supplied on each channel to accommodate thermocouple input modules. Each channel has two screw terminals for the outputconnections for the 4-20 mA output signals. Two 26-pin system connectors provide high level voltage I/O for all channels. Figure 1 illustrates the 3B Series backplane functional block diagram. In addition, complete specifications are shown in the table below.3B03Rev. 0 | Page 2 of 6GENERAL DESCRIPTIONThe 3B03 Series backplane provides the user with four channels, any of which may be used with any of the 3B series of modules offered by ADI.This backplane have been designed to operate in a wide temperature range, from -25o C up to +85o CThe 3B03 Series backplane has been evaluated by both Factory Mutual and also by CSA. The 3B03 has passed all agency testing and is listed by both organizations. In addition the 3B03 series back plane is also CE certified. The 3B03 backplane has several mounting options:o Surface Mount – stand alone or using Surface MountKit, model AC1333o 19-inch Rack Mount Kit model AC1330.Figure 23B03Rev. 0 | Page 3 of 63B03 Specifications(typical @ +25°C and ±15 V dc, and +24 V dc Power)Description Model 3B03Number of Channels 4 ISOLATIONInput-to-Output Continuous Channel-to-Channel Continuous1500 V rms, Maximum 1500 V rms, Maximum MECHANICAL DIMENSIONS – with modules7.8” x 5.2” x 4.373”(198.12 mm x 132.08 mm x 111.07 mm)Mounting Standoffs4 COLD JUNCTION TEMPERATURE SENSORS Number provided on backplane Initial Accuracy @ +25o C Accuracy +5o C to +45o C 4 +0.5o C+0.5o C (+0.0125o C/o C) SYSTEM I/O CONNECTOR Number Type2, 26-pin Amp 746290-6 POWER SUPPLY OPTIONS Voltage; AC Power Supply Voltage; DC Power Supply Voltage; External Supplies Fuse; AC Power Supply 115 VAC +25 VAC+15 VDC and +24 VDC 220 VAC @ 500 mAPOWER INDICATORLED’s indicate +15 VDC and + 24 VDC Power Applied EnvironmentalTemperature Range Rated Performance-25°C to +85°COperating -25°C to +85°C Storage -40°C to +85°CRelative Humidity, 24 hours 0 to 95% @ +60°C noncondensing3B03Rev. 0 | Page 4 of 6OUTLINE DIMENSIONSFigure 3 Outline Dimensions3B03 NOTESRev. 0 | Page 5 of 63B03Rev. 0 | Page 6 of 6NOTES© 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. D05409-0-2/05(0)。