SERIES B Operations Research B-422 Dynamic Enumeration of All Mixed Cells
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6630B Series Single-Output, 80-100 W GPIB Power SuppliesData SheetSpeed and accuracy for test optimizationThis series of linear-regulated 80-100 W DC power supplies is designed to max-imize the throughput of DUTs through the manufacturing test process. Both programming and measurement are optimized for speed. The active downprogrammer can sink up to the full rated current of the power supply, which quickly brings the power supply output to zero volts. The 6630B series offers many advanced programmable features including stored states and status reporting. Programming is done using industry standard SCPIcommands via the GPIB or RS-232. Test system integration is further simplified by using the VXI plug&play drivers. The optional relays simplify system design and troubleshooting.The optional front panel binding posts make the 6630B series convenient on the R&D lab bench. The built-in microamp measurement system helps the engineer to easily and accurately monitor the output voltage and currentwithout a complicated test setup.• Fast, low-noise outputs• Programmable active down-programmer sinks the full rated current • Dual-range, precision low current measurement • Optional isolation and polarity reversal relays• Built-in measurements and advanced programmable features • Protection features to ensure DUT safety 1981Specifications23Agilent Models: 6631B, 6632B 6633B, 6634BTopRearSupplemental characteristics for all model numbersDC floating voltage: Output terminals can be floated up to ± 240 VDC maximum from chassis ground Remote sensing: Up to two volts dropped in each load lead. Add 2 mV to the voltage load regulation speci-fication for each one volt change in the positive output lead due to load current change.Command processing time: Average time required for the output voltage to begin to change following receipt of digital data is 4 ms for the power supplies connected directly to the GPIB. (Display disabled).Output programming response time: The rise and fall time (10/90% and 90/10%) of the output voltage is less than 2 ms (400 μs in fast mode). The output voltage change settles within 1 LSB (0.025% x rated voltage) of final value in less than 6 ms (2 ms in the fast mode).GPIB interface capabilities: IEEE-488.2, SCPI command set, and 6630A Series programming compatibilitySoftware driver: VXI plug&play Measurement time : Average time to make a voltage or current measurement is 50 ms.Input power (full load): 3.5 A, 250 W Regulatory compliance: Complies with EMC directive 89/336/EEC (ISM 1B). Size:425.5 mm W x 88.1 mm H x 364.4 mm D (16.8 in x 3.5 in x 14.3 in)Weight: Net, 12.7 kg (28 lb) net; 15.0 kg (33 lb) shipping Warranty: One yearAgilent Email Updates/find/emailupdatesGet the latest information on the products and applications you select.Agilent Channel Partnersw w w /find/channelpartners Get the best of both worlds: Agilent’s measurement expertise and product breadth, combined with channel partner convenience.For more information on AgilentTechnologies’ products, applications or services, please contact your local Agilent office. The complete list is available at:/fi nd/contactusAmericas Canada (877) 894 4414Brazil (11) 4197 3600Mexico01800 5064 800United States(800) 829 4444Asia Pacifi c Australia 1 800 629 485China 800 810 0189Hong Kong 800 938 693India 1 800 112 929Japan 0120 (421) 345Korea 080 769 0800Malaysia 1 800 888 848Singapore 180****8100Taiwan 0800 047 866Other AP Countries (65) 375 8100Europe & Middle East Belgium 32 (0) 2 404 93 40Denmark 45 45 80 12 15Finland 358 (0) 10 855 2100France 0825 010 700**0.125 €/minuteGermany 49 (0) 7031 464 6333Ireland 1890 924 204Israel 972-3-9288-504/544Italy39 02 92 60 8484Netherlands 31 (0) 20 547 2111Spain 34 (91) 631 3300Sweden0200-88 22 55United Kingdom 44 (0) 118 927 6201For other unlisted countries: /fi nd/contactusRevised: January 6, 2012Product specifications and descriptions in this document subject to change without notice.© Agilent Technologies, Inc. 2012Published in USA, January 26, 20125990-9303EN/find/6630Agilent Advantage Services is committedto your success throughout your equip-ment’s lifetime. To keep you competitive, we continually invest in tools andprocesses that speed up calibration and repair and reduce your cost of ownership. You can also use Infoline Web Services to manage equipment and services more effectively. By sharing our measurement and service expertise, we help you create the products that change our world./quality/find/advantageservicesOrdering informationOpt 100 87 to 106 VAC, 47 to 63 Hz Opt 120 104 to 127 VAC, 47 to 63 Hz Opt 220 191 to 233 VAC, 47 to 63 Hz Opt 230 207 to 253 VAC, 47 to 63 Hz Opt 020 Front-panel binding posts (N/A on 6631B)Opt 760 Isolation and reversal relays, only available at time of order (not available on the 6631B)Opt 8ZJ R emoves feet for use in a racked systemOpt 0L1 Full documentation on CD-ROM, and printed standard docu-mentation package. CD-ROM includes User’s Guide, Programming Guide, Service Manual and Quick Start Guide Opt 0B3 Service manual Accessoriesp/n 1494-0060 Rack slide kitE3663AC Support rails for Agilent rack cabinets1CM002A* Rack mount flange kit 88.1mm H (2U), two flange brackets: 1.75 inch hole spacing1CP001A* Rack mount flange and handle kit 88.1 mm H (2U), two brackets and front handlesApplication notes10 Practical Tips You Need to Know About Your Power Products , 5965-8239E10 Hints for Using Your Power Supply to Decrease Test Time , 5968-6359E Understanding Linear Power Supply Operation (AN1554), 5989-2291EN* Support rails required。
The bhyve Operator's ManualMichael DexterAsiaBSDCon 2013OVERVIEWbhyve is a legacy-free Type-2 hypervisor for FreeBSD that was imported into the mainline FreeBSD development repository in January of 2013 with svn revision r245652. A hypervisor allow for the operation of one or more guest operating systems within a host operating system. As a legacy-free hypervisor, a bhyve host requires the Extended Page Tables (EPT) feature found on "Nehalem" and newer generations of Intel processors. This requirement eliminates the need for memory management routines that are traditionally implemented in software and yields virtually bare metal guest performance. A bhyve guest requires VirtIO network and block devices, which were already available in FreeBSD 8-STABLE, 9-STABLE and 10-CURRENT at the time of bhyve's import. If these two requirements are satisfied, the bhyve host and guests will operate in the established FreeBSD manner.HARDWARE REQUIREMENTSThe presence of the Extended Page Table (EPT) feature can be determined by examining the host's demesg(8) output for the presence of the POPCNT (POP Count) feature as the two are coupled but not related. Established dynamic memory and storage requirements apply otherwise with the caveat that there is a 1:1 relationship between the deduction of dynamic memory from the host and its allocation to guests.SOFTWARE REQUIREMENTSA FreeBSD 10-CURRENT system from svn revision r245652 onward will include all of the necessary bhyve host components: the vmm(4) kernel module, the libvmmapi library and the bhyveload(8),bhvye(8) and bhyvectl(8) utilities.A suitable FreeBSD 8-STABLE, 9-STABLE or 10-CURRENT guest can exist in a disk image or any valid storage device and only requires a modified /etc/ttys entry to work. All other options can be specified at runtime at the loader prompt. Permanent configuration changes however are generally desired and will be demonstrated.Permanent /etc/ttys configuration (can be appended):console "/usr/libexec/getty std.9600" vt100 on secureBoot time or permanent /etc/fstab configuration for a MBR-partitioned device:# Device Mountpoint FStype Options Dump Pass# /dev/vtbd0s1a / ufs rw 1 1or for a GPT-partitioned device:# Device Mountpoint FStype Options Dump Pass# /dev/vtbd0p1 / ufs rw 1 1 Example runtime or permanent /etc/rc.conf networking configuration:ifconfig_vtnet0="DHCP"Depending on how your guest is built, the /boot/loader.conf may require:virtio_load="YES"if_vtnet_load="YES"virtio_pci_load="YES"virtio_blk_load="YES"BHYVE OPERATIONAt a minimum, a bhyve host requires that the vmm.ko kernel module be loaded:su kldload vmmTo enable guest networking, load the if_tap.ko kernel module and create a tap(4) interface (tap0 on em0 as an example):su kldload if_tapsu ifconfig tap0 createsu ifconfig bridge0 addm tap0 addm em0 upsu ifconfig tap0 upThe host and guest are now configured for bhyve operation. The bhyve guest bootstrap process is a two-stage operation not unlike that of the host. The bhyveload(8) utility loads the guest kernel into memory and the bhyve(8) utility executes it. These commands should be run in tight sequence with identical memory, storage device and guest name parameters.All configuration parameters forward will be highly site-specific.su /usr/sbin/bhyveload -m 256 -M 0 -d mydiskimage myguestnamesu /usr/sbin/bhyve -a -A -m 256 -M 0 -I -H -g 0 \-s 0:0,hostbridge \-s 1:0,virtio-net,tap0 \-s 2:0,virtio-blk,mydiskimage \-S 31,uart,stdio \myguestnameAssuming a successful boot, the guest should behave like a standard FreeBSD system and'shutdown -p now' will cleanly shut it down.If you wish to terminate a guest at the loader prompt, simply type 'quit'.Executing guests can be viewed by name on the host system with:su ls /dev/vmmThe above bootstrap procedure will not free the memory allocated to the guest but it can be freed using bhyvectl(8):su /usr/sbin/bhyvectl --vm=myguestname --destroyPRAGMATIC BHYVE GUEST OPERATIONThe above procedures do not address the subjective matter of populating and configuring the guest userland or automating the guest operation lifecycle.Two efforts exist to automate the building and operation of bhyve guests.bhyve developer Neel Natu provides a script named 'vmrun.sh' that works in conjunction with a FreeBSD 10-CURRENT installation iso image named 'release.iso' to automate the creation of a bootable disk image named 'diskdev' that can be populated using the standard FreeBSD installer. This script provides an 8G disk image and 512M of dynamic memory by default but these parameters can be easily modified at runtime or by modifying the script.The 'vmrun.sh' script requires only a guest name such as 'vm1':su vmrun.sh vm1Mr. Natu's script and instructions can be obtained from:/~neel/bhyve/vmrun.sh/~neel/bhyve/bhyve_instructions.txtA suitable 10-CURRENT 'release.iso' image can be retrieved from:/pub/FreeBSD/snapshots/amd64/amd64/ISO-IMAGES/10.0/ Note that the versioning prefix must be removed for the iso to work.Alternatively, the web site provides a series of scripts that facilitate the creation and operation of bhyve guests in a highly-customizable manner.While evolving, at the time of writing these scripts include:0-make-softdevice.sh Create and mount a disk image or zvol1-format-device.sh Format the disk image or zvol1-format-zvol-gpt.sh Format a zfs zvol with a GPT layout2-install-guest.sh Populate the disk image with the OS3-host-prep.sh Prepare the host for bhyve and networking4-boot-guest.sh Boot the guest5-cleanup-guests.sh Clean up after the guestmount-diskdev.sh Mount a specified disk imageIn addition to the basic functionality provided by 'vmrun.sh', these scripts create and format disk images in MBR and GPT format, format zvol, iSCSI and hardware devices, populate FreeBSD 8-STABLE, 9-STABLE and 10-CURRENT userlands from the official mirrors and facilitate guest operation.Any and all jail(8) and NanoBSD configuration strategies should be applicable to bhyve and the creation of "thick" and "thin" bhyve hosts and guests.THE BHYVE DEVELOPMENT ENVIRONMENTAs a native FreeBSD 8-STABLE and later on FreeBSD 10-CURRENT computing environment, bhyve provides the ideal infrastructure for all categories of FreeBSD development. The hard partitioning provided by the vmm virtual machine manager allows the "unstable" FreeBSD 10-CURRENT environment to be used for "stable" FreeBSD 8 and 9 development with far fewer potential risks than emulated or jailed environments. Common development nuisances such as library incompatibilities are eliminated by the virtual machine divide.The inclusion of dtrace(1M) in FreeBSD 10-CURRENT provides an unprecedented level of system introspection that should prove invaluable to FreeBSD, bhyve and future foreign guest operating systems.Some rudimentary DTrace examples:su kldload dtraceallsu dtrace -n 'io:::start /execname == "bhyve"/ { @[ustack()] = count(); }' libc.so.7`0x800ed3fdabhyve`pci_vtblk_qnotify+0x59bhyve`pci_vtblk_write+0x220bhyve`pci_emul_io_handler+0x16ebhyve`emulate_inout+0x197bhyve`vmexit_inout+0x155bhyve`vm_loop+0x118bhyve`fbsdrun_start_thread+0x87libthr.so.3`0x800c53413505The sysutils/DTraceToolkit port provides FreeBSD-specific DTrace scripts.su /usr/share/dtrace/toolkit/hotuser -p `pgrep -n bhyve`Sampling... Hit Ctrl-C to end.^CFUNCTION COUNT PCNTbhyve`vm_loop 1 1.8% libvmmapi.so.5`0x800838920 1 1.8% libthr.so.3`0x800c59491 1 1.8% libthr.so.3`0x800c58df1 1 1.8% libvmmapi.so.5`0x800838950 1 1.8% libthr.so.3`0x800c5992f 1 1.8%libc.so.7`0x800f83bb3 1 1.8%bhyve`emulate_inout 1 1.8%libc.so.7`0x800ed3fd0 1 1.8% libthr.so.3`0x800c594c1 1 1.8%bhyve`pci_vtblk_write 1 1.8%bhyve`pci_vtblk_proc 1 1.8% libvmmapi.so.5`0x800838a78 2 3.6% libvmmapi.so.5`0x800838a2e 5 8.9%bhyve`vmexit_inout 6 10.7%libc.so.7`0x800f8875a 31 55.4%su /usr/share/dtrace/toolkit/hotkernelSampling... Hit Ctrl-C to end.^CFUNCTION COUNT PCNT vmm.ko`vm_guest_msrs 1 0.0% vmm.ko`vcpu_set_state 1 0.0% vmm.ko`vmx_setreg 1 0.0% vmm.ko`vm_nmi_pending 1 0.0% vmm.ko`vm_get_register 1 0.0% vmm.ko`lapic_intr_accepted 1 0.0% vmm.ko`vm_lapic 1 0.0% vmm.ko`vlapic_op_mem_read 2 0.0% vmm.ko`lapic_mmio_write 2 0.0% vmm.ko`vlapic_intr_accepted 2 0.0% vmm.ko`vm_set_register 2 0.0% vmm.ko`lapic_pending_intr 3 0.0% vmm.ko`vmm_fetch_instruction 3 0.0% vmm.ko`vmmdev_ioctl 3 0.0% vmm.ko`vmmdev_ioctl 3 0.0% vmm.ko`vm_exitinfo 3 0.0% vmm.ko`vcpu_stats 3 0.0% vmm.ko`vmm_emulate_instruction 4 0.0% vmm.ko`vmx_getreg 4 0.0% vmm.ko`lapic_timer_tick 5 0.0% vmm.ko`vm_gpa2hpa 7 0.0% vmm.ko`vlapic_pending_intr 7 0.0% vmm.ko`vlapic_op_mem_write 7 0.0% vmm.ko`vmm_decode_instruction 19 0.0% vmm.ko`vmcs_read 20 0.0% vmm.ko`ept_vmmmap_get 21 0.0% vmm.ko`vlapic_timer_tick 29 0.0% vmm.ko`vm_run 30 0.0% vmm.ko`restore_guest_msrs 32 0.0% vmm.ko`restore_host_msrs 42 0.0% vmm.ko`vlapic_update_ppr 142 0.1% vmm.ko`vmx_run 33275 16.3% kernel`acpi_cpu_c1 168750 82.6%In addition to the DTrace suite, the bhyvectl(8) command provides extensive bhyve-specific profiling information:su bhyvectl --get-lowmem --vm=guest0lowmem 0x0000000000000000/268435456su bhyvectl --get-stats --vm=guest0vcpu0number of ticks vcpu was idle 5244097number of NMIs delivered to vcpu 0vcpu migration across host cpus 1186676vm exits due to external interrupt 2229742number of times hlt was ignored 0number of times hlt was intercepted 2158532vcpu total runtime 288974908299BHYVE REFERENCEThe following options are available to the bhyveload(8) and bhyve(8) commands:Usage: bhyveload [-d <disk image path>] [-h <host filesystem path>] [-m <lowmem>] [-M <highmem>] <vmname>Usage: bhyve [-aehABHIP] [-g <gdb port>] [-z <hz>] [-s <pci>] [-S <pci>] [-p pincpu] [-n <pci>] [-m lowmem] [-M highmem] <vm>-a: local apic is in XAPIC mode (default is X2APIC)-A: create an ACPI table-g: gdb port (default is 6466 and 0 means don't open)-c: # cpus (default 1)-p: pin vcpu 'n' to host cpu 'pincpu + n'-B: inject breakpoint exception on vm entry-H: vmexit from the guest on hlt-I: present an ioapic to the guest-P: vmexit from the guest on pause-e: exit on unhandled i/o access-h: help-z: guest hz (default is 100)-s: <slot,driver,configinfo> PCI slot config-S: <slot,driver,configinfo> legacy PCI slot config-m: lowmem in MB-M: highmem in MB-x: mux vcpus to 1 hcpu-t: mux vcpu timeslice hz (default 200)FUTURE DEVELOPMENTSbhyve contains experimental PCI device pass-through support and is scheduled to include: • AMD Virtualization Extensions• Foreign Guest Operating System Support• ACPI Guest Suspend and Resume• Thin Provisioning of Memory• Generalization of CPUID Features for Guest Migratability• Sparse Image Support such as QCOW, VDI and VMDK• Porting to other Host Operating Systemsbhyve is arguably the most compelling FreeBSD development since jail(8) and continuesFreeBSD's tradition of providing innovative multiplicity options to operators and developers. jail(8) and bhyve are by no means mutually-exclusive technologies and should provide value when used in conjunction with one another in parallel or via encapsulation. bhyve also promisesto make the most of recent FreeBSD features such as the DTrace, the ZFS filesystem and FreeBSD’s virtual network stack. The fundamental point to remember about bhyve is that a FreeBSD bhyve system is simply a FreeBSD system that will fully leverage your FreeBSD administration and development experience.。
F618D - Foxboro I/A Series TM redundant fieldbus power systemINM F618DCONTENTS PAGE1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 COMPONENTS AND ACCESSORIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 MECHANICAL INSTALLATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2 Mounting overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.3 Surface mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.4 DIN-rail mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ELECTRICAL INSTALLATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45.1 Redundant Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45.2 FPS-ALM alarm modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45.3 Alarm contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45.4 FPS-IPM power modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45.5 Module Fieldbus connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55.6 Segment connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55.7 F809F diagnostic module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55.8 Address switch settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 TESTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 ROUTINE MAINTENANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7© 2008 MTL Instruments Group plc. All rights reserved.1 OVERVIEWThis manual explains the installation of the F618D redundant F OUNDATION fieldbus™ power system specifically designed for a Foxboro I/A Series® Control System using FBM228 modules.The MTL-Relcom redundant fieldbus power system (FPS-Series) provides redundant power conditioning for fieldbus network segments and facilitates the connection of redundant input power supplies.In general purpose, safe area applications, the system is fully ‘hot-swappable’ - meaning that individual power conditioning modules and input power supplies can be replaced without interrupting power or communication on the fieldbus segment.An alarm circuit provides warning in case of a power conditioning module or input power supply failure. The system is designed so that power for several fieldbus segments can be provided from a single assembly with minimal wiring.2 COM PONENTSANDACCESSORIESAn F618D system comprises the following components, as described below.F618D-CL Qty1FPS-IPM Qty16FPS-ALM Qty2It does not include the Foxboro FBM228 F OUNDATION fieldbus™Interface, or the optional F809F Fieldbus Diagnostic module.PART No DESCRIPTIONF618D-CLF618D baseplateFPS-IPMP ower moduleFPS-ALMA larm moduleF809FF ieldbus Diagnostic moduleFPS-BLK10B lanking module, pack of 10 (see text)INM F618D-2Sept 20083 DESCRIPTIONThe system comprises a baseplate that accommodates two redundant pairs of Foxboro FBM228 modules, and two MTL-Relcom FPS-IPM power modules for each of the eight fieldbus segments. The FPS-IPM modules function as redundant power conditioners, providing isolation and impedance between the input DC power supply and the fieldbus.A fieldbus terminator is provided on the baseplate for each of the eight fieldbus segments.Primary and secondary 24V DC input power is applied through two connectors provided on the baseplate and each fieldbus segment is provided with two-part pluggable terminals.Two sub-minature 9-way ‘D’ connectors provide the means of connection for the Foxboro ‘fieldbus’.Two alarm modules (type FPS-ALM) are fitted. Each one monitors the state of 4 redundant pairs of power conditioning modules and also the power inputs. If a fault is detected in any of these components, the alarm relay opens and an LED provides visual indication of the fault. This enables failed components to be identified and replaced, so that the integrity of the power system is maintained. The alarm relay output is galvanically isolated from the fieldbus segments and input power supplies.G reen LEDs on the power modules and two LEDs on each alarm module gives clear visual indication that the components are functioning properly.The baseplate may be mounted onto either vertical DIN rails or a flat panel. DIL switches on the circuit board allow the address of each baseplate to be set in accordance with Foxboro requirements. Available accessories include blanking modules that allow the baseplate to be operated in non-redundant powered mode with a single FPS-IPM module per segment.A separate, physical layer, fieldbus diagnostics module, type F809F, may be installed on the baseplate to automatically collect and distribute additional diagnostic information for each of the eight fieldbus segments.F618D - Foxboro I/A Series™ redundant fieldbus power system - F618D assembly4 M ECHANICAL INSTALLATIONImportant dimensions for the F618D baseplate are shown in Figure 4.1. The absolute maximum height from the underside of the board, including the front mounted connector on the F809F module, is 155mm.4.1 GeneralThese power systems may be mounted only in safe areas and wherever they are located, the mounting conditions must:(a) prevent any form of pollution that could compromise theoperation of the unit. For example, an unpolluted location or a suitable enclosure could be chosen.(b) provide an adequate level of mechanical protection. This can beachieved by selecting a protected location, a suitable cabinet or enclosure, or a combination of both.(c) ensure that all cable entries and connections are secure by makingprovision for the careful routing and securing of all cables.(d) provide adequate security against unauthorised interference.(e) ensure that the permitted ambient temperature range of the units(–40°C to + 60°C) is not exceeded. Power dissipation within the cabinet or enclosure and the use of shading against direct sunlight should be considered.4.2 M ounting overviewIt is recommended that the F618D baseplate is mounted on a vertical surface with the orientation of the IPM modules as shown in Figure 4.1 above. Any other orientation will not provide optimum airflow for the FPS-IPM power conditioning modules. Nine 5mm diameter mounting holes are provided for surface or DIN-rail mounting.MTL mounting kits - type SMS01 for surface mounting or DMK01 for DIN rail mounting - may be used for this purpose. 4.2.1 Outdoor mountingIf the assembly is to be mounted in an outdoor location, a suitable enclosure with a minimum of IP54 ingress protection is required. However, in some locations, a higher degree of ingress protection rating is recommended as corrosion resistance may be necessary or desirable and the emphasis should be placed on the suitability for the application.4.3 Surface mountingSurface mounting kit (type SMS01) is available for this purpose. SMS01 contains 40 sets of the components shown in Figure 4.2.4.3.1 Prepare panel Refer to figure 4.1.a) Prepare holes in the mounting surface at the centres shown.Thread these (M4) if retaining nuts will not be used.Figure 4.2 - SMS01 mounting kit components4.3.2 Fit baseplate Refer to figures 4.1 and 4.3.a) Select an M4 x 20mm screw (A).b) Place a locking washer (B) and a plain washer (C) over it.c) Insert the screw through a fixing hole on the baseplate.d) Fit a 10mm spacer (D) and retain it with washer (E).e) Repeat steps a) to d) for the other eight (8) mounting holes. f) Attach the baseplate using the prepared panel holes. Retain thescrews with a suitable nut if the holes are not tapped.4.4 DIN-rail mountingDIN-rail mounting kits (type DMK01 or DMK04) are available for this purpose. DMK01 contains 40 sets of the components shown in Figure4.4, while DMK04 contains 4 sets of these components.4.4.1Prepare DIN rail (Refer to Figure 4.1 & 4.5)a) Select three pieces of DIN-rail (T- or G-section) of the appropriatelength for the number of F618D baseplates to be mounted.b) Mount the lengths of DIN-rail vertically and in parallel. Measuringfrom the lefthand rail, mount the other two rails on 185mm and 340mm centres. See Figure 4.5.4.4.2 Fit baseplate Refer to figures 4.1 and 4.6.a) Select a mounting screw (A).b) Place a locking washer (B) and a plain washer (C) over it.c) Insert the screw through a fixing hole on the baseplate.d) Fit a spacer (D) and retain it with washer (E).e) Attach a DIN-rail mounting foot (F) to the baseplate using the screw.f) Repeat steps a) to e) for the other eight (8) mounting holes.g) Align the baseplate’s mounting feet with the DIN rail then pressthem onto it and finally, tighten the mounting-foot screws.Additional notes:h) For vertically orientated baseplates use an end stop at the lowerend of each DIN-rail to help support a column of carriers.i) Additional end stops, attached between baseplates, will increasethe stability of tall columns of baseplates.Figure 4.4 - DMK0x mounting kit components5 ELECTRICAL INSTALLATIONOther stages of the installation may be carried out in the order of the installer’s choosing.5.1 Redundant Power ConnectionsPrimary and secondary power terminals are located at the top righthand corner of the baseplate (see Figure 5.1). These accept standard Foxboro (P0926Kx) style power cables supplying redundant inputs of nominally 24V dc. The cable length to these bulk supply inputs will ideally be limited to a few metres within a single cabinet, but never to exceed a maximum of 30 metres.5.1.1 Over-current protectionA fully populated F618D baseplate (including all FPS-IPM power modules, FPS-ALM alarm modules, F809F Fieldbus diagnostic module and FBM228 Fieldbus interface modules) draws a maximum current of 6.1A at 24V DC input (5.6A typical). Suitably rated fuses or circuit breakers must be installed in the primary and secondary 24V DC power supply connections. For example, a rating of 10A is suitable for protection of a single F618D baseplate. This rating is required in the primary and secondary sources of supply, to ensure continued operation in the event of a failure of one supply. If a single means of over-current protection is provided for multiple baseplates, the power supply wiring must be capable of sustaining the short-circuit current.5.2 FPS-AL M alarm modulesThe two FPS-ALM alarm modules should be fitted at this stage prior to the fitting of the FPS-IPM modules. Identify their locations on the baseplate (refer to Figures 1.1 and 4.1), fit and secure them with their two fixing screws.5.3 Alarm contactsThe two alarm modules fitted to the baseplate respond to the failure of individual IPM power conditioners for which they are responsible. In addition, they will respond create an alarm condition if the voltage of the bulk supplies drops below 18V.A “failure” of an IPM module, or one of the bulk power supplies, will cause relay contacts in the appropriate alarm module to open. Two screw terminals A1 & A2 are provided on the baseplate (see Figure 5.1) to make connection to the alarm relay’s switch contacts. These terminals are the ends of a series connection of both alarm modules (see Figure 5.2). The alarm contacts may be daisy-chained with the alarm contacts on other F618D baseplates.5.4 FPS-IP M power modules5.4.1Fitting working modulesThe IPM modules should be fitted in a particular order and checks carried out after the addtion of each module. The following procedure is recommended.1 Ensure that the primary and secondary 24V DC power isconnected and applied.2 Install an FPS-IPM module in location '1A', and check for avoltage in the range 25.0 to 27.5V between the + and - terminals of the Segment 1 field wiring connector.3 Install a second (redundant) FPS-IPM module in location '1B',and repeat the measurement.4 Install the remaining FPS-IPM modules for segments 2 - 8(in locations 2A through to 8B), checking output voltage at the appropriate field wiring connectors.5 Check for a short-circuit between the alarm relay terminalsA1 and A2, indicating that no fault is present. A fault may be simulated by removing any FPS-IPM power module or by removing the primary or secondary power, in which case an open circuit will appear between terminals A1 and A2.5.4.2Fitting blanking modulesIf redundancy for the power conditioning is not required, or an FPS-IPM module has been temporarily removed, a “blanking module” (part number FPS-BLK) may be inserted in the baseplate connector in place of an FPS-IPM module.The purpose of this module is to provide continuity for the alarm circuit so that an alarm is not signalled when an FPS-IPM module isabsent.Figure 5.1 - Alarm and Power connectionsFigure 5.3 - FPS-BLK blanking moduleThis ensures that the F809F ground connection, used for its +S –+S –+S –+S –Figure 5.7 - Ground reference switch at '0'Figure 5.8 - Optional ground link wire6 TESTINGCheck that all the FPS-IPM power module green LEDs are lit.Remove each FPS-IPM power module (and replace in turn) and check that its associated FPS-ALM alarm module LED illuminates. Check also that the alarm chain is broken, i.e. the connection between A1 and A2 should go open circuit when a module is removed. The red alarm LED on the corresponding FPS-ALM alarm module will also illuminate. Disconnecting the primary and secondary power inputs, in turn, should also cause the alarm condition, and extinguish the power modules’ green LED. On completion of the testing, check once again that all power module green LEDs are lit.M AINTENANCE7 ROUTINECheck the general condition of the installation occasionally to make sure that no deterioration has occurred. At least every two years (and more frequently for particularly harsh environments) check:◆the condition of wire connection/terminations/screens◆that the dc output voltage on each of the four fieldbus segments is>25V. This can be performed using a multimeter or a MTL-Relcom FBT-3 or FBT-6 fieldbus tester◆that the Power A and Power B LEDs on the FPS-ALM module arefunctioning◆that the LEDs on all 16 FPS-IPM modules are on◆that all of the retaining screws are tight◆that there are no signs of damage or corrosionINM F618D-2 Sept 20087Group Internet home page /Members of The MTL Instruments Group MTL Instruments Pty Limited1/30 Canvale RoadCanning ValePerth, WA 6155AustraliaTel: +61 (0)8 9455 2994 Fax: +61 (0)8 9455 2805E-mail:********************.auMTL Canada Safety Instrumentation#102, 4249 97 StreetEdmonton, AlbertaCanada T6E 5Y7Tel: +1 780 485 3132 Fax: +1 780 485 3122E-mail:***************MTL Instruments China Co. Ltd.Room 1002A, The GatewayNo 10 Yabao Road, Chaoyang DistrictBeijing 100020ChinaTel: +86 010 8562 5718/5720/5721 Fax: +86 010 8562 5725E-mail:*******************MTL Instruments sarlLes Carrés du Parc10 rue des Rosiéristes69410 Champagne au Mont d’OrFranceTel: +33 (0)4 78 64 98 32 Fax: +33 (0)4 78 35 79 41E-mail:****************MTL Instruments GmbHAn der Gümpgesbrücke 17D-41564 KaarstGermanyTel: +49 (0)2131 718930 Fax: +49 (0)2131 7189333E-mail:***********MTL IndiaNo. 36, Nehru StreetOff Old Mahabalipuram RoadSholinganallurChennai - 600 119IndiaTel: + 91 (0)44 24501660/24501857 Fax: + 91 (0)44 24501463E-mail:******************MTL Italia srl Via Cantù 11I - 20092 Cinisello Balsamo MI Italy Tel: +39 (0)2 61802011 Fax: +39 (0)2 61294560E-mail:****************MTL Instruments KK 3rd Floor, Gotanda Masujima Building 1-8-13 Higashi-Gotanda, Shinagawa-Ku Tokyo 141-0022Japan Tel: +81 (0)3 5420 1281 Fax: +81 (0)3 5420 2405E-mail:**************.jp MTL Instruments BV PO Box 55, 6680 AB Bemmel de Houtakker 36, 6681 CW Bemmel The Netherlands Tel: +31 (0)481 450250 Fax: +31 (0)481 450260E-mail:*******************MTL Instruments Pte Limited 31 Ubi Road 1#04-01 Aztech Building Singapore 408694Tel: +65 6 487 7887 Fax: +65 6 487 7997E-mail:*****************.sg MTL Instruments Villa No. 4, Sector 2-17, Street 6PO Box 53234, Abu Dhabi, UAE Tel: +971 2 446 6840 Fax: +971 2 446 6841E-mail:********************Measurement Technology Limited Power Court, Luton, Bedfordshire England LU1 3JJ Tel: +44 (0)1582 723633 Fax: +44 (0)1582 422283E-mail:********************MTL Incorporated 4001 W. Sam Houston Parkway N., Suite 150 Houston TX 77043USA Tel: +1 281 571 8065 Fax: +1 281 571 8069E-mail:*****************。
18/005/98SEW Encoder SystemsManualEdition 07/990919 6412 / 07992SEW encoder systems01861AEN Fig. 1: Unit designation of SEW encoder systems E S 1 T E Incremental encoder (encoder)A Absolute encoder N Proximity sensor X Non-SEW encoder S Spread shaft V Solid shaft H Hollow shaft E n c o d e r t y p e S h a f t d e s i g n S p e c i f i c a t i o n I n t e r f a c e t o e v a l u a t i o n A Design as mounting device C V = 24 V , HTL with zero track and negated signals R V = 24 V , TTL RS-422S V = 24 V , sin/cos 1 V T V = 5 V , TTL RS-422Y SSI interface 6 Number of pulses per revolution (proximity sensor)DC DC DC SS DC 12DesignPage 1System Description (4)1.1System overview (4)2Technical Data (7)2.1Technical description (7)2.1.1Incremental encoders with TTL and HTL signals (7)2.1.2Incremental encoders with high-resolution sin/cos signals (9)2.1.3Absolute encoders with MSSI interface (10)2.1.4Resolver (12)2.1.5Proximity sensors (13)2.2Incremental encoders (14)2.2.1Incremental encoders with spread shaft (14)2.2.2Incremental encoders with solid shaft (15)2.3Absolute encoder (16)2.4Resolver (17)2.5Proximity sensors (18)2.6Mounting devices (19)3Installation (20)3.1General information (20)3.2Incremental encoders (21)3.2.1Encoders for MOVITRAC® 31C frequency inverters (21)3.2.2Encoders for MOVIDRIVE® MDV60A drive inverters (22)3.3AV1Y absolute encoder (24)3.3.1Absolute encoder with MOVIDYN® MAS/MKS51A servo controller (24)3.3.2Connection of absolute encoder to MOVIDRIVE® MDS60A drive inverter (25)3.3.3Absolute encoder with MOVIDRIVE® MDV60A drive inverter (25)3.4Resolver (26)3.4.1Resolver with MOVIDYN® MAS/MKS51A servo controller (26)3.4.2Resolver with MOVIDRIVE® MDS60A drive inverter (27)3.5Proximity sensors (28)3.6Extended motor versions with encoder and mounting devices (29)3.6.1Incremental encoders ES1_/ES2_/EV1_ (29)3.6.2Encoder mounting devices ES1A/ES2A/EV1A (31)3.6.3Absolute encoder AV1Y (34)3.6.4Encoder mounting devices AV1A (36)3.7Pre-fabricated cables (37)SEW encoder systems34SEW encoder systems 11System Description 1.1System overview 01863BEN Fig. 2: System overview, SEW drive electronics and encoder systems Electronically controlled drive systems require actual value sensing and speed feedback; drives with synchronous motors also require the angle of the rotor position. As a systems supplier, SEW offers a comprehensive range of encoder systems.Various mounting devices are available to connect non-SEW encoders to SEW motors.Proximity sensors represent an inexpensive and easy-to-fit solution, if all that is required is theinformation about whether or not the drive is turning and in which direction.Encoders Absolute encoders and resolvers Encoder systems for asynchronous AC motors Encoder systems for synchronous motors1SEW encoder systems for asynchronous AC motors:•Incremental encoders-for5V DC supply voltage and with 5 V TTL signal level according to RS-422recommended for operation with the MOVITRAC® 31C frequency inverter-for24V DC supply voltage and with high-resolution sinusoidal signal levelrecommended for operation with the MOVIDRIVE® drive inverter-for24V DC supply voltage and with 5 V TTL signal level according to RS-422-for24V DC supply voltage and with 24V HTL signal level•Absolute encoder-for15V DC supply voltage and with MSSI interface-for24V DC supply voltage and with MSSI interface and two sinusoidal tracks•Proximity sensors-with six pulses per revolution-with A track or A+B track•Mounting devices for non-SEW encoders-mounting of spread shaft-mounting of full shaft with couplingSEW encoder systems for asynchronous servomotors:•Incremental encoders-for24V DC supply voltage and with high-resolution sinusoidal signal levelstandard feature in CT/CV motors-for24V DC supply voltage and with 5 V TTL signal level according to RS-422•Absolute encoder-for24V DC supply voltage and with MSSI interface and two sinusoidal tracksSEW encoder systems for synchronous servomotors:•Resolverstandard with synchronous servomotors for speed control•Absolute encoder15/24 V DC supply voltage with MSSI interfaceEncoder selection based on setting range:•Setting range up to 1:3000-with asynchronous AC motors → encoder with TTL signals and1024 increments/revolution-with synchronous motors → built-in resolver•Setting range up to 1:5000-with asynchronous AC motors → encoder with high-resolution sinusoidal signal levels-with asynchronous servomotors → encoder with high-resolution sinusoidal signal levelsSEW encoder systems56SEW encoder systems 1All encoder systems at a glance: *recommended encoder for operation with MOVITRAC ® 31C **recommended encoder for operation with MOVIDRIVE ® Mounting devices for non-SEW encoders Name For SEW motor size Type of encoder Shaft Specification Supply Signal ES1T*CT/DT 71...100Encoder Spread shaft - 5 V DC controlled 5 V DC TTL RS-422ES1S**24 V DC 1 V SS sin/cos ES1C 24 V DC HTL ES1R 5 V DC TTL RS-422ES2T*CV/DV 112...132S 5 V DC controlled 5 V DC TTL RS-422ES2S**24 V DC 1 V SS sin/cos ES2C 24 V DC HTL ES2R 5 V DC TTL RS-422EV1T*CT/CV71...180DT/DV71...225Solid shaft 5 V DC controlled 5 V DC TTL RS-422EV1S**24 V DC 1 V SS sin/cos EV1C 24 V DC HTL EV1R 5 V DC TTL RS-422NV16DT/DV 71...132S Proximity sensor Solid shaft A track 24 V DC 6 pulses/revolu-tion, NO contact NV26A+B track AV1Y DS56DY71...112CT/CV71...180DT/DV71...225Absolute encoder Solid shaft -15/24 V DC MSSI interface and 1 V SS sin/cos Name For SEW motor size Type of encoder Shaft Specification Supply Signal ES1A DT71...100Non-SEW encoder Spread shaft -Configured as mounting device ES2A DV112...132S EV1A DT/DV71...225Solid shaft AV1A DS56, DY71...112Solid shaft XV1A DT/DV71...225Solid shaftSEW encoder systems722Technical Data2.1Technical descriptionThis chapter explains the various types of signals, signal tracks and signal levels. The signal tracks are represented in the form of timing diagrams.Encoders have a sturdy light metal housing and generously sized precision ball bearings. Their solid metal housing protects the encoders against interference, which lends them a high degree of electromagnetic compatibility.2.1.1Incremental encoders with TTL and HTL signalsEncoders convert the angle of rotation input parameter into a number of electrical pulses. This is performed by means of an incremental disc incorporating radial slits permitting the passage of light. These slits are scanned by opto-electronic means. The number of slits defines the resolution (pulses/revolution).Signal tracks:SEW encoders are encoders with two tracks and one zero pulse track, which results in six tracks due to negation. Two light barriers are arranged at right angles to one another in the encoder. They supply two pulse sequences on tracks A (K1) and B (K2). Track A (K1) is 90° ahead of B (K2) when the encoder is turning clockwise (to the right as viewed looking onto the motor shaft, the “A” side).This phase relationship is used for determining the direction of rotation of the motor. The zero pulse (one pulse per revolution) is sensed by a third light barrier and made available on track C (K0) as a reference signal. With TTL encoders, tracks A (K1), B (K2) and C (K0) are negated in the encoder and made available on tracks A (K1), B (K2) and C (K0) as negated signals.01877AXXFig. 3: TTL signals with zero track and negated signalsHTL signals with zero track, but without negated signals 90°90°180°360°A (K1)A K1()B (K2)B K2()C (K0)C K0()8SEW encoder systems 2Signal levels:•TTL (T ransistor T ransistor L ogic) version The signal levels are V low ≤ 0.5 V and V high ≥ 2.5 V. The TTL signals are transmitted symmetri-cally and evaluated differentially. This design makes them resistant to asymmetrical interference and ensures good EMC behavior. The signal is transmitted in accordance with the RS-422 inter-face standard.Units with a 5 V DC encoder supply voltage, e.g. MOVITRAC ® 31C, allow the user to measure the actual supply voltage at the encoder via sensor leads. The supply voltage is corrected to 5 V DC and compensates for the voltage drop along the supply cable to the encoder. Encoders with 24 V DC supply voltage do not require any supply voltage compensation and, thus, no sensor leads.The maximum permissible distance between encoder and inverter is limited by the maximum pulse frequency of the encoder signals. SEW permits a maximum distance between encoder and inverter of 330 ft. (100 m).02542AEN Fig. 4: View of TTL signal levels •HTL (H igh-voltage T ransistor L ogic) version The signal levels are V low ≤ 3 V and V high ≥ V B minus 3.5 V. The HTL encoder is evaluated without the negated tracks; the signals cannot be evaluated differentially. The HTL signals are, therefore, suscep-tible to asymmetric interferences affecting the EMC behavior.V B is the encoder supply voltage in the range of 10 to 30 V DC , with 24 V DC +/- 20% being the most common value. HTL encoders do not require any supply voltage compensation and, thus, no sensor leads. The large voltage range between V high -V Low results in a high current consumption. A fact that has to be taken into consideration when planning the encoder supply.The maximum permissible distance between encoder and inverter is limited by the maximum pulse frequency of the encoder signals. SEW permits a maximum distance between encoder and inverter of 330 ft. (100 m).02543AEN Fig. 5: View of HTL signal levels 552.52.50.50.500TTL K K V [V ]DC "1" range "1" range "0" range "0" range V [V ]DC 2420.503HTL K V [V ]DC "1" range "0" rangeSEW encoder systems922.1.2Incremental encoders with high-resolution sin/cos signalsEncoders with high-resolution sin/cos signals are referred to as sine encoders. They provide two sine signals offset by 90°. The zero passages and the amplitudes (arc tan) of the sine/cosine waves are evaluated. This means the speed can be determined with a very high resolution. This encoder is suitable for drives which are operated with a wide setting range in conjunction with the require-ment to move smoothly at low speed.Signal tracks:SEW sinusoidal encoders are also dual-track encoders with a zero pulse and negated signals,resulting in six tracks. The 90° offset sine signals are on track A (K1) and B (K2). One sine half-wave per revolution is provided at track C (K0) as the zero pulse. Tracks A (K1), B (K2) and C (K0)are negated in the encoder and made available on tracks A (K1), B (K2) and C (K0) as negated sig-nals.01917AXXFig. 6: sin/cos signal s with zero track and negated tracksSignal levels:•The sine/cosine signals are superimposed on a DC voltage of 2.5 V. They have a peak-to-peak voltage of V SS = 1 V. This arrangement avoids voltage zero during signal transmission. The sine/cosine signals are transmitted symmetrically and evaluated differentially. This design makes them resistant to asymmetrical interference and ensures good EMC behavior. The signal is transmitted in accordance with the RS-422 interface standard. The supply voltage is 24 V DC .Sine encoders do not require any supply voltage compensation and, thus, no sensor leads.The maximum permissible distance between encoder and inverter is limited by the maximum pulse frequency of the encoder signals. SEW permits a maximum distance between encoder and inverter of 330 ft. (100 m).90°90°180°360°A (K1)A K1()B (K2)B K2()C (K0C C0()1V10SEW encoder systems 22.1.3Absolute encoders with MSSI interface SEW absolute encoders have a code disc with Gray Code instead of the incremental disc. This code disc is scanned by opto-electronic means. Every angle position has a unique code pattern assigned to it. The absolute position of the motor shaft is determined using this code pattern. The special feature of Gray Code is that only one bit changes with the transition from one resolvable angle stepto the next. This means the possible reading error is max. 1 bit.01927AXX Fig. 7: Code disc with Gray Code Multi-turn:In addition to the code disc for sensing the angle position, multi-turn absolute encoders have addi-tional code discs for absolute sensing of the number of revolutions. These code discs are only sep-arated from each other by one gear unit stage with the reduction i = 16. With three additonal code discs (number usually installed), 16 x 16 x 16 = 4096 revolutions can be resolved absolutely.02383AEN Fig. 8: Arrangement of code discs A single-turn absolute encoder with 12 bit resolution requires 12 pulses to display the 4096 mea-suring steps per revolution. A multi-turn absolute encoder with three additional code discs requires 12 additional pulses to display the 4096 distinguishable revolutions.Single-turn evaluation Pulse 123456789101112Data 20 21 22 23 24 25 26 27 28 29 210 211 Measuring steps per revolution in addition with multi-turn evaluation Pulse 131415161718192021222324Data 20 21 22 23 24 25 26 27 28 29 210 211 distinguishable revolutions i = 16i = 16i = 16Code discs for sensing the number of revolutions Code disc for sensing of angle position Decimal Gray Code Decimal Gray Code 00000811001000191101200111011113001011111040110121010501111310116010114100170100151000Signal outputs:Every scanned code pattern is a parallel data package and is read by a parallel/serial converter. The inverter must request the position value with a defined pulse sequence in order to transmit a posi-tion value from the encoder to the inverter. The pulse sequence starts by converting the current parallel data package and transmitting it to the inverter. The input of the parallel/serial converter is inhibited by the monoflop for the duration of the pulse sequence.01923AENFig. 9: Signal conditioning in absolute encoders with SSI interfaceIn addition to the absolute angle position, the SEW absolute encoders generate the incremental encoder signals A (K1), A (K1), B (K2)und B (K2) and make them available as 1 V SS sine signals.Signal transmission:SEW absolute encoders have an SSI interface (SSI = S ynchronous S erial I nterface) to transmit the absolute value signals and a RS-485 interface for transmission of the 1 V SS sine signals.01928AENFig. 10: Pulse diagram of data transmission via SSI interfaceInverterCycleSerialdataParallel dataCode discDriver InputcircuitSchmitt trigger P a r a l le l /S e r ialconverterPhoto transmitter Photo receiver MonoflopShift SI SOCycleSerialdataMonoflop P/SParalleldata2.1.4ResolverThe resolver determines the absolute position of the motor shaft. It consists of a rotor coil and two stator windings offset by 90° in relation to each other. It operates according to the principle of the rotary transformer. Furthermore, the resolver has one auxiliary winding each in the stator and on the rotor in order to transfer the supply voltage to the rotor without brushes. Both rotor windings are electrically connected.01931AEN Fig. 11: Schematic diagram and equivalent circuit diagram of the resolverSignal outputs:Voltages of varying magnitudes are induced in the stator windings depending on the rotor position. Voltages V1 and V2 on the two stator windings are modulated by the supply voltage through induc-tion. They possess sinusoidal envelopes. The two envelopes are electrically offset by 90° from one another and are evaluated in the inverter for zero passage and amplitude. This enables the rotor position, speed and direction of rotation to be established.00058AXX Fig. 12: Output voltages V1 and V2 of the resolverSignal level:The amplitude of the envelope depends on the r.m.s. value and frequency of the supply voltage V e.γS1S3S4S2R1R2V1stator statorrotorV2V RV estatorstationaryrotating stationarystationaryV2VRV1V1V22.1.5Proximity sensorsProximity sensors represent a simple and inexpensive means of monitoring whether the motor is turning. By using a two-track proximity sensor, it is also possible to determine the direction in which the motor is rotating. Proximity sensors are mounted on the side of the fan guard, and thus do not add to the length of the motor.Signal outputs:Proximity sensors react to the attenuation lugs on the fan. The number of attenuation lugs deter-mines the number of pulses per revolution.01929AXXFig. 13: Setup of the proximity sensor systemThe proximity sensors are constructed with HTL technology and have an NO contact output which is actuated every time there is a pulse. This NO contact output switches the connected supply volt-age. Proximity sensors have a mark-to-space ratio of 1:1.01930AENFig. 14: Signal output of the proximity sensorsSignal level:The signal level is determined by the supply voltage, usually 24 V DC. 90°ABPNPPNPV BV Badditional with two-track proximity sensor2.2Incremental encoders 2.2.1Incremental encoders with spread shaft 01934AXX Fig. 15: SEW encoder with spread shaft *recommended encoder for operation with MOVITRAC ® 31C**recommended encoder for operation with MOVIDRIVE ® Encoder type for asynchronous AC motors 71...100ES1T*ES1S**ES1R ES1C Encoder type for asynchronous AC motors 112...132S ES2T*ES2S**ES2R ES2C Supply voltage V B 5 V DC ±5 %24 V DC ±20 %Max. current consumption I in 180 mA RMS 160 mA RMS 180 mA RMS 340 mA RMS Max. pulse frequency f max 120 kHz Pulses (sine periods) per A, B revolution C 10241Output amplitude per track V high V low ≥ 2.5 V DC ≤ 0.5 V DC 1 V SS ≥ 2.5 V DC ≤ 0.5 V DC ≥ V B minus 3.5 V DC ≤ 1.5 V DC Signal output 5 V TTL sin/cos 5 V TTL HTL Output current per track I out 20 mA RMS 40 mA RMS 20 mA RMS 60 mA RMS Mark-to-space ratio 1 : 1 ±20 %Phase angle A : B 90° ±20 %Ambient temperature ϑamb -25 °C...+60 °C (EN 60721-3-3, class 3K3)Enclosure IP56 (EN 60529)Connection Terminal box on encoder2.2.2Incremental encoders with solid shaft01935AXXFig. 16: SEW encoder with solid shaft*recommended encoder for operation with MOVITRAC ® 31C **recommended encoder for operation with MOVIDRIVE ®Encoder type EV1T*EV1S**EV1R EV1C For motors asynchronous AC motors DT/DV/D 71 (225)Supply voltage V B 5 V DC ±5 %24 V DC ±20 %Max. current consumption I in 180 mA RMS 160 mA RMS 180 mA RMS 340 mA RMS Max. pulse frequency f max 120 kHzPulses (sine periods) per A, B revolution C 10241Output amplitude per track V highV low ≥ 2.5 V DC≤ 0.5 V DC 1 V SS ≥ 2.5 V DC ≤ 0.5 V DC ≥ VB minus 3.5 VDC≤ 1.5 V DCSignal output 5 V TTL sin/cos 5 V TTL HTL Output current per track I out 20 mA RMS 40 mA RMS 20 mA RMS 60 mA RMS Mark-to-space ratio 1 : 1 ±20 %Phase angle A : B 90° ±20 %Ambient temperature ϑamb -25 °C...+60 °C (EN 60721-3-3, class 3K3)Enclosure IP56 (EN 60529)Connection Terminal box on encoder2.3Absolute encoder01933BXX Fig. 17: SEW absolute encoderEncoder type AGYFor motors synchronous servomotors DS56, DY71 (112)asynchronous servomotors CT/CV71 (180)asynchronous AC motorsDT/DV71 (225)Supply voltage V B10 – 15 – 24 – 30 V DC protected against polarity reversal Max. current consumption I in250 mAMax. stepping frequency f max≥ 100 kHzPulses (sine periods) per revolutionA,B512Output amplitude per track 1 V SS sin/cosSensing code Gray CodeSingle-turn resolution4096 steps/revolution (12 bits)Multi-turn resolution4096 revolutions (12 bits)Data transfer, absolute values Synchronous, serial (SSI)Serial data output Driver to EIA RS-485Serial pulse input Opto-coupler, recommended driver to EIA RS-485 Switching frequency Permitted range: 90 – 300 – 1100 kHz(max. 330 ft./100 m cable length with 300 kHz) Monoflop time12 – 35 µsVibration (55...2000 Hz)≤ 100 m/s2 (DIN IEC 68-2-6)Maximum speed n max6000 rpmMass m0.30 kgOperating temperatureϑamb-15 °C...+60 °C (EN 60721-3-3, class 3K3) Enclosure IP65 (EN 60529)Connection 3.3 ft/1 m cable with 17-pin round connector plugfor socket plug SPUC 17B FRAN2.4ResolverMD0116AX Fig. 18: SEW resolverEncoder type RH1MFor motorssynchronous servomotorsDS56DY71DY90DY112Supply voltage V127 V AC_eff / 7 kHzMax. current consumption I1270 mA60 mA30 mANumber of poles2Ratio r0.50.450.46Output impedance Z SS200...330 Ω130...270 Ω350...500 ΩOperating temperatureϑB-55 °C...+125 °CConnection Terminal box (10-pin Phoenix terminal strip) or plug connector,depending on motor typePlug connector DS56: Intercontec, type ASTA021NN00 10 000 5 000Plug connector DY71...112: Framatone Souriou, type GN-DMS2-12S2.5Proximity sensors01932AXX Fig. 19: SEW proximity sensorsEncoder type NV16NV26For motors/brake motors asynchronous AC motors 71(BMG)...132S(BMG)Supply voltage V B10 – 24 – 65 V DCMax. operating current I max200 mAMax. pulse frequency f max 1.5 kHzPulses/revolution6A track6A+B trackOutput NO contact (pnp)Mark-to-space ratio 1 : 1 ±20 %Phase angle A : B-90° ±45 % (typical at 20 °C) Ambient temperatureϑamb0 °C...+60 °C (EN 60721-3-3, class 3K3)Enclosure IP67 (EN 60529)Connection M12 × 1 connector, e.g. RKWT4 (Lumberg)2.6Mounting devices01949AXXFig. 20: Mounting device for non-SEW encodersSee section 3.6.2, page 31 (ES1A, ES2A, EV1A) and section 3.6.4, page 36 (AV1A) regarding dimensions and extended motor lengths for encoder mounting devices.Mounting device ES1A ES2AFor motors asynchronous AC motors 71...100 asynchronous AC motors 100...132S For encoder Spread shaft encoder with 8 mm center bore Spread shaft encoder with 10 mm center boreMounting device EV1A AV1AFor motors asynchronous AC motors DT71...DV225synchronous servomotorsDS56, DY71 (112)For encoder Solid shaft encoder (synchro flange)Diameter of flange 58 mmDiameter of center hole 50 mmDiameter of shaft end 6 mmLength of shaft end 10 mmMounting 3 pcs. encoder mounting clamps (bolts with eccentric discs)for 3 mm flange thickness3Installation3.1General informationAlways follow the operating instructions for the relevant inverter when connecting the encoder to the SEW inverters!•Max. line length (inverter – encoder):330 ft (100 m) with a cable capacitance per unit length ≤ 120 nF/km (193 nF/mile)•Core cross section: 0.25 – 0.5 mm2 (AWG24 – AWG20)•Use a shielded cable with twisted pairs of cores (exception: HTL encoder cable) and connect the shield at both ends:- on the encoder in the PG fitting or in the encoder plug- on the inverter to the electronics shield clamp or to the housing of the Sub D connector •Route the encoder cable separately from the power cables.Connect the shield of the encoder cable over a large surface area:•on the inverter01937AXX Fig. 21: Connect the shield to the electronics shield clamp of the inverter01939BXX Fig. 22: Connect the shield in the Sub D connector•on the encoder01948AXX Fig. 23: Connect the shield to the PG fitting of the encoder33.2Incremental encoders01936AXXFig. 24: Connecting terminals of the SEW encoder3.2.1Encoders for MOVITRAC ® 31C frequency invertersSEW recommends the 5 V TTL encoders ES1T, ES2T or EV1T for operation with the MOVITRAC ®31C frequency inverter. The sensor leads have to be connected in order to compensate the encoder supply voltage. Connect the encoder as follows:*Connect the sensor leads on the encoder to UB and ⊥, do not jumper them on the encoder!01585BXXFig. 25: Connection of TTL encoders ES1T, ES2T or EV1T to MOVITRAC ® 31C Channels K0 (C) and K0 (C) are only required for position control (FPI31C option). Channels K0 (C)and K0 (C) are not required for speed control (FRN31C or FEN31C option) and synchronous opera-tion (FRS31C option). A (K1)()B (K2)()C (K0)()UB A K1B K2C K0⊥ES1T / ES2T / EV1T UB K1K2K0⊥K1K2K0UB A B C ⊥A B C max. 100 m (330 ft)8889909192939495*96*97MC31CFEN 31C/FPI 31CਠਠX6:33.2.2Encoders for MOVIDRIVE ® MDV60A drive inverters The core colors indicated in the wiring diagrams according to color code meeting IEC757 corre-spond to the core colors of the pre-fabricated cables by SEW (→ section 3.7).24 V sin/cos encoders ES1S, ES2S or EV1S SEW recommends the high-resolution 24 V sin/cos encoders ES1S, ES2S or EV1S for operation with the MOVIDRIVE ® drive inverter. 24 V encoders do not require sensor leads. Connect the encoder as follows:01381BXX Fig. 26: Connection of sin/cos encoder ES1S, ES2S or EV1S to MOVIDRIVE ® 24 V TTL encoders ES1R, ES2R or EV1R It is also possible to connect TTL encoders with 24 V DC encoder supply ES1R, ES2R, EV1R directly to MOVIDRIVE ® MDV60A. Install the TTL encoders in exactly the same way as the high-resolution sin/cos encoders (→ Fig. 26).HTL encoders ES1C, ES2C or EV1C If you are using an HTL encoder ES1C, ES2C or EV1C, you must not connect the negated channels A (K1), B (K2) and C (K0) to MOVIDRIVE ® !02558AXX Fig. 27: Connection of HTL encoder ES1C, ES2C or EV1C to MOVIDRIVE ® 162738954YE GN RD BU PK GY WH BN VT 1569X15:max. 100 m (330 ft)A (K1)()B (K2)()C (K0)()UB A K1B K2C K0⊥ES1S / ES2S / EV1S ES1R / ES2R / EV1R UB K1K2K0⊥K1K2K0ਠਠUB A B C ⊥A B C ¢1N.C. 62N.C. 73N.C. 895N.C. 4YE RD PK WH BN 1569X15:max. 100 m (330 ft)A (K1)()B (K2)()C (K0)()UB A K1B K2C K0⊥ES1C / ES2C / EV1C UB K1K2K0⊥K1K2K0ਠਠUB A B C ⊥A B C35V TTL encoders ES1T, ES2T or EV1TUse the “5 V encoder supply type DWI11A” MOVIDRIVE ® option (part number 822 759 4) if you have to connect an encoder with a 5 V DC encoder supply ES1T, ES2T or EV1T to MOVIDRIVE ® . The sensor leads have to be connected in order to compensate the supply voltage. Connect the encoder as follows:*Connect the sensor lead on the encoder to UB, do not jumper on the DWI11A!01377BXXFig. 28: Connection of TTL encoder ES1T, ES2T or EV1T to MOVIDRIVE ® 15516996DWI11AX2:Enc o derX1:MOV ID RIVE max. 5 m (16.5 ft)max. 100 m (330 ft)1569X15:ES1T / ES2T / EV1T 162738954*ਠਠYE GN RD BU PK GY WH BNVT*162738954A (K1)()B (K2)()C (K0)()UB A K1B K2C K0⊥ A (K1)()B (K2)()C (K0)()UB N.C.A K1B K2C K0⊥162738954ਠਠYE GN RD BU PK GY WH BN VT UB K1K2K0⊥K1K2K0UB A B C ⊥A B C 814 344 7198 829 8198 828 X33.3AV1Y absolute encoder The AV1Y absolute encoder has a permanently installed connector that is one meter long (3.3 ft.)with a 17-pin round connector plug fitting socket plug SPUC 17B FRAN by Interconnectron. The plug connection has the following pin assignment:AV1Y is connected to:•MOVIDYN ® MAS/MKS51A servo controller with option “APA12 single axis positioning control”•MOVIDRIVE ® MDS60A drive inverter with option “DPA11A single axis positioning control”•MOVIDRIVE ® MDS/MDV60A drive inverter with option “DIP11A absolute encoder card”Synchronous servomotors are speed-controlled with the resolver signals. Therefore, the incremen-tal encoder signals A, A, B and B are not evaluated by MOVIDYN ® MAS/MK51A or MOVIDRIVE ®MDS60A. The AV1Y connectors 12, 13, 15 and 16 will not be assigned in this instance. MOVID-RIVE ® MDV60A uses the incremental encoder signals A, A, B and B for speed control of asynchro-nous motors. The AV1Y connectors 12, 13, 15 and 16 will be directed to X15: “ENCODER IN“ of the MOVIDRIVE ® MDV60A.The core colors in the wiring diagrams according to color code meeting IEC757 correspond to the core colors in the pre-fabricated SEW cables (→ section 3.7).3.3.1Absolute encoder with MOVIDYN ® MAS/MKS51A servo controller The AV1Y absolute encoder is connected to the APA12 option:01940BXX Fig. 29: Connection to MOVIDYN ® MAS/MKS51A servo controller with APA12Pin Description Core color of pre-fabricated cable 6-core cable 10-core cable 7Supply voltage V S +13 – 15 – 24 V DC , protected against polarity reversal white (WH)white (WH)10Supply voltage GND Electrically isolated from the AGY housing brown (BN)brown (BN)14Serial data output D+“1” = High signal yellow (YE)black (BK)17Serial data output D-“0” = High signal green (GN)violet (VT)8Clock line, current loop T+7 mA towards T+ = “1”pink (PK)pink (PK)9Clock line, current loop T-7 mA towards T- = “0”grey (GY)grey (GY)15Incremental encoder - signal A 1 V ss sin/cos -yellow (YE)16Incremental encoder - signal A 1 V ss sin/cos -green (GN)12Incremental encoder - signal B 1 V ss sin/cos -red (RD)13Incremental encoder - signal B 1 V ss sin/cos -blue (BU)3456910111213141516171278891417107PK GY YE GN BN WH T+T-D+D-GND U S max. 100 m (330 ft)323334353839APA12X11:ਠਠAV1Y。
355 South 520 West, Suite 180Lindon, UT 84042Phone: (801) 765-9885Fax: (801) 765-9895rf-xperts@ (live chat support)XBee™ Series 2 OEM RF ModulesXBee Series 2 Series 2 OEM RF Modules ZigBee ™ Networks RF Module Operation RF Module Configuration AppendicesProduct Manual v1.x.2x - ZigBee ProtocolFor OEM RF Module Part Numbers:XB24-BxIT-00xZigBee OEM RF Modules by MaxStream, Inc. - a Digi International brand Firmware Versions:1.0xx - Coordinator , Transparent Operation 1.1xx - Coordinator , API Operation1.2xx - Router , End Device, Transparent Operation 1.3xx - Router , End Device, API Operation90000866_B 2007.07.019© 2007 Digi International, Inc. All rights reservedNo part of the contents of this manual may be transmitted or reproduced in any form or by any means without the written permission of Digi International, Inc. ZigBee® is a registered trademark of the ZigBee Alliance.XBee™ Series 2 is a trademark of Digi International, Inc.Technical Support: Phone: (801) 765‐9885Live Chat: E‐mail: rf‐xperts@Contents1. XBee Series 2 OEM RF Modules41.1. Key Features 41.1.1. Worldwide Acceptance 41.2. Specifications 51.3. Mechanical Drawings 61.4. Mounting Considerations 61.5. Pin Signals 71.6. Electrical Characteristics 82. RF Module Operation92.1. Serial Communications 92.1.1. UART Data Flow 92.1.2. Serial Buffers 92.1.3. Serial Flow Control 102.1.4. Transparent Operation 122.1.5. API Operation 122.2. Modes of Operation 132.2.1. Idle Mode 132.2.2. Transmit Mode 132.2.3. Receive Mode 142.2.4. Command Mode 142.2.5. Sleep Mode 153. ZigBee Networks173.1. ZigBee Network Formation 173.1.1. Starting a ZigBee Coordinator 173.1.2. Joining a Router 173.1.3. Joining an End Device 183.2. ZigBee Network Communications 193.2.1. ZigBee Device Addressing 193.2.2. ZigBee Application-layer Addressing 193.2.3. Data Transmission and Routing 204. XBee Series 2 Networks254.1. XBee Series 2 Network Formation 254.1.1. Starting an XBee Series 2 Coordinator 254.1.2. Joining an XBee Series 2 Router to an ex-isting PAN 254.1.3. Joining an XBee Series 2 End Device to anExisting PAN 254.1.4. Network Reset 264.2. XBee Series 2 Addressing 274.2.1. Device Addressing 274.2.2. Application-layer Addressing 294.2.3. XBee Series 2 Binding Table 294.2.4. XBee Series 2 Endpoint Table 314.3. Sleep Mode Operation 324.3.1. End Device Operation 324.3.2. Parent Operation 324.4. I/O Line Configuration 325. Advanced Features355.1. Device Discovery 355.2. Remote Configuration 355.3. Loopback Testing 355.3.1. AT Firmware 355.3.2. API Firmware 355.4. Join Indicators 355.5. Manual Device Identification 355.6. Battery Life Monitoring 366. XBee Series 2 Command Reference Tables377. API Operation437.0.1. API Frame Specifications 437.0.2. API Frames 448. Examples568.0.1. Starting an XBee Network 568.0.2. AT Command Programming Examples 578.0.3. API Programming Examples 579. Manufacturing Support599.1. Interoperability with other EM250 Devic-es 599.2. Customizing XBee Default Parameters599.3. XBee Series 2 Custom Bootloader 599.4. Programming XBee Series 2 Modules 599.5. XBee EM250 Pin Mappings 59 Definitions 61Agency Certifications 63Migrating from the 802.15.4 Protocol 67 Development Guide 68Additional Information 781. XBee Series 2 OEM RF ModulesThe XBee Series 2 OEM RF Modules were engineered to operate within the ZigBee protocol and support the unique needs of low-cost, low-power wireless sensor networks. The modules require minimal power and provide reliable delivery of data between remote devices.The modules operate within the ISM 2.4 GHz frequency band.1.1. Key Features1.1.1. Worldwide AcceptanceFCC Approval (USA) Refer to Appendix A [p50] for FCC Requirements.Systems that contain XBee Series 2 RF Modules inherit MaxStream Certifications.ISM (Industrial, Scientific & Medical) 2.4 GHz frequency band Manufactured underISO 9001:2000 registered standardsXBee Series 2 RF Modules are optimized for use in US , Canada , Australia, Israel and Europe (contact MaxStream for complete list of agency approvals).High Performance, Low Cost•Indoor/Urban: up to 133’ (40 m)•Outdoor line-of-sight: up to 400’ (120 m)•Transmit Power: 2 mW (+3 dBm)•Receiver Sensitivity: -96 dBm RF Data Rate: 250,000 bps Advanced Networking & Security Retries and AcknowledgementsDSSS (Direct Sequence Spread Spectrum)Each direct sequence channel has over65,000 unique network addresses available Point-to-point, point-to-multipoint and peer-to-peer topologies supported Self-routing, self-healing and fault-tolerant mesh networkingLow Power XBee Series 2•TX Current: 40 mA (@3.3 V)•RX Current: 40 mA (@3.3 V)•Power-down Current: < 1 µA @ 25o C Easy-to-UseNo configuration necessary for out-of box RF communicationsAT and API Command Modes for configuring module parameters Small form factor Extensive command setFree X-CTU Software(Testing and configuration software)Free & Unlimited Technical Support1.2. Specifications*The ranges specified are typical when using the integrated Whip (1.5 dBi) and Dipole (2.1 dBi) antennas. The Chipantenna option provides advantages in its form factor; however, it typically yields shorter range than the Whip and Dipole antenna options when transmitting outdoors. For more information, refer to the “XBee Series 2 Antenna” application note located on MaxStream’s web site/support/knowledgebase/article.php?kb=153Table 1‐01.Specifications of the XBee Series 2 OEM RF ModuleSpecification XBee Series 2Performance Indoor/Urban Range up to 133 ft. (40 m)*Outdoor RF line-of-sight Range up to 400 ft. (120 m)*Transmit Power Output (software selectable)2mW (+3dBm), boost mode enabled 1.25mW (+1dBm), boost mode disabled RF Data Rate250,000 bpsSerial Interface Data Rate (software selectable)1200 - 230400 bps(non-standard baud rates also supported)Receiver Sensitivity -96 dBm, boost mode enabled -95 dBm, boost mode disabledPower Requirements Supply Voltage2.1 -3.6 VOperating Current (Transmit, max output power)40mA (@ 3.3 V, boost mode enabled)35mA (@ 3.3 V, boost mode disabled)Operating Current (Receive))40mA (@ 3.3 V, boost mode enabled)38mA (@ 3.3 V, boost mode disabled) Idle Current (Receiver off) 15mA Power-down Current < 1 uA @ 25o C GeneralOperating Frequency Band ISM 2.4 GHzDimensions0.960” x 1.087” (2.438cm x 2.761cm)Operating Temperature -40 to 85º C (industrial)Antenna Options Integrated Whip, Chip, RPSMA, or U.FL Connector*Networking & Security Supported Network Topologies Point-to-point, Point-to-multipoint, Peer-to-peer & Mesh Number of Channels (software selectable)16 Direct Sequence ChannelsAddressing Options PAN ID and Addresses, Cluster IDs and Endpoints (optional)Agency ApprovalsUnited States (FCC Part 15.247)OUR-XBEE2Industry Canada (IC)4214A-XBEE2Europe (CE)ETSI1.3. Mechanical DrawingsFigure 1‐01.Mechanical drawings of the XBee Series 2 OEM RF Modules (antenna options not shown).1.4. Mounting ConsiderationsThe XBee Series 2 RF Module (through-hole) was designed to mount into a receptacle (socket) and therefore does not require any soldering when mounting it to a board. The XBee Series 2Development Kits contain RS-232 and USB interface boards which use two 20-pin receptacles to receive modules.Figure 1‐02.XBee Series 2 Module Mounting to an RS ‐232 Interface Board .The receptacles used on MaxStream development boards are manufactured by CenturyInterconnect. Several other manufacturers provide comparable mounting solutions; however , MaxStream currently uses the following receptacles:•Through-hole single-row receptacles -Samtec P/N: MMS-110-01-L-SV (or equivalent)•Surface-mount double-row receptacles -Century Interconnect P/N: CPRMSL20-D-0-1 (or equivalent)•Surface-mount single-row receptacles - Samtec P/N: SMM-110-02-SM-SMaxStream also recommends printing an outline of the module on the board to indicate the orientation the module should be mounted.XBee1.5. Pin SignalsFigure 1‐03.XBee Series 2 RF Module Pin Number (top sides shown ‐ shields on bottom)Design Notes:•Minimum connections: VCC, GND, DOUT & DIN•Minimum connections to support serial firmware upgrades: VCC, GND, DIN, DOUT , RTS & DTR •Signal Direction is specified with respect to the module •Module includes a 30k Ohm resistor attached to RESET•Several of the input pull-ups can be configured using the PR command •Unused pins should be left disconnectedTable 1‐02.Pin Assignments for the XBee Series 2 Modules(Low ‐asserted signals are distinguished with a horizontal line above signal name.)Pin #Name DirectionDescription 1VCC -Power supply 2DOUT Output UART Data Out 3DIN / CONFIG Input UART Data In 4DIO12Either Digital I/O 125RESET Input Module Reset (reset pulse must be at least 200 ns)6PWM0 / RSSI / DIO10Either PWM Output 0 / RX Signal Strength Indicator / Digital IO7PWM / DIO11Either Digital I/O 118[reserved]-Do not connect9DTR / SLEEP_RQ/ DIO8Either Pin Sleep Control Line or Digital IO 810GND -Ground 11DIO4Either Digital I/O 412CTS / DIO7Either Clear-to-Send Flow Control or Digital I/O 713ON / SLEEP / DIO9Output Module Status Indicator or Digital I/O 914[reserved]-Do not connect15Associate / DIO5Either Associated Indicator, Digital I/O 516RTS / DIO6 Either Request-to-Send Flow Control, Digital I/O 617AD3 / DIO3Either Analog Input 3 or Digital I/O 318AD2 / DIO2Either Analog Input 2 or Digital I/O 219AD1 / DIO1Either Analog Input 1 or Digital I/O 120AD0 / DIO0 / ID ButtonEitherAnalog Input 0, Digital I/O 0, or Node Identification1.6. Electrical CharacteristicsTable 1‐03.DC Characteristics of the XBee Series 2 (VCC = 2.8 ‐ 3.4 VDC)Symbol Parameter Condition Min Typical Max Units V IL Input Low Voltage All Digital Inputs-- 0.2 * VCC V V IH Input High Voltage All Digital Inputs0.8 * VCC- 0.18* VCC V V OL Output Low Voltage I OL = 2 mA, VCC >= 2.7 V--0.18*VCC V V OH Output High Voltage I OH = -2 mA, VCC >= 2.7 V0.82*VCC--V II IN Input Leakage Current V IN = VCC or GND, all inputs, per pin--0.5uA uA2. RF Module Operation2.1. Serial CommunicationsThe XBee Series 2 OEM RF Modules interface to a host device through a logic-level asynchronous serial port. Through its serial port, the module can communicate with any logic and voltage compatible UART; or through a level translator to any serial device (For example: Through a MaxStream proprietary RS-232 or USB interface board).2.1.1. UART Data FlowDevices that have a UART interface can connect directly to the pins of the RF module as shown in the figure below.Figure 2‐01.System Data Flow Diagram in a UART ‐interfaced environment(Low ‐asserted signals distinguished with horizontalline over signal name.)Serial DataData enters the module UART through the DIN (pin 3) as an asynchronous serial signal. The signal should idle high when no data is being transmitted.Each data byte consists of a start bit (low), 8 data bits (least significant bit first) and a stop bit (high). The following figure illustrates the serial bit pattern of data passing through the module.Figure 2‐02.UART data packet 0x1F (decimal number ʺ31ʺ) as transmitted through the RF moduleExample Data Format is 8‐N ‐1 (bits ‐ parity ‐ # of stop bits)The module UART performs tasks, such as timing and parity checking, that are needed for data communications. Serial communications depend on the two UARTs to be configured with compatible settings (baud rate, parity, start bits, stop bits, data bits).2.1.2. Serial BuffersThe XBee Series 2 modules maintain small buffers to collect received serial and RF data, which is illustrated in the figure below. The serial receive buffer collects incoming serial characters and holds them until they can be processed. The serial transmit buffer collects data that is received via the RF link that will be transmitted out the UART .DIN (data in)DIN (data in)DOUT (data out)DOUT (data out)XBee Series 2 OEM RF Modules ‐ ZigBee ‐ v1.x2x [2007.07.019]Chapter 2 ‐ RF Module Operation Figure 2‐03.Internal Data Flow DiagramSerial Receive BufferWhen serial data enters the RF module through the DIN Pin (pin 3), the data is stored in the serialreceive buffer until it can be processed. Under certain conditions, the module may not be able toprocess data in the serial receive buffer immediately. If large amounts of serial data are sent tothe module, CTS flow control may be required to avoid overflowing the serial receive buffer.Cases in which the serial receive buffer may become full and possibly overflow:1.If the module is receiving a continuous stream of RF data, the data in the serial receivebuffer will not be transmitted until the module is no longer receiving RF data.2.If the module is transmitting an RF data packet, the module may need to discover the des-tination address or establish a route to the destination. After transmitting the data, themodule may need to retransmit the data if an acknowledgment is not received, or if thetransmission is a broadcast. These issues could delay the processing of data in the serialreceive buffer.Serial Transmit BufferWhen RF data is received, the data is moved into the serial transmit buffer and is sent out theserial port. If the serial transmit buffer becomes full enough such that all data in a received RFpacket won’t fit in the serial transmit buffer, the entire RF data packet is dropped.Cases in which the serial transmit buffer may become full resulting in dropped RFpackets1. If the RF data rate is set higher than the interface data rate of the module, the modulecould receive data faster than it can send the data to the host.2. If the host does not allow the module to transmit data out from the serial transmit bufferbecause of being held off by hardware flow control.2.1.3. Serial Flow ControlThe RTS and CTS module pins can be used to provide RTS and/or CTS flow control. CTS flowcontrol provides an indication to the host to stop sending serial data to the module. RTS flowcontrol allows the host to signal the module to not send data in the serial transmit buffer out theuart. RTS and CTS flow control are enabled using the D6 and D7 commands.If CTS flow control is enabled (D7 command), when the serial receive buffer is 17 bytes awayfrom being full, the module de-asserts CTS (sets it high) to signal to the host device to stopsending serial data. CTS is re-asserted after the serial receive buffer has 34 bytes of space.If flow RTS control is enabled (D6 command), data in the serial transmit buffer will not be sent out the DOUT pin as long as RTS is de-asserted (set high). The host device should not de-assert RTS for long periods of time to avoid filling the serial transmit buffer. If an RF data packet is received, and the serial transmit buffer does not have enough space for all of the data bytes, the entire RF data packet will be discarded.2.1.4. Transparent OperationRF modules that contain the following firmware versions will support Transparent Mode:1.0xx (coordinator) and 1.2xx (router/end device).When operating in Transparent Mode, the modules act as a serial line replacement. All UART data received through the DIN pin is queued up for RF transmission. When RF data is received, the data is sent out the DOUT pin. The module configuration parameters are configured using the ATcommand mode interface. (See RF Module Operation --> Command Mode.)When RF data is received by a module, the data is sent out the DOUT pin.Serial-to-RF PacketizationData is buffered in the serial receive buffer until one of the following causes the data to bepacketized and transmitted:1. No serial characters are received for the amount of time determined by the RO (Packetiza-tion Timeout) parameter. If RO = 0, packetization begins when a character is received.2.Maximum number of characters that will fit (72) in an RF packet is received.3.The Command Mode Sequence (GT + CC + GT) is received. Any character buffered in theserial receive buffer before the sequence is transmitted.2.1.5. API OperationAPI (Application Programming Interface) Operation is an alternative to the default Transparent Operation. The frame-based API extends the level to which a host application can interact with the networking capabilities of the module. RF modules that contain the following firmware versions will support API operation: 1.1xx (coordinator) and 1.3xx (router/end device).When in API mode, all data entering and leaving the module is contained in frames that define operations or events within the module.Transmit Data Frames (received through the DIN pin (pin 3)) include:•RF Transmit Data Frame•Command Frame (equivalent to AT commands)Receive Data Frames (sent out the DOUT pin (pin 2)) include:•RF-received data frame•Command response•Event notifications such as reset, associate, disassociate, etc.The API provides alternative means of configuring modules and routing data at the hostapplication layer. A host application can send data frames to the module that contain address and payload information instead of using command mode to modify addresses. The module will send data frames to the application containing status packets; as well as source, and payloadinformation from received data packets.The API operation option facilitates many operations such as the examples cited below:->Transmitting data to multiple destinations without entering Command Mode->Receive success/failure status of each transmitted RF packet->Identify the source address of each received packetTo implement API operations, refer to the API Operation chapter 6.2.2. Modes of Operation2.2.1. Idle ModeWhen not receiving or transmitting data, the RF module is in Idle Mode. During Idle Mode, the RFmodule is also checking for valid RF data. The module shifts into the other modes of operationunder the following conditions:•Transmit Mode (Serial data in the serial receive buffer is ready to be packetized)•Receive Mode (Valid RF data is received through the antenna)•Sleep Mode (End Devices only)•Command Mode (Command Mode Sequence is issued)2.2.2. Transmit ModeWhen serial data is received and is ready for packetization, the RF module will exit Idle Mode andattempt to transmit the data. The destination address determines which node(s) will receive thedata.Prior to transmitting the data, the module ensures that a 16-bit network address and route to thedestination node have been established.If the 16-bit network address is not known, network address discovery will take place. If a route isnot known, route discovery will take place for the purpose of establishing a route to thedestination node. If a module with a matching network address is not discovered, the packet isdiscarded. The data will be transmitted once a route is established. If route discovery fails toestablish a route, the packet will be discarded.Figure 2‐04.Transmit Mode SequenceWhen data is transmitted from one node to another, a network-level acknowledgement istransmitted back across the established route to the source node. This acknowledgement packetindicates to the source node that the data packet was received by the destination node. If anetwork acknowledgement is not received, the source node will re-transmit the data. See DataTransmission and Routing in chapter 3 for more information.If a valid RF packet is received, the data is transferred to the serial transmit buffer2.2.4. Command ModeTo modify or read RF Module parameters, the module must first enter into Command Mode - astate in which incoming serial characters are interpreted as commands. Refer to the API Modesection for an alternate means of configuring modules.AT Command ModeTo Enter AT Command Mode:Default AT Command Mode Sequence (for transition to Command Mode):•No characters sent for one second [GT (Guard Times) parameter = 0x3E8]•Input three plus characters (“+++”) within one second [CC (Command Sequence Character) parameter = 0x2B.]•No characters sent for one second [GT (Guard Times) parameter = 0x3E8]All of the parameter values in the sequence can be modified to reflect user preferences.NOTE: Failure to enter AT Command Mode is most commonly due to baud rate mismatch. Ensure the ‘Baud’ setting on the “PC Settings” tab matches the interface data rate of the RF module. By default, the BD parameter = 3 (9600 bps).To Send AT Commands:Figure 2‐05. Syntax for sending AT CommandsTo read a parameter value stored in the RF module’s register, omit the parameter field.The preceding example would change the RF module Destination Address (Low) to “0x1F”. To storethe new value to non-volatile (long term) memory, subsequently send the WR (Write) command.For modified parameter values to persist in the module’s registry after a reset, changes must besaved to non-volatile memory using the WR (Write) Command. Otherwise, parameters arerestored to previously saved values after the module is reset.System Response. When a command is sent to the module, the module will parse and executethe command. Upon successful execution of a command, the module returns an “OK” message. Ifexecution of a command results in an error , the module returns an “ERROR” message.To Exit AT Command Mode:For an example of programming the RF module using AT Commands and descriptions of each configurable parameter, refer to the "Examples" and "XBee Series 2 Command Reference Tables" chapters.Send the 3-character command sequence “+++” and observe guard times before and after thecommand characters. [Refer to the “Default AT Command Mode Sequence” below.]Send AT commands and parameters using the syntax shown below.1. Send the ATCN (Exit Command Mode) command (followed by a carriage return).[OR]2. If no valid AT Commands are received within the time specified by CT (Command ModeTimeout) Command, the RF module automatically returns to Idle Mode.Sleep modes allow the RF module to enter states of low-power consumption when not in use. Toenter Sleep Mode, one of the following conditions must be met (in addition to the module having anon-zero SM parameter value):•Sleep_RQ (pin 9) is asserted•The module is idle (no data is transmitted or received) for the time defined by the ST (Time before Sleep) parameter .The SM command is central to setting Sleep Mode configurations. By default, sleep modes aredisabled (SM=0) and the module remains in Idle/Receive Mode. When in this state, the module isconstantly ready to respond to serial or RF activity.Zigbee Protocol: Sleep Modes Pin/Host Controlled Sleep Pin sleep puts the module to sleep and wakes it from sleep according to the state of Sleep_RQ(pin 9). When Sleep_RQ is asserted (high), the module will finish any transmit or receiveoperations, and then enter a low power state. The module will not respond to either serial or RFactivity while in sleep.To wake a module operating in pin sleep, de-assert Sleep_RQ (pin 9). The module will wake whenSleep_RQ is de-asserted and is ready to transmit or receive when the CTS line is low. When themodule wakes from pin sleep, it sends a transmission to its parent router or coordinator (called apoll request) to see if it has buffered any data packets for the end device. The module will continueto poll its parent for data while it remains awake. If the parent receives an RF data packet destinedfor one or more of its end device children, it will transmit the packet to the end device upon receiptof a poll request. See section 4.3, "Sleep Mode Operation" for more information.Cyclic SleepCyclic sleep allows modules to wake periodically to check for RF data and sleep when idle. Whenthe SM parameter is set to 4, the module is configured to sleep for the time specified by the SPparameter . After the SP time expires, the module will wake and check for RF or serial data. Tocheck for RF data, the module sends a transmission to its parent router or coordinator (called apoll request) to see if its parent has any buffered data packets for the end device. If the parenthas data for the module, the module will remain awake to receive the data. Otherwise, the modulewill return to sleep. (See section 4.3, "Sleep Mode Operation" for more information.)If serial or RF data is received, the module will start the ST timer and remain awake until the timerexpires. While the module is awake, it will continue to send poll request messages to its parent tocheck for additional data. The ST timer will be restarted anytime serial or RF activity occurs. Themodule will resume sleep when the ST timer expires.When the module wakes from sleep, it asserts On/Sleep (pin 13) to provide a wake indicator to ahost device. If a host device wishes to sleep longer than SP time or to wake only when RF dataarrives, the SN command can be used to prevent On/Sleep from asserting for a multiple of SPtime. For example, if SP = 20 seconds, and SN = 5, the On/Sleep pin will remain de-asserted(low) for up to 100 seconds.Table 2‐01.Sleep Mode Configurations (Router / End Device Firmware Only)Sleep ModeSettingTransition into Sleep Mode Transition out of Sleep Mode (wake)Characteristics Related Commands Power Consumption SM=1Assert (high)Sleep_RQ (pin 9)De-assert (0V) Sleep_RQ (pin 9)Pin/Host controlled SM < 1uA SM=4Automatictransition tosleep mode asdefined by theST parameter Transition occurs after the cyclic sleep time interval elapses. The time interval is defined by the SP (Cyclic Sleep Period)parameter. RF module wakes after a pre-determined time interval to detect if RF data is present. SM, ST, SP, SN < 1uAIn the ZigBee protocol, sleep modes are only supported on end devices. See section 4.3, "SleepMode Operation" for more information.If CTS flow control is enabled, CTS (pin 12) is asserted (0V) when the module wakes and de-asserted (high) when the module sleeps, allowing for communication initiated by the host if desired.3. ZigBee Networks3.1. ZigBee Network FormationA ZigBee Personal Area Network (PAN) consists of one coordinator and one or more routers and/orend devices. A ZigBee Personal Area Network (PAN) is created when a coordinator selects achannel and PAN ID to start on. Once the coordinator has started a PAN, it can allow router andend device nodes to join the PAN.When a router or end device joins a PAN, it receives a 16-bit network address and can transmitdata to or receive data from other devices in the PAN. Routers and the coordinator can allow otherdevices to join the PAN, and can assist in sending data through the network to ensure data isrouted correctly to the intended recipient device. When a router or coordinator allows an enddevice to join the PAN, the end device that joined becomes a child of the router or coordinator thatallowed the join.End devices, however can transmit or receive data but cannot route data from one node toanother, nor can they allow devices to join the PAN. End devices must always communicatedirectly to the parent they joined to. The parent router or coordinator can route data on behalf ofan end device child to ensure it reaches the correct destination. End devices are intended to bebattery powered and can support low power modes.Figure 3‐01.Node Types / Sample of a Basic ZigBee Network TopologyThe network address of the PAN coordinator is always 0. When a router joins a PAN, it can alsoallow other routers and end devices to join to it. Joining establishes a parent/child relationshipbetween two nodes. The node that allowed the join is the parent, and the node that joined is thechild. The parent/child relationship is not necessary for routing data.3.1.1. Starting a ZigBee CoordinatorWhen a coordinator first comes up, it performs an energy scan on multiple channels (frequencies)to select an unused channel to start the PAN. After removing channels with high detected energylevels, the coordinator issues an 802.15.4 beacon request command on the remaining, low energylevel channels. Nearby routers or coordinators that have already joined a PAN respond to thebeacon request frame with a small beacon transmission indicating the PAN identifier (PAN ID) thatthey are operating on, and whether or not they are allowing joining. The coordinator will attemptto start on an unused PAN ID and channel. After starting, the coordinator may allow other devicesto join its PAN.3.1.2. Joining a RouterWhen a router first comes up, it must locate and join a ZigBee PAN. To do this, it issues an802.15.4 beacon request command on multiple channels to locate nearby PANs. Nearby routersand coordinators that have already joined a PAN respond to the beacon request frame with a smallbeacon transmission, indicating which channel and PAN ID they are operating on. The routerlistens on each channel for these beacon frames. If a valid PAN is found from one of the receivedbeacons, the router issues a join request to the device that sent the beacon. If joining succeeds,the router will then receive a join confirmation from the device, indicating the join was successful.。
谢谢楼上,问题已解决,B24的端口默认是激活8端口的.后来咨询了800,问题出在B24上,如果B24的firmware6.2.0e及以上版本对DS3950 5020 5100 5300有影响,需在交换机上进行设置后端口才会正常.解决方法:在交换机上输入portcfgfillword x 0where x is the port numberAbstract: DS5000 SYSTEMS NOT WORKING WITH BROCADE ON 8 GBPS HOST PORTST extDS5000 SYSTEMS NOT WORKING WITH BROCADE ON 8 GBPS HOST PORTSISSUE:When attaching System Storage DS5000 series subsystems orSystem Storage DS3950 storage subsystems to Brocade 8 Gigabit(Gb) Fibre Channel switches running at 8 Gb host port speeds,the host connection will not establish at 8 Gigabits per second(Gbps). The following Brocade FC switches, running firmware6.2.0e or above, are affected:2498-B40 Brocade 51002498-B80 Brocade 53002499-192 Brocade DCX-4S2499-384 Brocade DCXISOLATION AIDS:- The system may be any o f the following IBM servers:DS3950 Express, T ype 1814, any modelDS5020 Disk Controller (1814-20A), any modelDS5100 Storage Controller (1818-51A), any modelDS5300 Storage Controller (1818-53A), any model- This tip is not option specific.- This tip is not software specific.- The system has the sympto m described above.WorkaroundThe following workaround should be used on the Brocade switch to establish 8 Gb host port connections.T o enable IDLE on ports, execute the following command on the switch consoleportcfg fillword x 0where x is the port number.Once ports are set to IDLE on Brocade switches, the connection with the DS5000 will be established at 8 Gbps.DET AILS:Brocade switches that support 8 Gbps host port speeds have a connection issue with DS5000 series subsystems. If one of the Brocade switches that supports 8 Gbps is shipped with 6.2.0e firmware and above, the fillword setting is ARB instead of IDLE.In order to work at 8 Gbps host port speeds, the following command should be executed on the affected switches:portcfg fillword x 0where x is the port number.T o check the status of the ports, use the following command:portcfgshow0- Fillword set to IDLE (This is how it should be set.)1- Fillword set to ARB。
非凸两分块问题乘子交替方向法的收敛性分析邓钊;晁绵涛;简金宝【摘要】The Alternating Direction Method of Multipliers(ADMM)is an effective method for large scale optimization problems.While the convergence of ADMM has been clearly recognized in the case of convex,the convergence result of ADMM in the case of nonconvex is still an open problem.In this paper,under the assumption that the augmented Lagrangian function satisfies the Kurdyka-Loj asiewicz inequality and the penalty parameter is greater than a constant,we an-alyze the convergence of ADMM for a class of nonconvex optimization problems whose obj ec-tive function is the sum of two block nonconvex functions.%乘子交替方向法(ADMM)求解大规模问题十分有效.ADMM在凸情形下的收敛性已被清晰认识,但非凸问题 ADMM的收敛性结果还很少.本文针对非凸两分块优化问题,在增广拉格朗日函数满足 Kurdyka-Loj as-iewicz不等式性质且罚参数大于某个常数的条件下,证明了 ADMM的收敛性.【期刊名称】《广西科学》【年(卷),期】2016(023)005【总页数】6页(P422-427)【关键词】乘子交替方向法;Kurdyka-Lojasiewicz不等式;非凸优化;收敛性【作者】邓钊;晁绵涛;简金宝【作者单位】广西大学数学与信息科学学院,广西南宁 530004;广西大学数学与信息科学学院,广西南宁 530004;玉林师范学院数学与统计学院,广西玉林537000【正文语种】中文【中图分类】O221.2【研究意义】乘子交替方向法(ADMM)求解大规模分布式计算问题十分有效.ADMM既能分散地收集和存储这些数据集,又能在并行和分布式的环境下求解这些问题.ADMM适合求解分布式凸优化问题,尤其适用于出现在统计学、机器学习和相关领域中的大规模问题,其重要性日益凸显.【前人研究进展】ADMM的思想最早起源于20世纪50年代,算法在20世纪70年代中期由Glowinski和Marrocco[1],以及Gabay和Mercier[2]首次提出.20世纪80年代,乘子交替方向法的研究和应用非常广泛,直到20世纪90年代中期,乘子交替方向法求解凸优化问题的很多理论结果,已经得到很好的证明.传统ADMM是求解凸两分块问题十分有效的方法[1-2],其直接应用到问题(0.5)的迭代框架如下在凸情形下,ADMM的收敛性已被充分认识[3].非凸问题ADMM的收敛性分析仅有初步的结果,其研究是当前的热点问题[4-6].文献[7]考虑如下非凸问题min f(x)+g(y)s.t. Ax=y,文献[8]分析如下Bregman ADMM算法的收敛性【本研究切入点】最近,文献[9]在矩阵A列满秩,增广拉格朗日函数满足KL性质(参见定义1.1)且罚参数大于某个常数的条件下,分析了传统ADMM算法(0.1)求解非凸问题(0.3)的全局收敛性.我们考虑如下两分块极小化问题min f(x) + g(y)s.t. Ax+By=0,【拟解决的关键问题】本文在不要求矩阵A列满秩,B不一定是单位阵,在Lβ(w)满足KL性质且罚参数β大于某个常数的条件下分析了ADMM算法(0.1)求解问题(0.5)的收敛性.下面,给出本文理论分析所需的一些概念与性质.λ++(BTB)表示矩阵BTB最小正特征值.∂f(x)表示函数f在点x处的极限次微分[5],对于任意x∈Rn是函数f的极小值点的必要条件是:0∈∂f(x),满足这个条件的点称为关键点或稳定点,函数f关键点集记为crit f.定义1.1[10](Kurdyka-Lojasiewicz性质)设函数f:Rn→Rn∪{+∞}是正常下半连续函数,对于任意实数η1,η2(η1<η2),令[η1<f<η2]=x∈{Rn∶η1<f(x)<η2,设x*∈dom∂f,若存在η∈(0,+∞],x*的邻域U,以及一个连续的凹函数φ:[0,η)→R+,满足如下条件(i)φ(0)=0;(ii)φ在0处连续,在区间(0,η)上一阶连续可微;(iii)φ′(s)>0,∀s∈(0,η);(iv)对于任意的x∈U∩[f(x*)<f<φ ′(f(x)-f(x*))d(0,∂ f(x))≥1.满足上述性质(i)、(ii)、(iii)的函数全体记为Φη.引理1.1[11](uniformized KL property)设Ω是一个紧集,函数f:Rn→Rn∪{+∞}是正常下半连续函数.设函数f在集合Ω上取常数,并在Ω中任一点处满足KL性质,则存在>0,η>0,φ ∈Φη,对于任意的和x∈{x∈Rn:d(x,ω)<},有引理1.2[12]若h:Rn→R为L-Lipschitz可微函|h(y)-h(x)-<‖y-x‖2.假设{wk=(xk,yk,λk)}是算法(0.1)产生的有界序列,算法(0.1)的收敛性分析框架如下:第一步,证明{Lβ(wk)}单调递减;第二步,证明‖wk+1-wk‖2<+∞;第三步,利用Lβ(·)的KL性质,得出序列{wk}的任一聚点都是问题(0.5)的一个稳定点.由算法(0.1)中每个子问题的最优性条件,有进一步,可得假设2.1 假设以下条件成立(i)Im(A)⊆Im(B);(ii)存在利普希茨系数分别为M>0,P>0的利普希茨连续函数H:Im(B)→Rn,F:Im(A)→Rn,使得首先,证明{Lβ(wk)}k∈N是递减序列.引理2.1 Lβ(wk+1)≤Lβ(wk)-δ‖yk+1-yk‖2,其中.证明由增广拉格朗日函数的定义,可得利用yk+1的最优性可得由引理1.2和式(2.2)中第二式可得把上式代入式(2.4)可得由λk+1=λk-β(Axk+1+Byk+1)可得把上式代入式(2.5)右端可得由λk+1=λk-β(Axk+1+Byk+1)可得λk+1-λk=-β(Axk+1+Byk+1)∈Im(B).‖λk+1-λk‖≤μ‖B(λk+1-λk)‖=μ‖g(yk+1)-g(yk)‖≤μL‖yk+1-yk‖.由H的性质可得yk=H(Byk),从而‖yk+1-yk‖=‖H(Byk+1)-H(Byk)‖≤M‖B(yk+1-yk)‖.Lβ(xk+1,yk+1,λk+1)≤Lβ(xk+1,yk,λk)+结合式(2.7)、式(2.8)有利用xk+1的最优性可得引理‖wk+1-wk‖2<+∞.证明由于序列{wk=(xk,yk,λk)}有界,则存在收敛子列{wkj},设.由f下半连续及g 连续,可知Lβ(w)下半连续.从而接下来只需证明‖xk+1-xk‖2<+∞.由ADMM算法(0.1)第三式有两式相减,可得λk+1-λk=(λk-λk-1)+β(Axk-Axk+1)+β(Byk-Byk+1).利用不等式(a+b+c)2≤3(a2+b2+c2)可得‖β(Axk-Axk+1)‖2≤3(‖λk+1-λk‖2+‖λk-λk-1‖2+β2‖B(yk+1-yk)‖2).由F的性质可得xk=F(Axk),进而‖‖xk-xk+1‖2.故‖wk+1-wk‖2<+∞.引理2.3 存在ζ>0,对于任意k有d(0,∂Lβ(wk+1))≤ζ‖yk+1-yk‖.证明由增广拉格朗日函数定义,可得进一步结合式(2.2)可得令,‖‖≤ζ1‖yk+1-yk‖+ζ2‖λk+1-λk‖.d(0,∂Lβ(wk+1))≤ζ‖yk+1-yk‖.引理2.4 设序列{wk}的全体极限点记为S(w0),则(i)S(w0)是一个非空紧集,并且d(wk,S(w0))→0,k→+∞;(ii)S(w0)⊂critLβ;(iii)Lβ(·)在S(w0)上取有限值且为常数,且证明(i)式由S(w0)的定义直接可得.(ii)设(x*,y*,λ*)∈S(w0),则存在子列{(xkj,ykj,λkj)}使得(xkj,ykj,λkj)→(x*,y*,λ*),(kj→+∞).由xk+1的最优性有Lβ(xk+1,yk,λk)≤Lβ(x*,yk,λk).由函数Lβ(·)的下半连续性,有(iii)对于任意点(x*,y*,λ*)∈S(w0),存在子列(xkj,ykj,λkj)→(x*,y*,λ*).结合Lβ(xkj+1)收敛,以及{Lβ(wk)}k∈N单调递减,可得最后,给出非凸问题(0.5)的ADMM算法(0.1)的收敛性分析.定理2.1 若Lβ(w)满足KL性质,则(ii)序列{wk}收敛到函数Lβ(·)的一个关键点.证明由引理2.4知(i)存在整数k0使得Lβ(wk0)=Lβ(w*)成立,由引理2.1可知,对于任意的k>k0,有‖yk+1-yk‖2≤Lβ(wk)-Lβ(wk+1)≤(ii)对任意的k均有Lβ(wk)>Lβ(w*)成立.由d(wk,S(w0))→0可知,对于任意给定的ε>0,存在k1>0,当k>k1时,有d(wk,S(w0))<ε.又根据Lβ(wk)→Lβ(w*)可知,对于任意给定的η>0,存在k2>0,当k>k2时,有Lβ(wk)<Lβ(w*)+η.从而当时,有d(wk,S(w0))<ε,Lβ(w*)<Lβ(wk)<Lβ(w*)+η.由于S(w0)是非空紧集,函数Lβ(·)在集合φ′(Lβ(wk)-Lβ(w*))d(0,∂Lβ(wk))≥φ(Lβ(wk)-Lβ(w*))-φ(Lβ(wk+1)-由引理2.3及φ′(Lβ(wk)-Lβ(w*))>0,可得Lβ(wk)-Lβ(wk+1)≤令Δp,q=φ(Lβ(wp)-Lβ(w*))-φ(Lβ(wq)-Lβ(w*)).由引理2.1可得,对于任意的有δ‖yk+1-yk‖2≤ζ‖yk-yk-1‖Δk,k+1,‖yk+1-yk‖‖.2‖yk+1-yk‖≤‖yk-yk-1‖,注意到φ(Lβ(wm+1)-Lβ(w*))>0,移项并且令m→+∞,可得‖xk+1-xk‖(‖λk+1-λk‖2+‖λk-λk-1‖2+β2‖(‖λk+1-λk‖+‖λk-λk-1‖+β‖B(yk+1-yk)‖),‖wk+1-wk‖=(‖xk+1-xk‖2+‖yk+1-yk‖2+‖‖xk+1-xk‖+进一步可知序列wk是Cauchy序列(参见文献[11]),所以序列{wk}收敛,定理得证. 本文针对非凸两分块优化问题,在不要求矩阵A列满秩,B不一定是单位阵,在Lβ(w)满足Kurdyka-Lojasiewicz性质且罚参数大于某个常数的条件下,证明了非凸问题ADMM的收敛性.【相关文献】[1] GLOWINSKI R,MARROCO A.Sur l’approximation,par elements finis d’ordre un,et la resolution,par penalisation-dualité,d’une classe de problèms de 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SOE主卡FW422(B)1基本说明SOE主卡是整个SOE系统的核心部件(在SCnetⅡ中FW422(B)处于与主控制卡同等的地位),负责收集从卡中的SOE原始记录,并将SOE原始数据打上完整的时间标签后保存到本地数据记录库中,当服务器来索要数据时,将SOE记录送给服务器。
主卡可诊断网络上各SOE从卡的状态,通信网络、同步网络的故障情况。
1.1FW422(B)的功能特点FW422(B)具备以下功能特点:¾采用一个32位嵌入式微处理器,功能强、速度快、单站容量大。
¾控制软件和算法模块采用模块化设计,核心程序固化在FLASH存储器中;¾提供3M字节的存储空间;¾提供1M字节的数据区,为SOE原始数据库准备了充足的数据空间(≥10000条);¾SCnetⅡ网络采用冗余的10M/100Mbps工业以太网,充分保证了系统数据传输的实时性、可靠性和网络开放性;¾提供SOE系统主卡、SOE系统从卡的综合故障诊断;¾具有掉电保护功能,在系统断电的情况下,组态、SOE系统记录数据均不会丢失;¾SOE分辨率精度:同一SOE主卡内≤ 1ms;不同SOE主卡内≤ 2ms;¾采用SNTP和GPS秒脉冲信号(PPS)实现SOE系统的时钟同步方式。
1.2FW422(B)适用系统SOE系统主卡FW422(B)适用于ECS-100控制系统的SOE系统。
2性能指标表 2-1卡件性能指标型号 FW422(B)电源5V电源(5.0~5.3)VDC,400mA供电24V电源(24±0.7)VDC,<50mA技术指标驱动能力最多可带16个SOE从卡。
卡件内存SOE记录存储10000条(掉电保持)。
与SOE 从卡的通讯扫描周期<5 s同一SOE主卡内≤ 1msSOE分辨精度不同SOE主卡内≤ 2msRS485方式 ,波特率9600,11位方式 无中继器<100米,室内,非隔离 SOE 主卡与SOE 从卡 有中继器<600米,隔离EMC 指标抗电快速脉冲群干扰 满足IEC 61000-4-4(GB/T 17626.4) 抗浪涌冲击干扰 满足IEC 61000-4-5(GB/T 17626.5) 抗射频电磁波干扰 满足IEC 61000-4-3(GB/T 17626.3) 抗静电放电干扰 满足IEC 61000-4-11(GB/T 17626.11) 其它工作温度 (0~50)℃工作湿度 (10~90)%,无凝露 存储温度 (-40~+80)℃存储湿度 (5~95)%,无凝露 工作大气压(62~106)kPa3 使用说明SOE 系统主卡FW422(B )工作原理如图 3-1所示。
SP339E RS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATIONGENERAL DESCRIPTIONThe SP339 is an advanced multiprotocol transceiver supporting RS-232, RS-485, and RS-422 serial standards in a 40 pin QFN package. Integrated cable termination and four configuration modes allow all three protocols to be used interchangeably over a single cable or connector with no additional switching components. Full operation requires only four external charge pump capacitors.The RS-485/422 modes feature one driver and one receiver (1TX/1RX) in both half and full duplex configurations. The RS-232 mode (3TX/5RX) provides full support of all eight signals commonly used with the DB9 RS-232 connector. A dedicated diagnostic loopback mode is also provided.The high speed drivers operate up to 20Mbps in RS-485/422 modes, and up to 1Mbps in RS-232 mode. All drivers can be slew limited to 250kbps in any mode to minimize electromagnetic interference (EMI). All transmitter outputs and receiver inputs feature robust electrostatic discharge (ESD) protection to±15kV IEC-61000-4-2 Air Gap, ±8kV IEC-61000-4-2 Contact, and ±15kV Human Body Model (HBM). Each receiver output has full fail-safe protection to avoid system lockup, oscillation, or indeterminate states by defaulting to logic-high output level when the inputs are open, shorted, or terminated but undriven. No external biasing resistors are required. The RS-232 receiver inputs include a 5kΩ pull-down to ground. The RS-485/422 receiver inputs are high impedance (>96kΩwhen termination is disabled), allowing up to 256 devices on a single communication bus (1/8th unit load).The SP339 operates from a single power supply, either 3.3V or 5V, with low idle current (2mA typical in all modes). The shutdown mode consumes less than 10µA for low power standby operation.FEATURES∙Pin selectable Cable Termination∙No external resistors required for RS-485/422 termination and biasing∙3.3V or 5V Single Supply Operation∙Robust ESD Protection on bus pinsn±15kV IEC 61000-4-2 (Air Gap)n± 8kV IEC 61000-4-2 (Contact)n±15kV Human Body Model (HBM)∙Max Data Rate of 20Mbps in RS-485/422 Modes and up to 1Mbps in RS-232 Modes∙Pin selectable 250kbps Slew Limiting∙3 Drivers, 5 Receivers RS-232/V.28∙1 Driver, 1 Receiver RS-485/422n Full and Half Duplex Configurationn1/8th Unit Load, up to 256 receivers on bus∙RS-485/422 Enhanced Failsafe for open, shorted, or terminated but idle inputs∙Space saving 6mm x 6mm QFN-40 Package∙Pin compatible with SP338ETYPICAL APPLICATIONS∙Dual Protocol Serial Ports (RS-232 or RS-485/422)∙Industrial Computers∙Industrial and Process Control Equipment∙Point-Of-Sale Equipment∙Networking Equipment∙HVAC Controls Equipment∙Building Security and Automation EquipmentORDERING INFORMATION(1)P ART N UMBER O PERATING T EMPERATURE R ANGE L EAD-F REE P ACKAGE P ACKAGING M ETHODSP339EER1-L-40°C to +85°CYes(2)40-pin QFN TraySP339EER1-L/TR-40°C to +85°C40-pin QFN Tape and Reel NOTE:1. Refer to /SP339E for most up-to-date Ordering Information.2. Visit for additional information on Environmental Rating.1SP339E2RS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATIONREV. 1.0.6CAUTION:ESD (ElectroStatic Discharge) sensitive device. Permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. Personnel should be properly grounded prior to handling this device. The protective foam should be discharged to the destination socket before devices are removed.ABSOLUTE MAXIMUM RATINGSThese are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections to the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device.Supply Voltage V CC-0.3V to +6.0VReceiver Input Voltage (from Ground)±18V Driver Output Voltage (from Ground)±18V Short Circuit Duration, TX out to Ground Continuous Voltage at TTL Input Pins -0.3V to (V CC + 0.5V)Storage Temperature Range -65°C to +150°CLead Temperature (soldering, 10s)+300°C Power Dissipation 40-pin QFN (derate 17mW/°C above +70°C)500mWESD RatingsHBM - Human Body Model (Tx Output & Rx Input pins, R1-R9)±15kV HBM - Human Body Model (All other pins)±4kV IEC 61000-4-2 Airgap Discharge (Tx Output & Rx Input pins, R1-R9)±15kV IEC 61000-4-2 Contact Discharge (Tx Output & Rx Input pins, R1-R9)±8kVSP339E3REV. 1.0.6RS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATIONPIN DESCRIPTIONS BY MODE (MODE1, MODE0)Pin Name 00, Figure 101, Figure 210, Figure 311, Figure 41L1R1 Output 112L2R2 Output R1 Output R1 Output 3L3T1 Input T1 InputT1 Input4L4T2 Input 5L6R3 Output 116L7T3 Input 7L8R4 Output 118L9R5 Output119VCC V CC 10GND Ground11SLEW SLEW = V CC enables 250kbps slew limiting12DIR1T1 Enable,R1 DisableT1 Enable13N/C This pin is not used and is not connected internally14MODE0010115MODE1001116N/C This pin is not used and is not connected internally17TERM Enables RS-485/422 receiver termination18N/C This pin is not used and is not connected internally 19ENABLE ENABLE = V CC for operation, ENABLE = 0V for shutdown20VCCV CCSP339ERS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATION REV. 1.0.6 PIN DESCRIPTIONS BY MODE (MODE1, MODE0)Pin Name00, Figure101, Figure210, Figure311, Figure421R9R5 Input22R8R4 Input23GND Ground24R7T3 Output25R6R3 Input26GND Ground27R4T2 Output R1 Input B 28R3T1 Output R1 Input A 29GND Ground30R2R2 Input R1 Input A, T1 Out A T1 Out A 31R1R1 Input R1 Input B, T1 Out B T1 Out B 32VCC V CC - 1.0μF to ground recommended for supply decoupling33VSS V SS - Charge pump negative supply, 0.1μF from ground34C2-C2+ - Charge pump cap 2 negative lead35C1-C1- - Charge pump cap 1 negative lead36GND Ground37C1+C1+ - Charge pump cap 1 positive lead, 0.1μF38VCC V CC39C2+C2+ - Charge pump cap 2 positive lead, 0.1μF40VDD V DD - Charge pump positive supply, 0.1μF to ground4SP339E5REV. 1.0.6RS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATIONSUGGESTED DB9 CONNECTOR PINOUTDB9Pin RS-232RS-485/422Full DuplexRS-485Half Duplex1DCD TX-Data-2RXD TX+Data+3TXD RX+4DTRRX-5Ground6DSR 7RTS 8CTS 9RISP339E6RS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATIONREV. 1.0.6ELECTRICAL CHARACTERISTICSU NLESS OTHERWISE NOTED :V CC = +3.3V ±5% or +5.0V ±5%, C1-C4 = 0.1μF; T A = T MIN to T MAX . Typical values are at V CC = 3.3V, T A = +25°C.S YMBOLP ARAMETERSM IN .T YP .M AX .U NITSC ONDITIONSDC CHARACTERISTICSI CC Supply Current (RS-232)28mA No load, idle inputs I CC Supply Current (RS-485)28mA No load, idle inputs I CCVcc Shutdown Current110μAENABLE = 0VTRANSMITTER and LOGIC INPUT PINS: Pins 3, 4, 6, 11, 12, 14, 15, 17-19V IH Logic Input Voltage High 2.0V V CC = 3.3V V IH Logic Input Voltage High 2.4V V CC = 5.0VV IL Logic Input Voltage Low0.8V I IL Logic Input Leakage Current Low 1μA Input Low (V IN = 0V)I IH Logic Input Leakage Current High 1μA Input High (V IN = V CC ), pins 3, 4 and 6I PD Logic Input Pull-down Current 50μA Input High (V IN = V CC ), pins 11, 12, 14, 15, 17-19V HYSLogic Input Hysteresis200mVRECEIVER OUTPUTS: Pins 1, 2, 5, 7, 8V OH Receiver Output Voltage High V CC -0.6VI OUT = -1.5mA V OL Receiver Output Voltage Low 0.4V I OUT = 2.5mA I OSS Receiver Output Short Circuit Current ±20±60mA 0 ≤ V O ≤ V CC I OZReceiver Output Leakage Current±0.1±1μA0 ≤ V O ≤ V CC,Receivers disabledSP339E7REV. 1.0.6RS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATIONELECTRICAL CHARACTERISTICS (Continued)U NLESS OTHERWISE NOTED :V CC = +3.3V ±5% or +5.0V ±5%, C1-C4 = 0.1μF; T A = T MIN to T MAX . Typical values are at V CC = 3.3V, T A = +25°C.S YMBOLP ARAMETERSM IN .T YP .M AX .U NITSC ONDITIONSSINGLE-ENDED RECEIVER INPUTS (RS-232)V IN Input Voltage Range -15+15V V ILInput Threshold Low0.6 1.2V V CC = 3.3V 0.81.5V V CC = 5.0V V IH Input Threshold High 1.52.0V V CC =3.3V 1.8 2.4V V CC = 5.0VV HYS Input Hysteresis 0.3V R INInput Resistance357k Ω-15V ≤ V IN ≤ +15V SINGLE-ENDED DRIVER OUTPUTS (RS-232)V O Output Voltage Swing ±5.0±5.5V Output loaded with 3k Ω to Gnd ±7.0V No load output I SC Short Circuit Current ±60mA V O = 0VR OFFPower Off Impedance30010MΩV CC = 0V, V O = ±2VSP339E8RS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATIONREV. 1.0.6ELECTRICAL CHARACTERISTICS (Continued)U NLESS OTHERWISE NOTED :V CC = +3.3V ±5% or +5.0V ±5%, C1-C4 = 0.1μF; T A = T MIN to T MAX . Typical values are at V CC = 3.3V, T A = +25°C.S YMBOLP ARAMETERSM IN .T YP .M AX .U NITSC ONDITIONSDIFFERENTIAL RECEIVER INPUTS (RS-485 / RS-422)R IN Receiver Input Resistance 96k ΩTERM = 0V,-7V ≤ V IN ≤ +12VV TH Receiver Differential Threshold Voltage -200-125-50mV ∆V TH Receiver Input Hysteresis 25mV V CM = 0V I INReceiver Input Current125μA V IN = +12V -100μA V IN = -7VR TERM Termination Resistance100120155ΩTERM = V CC , Figure 5-7V ≤ V CM ≤ +12V R TERMTermination Resistance 100120140ΩTERM = V CC , Figure 5V CM = 0V DIFFERENTIAL DRIVER OUTPUTS (RS-485 / RS-422)V ODDifferential Driver Output2V CC V R L = 100Ω (RS-422), Figure 61.5V CC V R L = 54Ω (RS-485), Figure 61.5V CC V -7V ≤ V CM ≤ +12V, Figure 7V CCV No Load∆V OD Change In Magnitude of Differential Output Voltage-0.2+0.2V R L = 54Ω or 100Ω, Figure 6V CM Driver Common Mode Output Voltage 3V R L = 54Ω or 100Ω, Figure 6∆V CM Change In Magnitude ofCommon Mode Output Voltage 0.2V R L = 54Ω or 100Ω, Figure 6I OSDDriver Output Short Circuit Current-250250mA -7V ≤ V O ≤ +12V, Figure 8I ODriver Output Leakage Current100μADIR1 = 0V in Mode 11,or ENABLE = 0V,V O = +12V, V CC = 0V or 5.25V -100μA DIR1 = 0V in Mode 11,or ENABLE = 0V,V O = -7V, V CC = 0V or 5.25VSP339E9REV. 1.0.6RS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATIONTIMING CHARACTERISTICSU NLESS OTHERWISE NOTED :V CC = +3.3V ±5% or +5.0V ±5%, C1-C4 = 0.1μF; T A = T MIN to T MAX . Typical values are at V CC = 3.3V, T A = +25°C.S YMBOL P ARAMETERSM IN .T YP .M AX .U NITSC ONDITIONSALL MODES t ENABLE Enable from Shutdown 1000ns t SHUTDOWNEnable to Shutdown1000nsRS-232, DATA RATE = 250kbps (SLEW = Vcc), ONE TRANSMITTER SWITCHINGMaximum Data Rate250kbps R L = 3k Ω, C L = 1000pF t RHL , t RLH Receiver Propagation Delay 100ns C L = 150pF, Figure 9∣t RHL -t RLH ∣Receiver Propagation Delay Skew 100ns t DHL , t DLH Driver Propagation Delay 1400ns R L = 3k Ω, C L = 2500pF,Figure 10∣t DHL -t DLH ∣Driver Propagation Delay Skew600nst SHL, t SLHTransition Region Slew Rate from +3.0V to -3.0V or -3.0V to +3.0V430V/μsV CC = 3.3V, R L = 3k Ω to 7k Ω,C L = 150pF to 2500pF ,Figure 10t SHL, t SLHTransition Region Slew Rate from +3.0V to -3.0V or -3.0V to +3.0V630V/μsV CC = 3.3V, R L = 3k Ω to 7k Ω,C L = 150pF to 2500pF ,T A = 25°C, Figure 10RS-232, DATA RATE = 1Mbps (SLEW = 0V), ONE TRANSMITTER SWITCHINGMaximum Data Rate1Mbps R L = 3k Ω, C L = 250pF t RHL , t RLH Receiver Propagation Delay 100ns C L = 150pF, Figure 9∣t RHL -t RLH ∣Receiver Propagation Delay Skew 100ns t DHL , t DLH Driver Propagation Delay 300ns R L = 3k Ω, C L = 1000pF,Figure 10∣t DHL -t DLH ∣Driver Propagation Delay Skew150nst SHL, t SLHTransition Region Slew Rate from +3.0V to -3.0V or -3.0V to +3.0V15150V/μsV CC = 3.3V, R L = 3k Ω to 7k Ω,C L = 150pF to 1000pF ,Figure 10t SHL, t SLHTransition Region Slew Rate from +3.0V to -3.0V or -3.0V to +3.0V24150V/μsV CC = 3.3V, R L = 3k Ω to 7k Ω,C L = 150pF to 1000pF ,T A = 25°C, Figure 10SP339E10RS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATIONREV. 1.0.6TIMING CHARACTERISTICS (Continued)U NLESS OTHERWISE NOTED :V CC = +3.3V ±5% or +5.0V ±5%, C1-C4 = 0.1μF; T A = T MIN to T MAX . Typical values are at V CC = 3.3V, T A = +25°C.S YMBOLP ARAMETERSM IN .T YP .M AX .U NITSC ONDITIONSRS-485/RS-422, DATA RATE = 250kbps (SLEW = Vcc), ONE TRANSMITTER SWITCHINGMaximum Data Rate250kbps R L = 54Ω, C L = 50pF t RPHL , t RPLHReceiver Propagation Delay50150ns C L = 15pF , Figure 11∣t RPHL -t RPLH ∣Receiver Propagation Delay Skew 20ns t DPHL , t DPLHDriver Propagation Delay5001000ns R L = 54Ω, C L = 50pF,Figure 12∣t DPHL -t DPLH ∣Driver Propagation Delay Skew100ns t DR, t DFDriver Rise and Fall Time3006501200nst RZH , t RZL Receiver Output Enable Time 200ns C L = 15pF , Figure 13t RHZ , t RLZ Receiver Output Disable Time 200ns t DZH , t DZL Driver Output Enable Time 1000ns R L = 500Ω, C L = 50pF,Figure 14t DHZ , t DLZDriver Output Disable Time200nsRS-485/RS-422, DATA RATE = 20Mbps (SLEW = 0V), ONE TRANSMITTER SWITCHINGMaximum Data Rate20Mbps R L = 54Ω, C L = 50pF t RPHL , t RPLHReceiver Propagation Delay50150ns C L = 15pF , Figure 11∣t RPHL -t RPLH ∣Receiver Propagation Delay Skew 10ns t DPHL , t DPLHDriver Propagation Delay30100ns R L = 54Ω, C L = 50pF,Figure 12∣t DPHL -t DPLH ∣Driver Propagation Delay Skew10ns t DR, t DFDriver Rise and Fall Time1020nst RZH , t RZL Receiver Output Enable Time 200ns C L = 15pF , Figure 13t RHZ , t RLZ Receiver Output Disable Time 200ns t DZH , t DZL Driver Output Enable Time 200ns R L = 500Ω, C L = 50pF,Figure 14t DHZ , t DLZDriver Output Disable Time200nsREV. 1.0.6RS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATION BLOCK DIAGRAM BY MODE (MODE1, MODE0)F IGURE 1. M ODE 00 - L OOPBACKRS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATION REV. 1.0.6 F IGURE 2. M ODE 01 - RS-232REV. 1.0.6RS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATION F IGURE 3. M ODE 10 - RS-485 H ALF D UPLEXRS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATION REV. 1.0.6 F IGURE 4. M ODE 11 - RS-485/422 F ULL D UPLEXREV. 1.0.6RS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATION TEST CIRCUITSF IGURE 5. RS-485/422 R ECEIVER T ERMINATION R ESISTANCEF IGURE 6. RS-485/422 D IFFERENTIAL D RIVER O UTPUT V OLTAGEF IGURE 7. RS-485/422 D IFFERENTIAL D RIVER O UTPUT V OLTAGE OVER C OMMON M ODEF IGURE 8. RS-485/422 D RIVER O UTPUT S HORT C IRCUIT C URRENTRS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATION REV. 1.0.6 F IGURE 9. RS-232 R ECEIVER P ROPAGATION D ELAYF IGURE 10. RS-232 D RIVER P ROPAGATION D ELAYREV. 1.0.6RS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATION F IGURE 11. RS-485/422 R ECEIVER P ROPAGATION D ELAYF IGURE 12. RS-485/422 D RIVER P ROPAGATION D ELAY AND R ISE/F ALL T IMESRS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATION REV. 1.0.6 F IGURE 13. RS-485/422 R ECEIVER O UTPUT E NABLE/D ISABLE T IMESREV. 1.0.6RS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATION F IGURE 14. RS-485/422 D RIVER O UTPUT E NABLE/D ISABLE T IMESRS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATION REV. 1.0.6 PRODUCT SUMMARYThe SP339 is an advanced multiprotocol transceiver supporting RS-232, RS-485, and RS-422 serial standards in a 40 pin QFN package. Integrated cable termination and four configuration modes allow all three protocols to be used interchangeably over a single cable or connector with no additional switching components. The RS-485/422 modes feature one driver and one receiver (1TX/1RX) in both half and full duplex configurations. The RS-232 mode (3TX/5RX) provides full support of all eight signals commonly used with the DB9 RS-232 connector. A dedicated mode is also available for diagnostic loopback testing.INTERNALLY SWITCHED CABLE TERMINATIONEnabling and disabling the RS-485/422 termination resistor is one of the largest challenges system designers face when sharing a single connector or pair of lines across multiple serial protocols. A termination resistor may be necessary for accurate RS-485/422 communication, but must be removed when the lines are used for RS-232. SP339 provides an elegant solution to this problem by integrating the termination resistor and switching control, and allowing it to be switched in and out of the circuit with a single pin. No external switching components are required.ENHANCED FAILSAFEOrdinary RS-485 differential receivers will be in an indeterminate state whenever the data bus is not being actively driven. The enhanced failsafe feature of the SP339 guarantees a logic-high receiver output when the receiver inputs are open, shorted, or terminated but idle/undriven. The enhanced failsafe interprets 0V differential as a logic high with a minimum 50mV noise margin, while maintaining compliance with the EIA/TIA-485 standard of ±200mV. No external biasing resistors are required, further easing the usage of multiple protocols over a single connector.±15kV ESD PROTECTIONESD protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. The bus pins (driver outputs and receiver inputs) have extra protection structures, which have been tested up to ±15kV without damage. These structures withstand high ESD in all states: normal operation, shutdown and powered down.ESD protection is be tested in various ways. MaxLinear uses the following methods to qualify the protection structures designed into SP339:±15kV using the Human Body Model (HBM)± 8kV using IEC 61000-4-2 Contact Discharge± 15kV using IEC 61000-4-2 Air Gap DischargeThe IEC 61000-4-2 standard is more rigorous than HBM, resulting in lower voltage levels compared with HBM for the same level of ESD protection. Because IEC 61000-4-2 specifies a lower series resistance, the peak current is higher than HBM. The SP339 has passed both HBM and IEC 61000-4-2 testing without damage. DIAGNOSTIC LOOPBACK MODEThe SP339 includes a diagnostic digital loop back mode for system testing as shown in Figure1. The loopback mode connects the TTL driver inputs to the TTL receiver outputs, bypassing the analog driver and receiver circuitry. The analog/bus pins are internally disconnected in this mode.SP339E REV. 1.0.6RS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATION MECHANICAL DIMENSIONSF IGURE 15. QFN-40 P ACKAGE O UTLINE D RAWINGSP339ERS-232/RS-485/RS-422 TRANSCEIVER WITH INTERNAL TERMINATION REV. 1.0.6 RECOMMENDED LAND PATTERN AND STENCILF IGURE 16. QFN-40 R ECOMMENDED PCB L AND P ATTERN AND S TENCILF IGURE 17. P IN 1 O RIENTATION IN T APEThe content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by MaxLinear, Inc. MaxLinear,Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in the informational content contained in this guide. Complying with all applicable copyright laws is the responsibility of the user. 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Research Reports onMathematical andComputing SciencesDepartment of Mathematical and Computing Sciences ISSN 1342-2804Dynamic Enumeration of All Mixed CellsTomohiko Mizutani,Akiko Takeda andMasakazu KojimaJanuary 2006,B–422B-422Dynamic Enumeration of All Mixed CellsTomohiko Mizutani†1,Akiko Takeda†2and Masakazu Kojima†3January2006Abstract.The polyhedral homotopy method,which has been known as a powerful numerical method for computing all isolated zeros of a polynomial system,requires all mixed cells of the support of the system to construct a family of homotopy functions.Finding the mixed cells is formulated in terms of a linear inequality system with an additional combinatorial condition.It is essential in computational efficiency how we construct an enumeration tree among a family of linear inequalities induced from it such that every mixed cell corresponds to a unique feasible leaf node.This paper proposes a dynamic construction of an enumeration tree,which branches each parent node into its child nodes so that the number of feasible child nodes is expected to be small;hence we can prune a lot of subtrees which do not contain any mixed cell.Numerical results exhibit that our dynamic construction of an enumeration tree works very efficiently for large scale polynomial systems; for example,it generated all mixed cells of the cyclic-15problem for thefirst time in less than16hours.Key words.Mixed Cell,Polyhedral Homotopy Method,Polynomial System,Dynamic Enumeration, Linear Programming.†Department of Mathematical and Computing Sciences,Tokyo Institute of Technology,2-12-1Oh-Okayama,Meguro-ku,Tokyo152-8552Japan.†1:mizutan8@is.titech.ac.jp.†2:takeda@is.titech.ac.jp.†3:kojima@is.titech.ac.jp.1IntroductionThe polyhedral homotopy continuation method[12],which is based on Bernshtein’s theory [1],is known to be a powerful numerical method[5,10,11,13,14,22]for computing all isolated zeros of a polynomial system f(x)=(f1(x),...,f n(x)).Let R and C be the set of real and complex numbers,respectively.Each f i(x)denotes a complex valued polynomial in a variable vector x=(x1,...,x n)∈C n.Let Z n+denote the set of nonnegative integer vectors in R n.We represent each component polynomial f i(x)asf i(x)= a∈A i c i(a)x a,for some nonemptyfinite subset A i of Z n+and some nonzero c i(a)∈C,a∈A i.Here x a=x a11x a22···x a n n for a=(a1,a2...,a n)∈Z n+.The set A i consists of m i elements,and is called the support of f i(x).Also,A=(A1,A2,...,A n)is called the support of f(x).In this paper we focus on a fully mixed polynomial system where all supports A1,A2,...,A n are all distinct.See the papers[8,12]for the semi-mixed case where some of them are identical to each other.Enumeration of all mixed cells of the support A of a polynomial system f(x),which is the subject of this paper,plays an essential role in the polyhedral homotopy ing the mixed cells,we construct a family of polyhedral homotopy functions between start systems, which are auxiliary polynomial systems whose zeros can be computed easily,and the target system f(x).Starting from zeros of every start system,we then trace all curves of zeros, so-called homotopy paths,of every polyhedral homotopy function.Some formulations were proposed forfinding all mixed cells.Among others,the formulation offinding all mixed cells as a system of linear inequalities with a certain additional combinatorial condition [7,8,15,19](or a family of systems of linear inequalities)is more efficient in computational time and memory requirement than a geometric formulation used in the papers[22].This paper is founded on the former formulation.In this formulation,an enumeration tree is constructed among a family of systems of linear inequalities,which are induced from the system of linear inequalities with a combinatorial condition describing all mixed cells. The enumeration tree satisfies the following properties.(i)A leaf node describes a mixed cell if and only if it is feasible(or more precisely thesystem of linear inequalities attached to the leaf node is feasible).(ii)Each mixed cell is corresponding to a unique feasible leaf node.(iii)Each node different from leaf nodes is a common subsystem of its child nodes,so that if it is infeasible then so are all of its descendant nodes.(iv)The root node is an empty system,which is always feasible.We then apply an enumeration method forfinding all feasible leaf nodes;if a node is determined to be infeasible then so are their descendant nodes;hence the subtree having the node as a root can be pruned because it does not contain any mixed cell.There are two important issues in efficient implementation of enumeration of all mixed cells which are corresponding to feasible leaf nodes of an enumeration tree satisfying prop-erties(i),(ii),(iii)and(iv).One is how we check feasibility of each node.For this purpose, the papers[7,8,15,19]utilize a linear programming(LP)problem having a linear system of inequalities attached to each node as its constraint and check feasibility of the linear system. The papers[7,8,15]applies the primal simplex method to the LP problem while the paper [19]applies the dual simplex method to the LP problem.If we take account of effective use of information obtained at a node for its child nodes,the dual simplex method has an advantage.Specifically,we can easily choose a feasible solution of the dual of the child LP from an optimal solution of the dual of the parent LP since the linear inequality constraints of each child node are a super set of the linear inequality constraints of its parent and they share a common linear objective function.At least,the application of the dual simplex method is popular in thefield of optimization to effectively deal with such a situation[16]. This paper also applies the dual simplex method to an LP problem attached with each node to check its feasibility,which will be described as the application of the primal simplex method to the dual of the LP problem.The other important issue is how we construct enumeration trees.Enumeration trees need to satisfy properties(i),(ii),(iii)and(iv)as we mentioned above.Specifically,the root node isfixed to be an empty system of linear inequalities by property(iv),and properties (i)and(ii)determine the collection of leaf nodes.There are lots of freedom in choosing and allocating systems of linear inequalities,which are induced from the system of linear inequalities with a combinatorial condition describing the mixed cells,for intermediate level nodes.In the existing works[7,8,15,19],the structure of enumeration trees is determined andfixed before enumerating mixed cells.In such a static construction of an enumeration tree,any information obtained at a node during execution of enumeration is never utilized at all to branch the node into its child nodes because a branching rule isfixed in advance. For numerical efficiency,however,it is ideal to branch the node into its child nodes so that a larger portion of its child nodes are infeasible and are pruned.To pursue this idea,this paper proposes dynamic enumeration where branching at a node is carried out with the effective use of information which is obtained from the dual simplex method applied to some“child LP problems”at the node;hence the dual simplex method plays an essential role in this situation too.We note that dynamic enumeration is often utilized in the branch-and-bound method for integer programs[16].We now describe mixed cells in terms of systems of linear inequalities and the basic idea of our dynamic enumeration of them.For every L⊆N:={1,2,...,n},defineΩ(L)= C=(C1,C2,...,C n):C i∈A i,#C i=2(i∈L),C j=∅(j∈L) ,Ω=∪L⊆NΩ(L).The setΩserves as candidates of nodes of enumeration trees.Specifically,∅n∈Ω(∅)={∅n} is the root node,andΩ(N)⊂Ωthe leaf nodes.In general,theℓth level nodes of an enumeration tree are chosen from∪L⊆N,#L=ℓΩ(L).For every C∈Ω,let L(C)={i∈N: C i=∅}.For every C∈Ωand L⊆N,we denote the vector consisting of C i(i∈L)by C L=(C i:i∈L).For every i∈N and every a∈A i,letωi(a)denote a random number chosen from some bounded interval of R.The numberωi(a)is called a lifting in the literature.For every C∈Ωwith C i={a p i,a q i}(i∈L(C)),we consider a linear inequality system in a variable vectorα∈R n:I(C): a p i−a q i,α =ωi(a q i)−ωi(a p i),a p i−a,α ≤ωi(a)−ωi(a p i),(a∈A i\{a p i,a q i},i∈L(C)).We say that C∈Ωis feasible when I(C)is feasible.LetΩ∗(L)={C∈Ω(L):C is feasible}.ThenΩ∗(N)defines the set of all mixed cells.Note that a leaf node C∈Ω(N)is a mixed cell if and only if C is feasible,so properties(i)and(ii)are satisfied.Thus,for enumeration of all mixed cells,we need tofind all elements inΩ∗(N).For every C∈Ωwith a proper subset L(C)of N and every t∈N\L(C),define a set of child nodes of C byW(C,t)= ¯C∈Ω(L(C)∪{t}):¯C L(C)=C L(C) .We can build an enumeration tree if we successively choose t∈N\L(C)at each node C of the tree starting from the root node C=∅n with L(C)=∅(see Algorithm2.1for more details).In the static enumeration method employed in the papers[7,8,15,19],we first choose a permutation of N or a one-to-one mappingπ:N→N,and restrict nodes of enumeration trees to C∈Ω({π(1),...,π(ℓ)})with someℓ∈{0,1,...,n}.Note that if we takeℓ=0orℓ=n,we have the root node∅n∈Ω(∅)or the setΩ(N)of leaf nodes, respectively.Suppose that a node C∈Ω({π(1),...,π(ℓ)})for someℓ<n has been found to be feasible.Then the static enumeration method generates W(C,π(ℓ+1))as the set of child nodes of C.Thus the structure of the static enumeration tree is completely determined by a permutationπ:N→N.In the enumeration method that we propose in this paper,an enumeration tree is con-structed dynamically as the enumeration of nodes proceeds.As in the static enumeration,∅n∈Ω(∅)serves as the root node andΩ(N)as the set of leaf nodes.Suppose that a node C with some proper subset L(C)of N has been found to be feasible.Then we try to choose a t∈N\L(C)so that only a small portion of its child nodes W(C,t)are expected to be feasible.The important issue here is how inexpensively we estimate the number of feasible child nodes in W(C,s)for all s∈N\L(C).For this purpose,we propose a simple technique of feasibility check which applies a criterion of unboundedness detection in the simplex method.We also utilize the relation table given in[8]tofind some infeasible child nodes in W(C,s).Numerical results exhibit that our dynamic enumeration method works very efficiently forfinding all mixed cells in comparison to the existing static enumeration methods[6,8,9, 15,22,19].For instance,our dynamic enumeration method solved the cyclic-14problem(i.e. generates all mixed cell of the cyclic-14problem),which had been the largest one in cyclic-n problems solved by the existing methods,in1hours36minutes,while MixedVol[8,9], which is known as the fastest software among the existing ones,solves the same problemin7hours14minutes.Furthermore,our method solved the cyclic-15problem for thefirst time in15hours45minutes.As for noon-n and chandra-n problems,it is shown that the speedup ratio between the computational times of our method and MixedVol increases as the size of these problems becomes larger.This paper is organized as follows.In Section2we describe a procedure for construction of an enumeration tree satisfying properties(i),(ii),(iii)and(iv),and then outline our dynamic enumeration algorithm.Section3is devoted to technical details of the algorithm. Wefirst show a LP formulation for checking feasibility of each node in an enumeration tree, and discuss the size of the primal-dual pair of LP problems.Next,we mention how to choose t∈N\L(C)at a parent node C so that the number of child nodes of C is as smaller as possible.In Section4,we show numerical results for some benchmark polynomial systems. 2An outline of the dynamic enumeration algorithm forfinding all mixed cellsWefirst explain how to construct an enumeration tree,which satisfies properties(i),(ii), (iii)and(iv)described in the previous section,and next propose an algorithm for dynamic enumeration of all mixed cells.To explain a procedure for construction of such a tree,we define some notation.Let T=(V,E)be a rooted tree such that the vertex set V and edge set E are written as V= nℓ=0Vℓand E= nℓ=0Eℓ.V0consists of the root node∅n,and we define E0as an empty set for consistence with below discussions.The procedure forconstruction of a tree T with allocating nodes dynamically is written as follows: Construction of a tree TInput:A support A=(A1,A2,...,A n).Output:A tree T=(V= nℓ=0Vℓ,E= nℓ=0Eℓ).Vℓ←∅n(ℓ=0,...,n),Eℓ←∅(ℓ=0,...,n)andℓ←0.whileℓ=n dofor all C∈VℓdoChoose t from N\L(C).Vℓ+1←Vℓ+1∪W(C,t)and Eℓ+1←Eℓ+1∪{(C,¯C)∈Vℓ×Vℓ+1:¯C∈W(C,t)}.end forℓ←ℓ+1.end whileThis procedure for the input data A produces a various type of tree T depending on a choice of an index t from N\L(C).For instance,a static enumeration tree proposed in the existing algorithm[7,8,15,19]is constructed when for any C∈Vℓthe index t is set to π(ℓ+1)according to the given permutationπof N.If two nodes C∈Vℓand¯C∈Vℓ+1of a tree are joined with a edge,we say that¯C is the child node of a parent node C.The descendant node of C is corresponding to any node onall paths from C to reachable leaf nodes which are elements in V n.Each feasible leaf nodes are corresponding to mixed cells.By deleting worthless nodes which do not contain any mixed cell,we can efficiently enumerate all feasible leaf nodes of a tree.Indeed,if a node is infeasible,all of its descen-dant nodes are infeasible,and thus,we need not to check feasibility of descendant nodes. Furthermore,we employ a depth-first order for applying feasibility check to all nodes of an enumeration tree in order to save memory requirement during execution of enumeration. Taking account of these factors,the depth-first search algorithm for the enumeration of all mixed cells is constructed.It is convenient to use the words“list”used in this algorithm.If A is afinite set,we denote list(A)is an ordered sequence of the elements in A,where the actual order is not relevant in our succeeding discussions butfixed.For a pair of list(A)and list(B),where A and B arefinite sets,list(A)+list(B)stands for the list which is generated by connecting list(B)with list(A)by“stacking”list(B)on list(A);for example,if list(A)=(a,b,c)and list(B)=(d,e),then list(A)+list(B)=(a,b,c,d,e).Algorithm2.1.(A general depth-first search algorithm for all mixed cells).Input:A support A=(A1,A2...,A n).Output:All mixed cells C∈Ω∗(N)and an evaluation measureν∗.Step1:Let V a be the empty list of nodes,and V a=list(V a)+list(Ω(∅)),where V a serves as the set of active nodes during the depth-first search.Letν=1which serves as the counter of nodes generated;νis used only for evaluating the efficiency of the algorithm but not essential in any step below.Step2:If V a is empty,then outputν∗=νand stop.Step3:Take out the last element C of V a and remove C from V a.Step4:Check whether C is feasible or infeasible.If C is infeasible(C∈Ω∗(L(C))or I(C)is infeasible)then go to Step2.If C is feasible(C∈Ω∗(L(C))or I(C)is feasible)and L(C)=N,then output C as a mixed cell and go to Step2.Otherwise go to Step5.Step5:Choose a t from N\L(C)andν=ν+#W(C,t).Step6:Let V a=list(V a)+list(W(C,t))and go to Step2.The total amount of works to generate all mixed cells by Algorithm2.1is measured by ν∗which represents the total number of nodes generated during execution of Algorithm2.1; recall that for each node C,the system of linear inequalities I(C)is solved to see whether C is feasible or infeasible.Since the efficiency of the algorithm depends on the size of V a, we utilize the one point test[7,8,15,19]to narrow down the number of elements in V a.ForC∈V a and t∈N\L(C),the one point test checks the feasibility of the system of linear inequalities inα∈R n withfixed a∈A t,I(C,t,a): I(C), a−b,α ≤ωt(b)−ωt(a),(b∈A t\{a}).(1)If I(C,t,a)is infeasible,we can delete¯C∈W(C,t)whose¯C t={a,a′}consists of a and any a′∈A t\{a}from the set V a of solution candidates,since such I(¯C)is also infeasible. Therefore,as solution candidates we only considerW1(C,t)= ¯C∈Ω(L(C)∪{t}):¯C L=C L and¯C t⊆A t(C) ,where A t(C)={a∈A t:I(C,t,a)is feasible}.After m t(=#A t)feasibility checks of linear inequality systems for constructing A t(C),we have W1(C,t)satisfying¯C∈W(C,t):¯C is feasible ⊆W1(C,t)⊆W(C,t).Thus we can replace Step6byStep6’:Let V a=list(V a)+list(W1(C,t))and go to Step2.This technique called one point test is known to be very effective to increase the computa-tional efficiency of enumeration[7,8,15,19].Ideally we would like to choose a t∈N\L(C)at Step5so that the size of W1(C,t)is the smallest among the sizes of W1(C,s)(s∈N\L(C)).Finding such a t∈N\L(C)exactly, however,is expensive because all W1(C,s)(s∈N\L(C))are constructed.Therefore,we propose to replace W1(C,s)by another set which can be obtained easily.Indeed,utilizing a feasible solution x init of I(C,t,a)which is generated from an solution of I(C),our method computesˆW1(C,s,x init)(s∈N\L(C))satisfyingW1(C,s)⊆ˆW1(C,s,x init)⊆W(C,s)(s∈N\L(C)),and chooses a t∈N\L(C)such that the size ofˆW1(C,t,x init)attains the minimum among the sizes ofˆW1(C,s,x init)(s∈N\L(C)).We call this method a dynamic enumeration method.In Subsection3.2,we explain how to generate the setˆW1(C,s,x init)(s∈N\L(C)). Also the relation table proposed in[8]can be used tofind some infeasible child nodes in W(C,s).In our numerical experiments,the relation table is applied to remove infeasible child nodes from W(C,s)beforeˆW1(C,s,x init)is constructed.3Technical details of the algorithm3.1Formulation of checking feasibility of a system of linear in-equalitiesThe feasibility check of C∈Ω,conducted at Step4of Algorithm2.1,can be formulated via an LP ly,we test feasibility of the following problem in the vectorα∈R n of decision variables:P(C):max. γ,α s.t.I(C),whereγ∈R n is somefixed vector.For every C∈Ωwith C i={a p i,a q i}(i∈L(C)),the dual problem is written asD(C):min.Φ(x;C)s.t.Ψ(x;C)=γ,x a≥0(a∈A i\{a p i,a q i}),−∞<x a q i<+∞,(i∈L(C)).Here,a vector of decision variables is given by the column vectorx=(x a:a∈A i\{a p i},i∈L(C))∈Rδ,whereδ:= i∈L(C)(m i−1),(2) and the symbolΦ(x;C)andΨ(x;C)are linear functions in x such thatΦ(x;C)= i∈L(C) a∈A i\{a p i}(ωi(a)−ωi(a p i))x aandΨ(x;C)= i∈L(C) a∈A i\{a p i}(a p i−a)x a.Any real vectorγin P(C)can be taken for the cost vector.Accordingly we setγso that D(C)becomes feasible.Since this primal-dual pair satisfies the duality theorem,P(C)is feasible if and only if D(C)is bounded below,and P(C)is infeasible if and only if D(C) is unbounded.Therefore,to determine feasibility of C,we need to see whether D(C)is bounded or not.Now we consider a formulation of an LP asmin. c,xs.t.Gx=h(3)x i≥0,(i∈I),−∞<x j<+∞,(j∈J),where a coefficient matrix G∈R k×d,cost vector c∈R d and constant vector h∈R k are given,and x∈R d is a vector of decision variables.These index sets I and J of decision variables satisfy I∩J=∅and I∪J={1,2,...,d}.Here,x i(i∈I)and x j(j∈J)are called as a nonnegative variable and a free variable,respectively.The primal-dual pair P(C)and D(C)can be transformed into(3)by introducing slack variables to the inequalities of P(C) and replacing the cost vectorγof P(C)by−γ.In consequence of these transformations, P(C)has d P variables and k P equalities such thatd P=n+ i∈L(C)(m i−2)and k P= i∈L(C)(m i−1).On the other hand,D(C)has d D variables and k D equalities such thatd D= i∈L(C)(m i−1)and k D=n.Here d D is not greater than d P for any L(C)⊆N.Also k D is constant whereas k P is monotonic increasing with respect to the cardinality of L(C).When any polynomialsf i(x)(i∈N)have at least two terms,i.e.,m i≥2,there exists L′⊆N such as k P≥k D. Consequently for any L such as L′⊆L⊆N,the number of constraints and that of variables in D(C)are not greater than those of P(C).Therefore,it is reasonable to observe whether D(C)is bounded for checking feasibility of C.We formulate the one point test,stated in the previous section,via an LP problem.For every C∈Ω,t∈N\L(C)and a∈A t,checking feasibility of(1)can be written as the following LP problem in the vectorα∈R n of decision variables:P1(C,t,a):max. γ,α s.t.I(C,t,a),whereγ∈R n is somefixed vector.As the one point test,we check feasibility of this problem for all a∈A t.The dual problem of P1(C,t,a)is given byD1(C,t,a):min.Φ(x;C)+ b∈A t\{a}(ωt(b)−ωt(a))y bs.t.Ψ(x;C)+ b∈A t\{a}(a−b)y b=γx a≥0(a∈A i\{a p i,a q i})and−∞<x a q i<+∞,for i∈L(C),y b≥0(b∈A t\{a}).Using x∈Rδof(2)and the column vector y=(y b:b∈A t\{a p t})∈R(m t−1),the vector of decision variables in this problem is represented asx y ∈R¯δ,where¯δ:=(m i−1).i∈L(C)∪{t}This primal-dual pair satisfies the duality theorem because we setγso that D1(C,t,a)is feasible.Similar to P(C)and D(C),we can say that the size of D1(C,t,a)is not larger than that of P1(C,t,a)for any C∈Ω,t∈N\L(C)and a∈A t.Therefore,we deal with D1(C,t,a)as the one point test,and check whether this problem is bounded or not. From the results of the one point test,we can generate the set W1(C,t)which satisfies W1(C,t)⊆W(C,t).We refer to how tofix a right-hand constant vectorγon D(C)and D1(C,t,a).For C∈Ω(L)with C i={a p i,a q i}(i∈L(C))and a proper subset L(C)of N,let us consider the problem D(C).Using the arbitrary nonnegative vectorˆx∈Rδ,we computeˆγ=Ψ(ˆx;C)and set thisˆγas a right-hand vectorγof the problem D(C)and D1(C,t,a)for some a∈A t and t∈N\L(C).As a result,D(C)is feasible.Let us suppose that the problem D(C)is bounded,and denote an optimal solution of this problem by x∗∈Rδ.Then,the vectorx init= x∗0 ∈R¯δ(4)is feasible solution in D1(C,t,a)(a∈A t and t∈N\L(C))because D1(C,t,a)withfixed y=(y b:b∈A t\{a p t})=0is equivalent to D(C).Also,we consider the problem D(¯C)(¯C∈Ω(L(C)∪{t}))with¯C L=C L,and useˆγas a right-hand vectorγof this problem.We easily see that this problem is feasible.Furthermore,an optimal solution of D1(C,t,a)is a feasible solution of D(¯C).Since the simplex method is suitable for solving a lot of LP problems with a similar structure,we employ the method to solve problems arising from checking feasibility of linear inequality systems.3.2How to choose an index t from N\L(C)Choice of a t∈N\L(C)at Step5of Algorithm2.1has a major effect on computational efficiency of this algorithm.As stated in Section2,we want to choose a t∈N\L(C) such that the size of W1(C,s)is the smallest among s∈N\L(C).However,this task is expensive in general because we need to check feasibility of I(C,t,a)for every a∈A t and t∈N\L(C)at Step5additionally.We will employ a less expensive technique to choose a t∈N\L(C)so that an evaluation measureν∗of efficiency of our dynamic enumeration method becomes smaller.To check feasibility of C∈Ω(L)with a proper subset L of N,we have solved the dual problem D(C),and in Step5we have an optimal solution x∗∈Rδof D(C).As stated in the previous subsection,if we set x init∈R¯δby(4)using x∗of D(C),the vector x init is a feasible solution of D1(C,t,a)for any a∈A t and t∈N\L(C).Because the structure of D1(C,t,a)and D(C)is similar to each other,we usually require only a few iterations to solve D1(C,t,a)when using x init as an initial feasible solution of the simplex method. Thus we expect that x init is incident to unbounded directions in cases where corresponding problems are unbounded.Accordingly,instead of applying the simplex method to check the feasibility of D1(C,t,a)(a∈A t and t∈N\L(C)),we propose to test whether the feasible solution x init of D1(C,t,a)has unbounded directions or not.At Step5we considerˆW(C,s,x init)={¯C∈Ω(L(C)∪{s}):¯C L=C L and¯C s⊆ˆA s(C,x init)}1whereˆA(C,x init)={a∈A t:x init of D1(C,t,a)has no unbounded direction}tand choose an indexˆt∈N\L(C)which attains#ˆW1(C,s,x init).mins∈N\L(C)In general,this indexˆt does not coincide with the index t which achieves the minimum number of elements in W1(C,s)(s∈N\L(C)).We will observe from numerical results, however,that the evaluation measureν∗is much smaller for our dynamic enumeration method than the static enumeration method,and the total computational time forfinding all mixed cells is reduced dramatically.We next explain how to compute elements inˆW1(C,t,x init)(t∈N\L(C))more precisely,using an LP form of(3)instead of D1(C,t,a)for simplicity of notation.For(3), let us assume that the number of variables d is not less than that of constraints k and the matrix G=(g1,g2,...,g d)has full row rank.If this problem(3)is feasible,there exists a vertex x∈R d on the feasible region which consists of two components of the vector of basic variables x B=G−1B h∈R k and of nonbasic variables x N=0∈R d−k where G B∈R k×kis a basic matrix.Note that x B=(x b1,x b2,...,x bk)T and x N=(x n1,x n2,...x nd−k)T.Inparticular,the set of basic variables and nonbasic variables are called a basis and nonbasis. An adjacent vertex˜x of x is represented as˜x=x+θdby using a nonnegative scalarθand a direction vector d.Let D={1,2,...,d},and we denote the set of basic indices B={b1,b2,...,b k}⊂D.Note that(d−k)extreme rays extend from a vertex x and one direction d is chosen byfixing an index j∈D\B.The direction d is composed of two components vectors d B and d N such thatd B=−G−1B g j∈R k and d N= d i=1i=jd i=0i∈D\(B∪{j})∈R d−k,where d i represents a component of d.When we move from x to˜x,the cost change per unitθis c,d .Using a component c B of a cost vector c which corresponds to a basis B, this amount can be written asc,d =c j−c T B G−1B g j(5) and called a reduced cost for j∈D.To obtain an adjacent vertex˜x of x so that the value of a cost function decreases from x,we search for a direction d with j∈D such that its reduced cost is negative,and determine the step sizeθ≥0such that a new vertex ˜x=x+θd satisfies its constraints;if components d i of a direction vector d are nonnegative for all i∈B∩I where I is the index set of nonnegative variables in(3),this problem is unbounded and we say that x has an unbounded direction.Otherwise,we compute the largestθallowed by constraints for variables.Now,we provide the criteria for detecting that the feasible solution x init of D1(C,t,a)(a∈A t and t∈N\L(C))has an unbounded direction.Notice that the optimal basic ma-trix G B∈R n×n of D(C)is equal to the basic matrix on x init of D1(C,t,a)for any a∈A t and t∈N\L(C))because the number of constraints is equal to each other, and a feasible solution x init can be represented as(4)using an optimal solution x∗of D(C). Also,note that the vector(G−1B)T c B in(5)is an optimal solution of its dual problem when the duality theorem holds for this primal-dual pair.Letα∗∈R n be an optimal solution of P(C).For some a p t∈A t and t∈N\L(C),reduced costs on x init of D1(C,t,a p t)with C i={a p i,a q i}(i∈L(C))are written asωi(b)−ωi(a p i)− a p i−b,α∗ ,for i∈L(C)∪{t}and b∈A i\{a p i}.Sinceα∗is an optimal solution of P(C)which has I(C)as a constraint,these reduced costs are nonnegative for every b∈A i\{a p i}and i∈L(C).Consequently,if there are b∈A t\{a p t}such that(i)ωt(b)−ωt(a p t)− a p t−b,α∗ <0(ii)All components of a vector−G−1B(a p t−b),which corresponds to nonnegative variables in the basis,are nonnegative,we see that the feasible solution x init of D1(C,t,a p t)for a p t∈A t has an unbounded direction.Conversely,if the feasible solution x init of D1(C,t,a p t)has no such b∈A t\{a p t}, a p t is added toˆA t(C,x init).The problem D(C)with#L(C)=ℓhasℓfree variables,and the optimal basis con-tains all free variables if this problem is bounded.Therefore,since the basis on x init of D1(C,t,a)(a∈A t and t∈N\L(C))hasℓfree variables,it is enough to check(n−ℓ) components of a vector−G−1B(a p t−b)in(ii).4Numerical resultsThe proposed algorithm has been implemented and coded in C++language.All numerical experiments were executed on a2.4GHz Opteron850with8GB memory,running Linux. First,let us observe an evaluation measureν∗generated by the static and dynamic enumer-ation,described in Section2,for the cyclic-n[2]and noon-n[18]problems.In the cyclic-n problem,one polynomial has2monomials and others have n monomials such asx1+x2+···+x n−1+x n,x1x2+x2x3+···+x n−1x n+x n x1,x1x2x3+x2x3x4+···+x n−1x n x1+x n x1x2,...x1x2···x n−1.In the noon-n problem,all polynomials have(n+1)monomials such asx1x22+x1x23+···+x1x2n−1.1x1+1,x2x21+x2x23+···+x2x2n−1.1x2+1,...x n x21+x n x22+···+x n x2n−1−1.1x n+1.For each polynomial system,we denote the support set of the i th polynomial from top as A i and set the support set A=(A1,A2,...,A n)as the input data of Algorithm2.1.Table1shows an evaluation measureν∗generated by the static and dynamic enumeration (abbreviated by“Static Enum.”and“Dynamic Enum.”,respectively)for the cyclic-n and noon-n problem,and the below row“Ratio”indicates the ratio betweenν∗given by these two methods.For these systems,this table reveals efficiency of the dynamic enumeration method by comparison with the static one,and we can see that the ratio increases as the size of each system becomes larger.。