CAT24C44LA-TE13中文资料

i n ue dPa rt 1© 2005 by Catalyst Semiconductor, Inc.Characteristics subject to change without notice.Doc. No. 1054, Rev. I* Catalyst Semiconductor is licensed by Philips Corporation to carry the I 2C Bus Protocol.PIN CONFIGURATIONBLOCK DIAGRAMPIN FUNCTIONSPin Name Function NC No Connect SDA Serial Data/Address SCL Serial Clock WP Write ProtectV CC2.5 V to 5.5 V Power Supply V SSGroundDIP Package (P, L)TSSOP Package (U, Y)SOIC Package (J, W)FEATURESI 400 kHz (2.5 V) I 2C bus compatible I 2.5 to 5.5 volt operation I Low power CMOS technology I 16-byte page write bufferI Industrial and extended temperature ranges I Self-timed write cycle with auto-clear I 1,000,000 program/erase cyclesI 100 year data retentionI 8-pin DIP, SOIC, TSSOP, MSOP and TDFNpackages- “Green” package option availableI 2,048 x 8 memory organization I Hardware write protectDESCRIPTIONThe CAT24FC16 is a 16-kb Serial CMOS EEPROM internally organized as 2048 words of 8 bits each.Catalyst’s advanced CMOS technology substantially reduces device power requirements. The CAT24FC16features a 16-byte page write buffer. The device operates via the I 2C bus serial interface and is available in 8-pin DIP, SOIC, TSSOP, MSOP and TDFN packages.EXTERNAL LOADTDFN Package (RD4, ZD4)SSV V V CC WP SCL SDAMSOP Package (R, Z)V CC WP SCL SDAV CC WP SCL SDANC NC NC V SSNC NC NCV SSV CC WP SCL SDANC NC NCV SSDis co n ti n ue dPa rt CAT24FC162Doc. No. 1054, Rev. ICAPACITANCE T A = 25°C, f = 400 kHz, V CC = 5 V Symbol TestConditions MinTyp Max Units C I/O (3)Input/Output Capacitance (SDA)V I/O = 0 V 8pF C IN (3)Input Capacitance (other pins)V IN = 0 V6pFRELIABILITY CHARACTERISTICS (3)Symbol Parameter MinTyp Max Un itsN END Endurance 1,000,000Cycles/Byte T DR Data Retention 100Years V ZAP ESD Susceptibility4000Volts I LTH (4)Latch-up100mAABSOLUTE MAXIMUM RATINGS*Temperature Under Bias–55°C to +125°CStorage Temperature.......................–65°C to +150°C Voltage on Any Pin withRespect to Ground (1)............–2.0 V to V CC + 2.0 V V CC with Respect to Ground .............–2.0 V to +7.0 V Package Power DissipationCapability (T A = 25°C)..................................1.0 W Note:(1)The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DCvoltage on output pins is V CC + 0.5 V, which may overshoot to V CC + 2.0 V for periods of less than 20 ns.(2)Output shorted for no more than one second. No more than one output shorted at a time.(3)These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100and JEDEC test methods.(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1.0 V to V CC + 1.0 V.(5)Maximum standby current (I SB ) = 10µA for the Extended Automotive temperature range.D.C. OPERATING CHARACTERISTICSV CC = 2.5 V to 5.5 V, unless otherwise specified.Symbol ParameterTest ConditionsMin TypMax Units I CC Power Supply Current (Read)f SCL = 400 kHz 1mA I CC Power Supply Current (Write)f SCL = 400 kHz3mA I SB (5)Standby Current (V CC = 5.0 V)V IN = GND or V CC 1µA I LI Input Leakage Current V IN = GND to V CC1µA I LO Output Leakage Current V OUT = GND to V CC1µA V IL Input Low Voltage –1V CC x 0.3V V IH Input High VoltageV CC x 0.7V CC + 1.0V V OLOutput Low Voltage (V CC = 3.0 V)I OL = 3 mA 0.4VLead Soldering Temperature (10 seconds)......300°C Output Short Circuit Current (2).......................100 mA*COMMENTStresses above those listed under “Absolute Maximum Ratings ” may cause permanent damage to the device. These are stress ratings only,and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.Dis co n ti n ue dPa rt CAT24FC163Doc No. 1054, Rev. IWrite Cycle Limits Symbol ParameterMinTyp Max Un its t WRWrite Cycle Time5msA.C. CHARACTERISTICSV CC = 2.5 V to 5.5 V, unless otherwise specified.Read & Write Cycle Limits SymbolParameter2.5 V - 5.5 V MinMaxUn its F SCL Clock Frequency400kHzT I (1)Noise Suppression Time Constant at SCL, SDA Inputs 100ns t AA SCL Low to SDA Data Out and ACK Out900ns t BUF (1)Time the Bus Must be Free Before a New Transmission 1300ns Can Startt HD:STA Start Condition Hold Time 600ns t LOW Clock Low Period 1300ns t HIGH Clock High Period600ns t SU:STA Start Condition Setup Time600ns (for a Repeated Start Condition)t HD:DAT Data In Hold Time 0ns t SU:DAT Data In Setup Time 100ns t R (1)SDA and SCL Rise Time 300ns t F (1)SDA and SCL Fall Time 300ns t SU:STO Stop Condition Setup Time 600ns t DHData Out Hold Time100nsNote:(1)This parameter is tested initially and after a design or process change that affects the parameter.(2)t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated.Power-Up Timing (1)(2)Symbol Parameter MinTyp Max Un its t PUR Power-up to Read Operation1ms t PUWPower-up to Write Operation1msThe write cycle time is the time from a valid stopcondition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the businterface circuits are disabled, SDA is allowed to remainhigh, and the device does not respond to its slave address.dPa rt CAT24FC164Doc. No. 1054, Rev. IFUNCTIONAL DESCRIPTIONThe CAT24FC16 supports the I 2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24FC16 operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated.START BITSDA STOP BITSCLFigure 3. Start/Stop TimingSCLSDA INSDA OUTPIN DESCRIPTIONSSCL: Serial ClockThe CAT24FC16 serial clock input pin is used to clock all data transfers into or out of the device. This is an input pin.SDA: Serial Data/AddressThe CAT24FC16 bidirectional serial data/address pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs.WP: Write ProtectThis input, when tied to GND, allows write operations to the entire memory. For CAT24FC16 when this pin is tied to V CC , the entire array of memory is write protected.When left floating, memory is unprotected.D i s co nt i nu ed Pa r tCAT24FC165Doc No. 1054, Rev. II2C BUS PROTOCOLThe following defines the features of the I2C bus proto-col:(1)Data transfer may be initiated only when the bus isnot busy.(2)During a data transfer, the data line must remainstable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START ConditionThe START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24FC16 monitor the SDA and SCL lines and will not respond until this condition is met.STOP ConditionA LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition.DEVICE ADDRESSINGThe Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 for the CAT24FC16 (see Fig. 5). The next three significant bits (A10, A9, A8) are the memory array address bits. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected.After the Master sends a START condition and the slave address byte, the CAT24FC16 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24FC16 then performs a Read or a Write operation depending on the state of the R/W bit.AcknowledgeAfter a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledg-ing device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data.The CAT24FC16 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each byte.When the CAT24FC16 begins a READ mode, it trans-mits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this ac-knowledge, the CAT24FC16 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition.Figure 4. Acknowledge TimingFigure 5. Slave Address BitsACKNOWLEDGE STARTSCL FROMMASTERDATA OUTPUTFROM TRANSMITTERDATA OUTPUTFROM RECEIVER1DEVICE ADDRESS010A10A9A8R/W Normal Read and WriteDis co n ti n ue dPa rt CAT24FC166Doc. No. 1054, Rev. IWRITE OPERATIONSByte WriteIn the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT24FC16. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the addressed memory location. The CAT24FC16 acknowledges once more and the Master generates the STOP condition, at which time the device begins its internal programming to nonvolatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device.Page WriteThe CAT24FC16 writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the initial word is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted the CAT24FC16 will respond with an acknowledge, and internally increment the low order address bits by one. The high order bits remain unchanged.If the Master transmits more than 16 bytes prior to sending the STOP condition, the address counter ‘wraps around ’, and previously transmitted data will be overwritten.Once all 16 bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point all received data is written to the CAT24FC16 in a single write cycle.Acknowledge PollingThe disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host ’s write operation,the CAT24FC16 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT24FC16 is still busy with the write operation, no ACK will be returned. If the CAT24FC16 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.WRITE PROTECTIONThe CAT24FC16 is designed with a hardware protect pin that enables the user to protect the entire memory.The hardware protection feature of the CAT24FC16 is designed into the part to provide added flexibility to the design engineers. The write protection feature of CAT24FC16 allows the user to protect against inadvertent programming of the memory array. If the WP pin is tied to Vcc, the entire memory array is protected and becomesread only. The entire memory becomes write protected regardless of whether the write protect register has been written or not. When WP pin is tied to Vcc, the user cannot program the write protect register. If the WP pin is left floating or tied to Vss, the device can be written into.Figure 7. Page Write TimingBYTE ADDRESSSLAVEADDRESS SDATAS T O PPBUS ACTIVITY:MASTERSDA LINES T A R T BUS ACTIVITY:MASTERSDA LINEBYTE C KC KC KS T O C KC KS T A R SLAVE NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0Figure 6. Byte Write TimingDis co n ti n ue dPa rt CAT24FC167Doc No. 1054, Rev. IRead OperationsThe READ operation for the CAT24FC16 is initiated in the same manner as the write operation with the one exception that the R/W bit is set to a one. Three different READ operations are possible: Immediate Address READ, Selective READ and Sequential READ.Immediate Address ReadThe CAT24FC16’s address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N + 1. If N = 2047 for 24FC16, then the counter will ‘wrap around ’ to address 0 and continue to clock out data. After the CAT24FC16 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition.Selective ReadSelective READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy ’write operation by sending the START condition, slave address and byte address of the location it wishes to read. After the CAT24FC16 acknowledge the word address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The CAT24FC16 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition.Sequential ReadThe Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT24FC16 sends the initial 8-bit data requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24FC16 will continue to output a byte for each acknowledge sent by the Master. The operation will terminate operation when the Master fails to respond with an acknowledge, thus sending the STOP condition.The data being transmitted from the CAT24FC16 is outputted sequentially with data from address N followed by data from address N + 1. The READ operation address counter increments all of the CAT24FC16address bits so that the entire memory array can be read during one operation. If more than the 2047 bytes are read out, the counter will “wrap around ” and continue to clock out data bytes.Figure 8. Immediate Address Read TimingSCL 98SDA8TH BIT STOPNO ACK DATA OUTSLAVEADDRESSS A C KDATAN O A C KST O P PBUS ACTIVITY:MASTERSDA LINES T A R TDis co n ti n uert CAT24FC168Doc. No. 1054, Rev. IFigure 9. Selective Read TimingFigure 10. Sequential Read TimingSLAVE ADDRESS SA C KN O A C KS T O P PBUS ACTIVITY:MASTERSDA LINES T A R T BYTE ADDRESS (n)SA C KDATA nSLAVE ADDRESSA C K S T A R T BUS ACTIVITY:MASTERSDA LINEC K C K C KST O O A C KC KSLAVEDis coCAT24FC169Doc No. 1054, Rev. IORDERING INFORMATIONNotes:(1) The device used in the above example is a 24FC16JI-TE13 (SOIC, Industrial Temperature, 2.5 Volt to 5.5 Volt Operating Voltage, Tape & Reel)Dis co n ti n ue dPa rt CAT24FC1610Doc. No. 1054, Rev. IREVISION HISTORYe t a D n o i s i v e R st n e m m o C 30/81/11A eu s s I l a i t i n I 30/90/21B g n i r e d r o n i ”k n a l B “m o r f ”I “o t p m e T l a i r t s u d n I d e g n a h C no i t a m r o f n i 40/01/30C o f n i g n i r e d r o N F D T d e t c e r r o C 40/20/40D no i t a n g i s e d t e e h s a t a d d e t a n i m i l E ”n o i t c e t o r P e t i r W “n i r e t s i g e r t c e t o r p e t i r w a o t e c n e r e f e r d e v o m e R 40/51/50Es c i t s i r e t c a r a h C g n i t a r e p O .C .D st i m i L e l c y C e t i r W n o i t a m r o f n I g n i r e d r O e t a d p U y r o t s i H n o i s i v e R e t a d p U re b m u N v e R e t a d p U 40/70/60F s t i m i L e l c y C e t i r W e t a d p U 40/72/7G 2e g a p n o s e t o n e t a d p U 50/42/30Hs e r u t a e F d e t a d p U n o i t p i r c s e D d e t a d p U no i t c n u F n i P d e t a d p U s c i t s i r e t c a r a h C y t i l i b a i l e R d e t a d p U s c i t s i r e t c a r a h C g n i t a r e p O d e t a d p U s c i t s i r e t c a r a h C .C .A d e t a d p U no i t a m r o f n I g n i r e d r O de t a d p U 50/32/60I no i t a m r o f n I g n i r e d r O e t a d p UD i s co nt i nu ed Pa r tCatalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089Phone: 408.542.1000Fax: 408.542.1200 Publication #:1054 Revison:IIssue date:06/23/05Copyrights, Trademarks and PatentsTrademarks and registered trademarks of Catalyst Semiconductor include each of the following:DPP ™DPPs ™AE2 ™Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create asituation where personal injury or death may occur.Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.元器件交易网。

CAT24C44S-TE13中⽂资料2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1Doc. No. 1083, Rev. R2Doc. No. 1083, Rev. R2005 by Catalyst Semiconductor, Inc.Characteristics subject to change without notice3Doc. No. 1083, Rev. R2005 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeABSOLUTE MAXIMUM RATINGS*Temperature Under Bias .................–55°C to +125°C Storage Temperature.......................–65°C to +150°C Voltage on Any Pin withRespect to Ground (2).............–2.0 to +VCC +2.0V V CC with Respect to Ground ...............–2.0V to +7.0V Package Power DissipationCapability (Ta = 25°C)...................................1.0W Lead Soldering Temperature (10 secs)............300°C Output Short Circuit Current (3)........................100 mA *COMMENTStresses above those listed under “Absolute Maximum Ratings ” may cause permanent damage to the device.These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica-tion is not implied. Exposure to any absolute maximum rating for extended periods may affect device perfor-mance and reliability.Note:(1)These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100and JEDEC test methods.(2)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is V CC +0.5V, which may overshoot to V CC +2.0V for periods of less than 20 ns.(3)Output shorted for no more than one second. No more than one output shorted at a time.(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V. CAPACITANCE T A = 25°C, f = 1.0 MHz, V CC = 5V Symbol ParameterMax.Unit Conditions C I/O (1)Input/Output Capacitance 10pF V I/O = 0V C IN (1)Input Capacitance6pFV IN = 0VD.C. OPERATING CHARACTERISTICS V CC = 5V ±10%, unless otherwise specified.LimitsSymbol ParameterMin.Typ.Max.Unit Conditions I CCO Current Consumption (Operating)3mA Inputs = 5.5V, T A = 0°C All Outputs Unloaded I SB Current Consumption (Standby)30µA CE = V IL I LI Input Current2µA 0 ≤ V IN ≤ 5.5V I LO Output Leakage Current 10µA 0 ≤ V OUT ≤ 5.5VV IH High Level Input Voltage 2V CC V V IL Low Level Input Voltage 00.8V V OH High Level Output Voltage 2.4V I OH = –2mA V OLLow Level Output Voltage0.4VI OL = 4.2mARELIABILITY CHARACTERISTICS Symbol ParameterMin.Typ.Max.Units N END (1)Endurance 100,000Cycles/Byte T DR (1)Data Retention 10Years V ZAP (1)ESD Susceptibility 2000Volts I LTH (1)(4)Latch-up100mA4Doc. No. 1083, Rev. R2005 by Catalyst Semiconductor, Inc.Characteristics subject to change without notice5Doc. No. 1083, Rev. R2005 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeDEVICE OPERATIONThe CAT24C44 is intended for use with standard micro-processors. The CAT24C44 is organized as 16 registers by 16 bits. Seven 8-bit instructions control the device ’s operating modes, the RAM reading and writing, and the EEPROM storing and recalling. It is also possible to control the EEPROM store and recall functions in hard-ware with the STORE and RECALL pins. The CAT24C44operates on a single 5V supply and will generate, on chip, the high voltage required during a RAM to EEPROM storing operation.Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin remains in a high impedance state except when outputting data from the device. The CE (Chip Enable)pin must remain high during the entire data transfer.The format for all instructions sent to the CAT24C44 is a logical ‘1’ start bit, 4 address bits (data read or write operations) or 4 “Don ’t Care ” bits (device mode opera-tions), and a 3-bit op code (see Instruction Set). For data write operations, the 8-bit instruction is followed by 16bits of data. For data read instructions, DO will come out of the high impedance state and enable 16 bits of data to be clocked from the device. The 8th bit of the read instruction is a “Don ’t Care ” bit. This is to eliminate any bus contention that would occur in applications where the DI and DO pins are tied together to form a common DI/DO line. A word of caution while clocking data to and from the device: If the CE pin is prematurely deselected while shifting in an instruction, that instruction will not be executed, and the shift register internal to theCAT24C44will be cleared. If there are more than or less than 16clocks during a memory data transfer, an improper data transfer will result. The SK clock is completely static allowing the user to stop the clock and restart it to resume shifting of data.ReadUpon receiving a start bit, 4 address bits, and the 3-bit read command (clocked into the DI pin), the DO pin of the CAT24C44 will come out of the high impedance state and the 16 bits of data, located at the address specified in the instructions, will be clocked out of the device.When clocking data from the device, the first bit clocked out (DO) is timed from the falling edge of the 8th clock,all succeeding bits (D1–D15) are timed from the rising edge of the clock.WriteAfter receiving a start bit, 4 address bits, and the 3-bit WRITE command, the 16-bit word is clocked into the device for storage into the RAM memory location speci-fied. The CE pin must remain high during the entire write operation.Note:(1)Bit 8 of READ instruction is “Don ’t Care ”.SKCEDISKCEDI DO1234567891011122223246Doc. No. 1083, Rev. R2005 by Catalyst Semiconductor, Inc.Characteristics subject to change without notice7Doc. No. 1083, Rev. R2005 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeRCL/RECALLData is transferred from the EEPROM data memory to RAM by either sending the RCL instruction or by pulling the RECALL input pin low. A recall operation must be performed before the EEPROM store, or RAM write operations can be executed. Either a hardware or soft-ware recall operation will set the “previous recall ” latch internal to the CAT24C44.POWER-ON RECALLThe CAT24C44 has a power-on recall function that transfers the EEPROM data to the RAM. After Power-up, all functions are inhibited for at least 200ns (T pur )from stable V cc .STO/STOREData in the RAM memory area is stored in the EEPROM memory either by sending the STO instruction or by pulling the STORE input pin low. As security against anyinadvertent store operations, the following conditions must each be met before data can be transferred into nonvolatile storage:The “previous recall ” latch must be set (either a software or hardware recall operation).The “write enable ” latch must be set (WREN instruction issued).?STO instruction issued or STORE input low.During the store operation, all other CAT24C44 func-tions are inhibited. Upon completion of the store opera-tion, the “write enable ” latch is reset. The device also provides false store protection whenever V CC falls below a 3.5V level. If V CC falls below this level, the store operation is disabled and the “write enable ” latch is reset.Figure 6. Hardware Store Cycle TimingSTOREDO8Doc. No. 1083, Rev. R2005 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeCatalyst Semiconductor, Inc.Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089Phone:408.542.1000Fax: 408.542.1200/doc/4fd0c5242af90242a895e5ed.htmlCopyrights, Trademarks and PatentsTrademarks and registered trademarks of Catalyst Semiconductor include each of the following:DPP ?AE 2 ?MiniPot?Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at408.542.1000.CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.REVISION HISTORYe t a D n o i s i v e R st n e m m o C 4002/71/40Oo g o L e e r F d a e L d d A se r u t a e F e t a d p U n o i t a r u g if n o C n i P e t a d p U m a rg a i D k c o l B e t a d p U t e S n o i t c u r t s n I e t a d p U n o i t a r e p O e c i v e D e t a d p U n o i t a m r o f n I g n i r e d r O e t a d p U y r o t s i H n o i s i v e R d d A r e b m u N v e R e t a d p U 4002/61/11P n o i t a r u g i f n o C n i P e t a d p U n o i t a m r o f n I g n i r e d r O e t a d p U 4002/71/40Q n o i t a m r o f n I g n i r e d r O e t a d p U 5002/30/80Rno i t a r u g i f n o C n i P e t a d p U s c i t s i r e t c a r a h C y t i l i b a i l e R e t a d p U no i t a m r o f n I g n i r e d r O e t a d p U Publication #:1083Revison:RIssue date:08/03/05。

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24C02串行E2PROM的读写I2C总线是一种用于IC器件之间连接的二线制总线。

它通过SDA（串行数据线）及SCL（串行时钟线)两根线在连到总线上的器件之间传送信息，并根据地址识别每个器件：不管是单片机、存储器、LCD驱动器还是键盘接口。

1．I2C总线的基本结构采用I2C总线标准的单片机或IC器件，其内部不仅有I2C接口电路，而且将内部各单元电路按功能划分为若干相对独立的模块，通过软件寻址实现片选，减少了器件片选线的连接。

CPU不仅能通过指令将某个功能单元电路挂靠或摘离总线，还可对该单元的工作状况进行检测，从而实现对硬件系统的既简单又灵活的扩展与控制。

I2C总线接口电路结构如图1所示。

2．双向传输的接口特性传统的单片机串行接口的发送和接收一般都各用一条线，如MCS51系列的TXD和RXD，而I2C 总线则根据器件的功能通过软件程序使其可工作于发送或接收方式。

当某个器件向总线上发送信息时，它就是发送器(也叫主器件)，而当其从总线上接收信息时，又成为接收器(也叫从器件)。

主器件用于启动总线上传送数据并产生时钟以开放传送的器件，此时任何被寻址的器件均被认为是从器件。

I2C总线的控制完全由挂接在总线上的主器件送出的地址和数据决定。

在总线上，既没有中心机，也没有优先机。

总线上主和从(即发送和接收)的关系不是一成不变的，而是取决于此时数据传送的方向。

SDA和SCL均为双向I/O线，通过上拉电阻接正电源。

当总线空闲时，两根线都是高电平。

连接总线的器件的输出级必须是集电极或漏极开路，以具有线“与”功能。

I2C总线的数据传送速率在标准工作方式下为100kbit/s，在快速方式下，最高传送速率可达400kbit/s。

3．I2C总线上的时钟信号在I2C总线上传送信息时的时钟同步信号是由挂接在SCL时钟线上的所有器件的逻辑“与”完成的。

SCL线上由高电平到低电平的跳变将影响到这些器件，一旦某个器件的时钟信号下跳为低电平，将使SCL线一直保持低电平，使SCL线上的所有器件开始低电平期。