NM93C66TLVN中文资料
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TL D 10045NM93C06L C46L C56L C66L256- 1024- 2048- 4096-Bit SerialEEPROMwithExtendedVoltage(2 7Vto5 5V)(MICROWIREBusInterface)November1996 NM93C06L C46L C56L C66L256- 1024- 2048- 4096-Bit Serial EEPROMwith Extended Voltage(2 7V to5 5V)(MICROWIRE TM Bus Interface)General DescriptionThe NM93C06L C46L C56L C66L devices are256 1024 2048 4096bits respectively of non-volatileelectrically erasable memory divided into16 64 128 256x16-bit registers(addresses) The NM93CxxL Family func-tions in an extended voltage operating range requires onlya single power supply and is fabricated using National Semi-conductor’s floating gate CMOS technology for high reliabili-ty high endurance and low power consumption These de-vices are available in both SO and TSSOP packages forsmall space considerationsThe EEPROM Interfacing is MICROWIRE compatible forsimple interface to standard microcontrollers and micro-processors There are7instructions that control these de-vices Read Erase Write Enable Erase Erase All WriteWrite All and Erase Write Disable The ready busy statusis available on the DO pin during programmingFeaturesY2 7V to5 5V operation in all modesY Typical active current of100m A Typical standbycurrent of1m AY No erase required before writeY Reliable CMOS floating gate technologyY MICROWIRE compatible serial I OY Self-timed programming cycleY Device status during programming modeY40years data retentionY Endurance 106data changesY Packages available 8-pin SO 8-pin DIP and8-pinTSSOPBlock DiagramTL D 10045–1TRI-STATE is a registered trademark of National Semiconductor CorporationMICROWIRE TM is a trademark of National Semiconductor CorporationC1996National Semiconductor Corporation RRD-B30M126 Printed in U S A http www national comConnection DiagramsDual-In-Line Package(N)8-Pin SO(M8)and8-Pin TSSOP(MT8)TL D 10045–2Top ViewNS Package Number N08E M08A or MTC08Pin NamesCS Chip SelectSK Serial Data Clock DI Serial Data Input DO Serial Data Output GND GroundV CC Power SupplyOrdering InformationCommercial Temp Range(0 C to a70 C)Order NumberNM93C06LN NM93C46LNNM93C56LN NM93C66LNNM93C06LM8 NM93C46LM8NM93C56LM8 NM93C66LM8NM93C06LMT8 NM93C46LMT8NM93C56LMT8 NM93C66LMT8Extended Temp Range(b40 C to a85 C)Order NumberNM93C06LEN NM93C46LENNM93C56LEN NM93C66LENNM93C06LEM8 NM93C46LEM8NM93C56LEM8 NM93C66LEM8NM93C06LEMT8 NM93C46LEMT8NM93C56LEMT8 NM93C66LEMT8Automotive Temp Range(b40 C to a125 C)Order NumberNM93C06LVN NM93C46LVNNM93C56LVN NM93C66TLVNNM93C06LVM8 NM93C46LVM8NM93C56LVM8 NM93C66LVM8NM93C06LVMT8 NM93C46LVMT8NM93C56LVMT8 NM93C66LVMT8http www national com2Absolute Maximum Ratings(Note1)If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Ambient Storage Temperature b65 C to a150 C All Input or Output Voltages a6 5V to b0 3V with Respect to GroundLead Temp (Soldering 10sec )a300 C ESD Rating2000V Operating ConditionsAmbient Operating TemperatureNM93C06L–NM93C66L0 C to a70 C NM93C06LE–NM93C66LE b40 C to a85 C NM93C06LV–NM93C66LV b40 C to a125 C Power Supply(V CC)Range2 7V to5 5VDC and AC Electrical Characteristics 2 7V k V CC k4 5VSymbol Parameter Part Number Conditions Min Max UnitsI CCA Operating Current CS e V IH SK e250kHz1mAI CCS Standby Current CS e V IL10m AI IL Input Leakage V IN e0V to V CCg1m AI OL Output LeakageV IL Input Low Voltage b0 10 15V CCVV IH Input High Voltage0 8V CC V CC a1V OL Output Low Voltage I OL e10m A0 1V CCVV OH Output High Voltage I OH e b10m A0 9V CCf SK SK Clock Frequency0250kHzt SKH SK High Time1m st SKL SK Low Time1m st SKS SK Setup Time SK Must Be at V IL for0 2m st SKS before CS goes hight CS Minimum CS(Note2)1m s Low Timet CSS CS Setup Time0 2m st DH DO Hold Time70nst DIS DI Setup Time0 4m st CSH CS Hold Time0m st DIH DI Hold Time0 4m st PD1Output Delay to‘‘1’’2m st PD0Output Delay to‘‘0’’2m st SV CS to Status Valid1m st DF CS to DO in CS e V IL0 4m sTRI-STATEt WP Write Cycle Time15mshttp www national com3DC and AC Electrical Characteristics 4 5V k V CC k5 5VSymbol Parameter Part Number Conditions Min Max UnitsI CCA Operating Current CS e V IH SK e1MHz1mAI CCS Standby Current CS e V IL50m AI IL Input Leakage V IN e0V to V CCg1m AI OL Output Leakage(Note4)V IL Input Low Voltage b0 10 8V V IH Input High Voltage2V CC a1V OL1Output Low Voltage I OL e2 1mA0 4V V OH1Output High Voltage I OH e b400m A2 4V OL2Output Low Voltage I OL e10m A0 2V V OH2Output High Voltage I OL e b10m A V CC b0 2f SK SK Clock Frequency(Note5)01MHzt SKH SK High Time NM93C06L-NM93C66L250nsNM93C06LE-NM93C66LE300t SKL SK Low Time250nst SKS SK Setup TIme SK Must Be at V IL for50nst SKS before CS goes hight CS Minimum CS(Note2)250ns Low Timet CSS CS Setup Time50nst DH DO Hold Time70nst DIS DI Setup Time NM93C06L-NM93C66L100nsNM93C06LE-NM93C66LE200t CSH CS Hold Time0nst DIH DI Hold Time20nst PD1Output Delay to‘‘1’’500nst PD0Output Delay to‘‘0’’500nst SV CS to Status Valid500nst DF CS to DO in100ns TRI-STATE CS e V ILt WP Write Cycle Time10ms http www national com4Capacitance(Note3)T A e25 C f e1MHzSymbol Test Typ Max UnitsC OUT Output Capacitance5pFC IN Input Capacitance5pFNote1 Stress above those listed under‘‘Absolute Maximum Ratings’’may cause permanent damage to the device This is a stress rating only and operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliabilityNote2 CS(Chip Select)must be brought low(to V IL)for an interval of t CS in order to reset all internal device registers(device reset)prior to beginning another opcode cycle(this is shown in the opcode diagrams in the following pages)Note3 This parameter is periodically sampled and not100%testedNote4 Typical leakage values are in the20nA rangeNote5 The shortest allowable SK clock period e1 f SK(as shown under the f SK parameter) Maximum SK clock speed(minimum SK period)is determined by the interaction of several AC parameters stated in the datasheet Within this SK period both t SKH and t SKL limits must be observed Therefore it is not allowable to set 1 t SK e t SKH(minimum)a t SKL(minimum)for shorter SK cycle time operationAC Test ConditionsV CC RangeV IL V IH V IL V IH V OL V OHI OL I OH Input Levels Timing Levels Timing Levels2 7V s V CC k4 5V0 3V 1 8V1 0V0 8V 1 5V g10m A (Extended Voltage Levels)4 5V s V CC s5 5V0 4V 2 4V1 0V 2 0V0 4V 2 4V b2 1mA 0 4mA(TTL Levels)Output Load 1TTL Gate(C L e100pF)Functional DescriptionThe NM93C06L C46L C56L C66L device have7instruc-tions as described below Note that the MSB of any instruc-tion is a‘‘1’’and is viewed as a start bit in the interface sequence For the C06and C46the next8bits carry the op code and the6-bit address for register selection For the C56and C66the next10-bits carry the op code and the8-bit address for register selectionRead(READ)The READ instruction outputs serial data on the DO pin After a READ instruction is received the instruction and ad-dress are decoded followed by data transfer from the se-lected memory register into a16-bit serial-out shift register A dummy bit(logical0)precedes the16-bit data output string Output data changes are initiated by a low to high transition of the SK clockErase Write Enable(WEN)When V CC is applied to the part it powers up in the Erase Write Disable(WDS)state Therefore all programming modes must be preceded by an Erase Write Enable WENinstruction Once an Erase Write Enable instruction is exe-cuted programming remains enabled until an Erase WriteDisable(WDS)instruction is executed or V CC is completelyremoved from the partErase(ERASE)The ERASE instruction will program all bits in the selectedregister to the logical‘‘1’’state CS is brought low followingthe loading of the last address bit This falling edge of theCS pin initiates the self-timed programming cycleThe DO pin indicates the READY BUSY status of the chip ifCS is brought high after the t CS interval DO e logical‘‘0’’indicates that programming is still in progress DO e logical‘‘1’’indicates that the register at the address specified inthe instruction has been erased and the part is ready foranother instructionhttp www national com 5Functional Description(Continued)Write(WRITE)The WRITE instruction is followed by16bits of data to be written into the specificed address After the last bit of data is put on the data-in(DI)pin CS must be brought low before the next rising edge of the SK clock This falling edge of CS initiates the self-timed programming cycle The DO pin indi-cates the READY BUSY status of the chip if CS is brought high after the t CS interval DO e logical0indicates that programming is still in progress DO e logical1indicates that the register at the address specified in the instruction has been written with the data pattern specified in the in-struction and the part is ready for another instruction Erase All(ERAL)The ERAL instruction will simultaneously program all regis-ters in the memory array and set each bit to the logical‘‘1’’state The Erase All cycle is identical to the ERASE cycle except for the different op-code As in the ERASE mode the DO pin indicates the READY BUSY status of the chip if CS is brought high after the t CS intervalWrite All(WRALL)The WRALL instruction will simultaneously program all reg-isters with the data pattern specified in the instruction As in the WRITE mode the DO pin indicates the READY BUSY status of the chip if CS is brought high after the t CS interval Write Disable(WDS)To protect against accidental data distrub the WDS instruc-tion disables all programming modes and should follow all programming operations Execution of a READ instruction is independent of both the WEN and WDS instructionsNote NSC CMOS EEPROMs do not require an‘‘ERASE’’or‘‘ERASE ALL’’operation prior to the‘‘WRITE’’and‘‘WRITE ALL’’instructions The‘‘ERASE’’and ‘‘ERASE ALL’’instructions are included to maintain compatibility with earlier technology EEPROMsInstruction Set for the NM93C06L and NM93C46LInstruction SB Op Code Address Data CommentsREAD110A5–A0Reads data stored in memory at specified address WEN10011XXXX Enable all programming modesERASE111A5–A0Erase selected registerWRITE101A5–A0D15–D0Writes selected registerERAL10010XXXX Erases all registersWRALL10001XXXX D15–D0Writes all registersWDS10000XXXX Disables all programming modesNote Address bits A5and A4become‘‘Don’t Care’’for the NM93C06LInstruction Set for the NM93C56L and NM93C66LInstruction SB Op Code Address Data CommentsREAD110A7–A0Reads data stored in memory at specified address WEN10011XXXXXX Enable all programming modesERASE111A7–A0Erase selected registerWRITE101A7–A0D15–D0Writes selected registerERAL10010XXXXXX Erases all registersWRALL10001XXXXXX D15–D0Writes all registersWDS10000XXXXXX Disables all programming modesNote Address bit A7is‘‘Don’t Care’’for the NM93C56Lhttp www national com6Timing DiagramsSynchronous Data TimingTL D 10045–13READTL D 10045–5WENTL D 10045–67http www national comTiming Diagrams(Continued)WDSTL D 10045–7WRITETL D 10045–8WRALLTL D 10045–9 http www national com8Timing Diagrams(Continued)ERASETL D 10045–10ERALTL D 10045–119http www national comPhysical Dimensions inches(millimeters)unless otherwise notedMolded Small Out-Line Package(M8)NS Package Number M08Ahttp www national com10Physical Dimensions inches(millimeters)unless otherwise noted(Continued)Notes Unless otherwise specified1 Reference JEDEC Registration M0-153 Variation AA Dated7 938-Pin Molded TSSOP JEDEC(MT8)NS Package Number MTC0811http www national comN M 93C 06L C 46L C 56L C 66L 256- 1024- 2048- 4096-B i tS e r i a l E E P R O M w i t h E x t e n d e d V o l t a g e (2 7V t o 5 5V )(M I C R O W I R E B u s I n t e r f a c e )Physical Dimensions inches (millimeters)unless otherwise noted (Continued)Molded Dual-In-Line Package (N)NS Package Number N08E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a)are intended for surgical implantsupport device or system whose failure to perform can into the body or (b)support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the userNational SemiconductorNational Semiconductor National Semiconductor National Semiconductor Corporation EuropeSoutheast Asia Japan Ltd Fax a 49(0)180-5308586Fax (852)23763901Tel 81-3-5620-7561。
