FEATURES DESCRIPTIONAPPLICATIONSTPA3120D2SIMPLIFIED APPLICATION CIRCUITTPA3120D2SLOS507C–MARCH2007–REVISED MAY2007 25-W STEREO CLASS-D AUDIO POWER AMPLIFIER•25-W/ch into a4-ΩLoad from a27-V Supply The TPA3120D2is a25-W(per channel)efficient,Class-D audio power amplifier for driving stereo •20-W/ch into a4-ΩLoad from a24-V Supplyspeakers in a single-ended configuration or a mono •Operates from10V to30Vbridge-tied speaker.The TPA3120D2can drive •Efficient Class-D Operation Eliminates Need stereo speakers as low as4Ω.The efficiency of the for Heat Sinks TPA3120D2eliminates the need for an external heatsink when playing music.•Four Selectable,Fixed Gain Settings•Internal Oscillator(No External Components The gain of the amplifier is controlled by two gain Required)select pins.The gain selections are20,26,32,36dB.•Single Ended Analog InputsThe patented start-up and shut-down sequences •Thermal and Short-Circuit Protection withminimize"pop"noise in the speakers without Auto Recoveryadditional circuitry.•Space-Saving Surface Mount24-pin TSSOPPackage•TelevisionsPlease be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2007,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.PVCCLSDPVCCLMUTELINRINBYPASSAGNDAGNDPVCCRVCLAMPPVCCRPGNDLPGNDLLOUTBSLAVCCAVCCGAIN0GAIN1BSRROUTPGNDRPGNDRTPA3120D2SLOS507C–MARCH2007–REVISED MAY2007These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.PWP(TSSOP)PACKAGE(TOP VIEW)TERMINAL FUNCTIONSTERMINALI/O/P DESCRIPTION24-PINNAME(PWP)Shutdown signal for IC(low=disabled,high=operational).TTL logic levels with compliance to SD2IAVCC.RIN6I Audio input for right channel.LIN5I Audio input for left channel.GAIN018I Gain select least significant bit.TTL logic levels with compliance to AVCC.GAIN117I Gain select most significant bit.TTL logic levels with compliance to AVCC.Mute signal for quick disable/enable of outputs(high=outputs switch at50%duty cycle,low= MUTE4Ioutputs enabled).TTL logic levels with compliance to AVCC.BSL21I/O Bootstrap I/O for left channel.PVCCL1,3P Power supply for left channel H-bridge,not internally connected to PVCCR or AVCC.LOUT22O Class-D1/2-H-bridge positive output for left channel.PGNDL23,24P Power ground for left channel H-bridge.VCLAMP11P Internally generated voltage supply for bootstrap capacitors.BSR16I/O Bootstrap I/O for right channel.ROUT15O Class-D1/2-H-bridge negative output for right channel.PGNDR13,14P Power ground for right channel H-bridge.PVCCR10,12P Power supply for right channel H-bridge,not connected to PVCCL or AVCC.AGND9P Analog ground for digital/analog cells in core.AGND8P Analog Ground for analog cells in core.Reference for pre-amplifier inputs.Nominally equal to AVCC/8.Also controls start-up time via BYPASS7Oexternal capacitor sizing.AVCC19,20P High-voltage analog power supply.Not internally connected to PVCCR or PVCCLConnect to ground.Thermal Pad should be soldered down on all applications to properly Thermal Pad Die Pad Psecure device to printed wiring board.2Submit Documentation FeedbackABSOLUTE MAXIMUM RATINGSDISSIPATION RATINGSRECOMMENDED OPERATING CONDITIONSTPA3120D2 SLOS507C–MARCH2007–REVISED MAY2007over operating free-air temperature range(unless otherwise noted)(1)VALUE UNITV CC Supply voltage AVCC,PVCC–0.3to36VV I Logic input voltage SD,MUTE,GAIN0,GAIN1–0.3to V CC+0.3VV IN Analog input voltage RIN,LIN-0.3to7V Continuous total power dissipation See Dissipation Rating TableT A Operating free-air temperature range–40to85°CT J Operating junction temperature range–40to150°CT stg Storage temperature range–65to150°CR L Load resistance(Minimum value) 3.2ΩHuman body model(all pins)±2ESD Electrostatic Discharge kVCharged-device model(all±500pins)(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratingsonly,and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.PACKAGE(1)(2)T A≤25°C DERATING FACTOR T A=70°C T A=85°C24-pin TSSOP 4.16W33.3mW/°C 2.67W 2.16W(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TIwebsite at .(2)The PowerPAD must be soldered to a thermal land on the printed circuit board.See the PowerPAD Thermally Enhanced Packageapplication note(SLMA002).MIN MAX UNITV CC Supply voltage PVCC,AVCC1030VV IH High-level input voltage SD,MUTE,GAIN0,GAIN12VV IL Low-level input voltage SD,MUTE,GAIN0,GAIN10.8VSD,V I=V CC,V CC=30V125I IH High-level input current MUTE,V I=V CC,V CC=30V125µAGAIN0,GAIN1,V I=V CC,V CC=24V125SD,V I=0,V CC=30V1I IL Low-level input current MUTE,V I=0V,V CC=30V1µAGAIN0,GAIN1,V I=0V,V CC=24V1T A Operating free-air temperature–4085°C3Submit Documentation FeedbackDC CHARACTERISTICSAC CHARACTERISTICSTPA3120D2SLOS507C–MARCH 2007–REVISED MAY 2007T A =25°C,V CC =24V,R L =4Ω(unless otherwise noted)PARAMETERTEST CONDITIONSMINTYP MAX UNIT Class-D output offset voltage |V OS |(measured differentially in BTL V I =0V,A V =36dB 7.550mV mode as shown in Fig 30)V (BYPASS)Bypass output voltage No loadAVCC/8V I CC(q)Quiescent supply current SD =2V,MUTE =0V,No load 2337mA I CC(q)Quiescent supply current in MUTE =0.8V,No load 23mA mute modeI CC(q)Quiescent supply current in SD =0.8V ,No load0.391mA shutdown mode r DS(on)Drain-source on-state 200m ΩresistanceGAIN0=0.8V 182022GAIN1=0.8VGAIN0=2V 242628GGaindBGAIN0=0.8V 303234GAIN =2VGAIN0=2V343638Mute AttenuationV I =1Vrms-82dB T A =25°C,V CC =24V,R L =4Ω(unless otherwise noted)PARAMETERTEST CONDITIONSMINTYP MAXUNIT V CC =24,V ripple =200mV PP 100Hz –48ksvrSupply ripple rejection dBGain =20dB1kHz–52V CC =24V,R L =4Ω,f =1kHz 16Output Power at 1%THD+NV CC =24V,R L =8Ω,f =1kHz 8P OWV CC =24V,R L =4Ω,f =1kHz 20Output Power at 10%THD+NV CC =24V,R L =8Ω,f =1kHz 10R L =4Ω,f =1kHz,P O =10W 0.08%Total harmonic distortion +THD+N noiseR L =8Ω,f =1kHz,P O =5W 0.08%85µV 20Hz to 22kHz,A-weighted filter,V nOutput integrated noise floor Gain =20dB-80dBV CrosstalkP O =1W,f =1kHz;Gain =20dB -60dB Max Output at THD+N <1%,f =1kHz,SNRSignal-to-noise ratio 99dB Gain =20dBThermal trip point 150°C Thermal hysteresis30°C f OSCOscillator frequency230250270kHz 4Submit Documentation FeedbackFUNCTIONAL BLOCK DIAGRAMBSLPVCCLBSR PVCCRTPA3120D2SLOS507C–MARCH 2007–REVISED MAY 20075Submit Documentation FeedbackTYPICAL CHARACTERISTICSf −Frequency −Hz2010010k T H D +N T o t a l H a r m o n i c D i s t o r t i o n + N o i s e %--0.11020k 10.01f −Frequency −Hz201001k10k T H D +N T o t a l H a r m o n i c D i s t o r t i o n + N o i s e %--0.11020k10.01f −Frequency −Hz201001k10k T H D +N T o t a l H a r m o n i c D i s t o r t i o n + N o i s e %--0.11020k10.01P −Output Power −WO 10 m100 m 110T H D +N T o t a l H a r m o n i c D i s t o r t i o n + N o i s e %--140100.010.1TPA3120D2SLOS507C–MARCH 2007–REVISED MAY 2007All tests are made at frequency =1kHz unless otherwise noted.TOTAL HARMONIC DISTORTION +NOISETOTAL HARMONIC DISTORTION +NOISEvsvsFREQUENCYFREQUENCYFigure 1.Figure 2.TOTAL HARMONIC DISTORTION +NOISETOTAL HARMONIC DISTORTION +NOISEvsvsFREQUENCYOUTPUT POWERFigure 3.Figure 4.6Submit Documentation FeedbackT H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %P −Output Power −WO1010 m100 m 11040-100201001 k20kf −Frequency −HzC r o s s t a l k d B-10k -90-80-70-60-50-40-30-20-100-300200-200-100100f −Frequency −HzG a i n d B-P h a s e -o-100f −Frequency −Hz-90-80-70-60-50-40-30-20-100C r o s s t a l k d B-TPA3120D2SLOS507C–MARCH 2007–REVISED MAY 2007TYPICAL CHARACTERISTICS (continued)All tests are made at frequency =1kHz unless otherwise noted.TOTAL HARMONIC DISTORTION +NOISECROSSTALKvsvsOUTPUT POWERFREQUENCYFigure 5.Figure 6.CROSSTALKGAIN/PHASEvsvsFREQUENCYFREQUENCYFigure 7.Figure 8.7Submit Documentation Feedbackf −Frequency −HzG a i n d B-P h a s e -oV −Supply Voltage −VSS P O u t p u t P o w e r WO --2228432126821418101620243026V - Supply Voltage - V SS P - O u t p u t P o w e r - WO 16263012107141820222428171615141312111096185432P −Output Power −WO 616E f f i c i e n c y %-80201010030040602050709024810121418TPA3120D2SLOS507C–MARCH 2007–REVISED MAY 2007TYPICAL CHARACTERISTICS (continued)All tests are made at frequency =1kHz unless otherwise noted.GAIN/PHASEOUTPUT POWERvsvsFREQUENCYSUPPLY VOLTAGEFigure 9.A.Dashed line represents thermally limited region.Figure 10.OUTPUT POWEREFFICIENCYvsvsSUPPLY VOLTAGEOUTPUT POWERFigure 11.Figure 12.8Submit Documentation FeedbackP −Output Power −WO E f f i c i e n c y %-8010100300406020507090P −Output Power −WO I −S u p p l y C u r r e n t −AC C 1232404081620242836-120201001 k20kf −Frequency −HzP o w e r S u p p l y R e j e c t i o n R a t i o d B-10k -110-100-90-80-70-500-40-30-20-10-600.702.557.51012.51517.52022.525P - Output Power - WO I - S u p p l y C u r r e n t -AC C TPA3120D2SLOS507C–MARCH 2007–REVISED MAY 2007TYPICAL CHARACTERISTICS (continued)All tests are made at frequency =1kHz unless otherwise noted.EFFICIENCYSUPPLY CURRENTvsvsOUTPUT POWEROUTPUT POWERFigure 13.Figure 14.SUPPLY CURRENTPOWER SUPPLY REJECTION RATIOvsvsOUTPUT POWERFREQUENCYFigure 15.Figure 16.9Submit Documentation Feedbackf −Frequency −Hz201001k10k T H D +N T o t a l H a r m o n i c D i s t o r t i o n + N o i s e %--0.11020k10.010.001P −Output Power −WO 10 m100 m 110T H D +N T o t a l H a r m o n i c D i s t o r t i o n + N o i s e %--140100.010.1-200400-1000100200300-30-20-10f - Frequency - HzP h a s e - °G a i n - d BV −Supply Voltage −VSS P O u t p u t P o w e r WO --40550651520301025354560505TPA3120D2SLOS507C–MARCH 2007–REVISED MAY 2007TYPICAL CHARACTERISTICS (continued)All tests are made at frequency =1kHz unless otherwise noted.TOTAL HARMONIC DISTORTION +NOISETOTAL HARMONIC DISTORTION +NOISEvsvsFREQUENCYOUTPUT POWERFigure 17.Figure 18.GAIN/PHASEOUTPUT POWERvsvsFREQUENCYSUPPLY VOLTAGEFigure 19.A.Dashed line represents thermally limited region.Figure 20.10Submit Documentation FeedbackP −Output Power −WO 32E f f i c i e n c y %-8040101003040602050709048162024283612-140201001 k20kf −Frequency −HzP o w e r S u p p l y R e j e c t i o n R a t i o d B-10k -120-100-80-60-40-200SLOS507C–MARCH 2007–REVISED MAY 2007TYPICAL CHARACTERISTICS (continued)All tests are made at frequency =1kHz unless otherwise noted.EFFICIENCYPOWER SUPPLY REJECTION RATIOvsvsOUTPUT POWERFREQUENCYFigure 21.Figure 22.APPLICATION INFORMATIONCLASS-D OPERATIONTraditional Class-D ModulationScheme+V CC 0 VOutput CurrentOutput Current+V CC 0 V +V CC 0 V+V CC0 V -VCCDifferential Voltage Across SpeakerSupply PumpingSLOS507C–MARCH 2007–REVISED MAY 2007This section focuses on the class-D operation of the TPA3120D2.The TPA3120D2operates in AD mode.There are two main configurations that may be used.For stereo operation,the TPA3120D2should be configured in a single-ended (SE)half bridge amplifier.For mono applications,TPA3120D2may be used as a bridge tied load (BTL)amplifier.The traditional class-D modulation scheme,which is used in the TPA3120D2BTL configuration,has a differential output where each output is 180degrees out of phase and changes from ground to the supply voltage,V CC .Therefore,the differential prefiltered output varies between positive and negative V CC ,where filtered 50%duty cycle yields 0V across the load.The class-D modulation scheme with voltage and current waveforms are shown in Figure 23and Figure 24.Figure 23.Class-D Modulation for TPA3120D2SE ConfigurationFigure 24.Class-D Modulation for TPA3120D2BTL ConfigurationOne issue encountered in single ended (SE)class D amplifier designs is supply pumping.Power supply pumping is a rise in the local supply voltage due to energy being driven back to the supply by operation of the Class D amplifier.This phenomenon is most evident at low audio frequencies and when both channels are operating at the same frequency and phase.At low levels,power supply pumping results in distortion in the audio output due to fluctuations in supply voltage.At higher levels,pumping can cause the overvoltage protection to operate,which temporarily shuts down the audio output.Gain setting via GAIN0and GAIN1inputs INPUT RESISTANCEInputSignalf =12Z Cpi i(1)SLOS507C–MARCH2007–REVISED MAY2007 APPLICATION INFORMATION(continued)There are several things which can be done to relieve the power supply pumping.The lowest impact is to operate the two inputs out of phase180°and reverse the speaker connections.Since most audio is highly correlated,this causes the supply pumping to be out of phase and not as severe.If this is not enough,the amount of bulk capacitance on the supply will need to be increased.Also,improvement is realized by hooking other supplies to this node which sinks some of the excess current.Power supply pumping should be tested by operating the amplifier at low frequencies and high output levels.The gain of the TPA3120D2is set by two input terminals,GAIN0and GAIN1.The gains listed in Table1are realized by changing the taps on the input resistors and feedback resistors inside the amplifier.This causes the input impedance(Z I)to be dependent on the gain setting.The actual gain settings are controlled by ratios of resistors,so the gain variation from part-to-part is small.However,the input impedance from part-to-part at the same gain may shift by±20%due to shifts in the actual resistance of the input resistors.For design purposes,the input network(discussed in the next section)should be designed assuming an input impedance of8kΩ,which is the absolute minimum input impedance of the TPA3120D2.At the higher gain settings,the input impedance could increase as high as72kΩTable1.Gain SettingINPUT IMPEDANCEAMPLIFIER GAIN(dB)(kΩ)GAIN1GAIN0TYPICAL TYPICAL002010012615103230113660Changing the gain setting can vary the input resistance of the amplifier from its smallest value,10kΩ±20%,to the largest value,60kΩ±20%.As a result,if a single capacitor is used in the input high-pass filter,the–3dB or cutoff frequency may change when changing gain steps.The–3-dB frequency can be calculated using e the Z I values given in Table1.INPUT CAPACITOR,C If =c 12Z C p i i-3 dBf c(2)C =i 12Z f p i c(3)Single Ended Output Capacitor,C OSLOS507C–MARCH 2007–REVISED MAY 2007In the typical application,an input capacitor (C I )is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation.In this case,C I and the input impedance of the amplifier (Z I )form a high-pass filter with the corner frequency determined in Equation 2.The value of C I is important,as it directly affects the bass (low-frequency)performance of the circuit.Consider the example where Z I is 20k Ωand the specification calls for a flat bass response down to 20Hz.Equation 2is reconfigured as Equation 3.In this example,C I is 0.4µF;so,one would likely choose a value of 0.47µF as this value is commonly used.If the gain is known and is constant,use Z I from Table 1to calculate C I .A further consideration for this capacitor is the leakage path from the input source through the input network (C I )and the feedback network to the load.This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom,especially in high gain applications.For this reason,a low-leakage tantalum or ceramic capacitor is the best choice.When polarized capacitors are used,the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 2V,which is likely higher than the source dc level.Note that it is important to confirm the capacitor polarity in the application.Additionally,lead-free solder can create dc offset voltages and it is important to ensure that boards are cleaned properly.In single ended (SE)applications,the DC blocking capacitor forms a high pass filter with speaker impedance.The frequency response rolls of with decreasing frequency at a rate of 20dB/decade.The cutoff frequency is determined byfc =1/2πC O Z LTable 2shows some common component values and the associated cutoff frequencies:Table mon Filter ResponsesC SE -DC Blocking Capacitor (µF)Speaker Impedance (Ω)f c =60Hz (-3dB)f c =40Hz(-3dB)f c =20Hz(-3dB)46801000220083304701000Output Filter and FrequencyResponsePower Supply Decoupling,C SBSN and BSP CapacitorsSLOS507C–MARCH 2007–REVISED MAY 2007For the best frequency response,a flat passband output filter (second order Butterworth)may be used.The output filter components consist of the series inductor and capacitor to ground at the LOUT and ROUT pins.There are several possible configurations depending on the speaker impedance,and whether the output configuration is single ended (SE)or bridge tied load (BTL).Table 3list the recommended values for the filter components.It is important to use a high quality capacitor in this application.A rating of at least X7R is required.Table 3.Recommended Filter Output ComponentsOutput Configuration Speaker Impedance (Ω)Filter Inductor (µH)Filter Capacitor (nF)422680Single Ended (SE)8473904101500Bridge Tied Load (BTL)822680Figure 25.BTL Filter Configuration Figure 26.SE Filter ConfigurationThe TPA3120D2is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD)is as low as possible.Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker.The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads.For higher frequency transients,spikes,or digital hash on the line,a good low equivalent-series-resistance (ESR)ceramic capacitor,typically 0.1µF to 1µF placed as close as possible to the device V CC lead works best.For filtering lower frequency noise signals,a larger aluminum electrolytic capacitor of 470µF or greater placed near the audio power amplifier is recommended.The 470-µF capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs.The PVCC terminals provide the power to the output transistors,so a 470-µF or larger capacitor should be placed on each PVCC terminal.A 10-µF capacitor on the AVCC terminal is adequate.These capacitors need to be properly derated for voltage and ripple current rating to insure reliability.The half H-bridge output stages use only NMOS transistors.Therefore,they require bootstrap capacitors for the high side of each output to turn on correctly.A 220-nF ceramic capacitor,rated for at least 25V,must be connected from each output to its corresponding bootstrap input.Specifically,one 220-nF capacitor must be connected from LOUT to BSL,and one 220-nF capacitor must be connected from ROUT to BSR.The bootstrap capacitors connected between the BSx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry.During each high-side switching cycle,the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on.VCLAMP CapacitorVBYP Capacitor SelectionSHUTDOWN OPERATIONMUTE OperationUSING LOW-ESR CAPACITORSSHORT-CIRCUIT PROTECTIONSLOS507C–MARCH 2007–REVISED MAY 2007To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded,one internal regulator clamps the gate voltage.One 1-µF capacitor must be connected from VCLAMP (pin 11)to ground and must be rated for at least 16V.The voltages at the VCLAMP terminal may vary with V CC and may not be used for powering any other circuitry.The scaled supply reference (VBYP)nominally provides an AVCC/8internal bias for the preamplifier stages.The external capacitor for this reference (C BYP )is a critical component and serves several important functions.During start-up or recovery from shutdown mode,C BYP determines the rate at which the amplifier starts.The start up time is proportional to 0.5sec per microfarad.Thus,the recommended 1µF cap results in a start-up time of approximately 500msec.The second function is to reduce noise produced by the power supply caused by coupling with the output drive signal.This noise could result in degraded power supply rejection and THD +N.The circuit is designed for a C BYP value of 1µF for best pop performance.The inputs caps should be the same value.A ceramic or tantalum low-ESR capacitor is recommended.The TPA3120D2employs a shutdown mode of operation designed to reduce supply current (I CC )to the absolute minimum level during periods of nonuse for power conservation.The SHUTDOWN input terminal should be held high (see specification table for trip point)during normal operation when the amplifier is in use.Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state.Never leave SHUTDOWN unconnected,because amplifier operation would be unpredictable.For the best power-up pop performance,place the amplifier in the shutdown or mute mode prior to applying the power supply voltage.The MUTE pin is an input for controlling the output state of the TPA3120D2.A logic high on this terminal causes the outputs to run at a constant 50%duty cycle.A logic low on this pin enables the outputs.This terminal may be used as a quick disable/enable of outputs when changing channels on a television or transitioning between different audio sources.The MUTE terminal should never be left floating.For power conservation,the SHUTDOWN terminal should be used to reduce the quiescent current to the absolute minimum level.Low-ESR capacitors are recommended throughout this application section.A real (as opposed to ideal)capacitor can be modeled simply as a resistor in series with an ideal capacitor.The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit.The lower the equivalent value of this resistance,the more the real capacitor behaves like an ideal capacitor.The TPA3120D2has short-circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts and output-to-GND shorts after the filter and output capacitor (at the speaker terminal.)Directly at the device terminals,the protection circuitry prevents damage to device during output-to-output,output-to-ground,and output-to-supply.When a short circuit is detected on the outputs,the part immediately disables the output drive.This is an unlatched fault.Normal operation is restored when the fault is removed.THERMAL PROTECTIONPRINTED-CIRCUIT BOARD(PCB)LAYOUT SLOS507C–MARCH2007–REVISED MAY2007Thermal protection on the TPA3120D2prevents damage to the device when the internal die temperatureexceeds150°C.There is a±15°C tolerance on this trip point from device to device.Once the die temperatureexceeds the thermal set point,the device enters into the shutdown state and the outputs are disabled.This isnot a latched fault.The thermal fault is cleared once the temperature of the die is reduced by30°C.The devicebegins normal operation at this point with no external system interaction.Because the TPA3120D2is a class-D amplifier that switches at a high frequency,the layout of the printed-circuitboard(PCB)should be optimized according to the following guidelines for the best possible performance.•Decoupling capacitors—The high-frequency0.1µF decoupling capacitors should be placed as close to the PVCC(pins1,3,10,and12)and AVCC(pins19and20)terminals as possible.The VBYP(pin7)capacitorand VCLAMP(pin11)capacitor should also be placed as close to the device as rge(220µF orgreater)bulk power supply decoupling capacitors should be placed near the TPA3120D2on the PVCCL andPVCCR terminals.•Grounding—The AVCC(pins19and20)decoupling capacitor and VBYP(pin7)capacitor should each be grounded to analog ground(AGND,pins8and9).The PVCCx decoupling capacitors and VCLAMP capacitors should each be grounded to power ground(PGND,pins13,14,23,and24).Analog ground and power ground should be connected at the thermal pad,which should be used as a central ground connection or star ground for the TPA3120D2.•Output filter—The reconstruction filter(L1,L2,C9,and C16)should be placed as close to the output terminals as possible for the best EMI performance.The capacitors should be grounded to power ground.•Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability.The dimensions of the thermal pad and thermal land are described in the mechanical section at the back of the data sheet.See TI Technical Briefs SLMA002and SLOA120for more information about using the thermal pad.For recommended PCB footprints,see figures at the end of this data sheet.For an example layout,see the TPA3120D2Evaluation Module(TPA3120D2EVM)User Manual,(SLOU189).Both the EVM user manual and the thermal pad application note are available on the TI Web site at.。
