Layout and Physical Design Guidelines for Capacitive Sensing

SIGNAL INTEGRITYRaymond Y. Chen, Sigrid, Inc., Santa Clara, CaliforniaIntroductionIn the realm of high-speed digital design, signal integrity has become a critical issue, and is posing increasing challenges to the design engineers. Many signal integr ity problems are electromagnetic phenomena in nature and hence related to the EMI/EMC discussions in the previous sections of this book. In this chapter, we will discuss what the typical signal integrity problems are, where they come from, why it is important to understand them and how we can analyze and solve these issues. Several software tools available at present for signal integrity analysis and current trends in this area will also be introduced.The term Signal Integrity (SI) addresses two concerns in the electrical design aspects – the timing and the quality of the signal. Does the signal reach its destination when it is supposed to? And also, when it gets there, is it in good condition? The goal of signal integrity analysis is to ensure reliable high-speed data transmission. In a digital system, a signal is transmitted from one component to another in the form of logic 1 or 0, which is actually at certain reference voltage levels. At the input gate of a receiver, voltage above the reference value Vih is considered as logic high, while voltage below the reference value Vil is considered as logic low. Figure 14-1 shows the ideal voltage waveform in the perfect logic world, whereas Figure 14-2 shows how signal will look like in a real system. More complex data, composed of a string of bit 1 and 0s, are actually continuous voltage waveforms. The receiving component needs to sample the waveform in order to obtain the binary encoded information. The data sampling process is usually triggered by the rising edge or the falling edge of a clock signal as shown in the Figure 14-3. It is clear from the diagram that the data must arrive at the receiving gate on time and settle down to a non-ambiguous logic state when the receiving component starts to latch in. Any delay of the data or distortion of the data waveform will result in a failure of the data transmission. Imagine if the signal waveform in Figure 14-2 exhibits excessive ringing into the logic gray zone while the sampling occurs, then the logic level cannot be reliably detected.SI ProblemsT ypical SI Problems“Timing” is everything in a high-speed system. Signal timing depends on the delay caused by the physical length that the signal must propagate. It also depends on the shape of the waveform w hen the threshold is reached. Signal waveform distortions can be caused by different mechanisms. But there are three mostly concerned noise problems:•Reflection Noise Due to impedance mismatch, stubs, visa and other interconnect discontinuities. •Crosstalk Noise Due to electromagnetic coupling between signal traces and visa.•Power/Ground Noise Due to parasitic of the power/ground delivery system during drivers’ simultaneous switching output (SSO). It is sometimes also called Ground Bounce, Delta-I Noise or Simultaneous Switching Noise (SSN).Besides these three kinds of SI problems, there is other Electromagnetic Compatibility or Electromagnetic Interference (EMC/EMI) problems that may contribute to the signal waveform distortions. When SI problems happen and the system noise margin requirements are not satisfied – the input to a switching receiver makes an inflection below Vih minimum or above Vil maximum; the input to a quiet receiver rises above V il maximum or falls below Vih minimum; power/ground voltage fluctuations disturb the data in the latch, then logic error, data drop, false switching, or even system failure may occur. These types of noise faults are extremely difficult to diagnose and solve after the system is built or prototyped. Understanding and solving these problems before they occur will eliminate having to deal with them further into the project cycle,and will in turn cut down the development cycle and reduce the cost[1]. In the later part of thischapter, we will have further investigations on the physical behavior of these noise phenomena, their causes, their electrical models for analysis and simulation, and the ways to avoid them.1. Where SI Problems HappenSince the signals travel through all kinds of interconnections inside a system, any electrical impact happening at the source end, along the path, or at the receiving end, will have great effects on the signal timing and quality. In a typical digital system environment, signals originating from the off-chip drivers on the die (the chip) go through c4 or wire-bond connections to the chip package. The chip package could be single chip carrier or multi-chip module (MCM). Through the solder bumps of the chip package, signals go to the Printed Circuit Board (PCB) level. At this level, typical packaging structures include daughter card, motherboard or backplane. Then signals continue to go to another system component, such as an ASIC (Application Specific Integrated Circuit) chip, a memory module or a termination block. The chip packages, printed circuit boards, as well as the cables and connecters, form the so-called different levels of electronic packaging systems, as illustrated in Figure 14-4. In each level of the packaging structure, there are typical interconnects, such as metal traces, visa, and power/ground planes, which form electrical paths to conduct the signals. It is the packaging interconnection that ultimately influences the signal integrity of a system.2. SI In Electronic PackagingTechnology trends toward higher speed and higher density devices have pushed the package performance to its limits. The clock rate of present personal computers is approaching gigahertz range. As signal rise-time becomes less than 200ps, the significant frequency content of digital signals extends up to at least 10 GHz. This necessitates the fabrication of interconnects and packages to be capable of supporting very fast varying and broadband signals without degrading signal integrity to unacceptable levels. While the chip design and fabrication technology have undergone a tremendous evolution: gate lengths, having scaled from 50 µm in the 1960s to 0.18 µm today, are projected to reach 0.1 µm in the next few years; on-chip clock frequency is doubling every 18 months; and the intrinsic delay of the gate is decreasing exponentially with time to a few tens of Pico-seconds. However, the package design has lagged considerably. With current technology, the package interconnection delay dominates the system timing budget and becomes the bottleneck of the high-speed system design. It is generally accepted today that package performance is one of the major limiting factors of the overall system performance.Advances in high performance sub-micron microprocessors, the arrival of gigabit networks, and the need for broadband Internet access, necessitate the development of high performance packaging structures for reliable high-speed data transmission inside every electronics system.Signal integrity is one of the most important factors to be considered when designing these packages (chip carriers and PCBs) and integrating these packages together.3、SI Analysis3.1. SI Analysis in the Design FlowSignal integrity is not a new phenomenon and it did not always matter in the early days of the digital era. But with the explosion of the information technology and the arrival of Internet age, people need to be connected all the time through various high-speed digital communication/computing systems. In this enormous market, signal integrity analysis will play a more and more critical role to guarantee the reliable system operation of these electronics products. Without pre-layout SI guidelines, prototypes may never leave the bench; without post-layout SI verifications, products may fail in the field. Figure 14-5 shows the role of SI analysis in the high-speed design process. From this chart, we will notice that SI analysis is applied throughout the design flow and tightly integrated into each design stage. It is also very common to categorize SI analysis into two main stages: reroute analysis and post route analysis.In the reroute stage, SI analysis can be used to select technology for I/Os, clock distributions, chip package types, component types, board stickups, pin assignments, net topologies, and termination strategies. With various design parameters considered, batch SI simulations on different corner cases will progressively formulate a set of optimized guidelines for physical designs of later stage. SI analysis at this stage is also called constraint driven SI design because the guidelines developed will be used as constraints for component placement and routing. The objective of constraint driven SI design at the reroute stage is to ensure that the signal integrity of the physical layout, which follows the placement/routing constraints for noise and timing budget, will not exceed the maximum allowable noise levels. Comprehensive and in-depth reroute SI analysis will cut down the redesign efforts and place/route iterations, and eventually reduce design cycle.With an initial physical layout, post route SI analysis verifies the correctness of the SI design guidelines and constraints. It checks SI violations in the current design, such as reflection noise, ringing, crosstalk and ground bounce. It may also uncover SI problems that are overlooked in the reroute stage, because post route analysis works with physical layout data rather than estimated data or models, therefore it should produce more accurate simulation results.When SI analysis is thoroughly implemented throughout the whole design process, a reliable high performance system can be achieved with fast turn-around.In the past, physical designs generated by layout engineers were merely mechanical drawings when very little or no signal integrity issues were concerned. While the trend of higher-speed electronics system design continues, system engineers, responsible for developing a hardware system, are getting involved in SI and most likely employ design guidelines and routing constraints from signal integrity perspectives. Often, they simply do not know the answers to some of the SI problems because most of their knowledge is from the engineers doing previous generations of products. To face this challenge, nowadays, a design team (see Figure 14-6) needs to have SI engineers who are specialized in working in this emerging technology field. When a new technology is under consideration, such as a new device family or a new fabrication process for chip packages or boards, SI engineers will carry out the electrical characterization of the technology from SI perspectives, and develop layout guideline by running SI modeling and simulation software [2]. These SI tools must be accurate enough to model individual interconnections such as visa, traces, and plane stickups. And they also must be very efficient so what-if analysis with alternative driver/load models and termination schemes can be easily performed. In the end, SI engineers will determine a set of design rules and pass them to the design engineers and layout engineers. Then, the design engineers, who are responsible for the overall system design, need to ensure the design rules are successfully employed. They may run some SI simulations on a few critical nets once the board is initially placed and routed. And they may run post-layout verifications as well. The SI analysis they carry out involves many nets. Therefore, the simulation must be fast, though it may not require the kind of accuracy that SI engineers are looking for. Once the layout engineers get the placement and routing rules specified in SI terms, they need to generate an optimized physical design based on these constraints. And they will provide the report on any SI violations in a routed system using SI tools. If any violations are spotted, layout engineers will work closely with design engineers and SI engineers to solve these possible SI problems.3.2.Principles of SI AnalysisA digital system can be examined at three levels of abstraction: log ic, circuit theory, and electromagnetic (EM) fields. The logic level, which is the highest level of those three, is where SI problems can be easily identified. EM fields, located at the lowest level of abstraction, comprise the foundation that the other levels are built upon [3]. Most of the SI problems are EM problems in nature, such as the cases of reflection, crosstalk and ground bounce. Therefore, understanding the physical behavior of SI problems from EM perspective will be very helpful. For instance, in the following multi-layer packaging structure shown in Figure 14-7, a switching current in via a will generate EM waves propagating away from that via in the radial direction between metal planes. The fields developed between metal planes will cause voltage variations between planes (voltage is the integration of the E-field). When the waves reach other visa, they will induce currents in those visa. And the induced currents in that visa will in turn generate EM waves propagating between the planes. When the waves reach the edges of the package, part of them will radiate into the air and part of them will get reflected back. When the waves bounce back and forth inside the packaging structure and superimpose to each other, resonance will occur. Wave propagation, reflection, coupling and resonance are the typical EM phenomena happening inside a packaging structure during signal transients. Even though EM full wave analysis is much more accurate than the circuit analysis in the modeling of packaging structures, currently, common approaches of interconnect modeling are based on circuit theory, and SI analysis is carried out with circuit simulators. This is because field analysis usually requires much more complicated algorithms and much larger computing resources than circuit analysis, and circuit analysis provides good SI solutions at low frequency as an electrostatic approximation.Typical circuit simulators, such as different flavors of SPICE, employ nodal analysis and solve voltages and currents in lumped circuit elements like resistors, capacitors and inductors. In SI analysis, an interconnect sometimes will be modeled as a lumped circuit element. For instance, a piece of trace on the printed circuit board can be simply modeled as a resistor for its finite conductivity. With this lumped circuit model, the voltages along both ends of the trace are assumed to change instantaneously and the travel time for the signal to propagate between the two ends is neglected. However, if the signal propagation time along the trace has to be considered, a distributed circuit model, such as a cascaded R-L-C network, will be adopted to model the trace. To determine whether the distributed circuit model is necessary, the rule of thumb is – if the signal rise time is comparable to the round-trip propagation time, you need to consider using the distributed circuit model.For example, a 3cm long stripling trace in a FR-4 material based printed circuit board will exhibits 200ps propagation delay. For a 33 MHz system, assuming the signal rise time to be 5ns, the trace delay may be safely ignored; however, with a system of 500 MHz and 300ps rise time, the 200ps propagation delay on the trace becomes important and a distributed circuit model has to be used to model the trace. Through this example, it is easy to see that in the high-speed design, with ever-decreasing signal rise time, distributed circuit model must be used in SI analysis.Here is another example. Considering a pair of solid power and ground planes in a printed circuit board with the dimension of 15cm by 15cm, it is very natural to think the planes acting as a large, perfect, lumped capacitor, from the circuit theory point of view. The capacitor model C= erA/d, an electro-static solution, assumes anywhere on the plane the voltages are the same and all the charges stored are available instantaneously anywhere along the plane. This is true at DC and low frequency. However, when the logics switch with a rise time of 300ps, drawing a large amount of transient currents from the power/ground planes, they perceive the power/ground structure as a two-dimensional distributed network with significant delays. Only some portion of the plane charges located within a small radius of the switching logics will be able to supply the demand. And voltages between the power/ground planes will have variations at different locations. In this case, an ideal lumped capacitor model is obviously not going to account for the propagation effects. Two-dimensional distributed R-L-C circuit networks must be used to model the power/ground pair.In summary, as the current high-speed design trend continues, fast rise time reveals the distributed nature of package interconnects. Distributed circuit models need to be adopted to simulate the propagation delay in SI analysis. However, at higher frequencies, even the distributed circuit modeling techniques are not good enough, full wave electromagnetic field analysis based on solving Maxwell’s equations must come to play. As presen ted in later discussions, a trace will not be modeled as a lumped resistor, or a R-L-C ladder; it will be analyzed based upon transmission line theory; and a power/ground plane pair will be treated as a parallel-plate wave guide using radial transmission line theory.Transmission line theory is one of the most useful concepts in today’s SI analysis. And it is a basic topic in many introductory EM textbooks. For more information on the selective reading materials, please refer to the Resource Center in Chapter 16.In the above discussion, it can be noticed that signal rise time is a very important quantity in SI issues. So a little more expanded discussion on rise time will be given in the next section.信号完整性介绍在高速数字设计领域，信号完整性已经成为一个严重的问题，是造成越来越多的挑战的设计工程师。

如何解决自习室占座现象英语作文The issue of seat-hogging in study halls is a prevalent problem that many students and educational institutions face. This phenomenon occurs when individuals claim a seat in a study area for an extended period, often without actively using the space for its intended purpose of studying or learning. This practice can be frustrating for other students who are seeking a quiet and productive environment to focus on their academic work. In this essay, I will explore several strategies and approaches that can be implemented to address this challenge and ensure fair and efficient utilization of study hall resources.Firstly, one of the most effective ways to mitigate the seat-hogging problem is to establish clear and well-communicated policies within the study hall. Educational institutions should consider implementing a set of guidelines or regulations that outline the expected behavior and usage of the study spaces. These policies could include time limits for individual seat occupancy, restrictions on leaving personal belongings unattended, and consequences for non-compliance. By setting clear expectations and enforcing them consistently, studentswill be more aware of the rules and less likely to engage in seat-hogging practices.Secondly, the implementation of a reservation system can be a valuable tool in managing the use of study hall spaces. This approach involves allowing students to reserve specific seats or study areas for a predetermined period, ensuring that the space is utilized efficiently and that no single individual monopolizes a particular spot. This system can be facilitated through an online platform or a physical sign-up sheet, making the process transparent and accessible to all students. By creating a fair and organized system for seat allocation, the seat-hogging problem can be significantly reduced.Another strategy to address this issue is to encourage a sense of community and shared responsibility among students within the study hall. This can be achieved through the implementation of a peer-monitoring or self-policing system, where students are empowered to respectfully remind their peers about the established policies and guidelines. By fostering a culture of mutual understanding and cooperation, students will be more inclined to be considerate of others and refrain from monopolizing study spaces. Additionally, educational institutions can consider designating "quiet zones" within the study hall, where stricter rules and expectations are enforced to maintain a focused and undisturbed learning environment.Furthermore, the physical design and layout of the study hall can play a crucial role in mitigating the seat-hogging problem. By creating a variety of seating options, such as individual desks, group study areas, and flexible seating arrangements, the study hall can cater to the diverse needs and preferences of students. This approach can help prevent the concentration of students in a few prime locations, thereby reducing the likelihood of seat-hogging. Additionally, the strategic placement of power outlets and access to resources, such as printers and whiteboards, can encourage students to utilize different areas of the study hall, rather than congregating in a single spot.In addition to the aforementioned strategies, educational institutions can also explore the implementation of technological solutions to address the seat-hogging issue. For instance, the use of a real-time occupancy monitoring system, which tracks the presence and duration of students in the study hall, can provide valuable data to inform decision-making and policy implementation. This information can be used to identify patterns of seat-hogging and guide the development of more effective strategies to address the problem.Moreover, the role of educational staff and administrators in addressing the seat-hogging challenge cannot be overlooked. By providing clear communication, regular monitoring, and promptintervention when necessary, the study hall can be maintained as a conducive and equitable learning environment. Staff members can engage in active dialogue with students, educate them on the importance of considerate behavior, and ensure that the established policies are consistently enforced.It is important to acknowledge that the seat-hogging problem is not unique to a single educational institution or study hall. It is a challenge faced by many academic communities worldwide. As such, it is crucial for educational institutions to collaborate and share best practices, learning from the successes and challenges of their peers. By fostering a collective effort to address this issue, a more comprehensive and effective solution can be developed, benefiting students and educational institutions alike.In conclusion, the problem of seat-hogging in study halls is a complex and multifaceted challenge that requires a multifaceted approach. By implementing clear policies, reservation systems, fostering a sense of community, optimizing physical design, leveraging technology, and engaging with educational staff, educational institutions can work towards creating a more equitable and efficient study environment for all students. Through a collaborative and proactive approach, the seat-hogging problem can be effectively mitigated, ensuring that study halls remain accessible, productive, and conducive to academic success.。

组织机构、职务职称英文译法通则Here is an essay on the topic of "Guidelines for Translating Organizational Structure and Job Titles into English", with the word count exceeding 1000 words, as requested.Organizations around the world have diverse structures and hierarchies, with a wide range of job titles and responsibilities. As businesses and companies expand their global reach, it becomes increasingly important to have a standardized approach to translating these organizational elements into English. This essay will provide guidelines and considerations for effectively translating organizational structure and job titles from other languages into English.When translating an organization's structure, it is crucial to understand the underlying principles and dynamics of the hierarchy. In many cultures, the organizational structure may be more vertical, with clear reporting lines and distinct levels of authority. In contrast, other organizations may have a flatter, more decentralized structure, with greater employee empowerment and cross-functional collaboration. It is essential to capture these nuances when translating the organizational structure into English.One key aspect to consider is the terminology used to describe different levels within the organization. For example, in some languages, there may be specific terms that denote seniority, such as "director," "manager," or "supervisor." It is important to carefully assess the responsibilities and decision-making authority associated with each of these positions, rather than simply providing a literal translation. In some cases, a direct translation may not accurately convey the intended meaning, and it may be necessary to use more appropriate English terms that better reflect the role and hierarchy within the organization.Another important factor to consider is the cultural context and organizational culture. Different countries and regions may have unique approaches to job titles, leadership structures, and decision-making processes. It is essential to understand these cultural nuances and adapt the English translation accordingly, rather than simply applying a one-size-fits-all approach. For example, in some Asian cultures, the use of honorifics or specific titles may be more prevalent, and it is crucial to find the appropriate English equivalent that captures the respect and authority associated with these positions.When translating job titles, it is essential to strike a balance between preserving the original meaning and ensuring that the Englishversion is clear and easily understood by a global audience. In some cases, a direct translation may be appropriate, but in others, it may be necessary to use a more descriptive or contextual term to convey the responsibilities and seniority of the role.For ex ample, a position such as "Direktør" in a Scandinavian organization may be accurately translated as "Managing Director" or "Chief Executive Officer," depending on the specific responsibilities and decision-making authority associated with the role. Similarly, a "Abteilungsleiter" in a German company may be best described as a "Department Head" or "Division Manager" in English.It is also important to consider the nuances and connotations of different English job titles. Some titles may have specific implications or expectations in certain contexts, and it is crucial to ensure that the translated title accurately reflects the role and responsibilities within the organization. For instance, the term "executive" may carry different meanings and expectations in different countries or industries, and it is essential to use it judiciously in the English translation.In addition to translating job titles, it is important to consider how to represent the overall organizational structure in English. This may involve creating visual representations, such as organizational charts or diagrams, to clearly communicate the reporting lines, decision-making processes, and the relative positions of different roles within the organization.When creating these visual representations, it is essential to use consistent and clear terminology, as well as to ensure that the layout and design effectively convey the intended hierarchy and relationships within the organization. This can be particularly important when communicating with stakeholders or partners who may not be familiar with the original organizational structure.Overall, the effective translation of organizational structure and job titles into English requires a nuanced and contextual approach. It is essential to understand the underlying principles and cultural factors that shape the organizational dynamics, and to use appropriate English terminology and visual representations that accurately convey the intended meaning and hierarchy. By following these guidelines, organizations can ensure that their global communications and collaborations are clear, effective, and respectful of cultural differences.。

一整套形象标识体系如下：形象标识体系，通常被称为品牌识别系统（Brand Identity System）或视觉识别系统（Visual Identity System），是一个组织、公司或产品通过视觉元素来传达其独特性和品牌形象的方式。

一个完整的形象标识体系通常包括以下几个核心组成部分：1. 标志/徽标（Logo）：一个独特的图形或文字组合，代表公司或品牌的核心身份。

2. 色彩方案（Color Palette）：一组选定的颜色，用于各种品牌材料和通信中，以保持品牌的一致性和识别度。

3. 字体/字型（Typography）：选定的一组字体，包括衬线、无衬线、脚本等，用于品牌的所有文本通信。

4. 图形元素（Graphic Elements）：如形状、图案、线条等，可以与标志一起使用，增强品牌的视觉吸引力。

5. 排版规则（Layout Guidelines）：指导如何在不同的媒介上排列和组合上述元素的规则。

6. 应用指南（Application Guidelines）：详细说明如何使用品牌标识的元素和规则，包括在不同背景、大小和媒介上的正确使用方法。

7. 品牌语言（Brand Language）：品牌的书面语言风格，包括口号、标语、语调和语气等。

8. 网站和数字媒体：网站的设计和界面，以及社交媒体平台上的视觉风格和交流方式。

9. 包装设计（Packaging Design）：产品的物理包装，它反映了品牌的形象和价值观。

10. 内部沟通材料：如员工手册、内部报告、演示模板等，确保内部沟通与品牌形象保持一致。

11. 宣传材料和广告：如传单、海报、广告、目录等，它们在外部传播品牌形象时起到关键作用。

12. 环境图形（Environmental Graphics）：也称为空间图形设计，涉及将品牌元素应用于物理空间，如办公室、零售店、展会等。

创建一个完整的形象标识体系需要深入的品牌策略研究、创意设计和细致的规划。

设计指南的标准和办法的要求的Design guidelines are essential for ensuring consistency, efficiency, and quality in any project. 设计指南对于确保项目的一致性、效率和质量至关重要。

They provide a set of rules and best practices that help designers make decisions and solve problems effectively. 它们提供了一套规则和最佳实践，帮助设计师有效地做出决策和解决问题。

By following these guidelines, designers can create products that are user-friendly, visually appealing, and easy to use. 通过遵循这些指南，设计师可以创建用户友好、视觉上吸引人且易于使用的产品。

The process of designing guidelines involves understanding the project requirements, researching user needs, and defining the design principles. 设计指南的制定过程涉及理解项目需求、研究用户需求和定义设计原则。

It also requires collaboration among team members to ensure that the guidelines are comprehensive and aligned with the project goals. 还需要团队成员之间的合作，以确保指南全面且与项目目标一致。

One of the key aspects of designing guidelines is establishing a clear design system. 设计指南的一个关键方面是建立清晰的设计系统。

2024年layout工程岗位职责13篇目录第1篇pcb layout工程师岗位职责、要求第2篇硬件layout工程师岗位职责硬件layout工程师职责任职要求第3篇版图工程师layout岗位职责第4篇高级layout工程师岗位职责第5篇pcblayout工程师岗位职责职位要求第6篇版图设计工程师（layout）岗位职责职位要求第7篇layout设计工程师岗位职责第8篇layout电子工程师岗位职责第9篇模拟layout工程师岗位职责第10篇工程师layout岗位职责第11篇硬件layout工程师岗位职责第12篇高级layout工程师岗位职责职位要求第13篇layout工程师岗位职责高级layout工程师岗位职责高级pcb layout工程师同为数码深圳市同为数码科技股份有限公司,同为数码,同为股份工作职责:1、独立进行公司产品pcb layout设计;2、和pcb板厂沟通,回复pcb板厂的相关工程资料沟通函;3、能独立完成从导入网表到出gerber文件工作;4、解决产品emc的问题;任职资格:1、本科及以上学历,电子通信相关专业;2、至少5年以上同等工作经验,具备较强的理论知识,有非常丰富的pcb layout经验,资深级别工程师;3、熟悉pcb生产工艺,做事责任心强,有pcb封装建库经验;4、熟悉smt制作流程及工艺,能和smt车间就相关问题进行明晰沟通,促进smt高效生产;5、熟练使用pcb layout工具—allegro 16.3及以上版本 ,熟练使用原理图设计工具or cad ,能看懂结构图以及拼板使用。

硬件layout工程师岗位职责硬件工程师— layout 江苏科曜能源科技有限公司江苏科曜能源科技有限公司,科曜职责描述:1、负责pcsbmsems等产品的pcb布板;2、负责维护元器件标准库及制定产品pcb设计规范;3、负责针对pcb布局、走线规则、可制造性等提出解决方案;4、负责layout的输出文档,制作gerber file及钢网文件等资料;5、负责pcb打样及smt过程,配合其他部门解决问题。

Cadence IC Design ManualFor EE5518ZHENG Huan QunLin Long YangRevised onMay 2017Department of Electrical & Computer EngineeringNational University of SingaporeContents1 INTRODUCTION (4)1.1 Overview of Design Flow (4)1.2 Getting Started with Cadence (6)1.3 Using Online Help (8)1.4 Exit Cadence (8)2 SCHEMATIC ENTRY (9)2.1 Creating a New Design Library (9)2.2 Creating a Schematic Cellview (10)2.3 Adding Components to Schematic (11)2.4 Adding Pins to Schematic (12)2.5 Adding Wires to Schematic (13)2.6 Saving Your Design (14)3 SYMBOL AND TEST CIRCUIT CREATION (15)3.1 Creating Symbol (15)3.2 Editing Symbol (16)3.3 Building Test Bench (18)4 SIMULATING YOUR CIRCUIT (21)4.1 Start the Simulation Environment (21)4.2 Selecting Project Directory (21)4.3 Setup Model Library (22)4.4 Choosing the Desired Analysis (22)4.5 Setup Variables (23)4.6 Saving Simulation Data (24)4.7 Saving Output for Plotting (24)4.8 Viewing the Netlists (25)4.9 Running the Simulation (25)5 PHYSICAL LAYOUT (28)5.1 Layout vs Symbol of CMOS Devices (28)5.2 Starting Layout Editor (29)5.3 Vias (31)5.4 Changing the Grid (33)5.5 Inserting and Editing Instances (34)5.6 Drawing Shapes / Paths (35)5.7 Creating Pins (36)6 DESIGN VERIFICATION: DRC AND LVS (38)6.1 Performing DRC (38)6.2 Performing LVS (40)6.3 Performing PEX (41)7 POST‐LAYOUT SIMULATION (45)7.1 Simulation the Extracted Cell View (45)8 CONCLUSION (46)1INTRODUCTIONThis manual describes how to use Cadence IC design tools. It covers the whole design cycle, from the front-end to the back-end, i.e., from the pre-layout design to the post-layout design.The manual aims to provide a guide for fresh users. Following the manual, users can start doing analog IC design even though the users don’t have any knowledge of the tools.An inverter is used to illustrate the whole cycle of analog IC design, and Cadence Generic 45nm (cg45nm) kit is the technology library used for implementing the inverter. The method stated in the manual can be applied to other type of analog circuit design.1.1Overview of Design FlowFigure 1 shows a typical analog IC design flow.The design flow starts from schematic entry with the Cadence schematic capture tool –Schematic Editor. Devices or cells from the cg45nm or other libraries are used to build your circuit. Your design is hierarchical; therefore higher level schematics also incorporate cells which you have already developed. The schematics which you enter at this stage therefore typically consist of a number of base library cells and also lower level cells designed yourself.These are described in Sections 2 and 3 of the manual.When you have finished designing a particular circuit, you need to simulate it to ensure that it works as expected. It would be unlikely that your circuit works as expected at the first time so you have to repeat the cycle to improve the circuit, as shown in Figure 1, until the circuit works satisfactorily. This must be done for each sub-circuit of your design and then for the top level design. How to simulate and view the performance of simulation results are presented in Sections 4 of the manual.When the performance of the circuit is satisfactory, it is ready to start the physical design or layout of the circuit. The layout starts with the cell or device placement. Once the cells have been placed, routing can be carried out. Routing connects the cells/device of the design.After finishing placement and routing, the layout has to go through the Design Rule Check (DRC) with rule decks provided by PDK provider, to ensure that there is no design rule violation in the layout. The layout has to be rectified accordingly to the rules’ requirement till it passes DRC.Upon a successful DRC, it is Layout-versus-Schematic (LVS) check, to assure that all connections in the layout are correct. The layout has to be amended accordingly to the schematic If LVS doesn’t pass. DRC has to be done whenever layout is changed. The process is repeated until the LVS passes.Figure 1. Analog IC Design FlowThe next step is parasitic extraction (PEX) to get the extracted view of the circuit, which is used for post–layout simulation. The extracted view includes the parasitic effects in both the instances/devices and the required wiring interconnects of the circuit.Following DRC, LVS and PEX, it is post-layout simulation. The post-layout simulation is essential to make sure that the circuit with the extra parasitic parameters functions well and still meet the design specifications. If the performance of the post-layout simulation is not acceptable, back to the stage of schematic entry to check the circuit. Basically, re-design the circuit is necessary. Repeat the whole flow until the results of the post-layout simulation meet the design specifications.If everything is satisfactory, the next stage is GDSII Generation. It generates a file which depicts the low level geometry of layout. GDSII format is industry standard format suitable fora semiconductor company to fabricate and manufacture the chip of layout. This is briefed inthe last section of the manual.1.2Getting Started with CadenceUpon logging into your account, you will be brought to the Linux Desktop Environment.Right click on the desktop and click Open Terminal to open a “window” on the desktop. This window is the Linux command line prompt at which you can run Linux commands. After running a Linux command, this window also shows the output of the command.The following steps show how to start Cadence with cg45nm kit.A.Create a working directory - project (it can be any name as you like) with thecommand:mkdir projectwhere mkdir is Linux command and the project is the directory name;B.Enter the working directory with the command:cd projectwhere the cd is the Linux command;C.Type the followings commands to do the environment setup for using Cadence Generic45nm PDK.cp /app11/cg45nm/USERS/cds.lib .cp /app11/cg45nm/USERS/assura_tech.lib .cp /app11/cg45nm/USERS/pvtech.lib .D.Start cadence in the working directory – project with the following command:virtuoso &where virtuoso is the command to start Cadence IC design tool.Now, Cadence tools are successfully started. Keeps only the Command Input Window (CIW) which is shown in Figure 2.Figure 2. CIW WindowDo not close this CIW and try to keep it in view whenever you are using Cadence. Error messages and output from some of the tools are always sent to the CIW. If something doesn't appear to be working, always check the CIW for error messages. In addition, the CIW allows the user great control over Cadence by interpreting skill commands which are typed into it.E.In the CIW, select Tools Library Manager. The Library Manager pop up as inFigure 3. The Library Manager is where you create, add, copy, delete and organizeyour libraries and cell views.Figure 3. Library Manager WindowYou can see that the library gpdk045 appears in the Library column of the librarymanager.Now, you have started Cadence tool and loaded the cg45nm kit successfully. There are some documents in /app11/cg45nm/ gpdk045_v4_0/docs, and you can always refer to these documents for the information such as devices, device models, DRC rules and others related to cg45nm kit.Next time, you need only to repeat the steps B and D, for launching Cadence virtuoso and doing your project.1.3Using Online HelpCadence provides a comprehensive online manuals for all Cadence tools. You can launch the online help by typing the following command at the Linux prompt.cdnshelpThis invokes the online software manuals. Alternately, there is a help menu on each Cadence window. Manual which is related to that window related will pop-up once clicking on the help button.1.4Exit CadenceTo exit Cadence, just click on the cross sign X or File Exit in CIW. It is necessary to exit Cadence when it is not in use. Your library file would be locked or cannot edited next time if Cadence was not exited properly.2SCHEMATIC ENTRYNow that Cadence is running, you are almost ready to start entering schematics. However, you must first create a library which will be used to store all the parts of your design. Then, schematic can be created in the library.2.1Creating a New Design LibraryA.In the Library Manager window, select File→New→Library. New Library formpops up as shown in Figure 4.B.In the New Library form referring to Figure 4, key in your design library name(example: test) in the field of Name, and then click Ok.C.Click Ok in the pop-up window - the Technology File for New Library, referring toFigure 5.D.Choose gpdk045 in the Attach Library to Technology Library form, referring toFigure 6, and then click Ok.Figure 4. New Library FormFigure 5. Technology File for New Library FormFigure 6. Attach Library to Technology File FormA new library, named test, should appear in your Library Manager window.2.2 Creating a Schematic CellviewA.In Library Manager, select the Library where you would like to create a schematic. Then,select File→New→Cell View.B.Set up the New File form as Figure 7Figure 7. Create CellViewC.Click OK when done. A blank schematic window for the "inv" (your cell name)schematic appears.Explore the functions available by putting your mouse over the toolbar and fixed menu icons.In addition, note that some of the menu selections have alphabets listed to the right of them. These are bind-key or shortcut-key definitions which are very useful in the long run.Test them out during the schematic drawing in subsequent steps.2.3Adding Components to SchematicFigure 8 shows the schematic which you are going to patch, and the property of each component is listed in Table 1.Figure 8. Inverter CircuitTabel 1. Component Properties of Figure 8: Inverter CircuitComponents Library Name Cell Name PropertiesPMOS gpdk045 pmos1v l:45nm w:120nm (default size)NMOS gpdk045 nmos1v l:45nm w:120nm (default size)Here is the example on how to add component instances by placing cell views from libraries. Type “i” bind-key or select Create Instance in the schematic window or click on the menu bar to display Add Instance form. Then in the Add Instance window, select gpdk045as Library, choose the NMOS transistor by selecting nmos1v in Cell and also choose symbol as View, as shown in Figure 9.Figure 9. Add Instance FormSimilarly, add the pmos1v into the schematic. As an example, here we just keep all theparameters as default.If you place a component with the wrong parameter values, select the component and type “q” bindkey or use the Edit→Properties→Objects command to change the parameters. Use the Edit→Move command or type “m” if you place components in the wrong location.2.4Adding Pins to SchematicYou must place I/O pins in your schematic to identify the inputs and the outputs. A pin can be an input, output or an input-output (bi-directional) pin.Type “p” or select Add →Pin from inv Schematic Window or click the Pin fixed menuicon in the schematic window. The Add Pin form appears as Figure 10.Figure 10. Add Pin FormClick Hide and move you cursor to the Schematic Window. Place pins at the correct places and click right mouse key to rotate the pin if necessary.Add pins according to Table 2, paying attention to the direction.Table 2. Pin Names and Direction of invPin Names DirectionVin InputVout OutputVDD, GND Input-OutputCaution: Do not use the add component form to place schematic pins.2.5 Adding Wires to SchematicAdd wires to connect the components and pins in the design.A.Type “w” or select Add →Wire (narrow) in Schematic Window or click (narrow)fixed menu icon.B.In the schematic window, click on a pin of one of your components as the first pointfor your wiring. A diamond shape appears over the starting point of this wire.C.Follow the prompts at the bottom of the design window and click left mouse key onthe destination point for your wire.D.Continue wiring the schematic. When done wiring, press Esc with your cursor in theschematic window to cancel wiring.2.6Saving Your DesignCheck the design to ensure that it is correct and save the design.A.Click the Check and Save icon in the schematic window.B.Observe the CIW output area, for the information of the check and save action.3SYMBOL AND TEST CIRCUIT CREATIONSymbols are useful when creating designs as it is impractical to show every transistor on the top level schematic. Instead, the symbols of cells are created in order to instantiate them in the higher level schematics and make them more readable (i.e. hierarchical designs). Create a symbol for your design so you can place it in a test circuit for simulation.3.1Creating SymbolA.In the inv schematic window, select Create → Cellview → From Cellview. CellviewFrom Cellview pops up as shown in Figure 11.Figure 11. Cellview From Cellview FormB.Click OK in the Cellview From Cellview form. The Symbol Generation Options formappears as Figure 12. Enter the information listed in Table 3 for the symbol.Table 3: Pin SpectificationsLeft Pins : VinRight Pins : VoutTop Pins: VDDBottom Pins: GNDFigure 12. Symbol Generation Options FormC.Click OK in the Symbol Generation Options form. A window with a symbol createdautomatically by the tools pops up, referring to Figure 13.Figure 13. Symbol Generated AutomaticallyD.Observe the CIW output pane and note the messages stating Adding ‘CDFinformation ...’.3.2Editing SymbolYou can modify the symbol to have a more meaningful shape for easy recognition.A.Move your cursor over the symbol, until the entire green rectangle is highlighted. Clickleft to select it.B.Click Delete icon in the symbol window to delete the green rectangle.C.Select Create→Shape→Polygon. Follow the prompts at the bottom of the symbol, anddraw the triangle shown in Figure 14.D.Type “m” or click Move icon in the symbol window, move the pins to the finaldestination.E.Select [@partName], and use Edit→Properties→Object to change it to inverter asshown in Figure 14.Figure 14. Edit Object Properties FormF.Save your edited symbol view. The final symbol is shown in Figure 15.Figure 15. Symbol of inv3.3Building Test BenchTo test the inverter that you have just built, you need to create a test bench. This test bench will also be used during the post-layout simulation.Creating an inv_test schematic cellview with the below information, following the steps listed in Section 2 – SCHEMATIC ENTRY. The test bench is as shown in Figure 17.Library Name : testCell Name : inv_testView Name : schematicLibrary Name Cell Name Propertiestest inv_testanalogLib Vdc VDDanalogLib vpulse Referring to Figure 16analogLib gnd GNDanalogLib cap 1f FFigure 16. Vpulse FormFigure 17. Test Bench – inv_test for inv CircuitNote:There are wire names Vin and Vout in Figure 17. These can be created by clicking on Create Wire Name on the inv_test schematic window. Key in Vin Vout in the Names field of the Add Wire Name form, and then click Hide. Moving your mouse to the schematic window, click the wire where you want it to be named in the same sequence as typing the names in the Names field.4SIMULATING YOUR CIRCUITBefore starting the simulation, make sure that the schematic (inv_test) is open, then perform the following steps.4.1Start the Simulation EnvironmentIn your schematic window, select Launch →ADE L. The Analog Design Environment (ADE) window appears as shown in Figure 18.Figure 18. ADE Window4.2Selecting Project DirectoryIn the ADE window, select Setup→Simulator/ Directory/ Host. A Choosing Simulator form appears as Figure 19. In the Project Directory blank, type in /var/tmp/(desired folder name) to save your simulation files in the /var/tmp directory on the local server. Click OK to confirm.Figure 19. Choosing Simulator/Directory/Host FormAs each user account has a limited quota, this helps to conserve memory space in your account and prevents you from exceeding your account quota. However, note that contents in this folder is deleted periodically every 30 days automatically.4.3Setup Model LibraryIn the ADE window, select Setup Model Libraries. The Model Library setup form appears. Double click the column of section, and then click the down arrow to choose tt which is typical N and P model parameters. The model library setup for the inv_test circuit is shown in Figure 20. Click ok on the setup form to finish the settings.The information of models can be found in/app11/cg45nm/gpdk045_v4_0/docs/gpdk045_pdk_referenceManual.pdf.Figure 20. Model Library Setup for inv_test4.4Choosing the Desired AnalysisIn the ADE window, click the Choose Analyses icon . The Choosing Analyses form appears. Cadence ADE is able to run several types of simulations consecutively. You are then able to view the signals from different simulations at the same time. In this example, we will do transient analysis, so we shall setup transient analyses through the ADE as Figure 21.Figure 21. Setup for Transient Analyses4.5Setup VariablesThere is a variable, VDD, in the inv_test circuit. We need to set a value to it before starting simulation.In the ADE window, click Variables. Enter the name as the variable name VDD, then set the valueas 1.1, and finally click Ok. Please take note that 1.1v is the nominal voltage for this technology.Figure 22. Editing Design Variables4.6Saving Simulation DataThe simulation environment is configured to save all node voltages in the design by default. In larger designs, where saving all of the data requires too much disk space, you can select a specific set of node to save. Following steps show you how to select terminals to save.A.In the ADE window, select Outputs→Save All.B.The Keep Options form appears. Do not modify the form at this time. However, if youneed to save less data, under the first option “Select signals to output”, Click “selected”.4.7Saving Output for PlottingSelect the signals that you would like to observe.A.Select Outputs→To Be Plotted→Select On Design.B.Note that if you click on wires / nets, voltage signals are selected. If you click onconnection nodes, currents flowing through that note and into the component are saved.C.Follow the prompts at the bottom of the schematic window. Click on the output wireslabeled with Vout and Vin (select the wire that you want to monitor).D.Press Esc with your cursor in the schematic window when finished.Now you have set up the simulation environment which as shown in Figure 23. You can save the simulation state. This saves all the information such as the Model Path, outputs, analyses, environment options, and variables so that you do not need to set these parameters the next time again.Figure 23. ADE window with completed settingsIn the ADE window, select Session→Save State. Tick Cellview and then click OK. You can recall your settings by selecting Session→Load State.4.8Viewing the NetlistsSometimes, you need to view the netlist of your circuit or design. You can do so through the ADE, select Simulation→Netlist→Create / Display / Recreate.If there are any errors encountered during this step, check the messages in the CIW and retrace your steps to see that all data was entered properly.4.9Running the SimulationSelect Simulation→Netlist and Run to start the simulation or click on the Run Simulation icon in the Simulation Window. After the simulation is done, a waveform window will pop up showing the simulation results as Figure 24.Click on the waveform window to separate Vin and Vout.You can create a horizontal or vertical marker by clicking Marker on the waveform window. For example, creating a horizontal marker on Figure 24 with put Y Postion at 0.5*VDD=550mV, and then zoom in. The waveform window will look like Figure 25. Delays of the inverter could be found from the reading on the marker.Figure 24. Output of SimulationFigure 25. Waveform with Marker.Explore the icons on the toolbar as well as the various items on the menu. Try to add markers as that is something that will be used often during your simulations. You can also update the titles and labels on your plot to make them easy to read or more meaningful, if necessary.*Quick Tip : Shortcuts “a” and “b” to place a delta marker where you observe the difference between two points. What does shortcuts “v” and “h” do?There are many other functions available in the calculator tool, explore and play around with them.By now, you have finished pre-layout simulation (schematic level simulation). Next, you need to draw the layout of the inverter circuit and then do post-layout simulation to check your circuitperformance.5 PHYSICAL LAYOUTBy now, you should know how to create and simulate your circuit. Once the performance of your design is satisfactory, the next step in the process of making an integrated circuit chip is to create a layout. What is a layout? A layout is basically a drawing of the masks from which your design will be fabricated. Therefore, layout is just as critical as specifying the parameters of your devices.Before we get into the layout, first you need to understand the design rules for layout. Design rules give guidelines for generating layouts. They dictate spaces between wells, sizes of contacts, minimum spacing between a poly and a metal, and many other similar rules.Design rules are essential to any successful layout design, since they account for the various allowances that need to be given during actual fabrication and to account for the sizes and the steps involved in generating masks for the final layout. Note that the layout is very much process dependent, since every process has a certain fixed number of available masks for layout and fabrication.You may find more details on the Design Rules Manual (DRM):/app11/cg45nm/gpdk045_v_4_0/docs/gpdk045_drc.pdf5.1 Layout vs Symbol of CMOS DevicesIn this section, we look at only three devices: nmos1v and pmos1v. Check the process document, you can find the information for other devices.Figure 26 shows the nmos1v device. From layout view, you can see that the terminal B is the black background of the layout window.Figure 26. Layout vs Symbol of NMOSFigure 27 shows the pmos1v device, which looks similar to NMOS device but with P type implant (orange-stripe layer) and N-well (purple surrounding layer). G D SBFigure 27. Layout vs Symbol of PMOS5.2Starting Layout EditorNow we are going to create a new layout in the cell “inv” in “test” library.A.In Library Manager, select File→New→Cellview ... A Create New File form pops up.B.Select "test" as Library Name; enter "inv" as Cell Name, "layout" as View Name.C.Choose Open with Layout XL, and then click OK.Figure 28. Create Cellview – LayoutUseful layerselectionfeatureFigure 29. Layout WindowCell "inv" with "layout" view in library "test" will be created. It is opened up automatically, followed by inv schematic window, as shown in Figure 29. The layout editor contains two main sub-windows, namely the Layers sub-window on the left and Layout Editing window on the right. Notice the Layers sub-window on the left side of the layout view. This sub-window displays the fabrication layers defined in the technology. You can find the cross sectional profile in the process documents.Each layer is represented by a different color and pattern for easier differentiation. The black background on the right can be interpreted as the p-substrate of the wafer.To hide a layer, use the middle scroll button to click on a layer. To disable a layer from use, use the right mouse button.You might notice that some layer names appear more than once in the Layers sub-window. For example, Metal1 appears two times: one as Metal1 drawing, the other as Metal1 pin. Metal1 drawing is a layer with drawing purpose, and such layers with drawing purposes will be fabricated in the mask. The pin layers are symbolic layers and serve to indicate position of I/O pins and define net names. Such layers are not part of the mask layout and will not be fabricated.5.3ViasVias are used to connect between layers, much like those used in PCB design.There are different types of vias for different layer pairs. Normally a via is only for connecting two successive layers, e.g., Metal 1 and Metal 2. In case there is a metal jump between more than two layers, via stacking is required.In the layout window, click Create→Via or type “o” to bring up the via menu. Place the vias on the layout editing window, you can observe the layers that are involved in each type of via. Experiment with the different modes and configurations in the via menu to create arrays and stacks of vias as well. For example,A.Click on Create→Via, the Create Via window pops up as figure 30 shows.B.Choose M1_PO under Via Definition, and click on the layout window to place it andthen press Esc button to stop the placing. You can change the number of Rows and Columns on the Create Via form.C.To view the layers of M1_PO, click to select it first and then press Shift + f key. Observethe via appears different.D.To check the layers used in via M1_PO, select it and then click Edit→Hierarchy→Flatten as shown in figure 31. Click OK on the pop-up form shown in Figure 32.E.Now, you can separate the layers and check layers’ property to find out the layers’ name.Via M1_PO connects layers Metal 1 and Poly as shown in Figure 33.Try to explore different options (Rows, Columns, Stack, etc.) under via menu by yourself, this will be very helpful for layout drawing.Figure 30. Create Via windowsFigure 31. Edit ViaFigure 32. Flatten FormFigure 33. Via M1_POThe M1_PSUB and M1_NWELL contacts are substrate and n-well contacts that are used to connect the bulks of the NMOS and PMOS respectively. For the inverter circuit used in this manual, the bulks of the NMOS and PMOS need to be connected to ground (GND) and VDD respectively.5.4Changing the GridIn Figure 29, the black window on the right is the layout editing window. The position of the cursor in layout editing window is indicated by the coordinate showed on the top right corner of the window after X: and Y:. The unit here is "µm". Move your cursor around the editing window and see the X: Y: values change with step size 0.1. Change the step size to 0.005 as that is the minimum step size for this technology.From Layout Editing window pull down menu, select Options →Display... change "X Snap Spacing" and "Y Snap Spacing" to 0.005 then click on "OK". Now move the cursor around the editing window again, you will see the X: Y: values change with step size 0.005.There are raw grid and fine grid (as small dots) on the window background. If you cannot clearly see the raw grids, from pull down menu select Window →Zoom out by 2In addition to pull down menu and bind key "z", "Zoom Out" is also listed in the picture tool bar to the left of the window. Find it and try it out.Also you may use up, down, left, and right arrows to move around the design window. You will need to use "Zoom in" and "Zoom out" and those arrows many times throughout your design process. So it's not a bad idea to practice them a little bit now.To save and close the cell view, from Virtuoso Editing window, Select Design →Save.。

设计规范指引（Design specification guidelines）DOC documents may experience poor browsing on the WAP side. It is recommended that you first select TXT, or download the source file to the local view.Design specification guidelinesParty A should submit the list at the start of the project, Party A shall provide to Party B at least the following information: 1, party a must design a landscape design plan (including Party A of the landscape design, planning and positioning, surrounding the project of building, etc.) 2 general layout planning CAD (intention to understand the original architecture planning, 3) the first floor of building CAD 4, planning for the elevation of CAD 5, CAD 6, the elevation of the base of the status of integrated network in Figure 7, the underground garage (including load requirements), overhead layer and Roof Garden (if Party B and Design) CAD 8, CAD single building, single building renderings, 9 fire exits. 10, other climbing surface data by Party B a written request (such as local tree species information price, base of existing plant name / specifications and location | base soil pH and soil aggregate structure The above information must be final design information, and Party A shall be responsible for the accuracy of the data. Party A shall promptly notify Party B in writing if any change occurs. First, the design phase (as the project and delete content) version with unified standard symbols, the following is not to say: name (size 12, Microsoft black font (size 12) map, CTXIKAISJ map in font) text (font size 8, CTHEITISF) the design specifications (size 8, font CTHEITISF) index box (red, 5PX) index points (red, 5PX) cable wire (black1PX), resolution 150 section symbols, facade vertical symbols, symbols, compass, scale, see the company unified legend (specific location). 2.1, the idea stage contains content 0, concept design notes, 1 landscape status analysis of resourcesOne2 traffic flow analysis figure3 landscape concept development sketches4 color plane5 main scenes perspectiverendering6 plant analysis and intention picture (plant functional zoning and descriptive text, reference pictures)7 facilities choice picture 2.2 main content contains 001 elements of landscape drawing resources analysis: content: the main figure for the base of the status map or plan index surrounding the scene pictures, major landmarks or Photo resources, site reservation or use value of the elements of the picture and so on, the expression of related characters corresponding to the position of the general situation. (advantages and disadvantages) present situation and location description, resource elements explanation, landscape design analysis text. Specifications: size (size8 font, CTHEITISF) index points (red, 5PX) cable wire (black 1PX) 002 landscape space analysis includes the secondary entrance, the main node space, the main green space, commercial street, tour, water, space club, main axis, axis series as far as possible the use of the contents of each node space, for the expression of different colors. Spatial analysis of text specification: size (size 8 font, CTHEITISF) legend color and the general layout of color match, size 003 line traffic flow analysis: using different colors to distinguish motors streamline classification, single lane two-way arrow indicates the nature, expression library location with color, groundparking, parking site. Main view axis, pedestrian streamline or model area visit route recommended. Pedestrian flow line, including the residential area within the line of people, the outer line of people flow. Description of road planning and design. Specifications: font size (font size 8, font CTHEITISF), legend color blocks and the general layout of the color matching, the size of the matchTwo004 landscape view of content: the landscape axis of sight, deputy landscape axis line of sight, the main site of sight, regional focus, analysis of each building two terminal and central line of sight, sight and pay attention to the design space and the external environment relations view. According to the above analysis, make the building number, landscape resource enjoyment degree table, line of sight analysis, text description. Specifications: the font size (font size 8, font CTHEITISF) legend is in accordance with the symbols in the general layout,Proportional to size. The 005 ideal function of graphic content: residential clubs, sports, leisure, children, the elderly, and other public gatherings of residential areas to express with different colors. In order to describe the reasonable layout of residential function. Residential area, ideal function, subsection, text analysis, explanation. Specifications: font size (font size 8, font CTHEITISF), legend and the general map of the symbols in line with the size of the match. The content of green space planning 006: Delta Center Green, green space, isolated green belt, green municipal greening with differentcharacteristics by different shades of green color to express, to level and function of green space planning. Green land planning text description. Specifications: font size (font size 8, font CTHEITISF), legend and the general map of the symbols in line with the size of the match. Note: all analysis should have text 007-1 landscape sketch plane: sketch, text, concise expression of ideas, the proportion of the total plane compass, 007-2 color: color plane, the main node naming and labeling, including the node space, simulation and planning, creative proportion, compass, caption: 007-3 concept to describe the whole idea of the text. 008 important scene amplification plane plan several (depending on circumstances): enlarge plane, correspond to reference picture (reference map should have its reference and pertinence), text description, index it in the general plan position. 009, the main scene perspective drawing renderings (depending on the situation): renderings, time permitting, you can add aerial view. Index its position in the general plan. 010, the number of elevation drawings of the important areas (as appropriate): elevation drawings, text notes, index in the general layout of the sectionThreeBroken position. 011 plant design intention picture 012 picture 013 lighting facilities intention intention picture two, design 3.1 stage design stage includes 0 design illustration analysis and intention function elevation profile 11 plants 1 Figure 2 Analysis of the current landscape resources landscape spatial analysis function of traffic flow figure 3 Figure 4 Analysis of landscape resources in view of the 5 landscape the idea of development of landscape color sketch 6 plane 7landscape vertical elevation map 8 important scenes and plans to enlarge the picture 9 main intention scene perspectiverendering 10 important areas (plant functional zoning and text description, reference picture) 12 lighting and lighting analysis intention picture 13 picture 14 intention facilities cost estimate three, preliminary design the stage version with unified standard symbols, the following is not to say: (name font size 12, Microsoft big black) That figure number (size 12, font CTXIKAISJ), map in the text (font size 8, CTHEITISF), design (size 8 font, CTHEITISF), the index box (red, 5PX), the index point (red 5PX), cable wire (black 1PX) split off the facade of symbols, symbols, the vertical scale, symbol, compass, see the company unified legend. One purpose: preliminary landscape design is mainly based on the design scheme and the idea concept of project design results, carried out detailed design of each landscape element in environmental planning, design and preliminary results provide specific project landscape for the owners, but also for the next phase of expansion construction drawing depthFourProvide basis for chemical design. Two, design content: A part: Landscape Design Outline 1, drawings cover 2 drawings directory B part: landscape design general plan (need based on CAD line diagram),To ensure the accuracy of scales) 1 landscape master plan (CAD) 2 (CAD) 3 general landscape orientation vertical landscape design plan (CAD) 4 of the total plane partition index map (CAD) 5 (with the general layout of landscape lighting lamp selection)6 for irrigation and drainage design drawings, Figure7 green seedlings table8 outdoor sketch layout9 material table, material pictures and briefly explain the 10 landscape project preliminary estimate part C: Standard node detailing (optional use of high frequency in the road project), pavement style, revetment, tree pool, stairs, walls, Wheelchair Access, railings, the bottom of the pool, drainage ditch part D: landscape 1. A detailed design plans to enlarge the proportion of 1:200 (A2) (including paving and indexing style) (anti cable plan) 2, a district landscape design map (CAD), 3 A vertical landscape design diagram (CAD) 4, the main attractions or landscape axis or cross section diagram facade (anti cable plane partition map) 5, a partition part part A: detail of plane partition (scene view) plane and sketch detail from the following aspects: the expression plane content, explain its relationship with the surrounding. The length and width of the vertical scale annotation, expression of paving materials. Elevation (vertical plan): vertical elevation, length, width, dimension, surface material, specification, color, process. (as the index profile details): vertical elevation, length and width and height dimensions, veneer material specifications color process. (as to index details) details: the size of the details, practice process, material expression.FiveLandscape sketch refinement, it is recommended to cross the garden sketch reference picture, in detail to do auxiliary explanation. Part B: general landscape design (to CAD line graph, to ensure the accuracy of scales), 1 landscape plan content: detailed expression of general layout scheme (CAD withhand-painted color plane) symbol: landscape description, design specifications, compass, scale. 2, hard landscape layout positioning (CAD export): general positioning is the main measure of landscape scale, only some of the main landscape mark size, such as the square of the length and the width of the lane width and turning radius, length and width of the private garden etc.. 3, vertical landscape design layout (CAD derived) content: the vertical design is mainly based on the design institute to provide the building and outdoor design elevation, combined with the landscape plan required the main control point (elevation elevation as little as possible changes to the original set of Design Institute) and the adjacent part of the elevation (mainly refers to the central line of the road and cross point the center of the square, and the edge pieces of the elevation control points, the main site of elevation, water bottom elevation, slope contour elevation, indicating the steps and series). Note: 3 and 4 can be combined into one drawing. 4. landscape lighting layout layout (general lighting) content: mainly lane and characteristics of landscape lighting layout, landscape lighting layout in detail can be arranged on the partition of landscape lighting, lamps have garden lights, lawn lamp, floodlight lamp, underwater lamp, underground lamp, lamp base, according to the design need to choose. The layout plan shall provide corresponding lamp intent pictures. Illumination symbol see company unified legend. 5, water supply and drainage irrigation layout design content: mainly according to vertical design and plant configuration requirements, layout rainwater inlet, quick water intake device and waterscape to water mouth. Water supply point, drainage direction, etc.. See the company's unified legend for water supply and drainage. 6, green design, seedling table.Content: green design concept is mainly a combination of landscape design requirements need, there is a close up effect, determine the spatial relations, the overall relationship between primary and secondary and greening design of the overall style, according to different design style and landscape clear trees and important ornamental tree species selection and location. Symbols: green design notes, plant pictures. 7, outdoor sketch layout content: mainly for outdoor background speakers, finished stools, garbage cans, signs and other supporting facilities and layout of the choice.Facilities legend can use the company's unified standard (pending) 8, the total plane pavement index (CAD fill, distinguish between different pavement)SixContent: the general layout of the road, site pavement, with different filling legend to distinguish materials, at a glance. Part C: standard joint detailing is mainly considering the unity of the landscape design, to avoid duplication, for some standard node or sketch such as steps, curb and Hua Shuchi, road pavement design, parking pavement is unified, clear. D: landscape design details 0 landscape general floor zoning map or landscape index content: mainly to express the general layout of the functional groups of the sub district or landscape index. Symbol: general layout, index, index, index box, text, compass, scale. 1, enlarge a floor plan content: the main expression of the specific design of the partition, such as plane layout, pavement design and materials, landscape ornaments, settings and details, index, etc.. Symbol: planepartition, indexing, indexing, text, index frame, compass, scale. 2. A landscape design map (CAD export) expression of the hard site size more than the general landscape orientation, size Pool Pond tree detailed annotation. 3, a vertical landscape design vertical (CAD export), the vertical design of the original landscape of the overall icon, a step further refinement. The site, flower beds, tree pool elevation, water bottom elevation, building elevation 4, a partition of landscape lighting distribution map is the main details of the landscape lighting layout. 5, the main attractions or landscape axis, elevation or cutaway section content: mainly to express some of the main attractions or landscape axis of the spatial hierarchy, large space effect. Mark symbol: major element content on the facade or profile, details see drawing. Mark its cut position. 6, a detail part of the plane partition partition (scene view) plane and sketch detail from the following aspects: the expression plane content, explain its relationship with the surrounding, the length and width dimension, the expression of paving materials. Elevation: vertical elevation, length, width, dimension, surface material, specification, color, process. Profile: vertical elevation, length, width, dimension, surface material, specification, color, process. Details: the size of the details, practice process, material expression. Landscape sketch refinement, it is recommended to cross the garden sketch reference picture, in detail to do auxiliary explanation.SevenOne。

高速电路设计与pcb绘制书籍When it comes to high-speed circuit design and PCB layout, there are several books available that can provide valuable insights and guidance. One such book is "High-Speed Digital Design: A Handbook of Black Magic" by Howard W. Johnson and Martin Graham. This book is widely regarded as a comprehensive resource for understanding theprinciples and techniques of high-speed digital design.The book covers a wide range of topics, including transmission line theory, signal integrity, power distribution, grounding, and EMI/EMC considerations. It delves into the intricacies of designing high-speedcircuits and provides practical tips and techniques to ensure signal integrity and minimize noise and interference. The authors explain complex concepts in a clear and concise manner, making it accessible to both beginners and experienced designers.Another recommended book is "Signal Integrity Issuesand Printed Circuit Board Design" by Douglas Brooks. This book focuses specifically on signal integrity issues that arise during PCB design. It explores topics such as transmission line effects, impedance matching, crosstalk, and termination techniques. The author provides practical guidelines and design rules to ensure reliable signal transmission and minimize signal degradation."High-Speed PCB Design: Layout and Routing Guidelines" by Lee W. Ritchey and John Zasio is another valuable resource for PCB design. This book emphasizes theimportance of proper layout and routing techniques in achieving high-speed performance. It covers topics such as layer stackup, component placement, trace routing, andpower distribution. The authors provide practical examples and case studies to illustrate the impact of various design choices on signal integrity.In addition to these books, "Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers" by Mark I. Montrose is highly recommended for designers concerned with electromagnetic compatibility (EMC)issues. This book explores various EMC design considerations, including grounding, shielding, andfiltering techniques. It provides practical guidelines to ensure that PCB designs meet EMC compliance requirements.Furthermore, "Advanced Signal Integrity for High-Speed Digital Designs" by Stephen H. Hall and Howard L. Heck is a comprehensive guide that addresses advanced topics in signal integrity. It covers advanced transmission line theory, equalization techniques, and noise analysis. The book also discusses the impact of advanced technologies, such as high-speed serial interfaces and multi-gigabit transceivers, on PCB design.Overall, these books offer a wealth of knowledge and practical guidance for high-speed circuit design and PCB layout. They cover a wide range of topics, from basic concepts to advanced techniques, and provide valuable insights from multiple perspectives. Whether you are a beginner or an experienced designer, these books can serve as essential references to enhance your understanding and skills in high-speed circuit design and PCB layout.。