CTA41CS5中文资料

请一定要采取安全措施以防止它们之间物理损伤一个故障情况下所造成火灾可能性和伤害或损害瑞萨电子产品如安全设计硬件和软件包括但不限于冗余度防火和防故障老化退化或其他任何适当措施适当治疗
芯片中文手册,看全文,戳
为我们客户,
旧公司名称产品目录等资料
接手两者所有业务
因此,尽管旧公司名称防护留这个文件中,它是一个有效 电子文档.我们感谢您理解.
3. 7.5厘米 × 0.7毫米,陶瓷电路板装
封装图（单位： mm）
6.5 ±0.2 5.0 ±0.2 1.5
4
2.3 ±0.2 0.5 ±0.1
1.6 ±0.2 1
2
3
5.5 ±0.2
1.1 ±0.2
13.7最小. 7.0最低
0.5
0.5
2.3 2.3
0.75
TO-251 (MP-3)
6.5 ±0.2 5.0 ±0.2 4.4 ±0.2
8. 你应该使用由瑞萨电子所指定范围内本文档中描述瑞萨电子产品,特别是相对于所述最大额定值,操作电源电压范围,移 动电源电压范围,热辐射特性,安装和其它产品特性.瑞萨电子有权对因使用瑞萨电子产品除这些特定范围故障或损坏 不承担任何责任.
9. 本公司一直致力于提高产品质量和可靠性,半导体产品有 具体特点,如故障以一定速率和故障某些使用条件下发生.进一步, 瑞萨电子产品不受辐射性设计.请一定要采取安全措施,以
芯片中文手册,看全文,戳
注意
1. 本文档中所有信息为发出这份文件日期.这样信息,但是,如有更改恕不另行通知.购买或使用本文中列出任何瑞萨电 子产品前,请确认与瑞萨电子营业部最新产品信息.另外,请大家定期和仔细额外和不同信息由瑞萨电子披露,例如,通 过我们网站披露.

ACTERISTICS
Parameter *
(Continued) Symbol Min Typ Max Units
Analog Output Characteristics - Minimum Attenuation; Unless Otherwise Specified.
44-pin PLCC 100-pin TQFP
CMOUT LINL LINR MINL MINR SDIN CLKIN CLKOUT XTL1IN XTL1OUT XTL2IN XTL2OUT PIO0 PIO1 D/C RESET PDN VA1 VA2 VD1 VD2 AGND1 AGND2 DGND1 DGND2 Control Interface and Registers Clock Generator 8 unsigned µ -law A-law decode + D/A Monitor Attenuator + Voltage Reference Serial Input/Output M U X Gain A/D A/D unsigned µ -law A-law encode TSIN TSOUT VREF MOUT1 MOUT2 D/A Output Attenuator Mute LOUTR LOUTL HEADC HEADR HEADL SDOUT SCLK FSYNC
DAC Resolution DAC Differential Nonlinearity Total Dynamic Range Instantaneous Dynamic Range (OLB = 1) Total Harmonic Distortion (OLB = 1) Interchannel Isolation Interchannel Gain Mismatch Frequency Response (Note 1) Programmable Attenuation Attenuation Step Size Absolute Attenuation Step Error Offset Voltage Line Out (All Outputs) TDR IDR THD 16 80 -0.5 0.2 2.55 3.6 7.3 1.8 1.8 3.6 (22 kHz to 100 kHz) Line Out 95 85 80 40 1.5 10 2.8 4.0 8.0 2.0 2.0 4.0 100 -60 ±0.9 0.025 0.2 0.32 0.5 0.5 +0.2 -94.7 0.75 3.08 4.4 8.8 2.2 2.2 4.4 1 Bits LSB dB dB % % % dB dB dB dB dB dB dB dB mV Vpp Vpp Vpp Vpp Vpp Vpp ppm/°C Degree dB

CS1256芯片用户手册带24bits ADC和BIM的高性能REV 1.2版本历史目录版本历史 (2)目录 (3)图清单 (5)表清单 (6)1简介 (7)主要特性 (7)应用场合 (7)功能说明 (8)极限值 (8)电气特性 (9)可靠性指标 (10)产品型号及引脚 (10)典型应用电路 (11)2功能寄存器说明 (12)功能寄存器列表 (12)功能寄存器说明 (12)2.2.1SYS—系统配置寄存器(地址00H) (12)2.2.2ADC0— ADC配置寄存器(地址01H) (13)2.2.3ADC1— ADC配置寄存器1(地址02H) (13)2.2.4ADC3— ADC配置寄存器3(地址04H) (14)2.2.5ADC4— ADC配置寄存器4(地址05H) (14)2.2.6ADC5— ADC配置寄存器5(地址06H) (15)2.2.7BIM0— BIM配置寄存器0(地址07H) (15)2.2.8BIM1— BIM配置寄存器(地址08H) (16)2.2.9ADO— ADC转换数据寄存器(地址09H) (16)2.2.10ADS— ADC转换数据读取标准寄存器(地址0AH) (16)3功能描述 (17)输入选择 (17)PGA和ADC (17)数字滤波器 (18)3.3.1频率响应 (18)3.3.2建立时间 (18)人体阻抗测量 (19)3.4.1正弦信号发生器 (20)3.4.2激励电极及测量电极 (21)3.4.3整流 (21)3.4.4阻抗校准 (21)参考电压源 (22)内部时钟源 (22)测量模式及其切换 (22)多种工作模式 (22)复位和掉电 (23)4转换有效位 (24)5典型特性 (25)LDO典型特性 (25)内部时钟典型特性 (25)BIM典型特性 (26)6三线串行通讯接口 (28)读时序 (28)写时序 (29)7封装 (31)8包装材料信息 (32)9产品丝印图说明 (33)图清单图 1-1 CS1256原理框图 (8)图 1-2 CS1256引脚图 (10)图 1-3 CS1256典型应用电路 (11)图 3-1模拟输入结构图 (17)图 3-2 PGA和ADC结构图 (17)图 3-3 COMB滤波器的频率响应特性(Fs=331Hz，DR=10Hz，3阶COMB） (18)图 3-4 COMB建立过程 (19)图 3-5 BIM模块结构图 (20)图 3-6 CS1256低功耗工作示意图 (23)图 5-1 LDO全电压全温度范围的典型特性(LDOS[1:0]=00，负载1mA) (25)图 5-2内部时钟全电压全温度范围的典型特性 (25)图 5-3 FWR模式下220欧姆纯电阻网络的测试结果 (26)图 5-4 FWR模式下510欧姆纯电阻网络的测试结果 (26)图 5-5 FWR模式下1958欧姆纯电阻网络的测试结果 (27)图 6-1读操作时序1(读AD值) (29)图 6-2读操作时序2(除AD值之外的寄存器) (29)图 6-3写操作时序 (29)图 7-1 芯片封装尺寸信息 (31)图 8-1 SOP16料管尺寸 (32)图 9-1 产品丝印图 (33)表清单表 1-1 CS1256 极限值 (8)表 1-2 CS1256电气特性 (9)表 1-3 CS1256引脚说明 (11)表 2-1功能寄存器列表 (12)表 2-2 SYS寄存器说明 (12)表 2-3 ADC0寄存器说明 (13)表 2-4 ADC1寄存器说明 (13)表 2-5 ADC3寄存器说明 (14)表 2-6 ADC4寄存器说明 (14)表 2-7 ADC5寄存器说明 (15)表 2-8 BIM0寄存器说明 (15)表 2-9 BIM1寄存器说明 (16)表 2-10 ADO寄存器说明 (16)表 2-11 ADO寄存器说明 (16)表 4-1 ADC信号链不同配置下的有效位(ENOB) (24)表 6-1串口通讯命令列表 (28)表 6-2 三线串行通讯接口时序表 (30)1简介主要特性✧BIM•支持4电极测量•支持5K/10K/25K/50K/100K/250KHz多档频率测量•支持阻抗绝对值和相角测量✧ADC•24-bit分辨率•输出速率10~1280Hz 8档可选✧ADC有效位• 2.35V参考、40Hz速率、128倍增益下19.5bits有效位✧LDO及内部参考电压•自带LDO，输出2.35/2.45/2.8/3.0V可选✧支持高性能、普通、低功耗、休眠模式✧支持电压测量、BIM测量及手动测量模式，可通过单命令切换✧低漂移片上时钟✧三线串行通讯应用场合✧人体阻抗分析✧交流测脂功能说明CS1256原理框图如图1-1所示。

Table 24: Truth Table – CKENotes: 1.Current state is defined as the state of the DDR4 SDRAM immediately prior to clockedge n.2.CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at theprevious clock edge.MAND (n) is the command registered at clock edge n, and ACTION (n) is a result ofCOMMAND (n); ODT is not included here.4.All states and sequences not shown are illegal or reserved unless explicitly describedelsewhere in this document.5.The state of ODT does not affect the states described in this table. The ODT function isnot available during self refresh.6.During any CKE transition (registration of CKE H->L or CKE H->L), the CKE level must bemaintained until 1 nCK prior to t CKE (MIN) being satisfied (at which time CKE may tran-sition again).7.DESELECT and NOP are defined in the Truth Table – Command table.8.For power-down entry and exit parameters, see the Power-Down Modes section.9.CKE LOW is allowed only if t MRD and t MOD are satisfied.10.The power-down mode does not perform any REFRESH operations.11.X = "Don’t Care" (including floating around V REF ) in self refresh and power-down. X al-so applies to address pins.12.The DESELECT command is the only valid command for power-down entry and exit.13.V PP and V REFCA must be maintained during SELF REFRESH operation.14.On self refresh exit, the DESELECT command must be issued on every clock edge occur-ring during the t XS period. READ or ODT commands may be issued only after t XSDLL issatisfied.15.The DESELECT command is the only valid command for self refresh exit.16.Self refresh cannot be entered during READ or WRITE operations. For a detailed list ofrestrictions see the SELF REFRESH Operation and Power-Down Modes sections.17.If all banks are closed at the conclusion of the READ, WRITE, or PRECHARGE command,then precharge power-down is entered; otherwise, active power-down is entered.8Gb: x4, x8, x16 DDR4 SDRAM Truth TablesFigure 135: Nonconsecutive READ (BL8) with 1t CK Preamble in Same or Different Bank GroupT0T16T1T2T3T4T5T10T11T12T13T14T15Command DQ CK_t CK_cDQS_t,DQS_cT21T17T18T19T20Bank GroupAddress Address Notes: 1.BL8, AL = 0, CL = 11, Preamble = 1t CK, t CCD_S/L = 5.2.DO n (or b ) = data-out from column n (or column b ).3.DES commands are shown for ease of illustration; other commands may be valid atthese times.4.BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READcommands at T0 and T5.5.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.Figure 136: Nonconsecutive READ (BL8) with 2tCK Preamble in Same or Different Bank GroupCommand DQ CK_t CK_cDQS_t,DQS_cBank GroupAddress Address Notes: 1.BL8, AL = 0, CL = 11, Preamble = 2t CK, t CCD_S/L = 6.2.DO n (or b ) = data-out from column n (or column b ).3.DES commands are shown for ease of illustration; other commands may be valid atthese times.4.BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 duringREAD commands at T0 and T6.5.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.6. 6 t CCD_S/L = 5 isn’t allowed in 2t CK preamble mode.8Gb: x4, x8, x16 DDR4 SDRAM READ Operation。