MC74ACT04D中文资料

MC74LCX04Low-Voltage CMOS Hex InverterWith 5 V−Tolerant InputsThe MC74LCX04 is a high performance hex inverter operating from a 2.0 to 5.5 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A V I specification of 5.5 V allows MC74LCX04 inputs to be safely driven from 5 V devices if V CC is less than 5.0 V.Current drive capability is 24 mA at the outputs.Features•Designed for 2.0 V to 5.5 V V CC Operation•5 V Tolerant Inputs − Interface Capability With 5 V TTL Logic •LVTTL Compatible•LVCMOS Compatible•24 mA Balanced Output Sink and Source Capability•Near Zero Static Supply Current (10 m A) Substantially Reduces System Power Requirements•Latchup Performance Exceeds 500 mA•ESD Performance:Human Body Model >2000 V;Machine Model >200 V•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS CompliantA=Assembly LocationWL, L=Wafer LotYY, Y=YearWW, W=Work WeekG or G= Pb−Free PackageTSSOP−14DT SUFFIXCASE 948G141SOIC−14D SUFFIXCASE 751A1LCX04ALYW GGMARKINGDIAGRAMSSee detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.ORDERING INFORMATION141(Note: Microdot may be in either location)Figure 1. Pinout: 14−Lead (Top View)1314121110982134567V CC A3O3A4O4A5O5A0O0A1O1A2O2GNDO0A0O1A1O2A2O3A3O4A4O5A5Figure 2. Logic DiagramMAXIMUM RATINGSSymbol ParameterValue ConditionUnit V CC DC Supply Voltage −0.5 to +7.0V V I DC Input Voltage −0.5 ≤ V I ≤ +7.0V V O DC Output Voltage −0.5 ≤ V O ≤ V CC +0.5Output in HIGH or LOW State (Note 1)V I IK DC Input Diode Current −50V I < GND mA I OK DC Output Diode Current−50V O < GND mA +50V O > V CCmA I O DC Output Source/Sink Current ±50mA I CC DC Supply Current Per Supply Pin ±100mA I GND DC Ground Current Per Ground Pin ±100mA T STG Storage Temperature Range −65 to +150°CMSLMoisture SensitivityLevel 1Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.1.I O absolute maximum rating must be observed.RECOMMENDED OPERATING CONDITIONSSymbol Parameter Min Typ Max UnitV CC Supply Voltage OperatingData Retention Only 2.01.52.5,3.32.5,3.35.55.5VV I Input Voltage0 5.5V V O Output Voltage(HIGH or LOW State) (3−State)0V CC VI OH HIGH Level Output Current V CC = 3.0 V − 3.6 VV CC = 2.7 V − 3.0 VV CC = 2.3 V − 2.7 V −24−12−8mAI OL LOW Level Output Current V CC = 3.0 V − 3.6 VV CC = 2.7 V − 3.0 VV CC = 2.3 V − 2.7 V +24+12+8mAT A Operating Free−Air Temperature−55+125°C D t/D V Input Transition Rise or Fall Rate, V IN from 0.8 V to 2.0 V, V CC = 3.0 V010ns/VDC ELECTRICAL CHARACTERISTICST A = −55°C to +125°C Symbol Characteristic Condition Min Max Unit V IH HIGH Level Input Voltage (Note 2) 2.3 V ≤ V CC≤ 2.7 V 1.7V2.7 V ≤ V CC≤3.6 V 2.0V IL LOW Level Input Voltage (Note 2) 2.3 V ≤ V CC≤ 2.7 V0.7V2.7 V ≤ V CC≤3.6 V0.8V OH HIGH Level Output Voltage 2.3 V ≤ V CC≤ 3.6 V; I OH = −100 m A V CC− 0.2VV CC = 2.3 V; I OH = −8 mA 1.8V CC = 2.7 V; I OH = −12 mA 2.2V CC = 3.0 V; I OH = −18 mA 2.4V CC = 3.0 V; I OH = −24 mA 2.2V OL LOW Level Output Voltage 2.3 V ≤ V CC≤ 3.6 V; I OL = 100 m A0.2VV CC = 2.3 V; I OL= 8 mA0.6V CC = 2.7 V; I OL= 12 mA0.4V CC = 3.0 V; I OL = 16 mA0.4V CC = 3.0 V; I OL = 24 mA0.55I OFF Power Off Leakage Current V CC = 0, V IN = 3.6 V or V OUT = 3.6 V10m A I IN Input Leakage Current V CC = 0 to 3.6 V, V IN = 3.6 V or GND±5m A I CC Quiescent Supply Current V CC = 3.6 V, V IN = 3.6 V or V OUT = 3.6 V10m AD I CC Increase in I CC per Input 2.3 ≤ V CC≤ 3.6 V; V IH = V CC− 0.6 V500m A2.These values of V I are used to test DC electrical characteristics only.AC CHARACTERISTICS t R = t F = 2.5 ns; R L = 500 WLimitsT A = −55°C to +125°CV CC = 3.3 V ± 0.3 V V CC = 2.7 V V CC = 2.5 V ± 0.2 VC L = 50 pF C L = 50 pF C L = 30 pFSymbol Parameter Waveform Min Max Min Max Min Max Unitt PLH Propagation Delay Time1 1.5 5.2 1.5 6.0 1.5 6.2nst PHL Input to Output 1.5 5.2 1.5 6.0 1.5 6.2t OSHL Output−to−Output Skew 1.0nst OSLH(Note 3) 1.03.Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t OSHL) or LOW−to−HIGH (t OSLH); parameter guaranteed by design.DYNAMIC SWITCHING CHARACTERISTICST A = +25°CSymbol Characteristic Condition Min Typ Max UnitV OLP Dynamic LOW Peak Voltage V CC = 3.3 V, C L = 50 pF, V IH = 3.3 V, V IL = 0 V0.8V (Note 4)V CC = 2.5 V, C L = 30 pF, V IH = 2.5 V, V IL = 0 V0.6VV OLV Dynamic LOW Valley Voltage V CC = 3.3 V, C L = 50 pF, V IH = 3.3 V, V IL = 0 V−0.8V (Note 4)V CC = 2.5 V, C L = 30 pF, V IH = 2.5 V, V IL = 0 V−0.6V4.Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output ismeasured in the LOW state.CAPACITIVE CHARACTERISTICSSymbol Parameter Condition Typical UnitC IN Input Capacitance V CC = 3.3 V, V I = 0 V or V CC7pFC OUT Output Capacitance V CC = 3.3 V, V I = 0 V or V CC8pFC PD Power Dissipation Capacitance10 MHz, V CC = 3.3 V, V I = 0 V or V CC25pF ORDERING INFORMATIONDevice Package Shipping†MC74LCX04DG SOIC−1455 Units / Rail(Pb−Free)2500 Tape & ReelMC74LCX04DR2G SOIC−14(Pb−Free)MC74LCX04DTG TSSOP−1496 Units / Rail(Pb−Free)2500 Tape & ReelMC74LCX04DTR2G TSSOP−14(Pb−Free)†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.WAVEFORM 1 − PROPAGATION DELAYS t R = t F = 2.5 ns, 10% to 90%; f = 1 MHz; t W = 500 nsV CC0 VV OHV OLAnOnSymbol V CC3.3 V $ 0.3 V2.7 V 2.5 V $ 0.2 VVmi 1.5 V 1.5 V V CC /2Vmo1.5 V1.5 VV CC/2Figure 3. AC WaveformsV R LC L = 50 pF at V CC = 3.3 0.3 V or equivalent (includes jig and probe capacitance)C L = 30 pF at V CC = 2.5 0.2 V or equivalent (includes jig and probe capacitance)R L = R 1 = 500 W or equivalentR T = Z OUT of pulse generator (typically 50 W )Figure 4. Test CircuitD SUFFIX CASE 751A−03 ISSUE J1.DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5.DIMENSION D DOES NOT INCLUDEDAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.127(0.005) TOTAL IN EXCESS OF THE DDIMENSION AT MAXIMUM MATERIALCONDITION.SBM0.25 (0.010)A STSEATINGPLANEDIM MIN MAX MIN MAXINCHESMILLIMETERSA8.558.750.3370.344B 3.80 4.000.1500.157C 1.35 1.750.0540.068D0.350.490.0140.019F0.40 1.250.0160.049G 1.27 BSC0.050 BSCJ0.190.250.0080.009K0.100.250.0040.009M0 7 0 7P 5.80 6.200.2280.244R0.250.500.0100.019____DIMENSIONS: MILLIMETERSSOLDERING FOOTPRINTDT SUFFIX CASE 948G −01ISSUE BDIM MIN MAX MIN MAX INCHES MILLIMETERS A 4.90 5.100.1930.200B 4.30 4.500.1690.177C −−− 1.20−−−0.047D 0.050.150.0020.006F 0.500.750.0200.030G 0.65 BSC 0.026 BSC H 0.500.600.0200.024J 0.090.200.0040.008J10.090.160.0040.006K 0.190.300.0070.012K10.190.250.0070.010L 6.40 BSC 0.252 BSC M0 8 0 8 NOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.4.DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.5.DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.6.TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY .7.DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W −.____14X REF 14X0.360.65PITCHSOLDERING FOOTPRINTON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at /site/pdf/Patent −Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION。

Octal D FlipĆFlopThe MC74AC273/74ACT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip- flop’s Q output.All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.•Ideal Buffer for MOS Microprocessor or Memory •Eight Edge-Triggered D Flip-Flops •Buffered Common Clock•Buffered, Asynchronous Master Reset•See MC74AC377 for Clock Enable Version•See MC74AC373 for Transparent Latch Version •See MC74AC374 for 3-State Version •Outputs Source/Sink 24 mA•′ACT273 Has TTL Compatible Inputs192018171615142134567V CC 1381291110Q 7D 7D 6Q 6Q 5D 5D 4Q 4CP MRQ 0D 0D 1Q 1Q2D 2D 3Q 3GNDPIN NAMES D 0–D 7 Data Inputs MR Master Reset CP Clock Pulse Input Q 0–Q 7Data Outputsassociated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.。

DevicePackage Shipping MC74HC04AN PDIP–142000 / Box MC74HC04AD SOIC–1455 / Rail MC74HC04ADR2SOIC–142500 / Reel MARKING DIAGRAMSA = Assembly Location WL or L = Wafer Lot YY or Y = YearWW or W = Work WeekMC74HC04ADT TSSOP–1496 / Rail MC74HC04ADTR2TSSOP–142500 / ReelTSSOP–14DT SUFFIX CASE 948GHC 04A ALYW114114PDIP–14N SUFFIX CASE 646MC74HC04AN AWLYYWW SOIC–14D SUFFIX CASE 751A114HC04A AWLYWW L HFUNCTION TABLEInputsOutputsA H LYON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATIONCENTRAL/SOUTH AMERICA:Spanish Phone:303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)Email:ONlit–spanish@ASIA/PACIFIC: LDC for ON Semiconductor – Asia SupportPhone:303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)Toll Free from Hong Kong & Singapore:001–800–4422–3781Email: ONlit–asia@JAPAN: ON Semiconductor, Japan Customer Focus Center4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549Phone: 81–3–5740–2745Email: r14525@。