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EDA数字系统设计实验——8位二进制乘法电路学院：电子工程学院学号：0210****姓名：***8位二进制乘法电路1．选题目的：通过八位二进制乘法器设计实验，进一步熟悉VHDL语言的电路设计，及数字电路的基本知识，为以后进一步在数字电路学习上奠定基础。
2.设计要求8位二进制乘法采用移位相加的方法。
即用乘数的各位数码，从低位开始依次与被乘数相乘，每相乘一次得到的积称为部分积，将第一次（由乘数最低位与被乘数相乘）得到的部分积右移一位并与第二次得到的部分积相加，将加得的和右移一位再与第三次得到的部分积相加，再将相加的结果右移一位与第四次得到的部分积相加。
直到所有的部分积都被加过一次。
例如：被乘数（M7M6M5M4M3M2M1M0）和乘数（N7N6N5N4N3N2N1N0）分别为11010101和10010011,其计算过程如下：1 1 0 1 0 1 0 1× 1 0 0 1 0 0 1 11 1 0 1 0 1 0 1 N0与被乘数相乘的部分积，部分积右移一位1 1 0 1 0 1 0 1 N1与被乘数相乘的部分积+ 1 1 0 1 0 1 0 11 0 0 1 1 1 1 1 1 11 0 0 1 1 1 1 1 1 1 两个部分积之和，部分积之和右移一位+ 0 0 0 0 0 0 0 0 N2与被乘数相乘的部分积0 1 0 0 1 1 1 1 1 1 10 1 0 0 1 1 1 1 1 1 1 与前面部分积之和相加,部分积之和右移一+ 0 0 0 0 0 0 0 0 N4与被乘数相乘的部分积· · ·· · · N7与被乘数相乘的部分积+ 1 1 0 1 0 1 0 11 1 1 1 0 1 0 0 1 0 0 1 1 1 1 与前面部分积之和相加0 1 1 1 1 0 1 0 0 1 0 0 1 1 1 右移一位得到最后的积为了实现硬件乘法器，根据上面的乘法的计算过程可以得出3点：一是只对两个二进制数进行相加操作，并用寄存器不断累加部分积；而是将累加的部分积左移（复制的被乘数不移动）；三是乘数的对应位若为0时，对累加的部分积不产生影响（不操作）。
将8421BCD转换为余3码源代码：Library ieee;Use ieee.std_logic_1164.all;Entity bcd isPort(a:in std_logic_vector(3 downto 0);y:out std_logic_vector(3 downto 0));End;Architecture rtl of bcd isBeginProcess(a)BeginCase a isWhen"0000"=>y<="0011";When"0001"=>y<="0100";When"0010"=>y<="0101";When"0011"=>y<="0110";When"0100"=>y<="0111";When"0101"=>y<="1000";When"0110"=>y<="1001";When"0111"=>y<="1010";When"1000"=>y<="1011";When"1001"=>y<="1100";When others=>y<="ZZZZ";End case;End process;End;仿真图形：（仿真结果均有延时，大约20ns）四输入表决器源代码：Library ieee;Use ieee.std_logic_1164.all;Entity bjq isPort(i:in std_logic_vector(3 downto 0);f:out std_logic);End;Architecture nm2 of bjq isBeginProcess(i)Begincase i isWhen"0000"=>f<='0';When"0001"=>f<='0';When"0010"=>f<='0';When"0011"=>f<='0';When"0100"=>f<='0';When"0101"=>f<='0';When"0110"=>f<='0';When"0111"=>f<='1';When"1000"=>f<='0';When"1001"=>f<='0';When"1010"=>f<='0';When"1011"=>f<='1';When"1100"=>f<='0';When"1101"=>f<='1';When"1110"=>f<='1';When"1111"=>f<='1';When others=>f<='Z';End case;End process;End;仿真图形：2位二进制相乘电路源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity multi isport(A,B:in std_logic_vector(1 downto 0);F:out std_logic_vector(3 downto 0));end;architecture bhv of multi isbeginprocess(A,B)beginif(A="01" and B="01" )thenF<="0001";elsif(A="01" and B="10")thenF<="0010";elsif(A="01" and B="11")thenF<="0011";elsif(A="10" and B="01")thenF<="0010";elsif(A="10" and B="10")thenF<="0100";elsif(A="10" and B="11")thenF<="0110";elsif(A="11" and B="01")thenF<="0011";elsif(A="11" and B="10")thenF<="0110";elsif(A="11" and B="11")thenF<="1001";elseF<="0000";end if;end process;end;仿真图形：一位二进制全减器源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity subtracter isport(A,B,Ci:in std_logic;F,Co:out std_logic);end;architecture bhv of subtracter isbeginprocess(A,B,Ci)beginif(A='0' and B='0' and Ci='0')thenF<='0';Co<='0';elsif(A='0' and B='0' and Ci='1')thenF<='1';Co<='1';elsif(A='0' and B='1' and Ci='0')thenF<='1';Co<='1';elsif(A='0' and B='1' and Ci='1')thenF<='0';Co<='1';elsif(A='1' and B='0' and Ci='0')thenF<='1';Co<='0';elsif(A='1' and B='0' and Ci='1')thenF<='0';Co<='0';elsif(A='1' and B='1' and Ci='0')thenF<='0';Co<='0';elseF<='1';Co<='1';end if;end process;end;仿真图形：开关控制电路源代码：Library ieee;Use ieee.std_logic_1164.all;Entity switch_control isPort(a,b,c:in std_logic;y:out std_logic);End;Architecture nm5 of switch_control isBeginProcess(a,b,c);V ariable comb:std_logic_vector(2 downto 0);BeginComb:=a&b&c;Case comb isWhen"000"=>y<='0';When"001"=>y<='1';When"011"=>y<='0';When"010"=>y<='1';When"110"=>y<='0';When"111"=>y<='1';When"101"=>y<='0';When"100"=>y<='1';When others=>y<='X';End case;End process;End;仿真图形：。
基于VHDL的乘法器的设计与对比赵杰【摘要】Multiplier is the core of digital signal calculation. It is also the key component of data processing and microprocessor. 8-bits multiplier is taken as the example. The simple parallel multiplier, the shift summation multiplier and the addition tree multiplier were introduced. They were described using VHDL. The three kinds of multipliers are simulated respectively through the Quartus II platform. Their simulation results were given. At the end of paper, the three multipliers were compared and discussed in the resource occupancy and operation speed.%在数字系统中，乘法器是进行数字信号运算的核心运算单元，同时也是微处理器中进行数据处理的关键部分。
以8位乘法器为例，根据简单并行乘法器、加法器树乘法器和移位相加乘法器的基本原理，利用VHDL分别进行描述和实现。
对三种乘法器分别通过QuartusⅡ软件平台进行仿真，再做进一步比较和讨论。
结果表明，三种乘法器在运行速度和资源占用上各有利弊，实践中可根据设计要求和硬件条件选择使用。
【期刊名称】《商洛学院学报》【年(卷),期】2015(000)006【总页数】4页(P3-6)【关键词】乘法器;移位相加;加法器树;仿真【作者】赵杰【作者单位】商洛学院电子信息与电气工程学院，陕西商洛 726000【正文语种】中文【中图分类】TP332.22乘法器在数字信号处理过程中发挥着重要的作用，在语音、图像处理、通信等领域中扮演着举足轻重的角色，它的运算速度与信号处理和整体效率的性能直接相关，并且在很大程度上左右着系统功能[1-3]。
利用VHDL設計乘法器Implement of Multiplier by Using VHDL許地申Dih-Shen Hsu中華技術學院電機系副教授Associate ProfessorDepartment of Electrical EngineeringChina Institute of Technology摘 要在計算機結構裡加，減，乘，除是常被用到的運算，本文提出以非常高速積體電路硬體描述語言(VHDL)來描述硬體，說明如何將兩個運算元作相乘的運算。
我們首先以無號數整數做乘法運算來說明其原理，設計其電路結構。
其實在VHDL 程式中，我們更可以載入STD_LOGIC_ARITH與STD_LOGIC_UNSIGNED元件盒之後，直接進行乘法運算，既簡單又容易擴充。
最後，我們將以4-bit X 4-bit 的例子來做電路描述、電路合成、電路模擬並以七段顯示器將其結果顯示出來。
關鍵字：非常高速積體電路硬體描述語言、電路描述、電路合成、電路模擬AbstractWe have known operation that perform addition, subtraction, multiplication, and division. In this paper we are presented primarily to describe hardware using by VHDL. We can explain how multiplication may be performed for two operand. Multiplication of unsigned numbers illustrates the main issues involved in the design of multiplier circuit. In fact, after the STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED packages were added to the VHDL program, it became not only simple but also easy to extended. Next, consider a 4 x 4 example to circuit description, circuit synthesis, and circuit simulation by using VHDL. Finally, this approach can also be displayed by 7-segment.Keyword : VHDL , circuit description , circuit synthesis, circuit simulation壹.簡介VHDL是Very High Speed Integrated Circuit Hardware Description Language 的英文縮寫。
一、介绍Verilog HDL（硬件描述语言）是一种用于建模电子系统的硬件描述语言，常用于数字电路设计和验证。
在Verilog HDL中，实现两位乘法器是一个常见的需求，本文将介绍如何使用Verilog HDL设计和实现一个两位乘法器。
二、两位乘法器的原理两位乘法器是用于计算两个二进制数的乘积的电路。
对于两个n位的二进制数A和B，它们的乘积可以使用shift-and-add算法来计算。
具体来说，可以将A拆分为A[0]和A[1]，B拆分为B[0]和B[1]，然后计算A[0]*B[0]、A[0]*B[1]、A[1]*B[0]和A[1]*B[1]，最后将它们的和相加即可得到A*B的结果。
三、Verilog HDL的实现使用Verilog HDL可以轻松地实现两位乘法器。
以下是一个简单的Verilog HDL代码实现：```verilogmodule two_bit_multiplier(input [1:0] A, // 两位输入input [1:0] B,output [3:0] result // 四位输出);reg [3:0] temp; // 临时变量用于保存计算的结果always (A or B) begintemp[0] = A[0] B[0]; // 计算A[0]*B[0]temp[1] = A[0] B[1]; // 计算A[0]*B[1]temp[2] = A[1] B[0]; // 计算A[1]*B[0]temp[3] = A[1] B[1]; // 计算A[1]*B[1]result = {temp[3],temp[2]+temp[1],temp[0]}; // 将计算结果相加并输出endendmodule```上述Verilog HDL代码描述了一个两位乘法器模块。
模块有两个2位输入A和B，以及一个4位输出result。
通过使用always块来计算A 和B的乘积，并将结果存储在temp变量中；将temp中的值相加并输出到result中。
9*9乘法器的VHDL的设计1 设计任务制作一个9*9乘法器2 设计说明输入两个四位二进制信号a，b分别作为被乘数和乘数，以8421bcd码编号，输入一个一位信号oc作为控制信号；输出两个四位二进制信号c，d分别作为结果的十位和个位，以8421bcd码编号。
3 设计结果3.1 原理图图1 原理图3.2 信号表a：被乘数，用4位二进制8421bcd码表示；b：乘数，用4位二进制8421bcd码表示；oc：控制信号；c：结果的十位，用4位二进制8421bcd码表示；d：结果的个位，用4位二进制8421bcd码表示；图2 信号表3.3仿真结果图3 oc、a、b分别为0、2、8和0、4、3时结果图4 oc、a、b分别为1、2、8和1、4、3时结果图5 oc、a、b分别为0、10、8和0、4、11时结果3.4 电路图图6 原理图3.5 程序清单LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY mul9 ISPORT (oc: IN std_logic;a,b: IN std_logic_vector (3 downto 0);c,d: OUT std_logic_vector(3 downto 0));END;ARCHITECTURE one OF mul9 ISBEGINPROCESS(a,b)BEGINIF(oc = '1') THENIF(a = "0001") THENCASE b ISWHEN "0001" =>c <= "0000"; d <= "0001"; WHEN "0010" =>c <= "0000"; d <= "0010";WHEN "0011" =>c <= "0000"; d <= "0011"; WHEN "0100" =>c <= "0000"; d <= "0100";WHEN "0101" =>c <= "0000"; d <= "0101"; WHEN "0110" =>c <= "0000"; d <= "0110";WHEN "0111" =>c <= "0000"; d <= "0111"; WHEN "1000" =>c <= "0000"; d <= "1000";WHEN "1001" =>c <= "0000"; d <= "1001"; WHEN OTHERS =>c <= "0000"; d <= "0000";END CASE;CASE b ISWHEN "0001" =>c <= "0000"; d <= "0010"; WHEN "0010" =>c <= "0000"; d <= "0100";WHEN "0011" =>c <= "0000"; d <= "0101"; WHEN "0100" =>c <= "0000"; d <= "1000";WHEN "0101" =>c <= "0001"; d <= "0000"; WHEN "0110" =>c <= "0001"; d <= "0010";WHEN "0111" =>c <= "0001"; d <= "0100"; WHEN "1000" =>c <= "0001"; d <= "0110";WHEN "1001" =>c <= "0001"; d <= "1000"; WHEN OTHERS =>c <= "0000"; d <= "0000";END CASE;ELSIF(a = "0011") THENCASE b ISWHEN "0001" =>c <= "0000"; d <= "0101"; WHEN "0010" =>c <= "0000"; d <= "0110";WHEN "0011" =>c <= "0000"; d <= "1001"; WHEN "0100" =>c <= "0001"; d <= "0010";WHEN "0101" =>c <= "0001"; d <= "0101"; WHEN "0110" =>c <= "0001"; d <= "1000";WHEN "0111" =>c <= "0010"; d <= "0001"; WHEN "1000" =>c <= "0010"; d <= "0100";WHEN "1001" =>c <= "0010"; d <= "0111"; WHEN OTHERS =>c <= "0000"; d <= "0000";END CASE;CASE b ISWHEN "0001" =>c <= "0000"; d <= "0100"; WHEN "0010" =>c <= "0000"; d <= "1000";WHEN "0011" =>c <= "0001"; d <= "0010"; WHEN "0100" =>c <= "0001"; d <= "0110";WHEN "0101" =>c <= "0010"; d <= "0000"; WHEN "0110" =>c <= "0010"; d <= "0100";WHEN "0111" =>c <= "0010"; d <= "1000"; WHEN "1000" =>c <= "0011"; d <= "0010";WHEN "1001" =>c <= "0011"; d <= "0101"; WHEN OTHERS =>c <= "0000"; d <= "0000";END CASE;ELSIF(a = "0101") THENCASE b ISWHEN "0001" =>c <= "0000"; d <= "0101"; WHEN "0010" =>c <= "0001"; d <= "0000";WHEN "0011" =>c <= "0001"; d <= "0101"; WHEN "0100" =>c <= "0010"; d <= "0000";WHEN "0101" =>c <= "0010"; d <= "0101"; WHEN "0110" =>c <= "0011"; d <= "0000";WHEN "0111" =>c <= "0011"; d <= "0101"; WHEN "1000" =>c <= "0100"; d <= "0000";WHEN "1001" =>c <= "0100"; d <= "0101"; WHEN OTHERS =>c <= "0000"; d <= "0000";END CASE;CASE b ISWHEN "0001" =>c <= "0000"; d <= "0110"; WHEN "0010" =>c <= "0001"; d <= "0010";WHEN "0011" =>c <= "0001"; d <= "1000"; WHEN "0100" =>c <= "0010"; d <= "0100";WHEN "0101" =>c <= "0011"; d <= "0000"; WHEN "0110" =>c <= "0011"; d <= "0110";WHEN "0111" =>c <= "0100"; d <= "0010"; WHEN "1000" =>c <= "0100"; d <= "1000";WHEN "1001" =>c <= "0101"; d <= "0100"; WHEN OTHERS =>c <= "0000"; d <= "0000";END CASE;ELSIF(a = "0111") THENCASE b ISWHEN "0001" =>c <= "0000"; d <= "0111"; WHEN "0010" =>c <= "0001"; d <= "0100";WHEN "0011" =>c <= "0010"; d <= "0001"; WHEN "0100" =>c <= "0010"; d <= "1000";WHEN "0101" =>c <= "0011"; d <= "0101"; WHEN "0110" =>c <= "0100"; d <= "0010";WHEN "0111" =>c <= "0100"; d <= "1001"; WHEN "1000" =>c <= "0101"; d <= "0110";WHEN "1001" =>c <= "0110"; d <= "0011"; WHEN OTHERS =>c <= "0000"; d <= "0000";END CASE;CASE b ISWHEN "0001" =>c <= "0000"; d <= "1000"; WHEN "0010" =>c <= "0001"; d <= "0110";WHEN "0011" =>c <= "0010"; d <= "0110"; WHEN "0100" =>c <= "0011"; d <= "0010";WHEN "0101" =>c <= "0100"; d <= "0000"; WHEN "0110" =>c <= "0100"; d <= "1000";WHEN "0111" =>c <= "0101"; d <= "0110"; WHEN "1000" =>c <= "0110"; d <= "0100";WHEN "1001" =>c <= "0111"; d <= "0010"; WHEN OTHERS =>c <= "0000"; d <= "0000";END CASE;ELSIF(a = "1001") THENCASE b ISWHEN "0001" =>c <= "0000"; d <= "1001"; WHEN "0010" =>c <= "0001"; d <= "1000";WHEN "0011" =>c <= "0010"; d <= "0111"; WHEN "0100" =>c <= "0010"; d <= "0110";WHEN "0101" =>c <= "0100"; d <= "0101"; WHEN "0110" =>c <= "0101"; d <= "0100";WHEN "0111" =>c <= "0101"; d <= "0110"; WHEN "1000" =>c <= "0111"; d <= "0010";WHEN "1001" =>c <= "1000"; d <= "0001"; WHEN OTHERS =>c <= "0000"; d <= "0000";END CASE;ELSEc <= "0000";d <= "0000";END IF;ELSE c <= "0000"; d <= "0000";END IF;END PROCESS;END one;4 实验总结通过这次课程设计，我进一步加深了对电子设计自动化的了解。
i ii 《现代电子技术》20 05 年第 18 期总第 20 9 期þ 集 成 电 路 ü基于 VH DL 语言的组合乘法器设计与仿真刘姝延1 , 吴 志2 , 丁 红1 , 马秋明1( 1. 烟台师范学院 物理与电子工程学 院 山东 烟台 26 40 25; 2 . 烟台师范学院 基建处 山东 烟台 26 40 25 )摘 要: 基于 V H DL 的数字系统设计具有设计技术 齐全、方法灵活、支持广泛等优点, 同时也是 E DA 技术的重要 组成 部分。
文章用 V H DL 语言设计了左移法和进位节省法实现的两种组 合乘法器, 通过功能仿真 , 对两种乘法器的性能进 行了 比较, 从而得知后者的传输延迟时间小, 即速度较快 。
通过设 计实例, 介绍了利用 VH D L 语言进行数字系统设计的方法。
关键词: V H D L ; 组合乘法器; 左移法; 进位节省法中图分类号: T N 7 9 文 献标识码: B 文章编号: 1 00 4 37 3X ( 2 00 5) 18 0 77 0 2Design an d Simulation of Combin a tion a l Mu l t ip l ier Based on VH DL LanguageL I U Sh u y a n 1 , WU Zh i 2 , D I N G H o n g 1 , MA Q i u m i n g 1( 1 . Scho o l o f P hy s i cs a nd Elect ro nic E ng ineer ing , Ya nt ai Nor m a l Un iver si t y, Yant ai, 2 64 02 5, Ch ina;2 . Dep ar tmen t of Basic Bu ilding , Ya nt ai Nor m a l Un iver si t y, Yan t ai, 2 64 02 5, Ch ina)Abs t r a ct : Dig i t a l s y s t e ms u s i n g V H D L h a s t h e adv a n t a ges of comp r eh e n s i v e d e s i gn t e ch n o l o g i e s , fl e xi b l e des i g n met ho d s an d w i dera ng e s u p p o r t , it ′s al s o an i m po r t ant comp o n e n t o f E D A . T he co m b i n a t i o n a l mul t i p l i er s t o us e t w o met h o d s of left sh i f t s an d car rys a ve ar e des i g n e d i n V H D L la ng u a ge , by fun c t i o n a l s i mu l a t i o n , comp a r in g t h e pecu l i a ri t y o f t wo m ul t i p i er s , fi n d t h e car ry s a ve mu l t i - pl i er ′s del a y s h o r t e r , s p e ed fa st er. T h r o u g h d e si g n ex a mp l es , t h i s p a per in t r od u c es t h e met h o d of di g it al s y s t e ms des i g n based o nV H D L .Ke yw o rd s : VH D L ; comb i n a t i o n a l m ul t i p l i er ; met h o d o f left sh i ft ; met h o d o f carr y s a ve1 引 言随着计算机技术和大规模集成电路技术的发展, 传统 的通过 逻辑图 和布尔方 程设计 硬件电路 的方法 已大大落 后于当今 技术的发展, 取而代之 的是硬件描 述语言 H D L 使 用通用逻辑元、器件的限制, 电路尺寸大为缩小, 保密 程度大为提高。
实验四乘法器设计一、实验目的1、掌握利用移位相加方法实现乘法运算的基本原理；2、通过一个4×4的二进制乘法器的设计，学习利用VHDL语言来描述简单的算法，3、熟悉VHDL语言的变量数据对象在描述算法中的作用；二、实验原理实现乘法运算的算法很多，比较常见的有以下几种方法：移位相加、查询表、逻辑树等。
这里主要介绍移位相加的方法。
这种方法实现起来相对简单，目前大多数的单片机和微处理器都采用这种方法。
但是这种方法的最大缺点是速度慢，8位乘法需要8个时钟周期才能得到结果。
根据运算过程中左移或者右移对象的不同，采用移位相加实现乘法运算又有两种算法：（1）部分和固定、部分积左移法（算法1）（2）部分和右移、部分积固定法（算法2）无论是从用时方面还是占用硬件资源方面看，算法2都要优于算法1。
在算法2中，部分积各位是固定的，部分和逐步右移。
下面以4位乘法运算为例，说明其工作原理。
假设4位被乘数X为X3X2X1X0, 乘数Y为Y3Y2Y1Y0, 4×4位结果得到8位的乘积S，将它存放在一个9位累加寄存器中。
累加器初始值为全零，即“000000000”。
算法2的运算过程如下：（1）移出乘数的最低位Y0乘以被乘数X得到第1个部分积S0;（2）第1个部分积S0与累加器S中高4位相加，结果仍然存放在累加器中，即S<=S+S0; （3）将累加器中内容向右移1位，结果仍然存放在累加器中；（4）移出乘数的次低位Y1, 乘以被乘数X得到第2个部分积S0;（5）第2个部分积S0 再与累加器S中高4位相加，结果仍然存放在累加器中，即S<=S+S0;……如此反复直到乘数中所有的位都被移出，第4个部分和与累加器中的值相加后右移，得到的和就是乘积。
算法2的流程图如下图4.1所示：在本实验中将设计一个如下图4.2所示的4位乘法器，输入信号X和Y分别是4位乘数和被乘数Y，CLK为输入时钟信号，START 是乘法启动信号。
