LT8911EX 龙迅中文资料

GL811E-MSGXX中⽂资料GL811EUSB 2.0 to ATA / ATAPI Bridge ControllerDatasheet Revision 1.25 May. 03, 2006Copyright:Copyright ?2006 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic Inc.. Disclaimer:ALL MATERIALS ARE PROVIDED “AS IS” WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE. Trademarks:is a registered trademark of Genesys Logic, Inc.All trademarks are the properties of their respective owners.Office:Genesys Logic, Inc.12F, No. 205, Sec. 3, Beishin Rd., Shindian City,Taipei, TaiwanTel: (886-2) 8913-1888Fax: (886-2) 6629-6168http :///doc/10bc2708b52acfc789ebc981.htmlRevision HistoryRevision Date Description1.00 06/13/2003 First formal release.1.01 06/24/2003 Changed product name from GL811 to GL811E.1.10 11/26/2003 1. Added some features in Chapter2.2. Added 64 pin LQFP data in pinouts, pin description and package dimension.3. Added Chapter 8 “Ordering Infromation”.2.1.20 05/05/2004 1. Removed PIO mode description.2. Changed package dimension1.21 09/23/2004 1. Added USB2.0 certified Test ID in Chapter 2 Features2. Updated IC Marking in package dimension diagram1.22 12/29/2004 Added TQFP package information in Features, Package Dimension and Ordering Information.1.23 02/02/2005 Changed IC marking in package dimension1.24 10/14/2005 Add IDE Bus voltage tolerance information, table3.1, p.11~12 1.25 05/03/2006 Delete 48 Pin TQFP and 64 Pin TQFP Pinout/PackageTABLE OF CONTENTSCHAPTER 1 GENERAL DESCRIPTION (7)CHAPTER 2 FEATURES (8)CHAPTER 3 PIN ASSIGNMENT (9)3.1P INOUTS (9)3.2P IN D ESCRIPTIONS (11)CHAPTER 4 BLOCK DIAGRAM (13)CHAPTER 5 FUNCTION DESCRIPTION (14)CHAPTER 6 ELECTRICAL CHARACTERISTICS (15)6.1A BSOLUTE M AXIMUM R ATINGS (15)6.2T EMPERATURE C ONDITIONS (15)6.3DC C HARACTERISTICS (15)6.3.1 I/O 8 Type digital pins (For pad type I/O 8 @ V CC=3.6V) (15)6.3.2 I/O 16 Type digital pins (For pad type I/O 16 @ V CC=3.6V) (16)6.3.3 D+/ D- (For pad type u20mia @ V CC=3.6V) (16)6.3.4 Switching Characteristics (16)6.4AC C HARACTERISTICS-ATA/ATAPI (17)6.4.1 Register Transfers (18)6.4.2 Multiword DMA data transfer (19)6.4.3 Ultra DMA data transfer (23)6.5AC C HARACTERISTICS -USB2.0 (30)CHAPTER 7 PACKAGE DIMENSION (31)CHAPTER 8 ORDERING INFORMATION (33)F IGURE 3.1-48P IN LQFP P INOUT D IAGRAM (9)F IGURE 3.2-64P IN LQFP P INOUT D IAGRAM (10)F IGURE 4.1-B LOCK D IAGRAM (13)F IGURE 6.1-I NITIATING A M ULTIWORD DMA D ATA B URST (20)F IGURE 6.2-S USTAINING A M ULTIWORD DMA D ATA B URST (21)F IGURE 6.3-D EVICE T ERMINATING A M ULTIWORD DMA D ATA B URST (21)F IGURE 6.4-H OST TERMINATING A M ULTIWORD DMA D ATA B URST (22)F IGURE 6.5-I NITIATING AN U LTRA DMA D ATA-I N B URST (24)F IGURE 6.6-S USTAINED U LTRA DMA D ATA-I N B URST (24)F IGURE 6.7-H OST P AUSING AN U LTRA DMA D ATA-I N B URST (25)F IGURE 6.8-D EVICE T ERMINATING AN U LTRA DMA D ATA-I N B URST (25)F IGURE 6.9-H OST T ERMINATING AN U LTRA DMA D ATA-I N B URST (26)F IGURE 6.10-I NITIATING AN U LTRA DMA D ATA-O UT B URST (27)F IGURE 6.11-S USTAINED U LTRA DMA D ATA-O UT B URST (27)F IGURE 6.12-D EVICE P AUSING AN U LTRA DMA D ATA-O UT B URST (28)F IGURE 6.13-H OST TERMINATING AN U LTRA DMA DATA-OUT BURST (29)F IGURE 6.14-D EVICE T ERMINATING AN U LTRA DMA D ATA-O UT B URST (30)F IGURE 7.1-GL811E48P IN LQFP P ACKAGE (31)F IGURE 7.3-GL811E64P IN LQFP P ACKAGE (32)LIST OF TABLEST ABLE 3.1-P IN D ESCRIPTIONS (11)T ABLE 6.1-M AXIMUM R ATINGS (15)T ABLE 6.2-T EMPERATURE C ONDITIONS (15)T ABLE 6.3-I/O8T YPE DIGITAL PINS (F OR PAD TYPE I/O8@V CC=3.6V) (15)T ABLE 6.4-I/O16T YPE DIGITAL PINS (F OR PAD TYPE I/O16@V CC=3.6V) (16)T ABLE 6.5-D+/D-(F OR PAD TYPE U20MIA @V CC=3.6V) (16)T ABLE 6.6-S WITCHING C HARACTERISTICS (16)T ABLE 6.7-U LTRA DMA DATA BURST TIMING REQUIREMENTS (23)T ABLE 8.1-O RDERING I NFORMATION (33)CHAPTER 1 GENERAL DESCRIPTIONThe GL811E is a highly-compatible, low cost USB 2.0 to A TA / A TAPI bridge controller, which integrates Genesys Logic own design high speed UTMI (USB 2.0 Transceiver Macrocell Interface) transceiver.only protocol), the GL811E can support not only plug and play but also Windows XP/ 2000/ ME default driver.The GL811E uses 12MHz crystal and slew-rate controlled pads to reduce the EMI issue. With 48-pin LQFP (9mmX9mm) package, the GL811E is the best cost/ performance solution to fit different situations in the USB 2.0 high speed storage class applications such as Hard Disk, CD-ROM, CD-R / RW and DVD-ROM.CHAPTER 2 FEATURESComplies with Universal Serial Bus specification rev. 2.0.Complies with A TA/A TAPI-6 specification rev 1.0.Complies with USB Storage Class specification ver.1.0. (Bulk only protocol)Operating system supported: Win XP / 2000 / Me / 98 / 98SE; Mac OS 9.X / X. Integrated USB 2.0 Transceiver Macrocell Interface (UTMI) transceiver and Serial Interface Engine (SIE). ?USB 2.0 certified (TestID=40380268)Supports 4 endpoints: Control (0) / Bulk Read (1) / Bulk Write (2) / Interrupt (3).64 / 512 bytes Data Payload for full / high speed Bulk Endpoint.Supports 16-bit Multiword DMA mode and Ultra DMA mode interface (Ultra 33 / 66). Embedded 7.5 MIPS RISC CPU. ROM size: 4k words; RAM size: 128 bytes.Supports Power Down mode and USB suspend indicator.Supports USB 2.0 TEST mode features.Supports 2 GPIO (GPIO5 & 6) for programmable AP (only for 64 pin package). Supports device power control for power on/off when running suspend mode (only for 64 pin package). ?Supports 32 bit and 48 bit LBA hard disk.Provides LED indicator for Full Speed and High Speed (only for 64 pin package).12 MHz external clock to provide better EMI.3.3V power input; 5V tolerance pad for IDE interface.Supports Wakeup ability.Available in 48-pin LQFP and 64-pin LQFP package.CHAPTER 3 PIN ASSIGNMENT3.1 PinoutsGP I O 71I O D D [8]2I O D D [9]3I O D D [10]4I O D D [11]5D V C C 16D G N D 17I O D D [12]8I O D D [13]9I O D D [14]10I O D D [15]11C B L I D _12 D I O W _D I O R _I O R D YD M A C K _D A 0C S 0_T E S TA G N D 1X 1X 2363534333231302928272625Figure 3.1 - 48 Pin LQFP Pinout DiagramGL811E LQFP - 64 X2 AVCC1 RREF AGND0 DMH DMF DPH DPF AVCC0 RPU RESET# DA2CS1_ NCNCNC3130292825242322212019181732 NC DMARQ IODD0 IODD1 IODD2 IODD3 DGND1 DVCC1 IODD4 IODD5 IODD6 IODD7 GPIO1 PWR_CT LF_LED H_LED 5051525354555659606162636449Figure 3.2 - 64 Pin LQFP Pinout Diagram3.2 Pin DescriptionsTable 3.1 - Pin DescriptionsPin Name 48Pin# 64 Pin# I/O Type DescriptionGPIO7 1 1B(tri) GPIO7 (**)GPIO5~6 - 3,4 O AP programmableIODD[8:11]2~5 5~8B(tri) IDE data bus 8~11 (*****)DVCC1~2 6,43 56,9 P Digital VCCDGND1~2 7,42 55,10 P Digital groundIODD[12:15]8~11 11~14 B(tri) IDE data bus 12~15 (*****)CBLID_ 12 15 I(tri) Cable select input (*****)CS1_ 13 20 O(tri) Chip select 1 (*****)DA2/SK 14 -O(tri) IDE address 2 / Serial data clock for EEPROM (*****) RESET# 15 22 I(pu) Reset pin (***)RPU 16 23 A 3.3v outputA VCC0~1 17,24 24,31 P Analog VCCDPF 18 25 B Full speed DPDPH 19 26 B High speed DPDMF 20 27 B Full speed DMDMH 21 28 B High speed DMAGND0~1 22,27 29,34 P Analog groundRREF 23 30 A Reference resister connect (****) X2 25 32 B Crystal output X1 26 33 I Crystal input, 12MhzTEST 28 -I(pd) TEST mode inputCS0_ 29 37O(tri) Chip select 0 (*****)DA0~1 30,31 38,39O(tri) IDE address 0~1 (*****)DA2 - 21O(tri) IDE address 2 (*****)INTRQ 32 44I(tri) IDE interrupt input (*****)DMACK_ 33 45O(tri) IDE acknowledge (*****)IORDY 34 46I(pu) IDE ready (*****)DIOR_ 35 47O(tri) IDE read signal (*****)DIOW_ 36 48O(tri) IDE write signal (*****)DMARQ 37 50I(pd) IDE request (*****)IODD[0:3]38~41 51~54B(tri) IDE data bus 0~3 (*****)IODD[4:7]44~47 57~60B(tri) IDE data bus 4~7 (*****)GPIO1 48 61B(tri) GPIO1PWR_CTL - 62 O Power control F_LED - 63 O Full speed LED H_LED - 64 O High speed LEDNC - 2,16~19,35,49,- No connection(*) The different of I/O 8 type from I/O 16 type is the typical drive current. The typical drive current of I/O 8 type is 8 mA, and for I/O pad 16 is 16 mA.(**) When operating in default mode: GPIO7 is the A TA/ A TAPI reset input , 5V tolerance.(***) When Reset pin is pulled low, the IDE bus will be in tri-state.(****) RREF must be connected with a 510 ohm resister to ground.(*****) 5V toleranceNotation:Type O OutputI InputB Bi-directionalB/I Bi-directional, default inputB/O Bi-directional, default outputP Power / GroundA AnalogSO Automatic output low when suspendpu Internal pull uppd Internal pull downodpu Open drain with internal pull uptri Tri-stateCHAPTER 4 BLOCK DIAGRAMFigure 4.1 - Block DiagramCPUCONTROL FIFORXFIFO1SIEControl RegisterUTMI LOGICUSB2.0 TXCVRClkgenTXFIFO0TXFIFO1CLK30 RXSTS TXCTLDA TA16CLK15 8RPUDPF DPHDMHDMF RREFIODD15-0DMACK_ DIOR_ DIOW_ CS1_, CS0_ DA2 DA1 DA0 12MHz4INTRQ CBLID_ DMARQ IORDY X40X10RXFIFO0GPIO1GPIO7 8/16-Bit IDEEngine12-96MHzCHAPTER 5 FUNCTION DESCRIPTION1. USB2.0 TXCVRThe USB 2.0 Transceiver is the analog circuitry to handle the USB HS/FS signaling.2. UTMI (USB 2.0 Transceiver Macrocell Interface) LogicThe UTMI Logic is compliant to Intel’s UTMI specification 1.01. This block handles the low level USB protocol and signaling. The major jobs of UTMI Logic is data and clock recovery, NRZI encoding/decoding, Bit Stuffing/De-stuffing, USB2.0 test modes supporting and serial / parallel conversion.3. SIE (S erial I nterface E ngine)The SIE contains the USB packet ID and address recognition logic, and other sequencing and state machine logic to handle USB packets and transactions.4. PLL10XPLL provides the 120MHz clock output for UTMI Logic block. UTMI operates in 120MHz for USB HS data processing. 40XPLL block will provide 480MHz for USB HS data transmission.5. CLKGENCLKGEN is the clock generator block for the logic blocks. It generates 15MHz clock for micro controller, 48MHz for MDMA mode, 96MHz for UDMA mode, and 30MHz clock for UTMI, SIE, and FIFO.6. CPUThe CPU is the control center of GL811E. It’s an 8-bit micro controller operating in 15MHz, 7.5 MIPS. After receiving a USB command, it decodes the host command, then it re-assigns tasks to the IDE engine, GPIO, FIFO, and response properdata/status to USB host.7. IDE EngineThe IDE engine is extended from standard A TA / A TAPI protocol. It supports multiword DMA mode, and ultra DMA mode data transfers.8. FIFOsControl FIFO is used as Control Read / Write FIFO. TXFIFO0 / TXFIFO1 are two sets of 512-byte ping-pong FIFO for Bulk Read endpoint. It buffers data from IDE engine, and re-direct to USB SIE logic. RXFIFO0 / RXFIFO1 are two sets of 512-byte ping-pong FIFO for Bulk Write endpoint. It buffers data from USB SIE logic, and re-direct to IDE engine.9. Control RegistersControl Register configures GL811E to proper operation. For example, CPU can set register to generate wakeup event, enter suspend, transmits proper USB packet to host.10. ATA/ATAPIThe GL811E complies with A TA/A TAPI-6 specification rev. 1.0. Please refer to the specifications for more information. 11. USB 2.0The GL811E complies with Universal Serial Bus specification rev. 2.0, and it integrates Genesys Logic own design UTMI transceiver that fully complies with the USB 2.0 Transceiver Macercell Interface (UTMI) specification rev. 1.01. Please refer to the specifications for more information.CHAPTER 6 ELECTRICAL CHARACTERISTICS6.1 Absolute Maximum RatingsTable 6.1 - Maximum RatingsSymbol Parameter Min. Max. UnitV CC DC supply voltage +3.0 +3.6 VV I DC input voltage -0.3 V CC + 0.3 VV I/O DC input voltage range for I/O -0.3 V CC + 0.3 VV AI/O DC input voltage for USB D+/D- pins -0.3 V CC + 0.3 VV ESD Static discharge voltage 4000 VT A Ambient Temperature 0 100 o C 6.2 Temperature ConditionsTable 6.2 - Temperature ConditionsItem ValueStorage Temperature -50o C ~ 150 o COperating Temperature 0 o C ~ 70 o C6.3 DC Characteristics6.3.1 I/O 8 Type digital pins (For pad type I/O 8 @ V CC=3.6V)Table 6.3 - I/O 8 Type digital pins (For pad type I/O 8 @ V CC=3.6V)Parameter Min. Typ. Max. Unit Current sink @ V OL = 0.4V 7.79 10.83 14.09 mA Current output @ V OH = 2.4V (TTL high) 16.36 19.87 23.39 mA Falling slew rate at 30 pF loading capacitance 0.26 0.50 0.80 V/ns Rising slew rate at 30 pF loading capacitance 0.30 0.57 0.91 V/ns Input high threshold voltage 1.64 V Input low threshold voltage 1.36 VHysteresis voltage - 0 - V Leakage current for pads with internal pull up or pulldown resistor 46 µA Pad internal pull down resister 51K 105K 152K Ohms Pad internal pull up resister 85K 168K 251K Ohms Supply current 109 mA6.3.2 I/O 16 Type digital pins (For pad type I/O 16 @ V CC=3.6V)Table 6.4 - I/O 16 Type digital pins (For pad type I/O 16 @ V CC=3.6V)Parameter Min. Typ. Max. Unit Current sink @ V OL = 0.4V 16.20 21.90 27.68 mA Current output @ V OH = 2.4V (TTL high) 24.13 29.46 34.80 mA Falling slew rate at 30 pF loading capacitance 0.51 0.93 1.35 V/ns Rising slew rate at 30 pF loading capacitance 0.46 0.83 1.27 V/ns Input high threshold voltage 2.15 V Input low threshold voltage 0.89 V Pad internal pull down resister 51K 105K 152K Ohms6.3.3 D+/ D- (For pad type u20mia @ V CC=3.6V)Table 6.5 - D+/ D- (For pad type u20mia @ V CC=3.6V)Parameter Min. Typ. Max. Unit D+/D- static output LOW (R L of 1.5K to V CC ) 0 0.3 V D+/D- static output HIGH (R L of 15K to GND ) 2.8 3.6 V Differential input sensitivity 0.2 V Single-ended receiver threshold 0.8 2.0 V Transceiver capacitance 20 pF Hi-Z state data line leakage -10 +10 µA Driver output resistance 28 43 Ohms6.3.4 Switching CharacteristicsTable 6.6 - Switching CharacteristicsParameter Min. Typ. Max. Unit X1 crystal frequency 11.97 12 12.03 MHz X1 cycle time 83.3 ns D+/D- rise time with 50pF loading 4 20 ns D+/D- fall time with 50pF loading 4 20 ns6.4 AC Characteristics- ATA/ ATAPIThe GL811E complies with ATA / ATAPI-6 specification rev 1.0, which supports following data transfer modes:1. DMA (Direct Memory Access) data transfer:DMA data transfer means of data transfer between device and host memory without host processor intervention.- Multiword DMA: Multiword DMA is a data transfer protocol used with the READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When aMultiword DMA transfer is enabled as indicated by IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data, this data transfer protocol shall be used for the data transfers associated with these commends. (Please refer to the A TA / A TAPI-6specification rev 1.0 for more information.) - Ultra DMA: Ultra DMA Is a data transfer protocol used with the READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When this protocol is enabled, the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. (Please refer to the A TA / A TAPI-6 specification rev 1.0 for more information.)Following listed the symbols and their respective definitions that are used in the timing diagram:All signals are shown with the asserted condition facing to the top of the page. The negated condition is shown towards the bottom of the page relative to the asserted condition.The interface uses a mixture of negative andpositive signals for control and data. The terms asserted and negated are used for consistency and are independent of electrical characteristics.In all timing diagrams, the lower line indicates negated, and the upper line indicates asserted. The following illustrates the representation of a signal named Test going from negated to asserted and back to negated, based on the polarity of the signal.- Signal transition (asserted or negated) - Data transition (asserted or negated) - Data valid- Undefined but not necessarily released - Asserted, negated or released -Released- The “other ” condition if a signal is shown with no change6.4.1 Register TransfersNotes:1. Device address consists of signals CS0_, CS1_ and DA(2:0).2. Data consists of IODD(7:0).3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination ofwhether the cycle is to be extended is made by the host after t A from the assertion of DIOR_ or DIOW_.The assertion and negation of IORDY are described as following:3.1Device never negates IORDY, devices keeps IORDY released: no wait is generated.3.2Device negates IORDY before t A, but causes IORDY to be asserted before t A. IORDY is releasedprior to negation and may be asserted for no more than 5 ns before release: no wait generated.3.3Device negates IORDY before t A, IORDY is released prior to negation and may be asserted for nomore than 5 ns before release: wait generated. The cycle completes after IORDY is released. Forcycles where a wait is generated and DIOR_ is asserted, the device shall read data on IODD(0:7) for t RD before asserting IORDY.4.D MACK_ shall remain negated during a register transfer.Register transfer timing parameters Timing (ns) t0Cycle time 2000t1Address valid to DIOR_/ DIOW_ setup 1000t2DIOR_/ DIOW_ pulse width 8-bit 300t2i DIOR_/ DIOW_ recovery time 900t3DIOW_ data setup 80t4DIOW_ data hold 40t5DIOR_ data setup -t6DIOR_ data hold -t6Z DIOR_ data tristate -t9DIOR_/ DIOW_ to address valid hold 900t RD Read Data V alid to IORDY active (if IORDY initially low after t A) t A IORDY Setup time -t B IORDY Pulse Width -t C IORDY assertion to release (max) -6.4.2 Multiword DMA data transferRegister transfer timing parameters Timing (ns) t0Cycle time 120t D DIOR_/ DIOW_ asserted pulse width 80t E DIOR_ data access -t F DIOR_ data hold -t G DIOR_/ DIOW_ data setup 40t H DIOW_ data hold 18t I DMACK to DIOR_/ DIOW_ setup 18t J DIOR_/ DIOW_ to DMACK hold 20t KR DIOR_ negated pulse width 36t KW DIOW_ negated pulse width 36t LR DIOR_ to DMARQ delay -t LW DIOW_ to DMARQ delay -t M CS(1:0) (max) valid to DIOR_/ DIOW_ 36t N CS(1:0) hold 18t Z DMACK_ to read data released -。

描述 Lontium LT86102UX HDMI2.0 分配器具有 1：2 的容量最大符合 HDMI2.0 / 1.4 规格的分配器 6Gbps 高速数据速率，自适应均衡 RX 输入和预加重 TX 输出以支持长电缆 应用，板上没有 XTAL 和 1.2V 电源节省 BOM 成本，内部 TX 通道交换以实现灵活的 PCB 路由。 LT86102UX HDMI2.0 分离器自动检测电缆损耗，并自适应优化均衡设置.CDR 清除输入数据抖 动，使其适用于长电缆和级联应用。 IT 支持 RX 端接电阻器校准可进一步改善信号 诚信。 LT86102UX 支持 符合 DDC / SCDC 与 HDMI2.0 / 1.4 规范。 这个包装是 TQFP100
14 毫米 x14 毫米。 它的工作温度范围为-40°C 至+ 85°C。 应用领域 1.多种显示/电视支持 2.HDMI / DVI 信号重复播放
LT861 02UX ---产品简介 HDMI2.0 1 进 2-0ut 分配器
特征 1.符合 HDMI 1.4 / 2.0 规范 2.支持 3D 视频格式和 4Kx2K 扩展分辨率 高达 6.0Gbps 的数据速率 3.支持 8/10 / 12bit 深色 4.支持高达 60Hz 帧频的 4K2K 视频 5.支持所有兼容的视频格式 HDMIl2.0 / 1.4 规格 6.自适应均衡和消除偏重补偿 电缆损耗大 7.ODT 和校准 8.集成 EDID 影子 RAM 和嵌入式 EDID 5V 耐压 DDC 接口 9. 1 个 HDMI 输入端口，最多 2 个 HDMI 输出端口 10.无限级联，更多输出端口或信号 重复 11.抖动清除 PLL，以获得更好的性能 12.DC / AC 耦合信号输入/输出 13.不需要多余的水晶 14.包装为 TQFP100 14mm x 14mm

概述：M8911是一款隔离式、单级有源功率因数校正的高精度原边反应LED恒流控制芯片，适用于全范围输入电压的反激式隔离LED恒流电源。

M8911集成有源功率因数校正电路，具有很高的功率因数和较低的总谐波失真。

工作在电感电流临界连续形式，功率MOS管处于零电流开通状态，减小开关损耗。

M8911工作于原边反应形式，无需次级反应电路，即可实现高精度输出恒流控制。

特点：1.内置单级有源功率因数校正，PF2.原边反应，无需光耦，TL431等器件3.高性能的线电压调整率和负载调整率4.±3%输出电流精度5.内置650V功率MOSFET6.启动电流(33uA)7.INV反应电阻值高，功耗低8.多重保护功能9.LED开路/短路保护10.电流采样电阻开路保护11.逐周期原边电流限流12.芯片供电过压/欠压保护13.自动重启功能14.过热调节功能15.采用SOP-8封装应用：☞L EDPAR灯☞L ED日光灯☞L ED球泡灯、射灯☞其它典型应用：图1M8911典型应用图管脚排列图:M8911图2M8911管脚排列图管脚描绘：管脚名称管脚号管脚描绘COMP 1 环路补偿点VDD 2 芯片供电INV 3 辅助绕组反应信号采样端SEN 4 电流采样端，接采样电阻到地DRAIN 5,6 内部高压MOSFET的漏极GND 7,8 芯片信号和功率地极限参数：推荐工作范围：注1：最大极限值是指超出该工作范围，芯片有可能损坏。

推荐工作范围指在该范围内，器件功能正常，但并不完全保证满足个别性能指标。

电气参数定义了器件在工作范围内并且在保证特定性能指标的测试条件下的直流和交流电参数标准。

对于未给定上下限值的参数，该标准不予保证其精度，但其典型值合理反映了器件性能。

注2：温度升高最大功耗一定会减小，这也是由TJMAX,θJA,和环境温度TA所决定的。

最大允许功耗为PDMAX=(TJMAX-TA)/θJA或是极限范围给出的数字中比拟低的那个值。

Uniwell TX-850 and TX-870 and DX-890 type 06 operation ManualDX890 - 06TX870 - 06TX850 - 06V1.0420 February 2004 This manual is available as PDF which allows for easier searching.THE SOCKET-OUTLET SHALL BE INSTALLED NEAR THE EQUIPMENT AND SHALL BE EASILY ACCESSIBLE.LA PRISE DOIT ETRE PRES DE L'APPAREIL ET FACILE D'ACCES.Note: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:-- Reorient or relocate the receiving antenna.-- Increase the separation between the equipment and receiver.-- Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.-- Consult the dealer or an experienced radio/TV technician for help.=================================================1. The contents of this manual are subject to change without notice.2. Uniwell cannot be held responsible if other products, which are not approved by Uniwell, are usedfor options or expendable supplies.=================================================CONTENTSRefer to the separate User's manual for the specifications, installation, display and screen layout.Set up and configuration of the ECR is performed by referencing the help file or programming manual.1.FUNCTION BUTTON LIST (1)2.CLERK OPERATIONS (3)2-1.Clerk systems (3)2-2.Signing on a clerk (3)a)Using hard clerk buttons (3)b)Using secret clerk codes (3)c)Using clerk card (4)d)Using iButton (4)2-3.Signing off a clerk (4)2-4.Assign HARD CLERK buttons in X key position [SF-21.C] (4)2-5.Clerk sign-on screen (5)2-6.Clerk log-on/off - time and attendance operation (6)a)Clerk Log-on/off Operation on Normal Screen (non clerk sign-on screen) (6)b)Clerk Log-on/off Operation on Clerk Sign-on Screen (7)2-7.Clerk training mode (9)3.PLU SALES OPERATIONS (10)3-1.PLU registration (10)a)Hard PLU buttons / Scanner (10)b)Coded PLUs (10)3-2.Look up PLU buttons (11)3-3.PLU multiplication (11)a)Hard PLU buttons / Scanner (11)b)Coded PLUs (12)c)Look up PLUs (12)d)4-digit multiplication (13)3-4.Manual price entry (14)a)Hard PLU buttons / Scanner (14)b)Coded PLUs (15)c)Look up PLUs (15)3-5.Prices (16)a)How to change price levels (16)b)How to change price within each level (16)3-6.PLU modifiers (half / double, small / large, or programmable value) (17)3-7.PLU menu levels (18)3-8.Price inquiry (display only) (19)3-9.Single item (19)plimentary PLUs (20)3-11.Coupon PLUs (21)3-12.Special PLUs (22)3-13.Cooking instructions (25)a)By linking them directly to specified PLUs in programming (SP-122 PLUs: COOK = 1~20) (25)b) By pressing a COOKING 1 ~ 64 buttons (SP-122 PLUs: COOK = 0) (25)c) Cooking instruction group 1 is listed by pressing COOKING MESSAGE (SP-122 PLUs: COOK = 0) (26)d) Manual cooking message entry by pressing MANUAL COOKING button (26)3-14.Condiments (27)3-15.Category Change (29)3-16.Automatic link PLUs (expanded Look Up PLU function) (31)a) Chained up to 40 PLUs [SF-20.E=YES, PF-04.F=YES] (31)b) One link PLU (unchained) [SF-20.E=NO, PF-04.F=YES] (33)3-17.Set menu - Course (expanded Look Up PLU function) (34)3-18.Topping (expanded Look Up PLU function) (38)a) Selectable topping lists - by pressing one of Look Up PLU buttons (38)b) Pre-programmed topping list - automatic topping list (39)3-19.Take out / Eat in system with Combo menu (expanded Look Up PLU function) (40)a) Eat in/Take out operation (41)b) Eat in/Take out operation with Price Level Shift (41)c) Eat in/Take out operation with Combo Menu (43)d) Mode selection for take-out system (44)e) Kitchen Printer for take-out and delivery items (45)f) Automatic tax shift in take-out system (46)g) Tax status changed by the Eat-in/Take-out/Delivery (47)h) Grouped PLU report used as Eat in/Take out/Delivery sales report (49)h) Grouped PLU report used as Eat in/Take out/Delivery sales report (49)3-20.Mix & Match (51)a) Programming Contents (51)b) Operation Samples (52)c) Mix & Match Report (59)d) Operational Restrictions (61)4.OTHER FUNCTIONS (62)4-1.No sale (62)4-2.Item correction (CR) (63)4-3.Void (64)4-4.Refund (65)4-5.Media Refund (66)4-6.Non-add number (Message Entry) (67)4-7.Tip (68)4-8.Amount discount (69)a) Preset amount discount (69)b) Manual amount discount (69)4-9.Adjustments (70)4-10.Percentages (71)a)Preset percentage on subtotal (71)b)Manual percentage on subtotal (71)c)Item discount / add-on charge (72)4-11.Repeat transaction (72)4-12.Media (Total) to finalize transaction (73)a)Tendering (Closing methods) (73)b)Preset tender (73)c)Special media (74)d)Media multiplication (74)e)Pre-payment (partial payment) media for track operation (75)f)Card payment (76)g)National (Local) currency symbol print (78)4-13.Euro currency (79)4-14.Foreign currency (81)4-15.Paid out (82)4-16.Deposit (83)a)Deposit in (83)b)Deposit out (84)4-17.Persons (85)4-18.Track systems (Billing systems) (87)a) Characteristics (87)b) Operation Sequence --- same for both bill and table number systems (88)c) Split Bill - Item Transfer [SF-37.E=NO] (96)Split Bill for Multiplied Items (98)d) Track Transfer (101)e) Clerk Track Transfer (102)f) Floating Track (108)g) Program Options for Track Systems (108)4-19.Seat number assignment (110)a) Seat assignment - assigning seat numbers to each person (110)b) Seat change - changing seat numbers on registered items (111)c) Seat transfer - splitting seats to another transaction (112)d) Notes (114)4-20.Tax system (115)a) Tax System Outline (115)b) Automatic Tax Exemption --- only for add-on tax items calculated by add-on tax method (117)c) Manual Tax Exemption --- only for add-on tax items calculated by add-on tax method (118)d) Tax Shift --- for add-on tax system and VAT system (120)e) Program Options (122)4-21.Ticket system (124)4-22.Customer file (126)a) Customer file addition during registration [SF-109.G=NO] (127)b) Broadcast customer file [SF-87.A=YES] (129)c) Customer file pick-up methods during registration (130)d) Picked up customer file cancellation during registration (132)e) Picked up customer file checking during registration (133)f) Limitations for customer file function (133)g) Customer name printed in header (133)g) Customer file search by customer name (134)4-23.Server number (135)4-24.Room system (136)4-25.Loyalty system (136)4-26.Cash declaration (137)4-27.2nd page on main screen (REG mode) (138)4-28.Automatic Order Number (139)bor Cost (140)a) Programming Contents (140)b) Setup (145)c) X/Z-20 Labor Cost Report (146)d) Labor Cost Report Sample (147)4-30.Scale function (152)a) Programming Contents (152)b) Registration of Scalable Items (154)c) Registration of Scalable Items with Tare Weight Entry (156)d) Print/Display of Scalable Item Registration (158)e) Refund of Scalable Item Registration (159)4-31.Customer Invoice (161)4-32.Track Name (161)4-33.Proforma Invoice Function (161)4-34.Table Plan (161)4-35.Piece Count System (161)4-36.Add Value to Smart Card Function (161)4-37.Broadcast in location (161)4-38.Person Average Sales (161)4-39.FTP Comms (161)4-40.Split Bill by Quantity (161)bel Print on KP (161)4-42.KP, RCT Server (161)4-43.Media count on report (161)4-44.UDP Streaming (161)4-45.Trintech Operations (161)5.PRINT FUNCTION (162)5-1.Types of printer (162)5-2.Flexible receipt printing (162)5-3.Graphic logo (162)5-4.Receipt on/off (162)5-5.Direct sales print (162)5-6.Direct sales print (163)5-7.Media prints the signature line (163)5-8.Buffer print system (164)5-9.Subtotal bills (165)5-10.Final checkout bills (165)5-11.KP server / Receipt server (165)5-12.Order (kitchen) printer (166)5-13.Slip printer (167)5-14.Cheque printing by slip printer TP-620 (167)MUNICATION (168)7.REPORTING (169)7-1.X/Z reports (169)7-2.Electronic Journal Function (EJF) (170)7-3.FTP Communication and UDP Streaming (170)7-4.Program Dump Reports (170)7-5.Report List (171)7-6.IRC Report List (172)8.WARNING MESSAGE (173)This is a “Table of Contents preview” for quality assuranceThe full manual can be found at /estore/catalog/ We also offer free downloads, a free keyboard layout designer, cable diagrams, free help andsupport. : the biggest supplier of cash register and scale manuals on the net。