Table of Contents1.Description (3)2.Features (4)3.Ordering Information (5)4.Block Diagram (5)5.Pin Assignment (6)5.1SSOP28 (6)5.2SSOP16 (7)5.3SSOP28/SSOP16 Pin Description (8)6.Electrical Characteristics (10)6.1Absolute Maximum Ratings (10)6.2Operating Conditions (10)6.3DC Characteristics (10)6.4Power on Sequence (11)7.Power Consumption Measurements (12)8.Package (13)8.1SSOP28 Outline (13)8.2SSOP16 Outline (14)1. DescriptionThe MA8601 is a high performance solution for USB 2.0 High Speed 4-port hub controller that is fully compliant with Universal Serial Bus Specification 2.0. The MA8601 inherits advanced serial interface technology to consume the least power when 4 DS (downstream) ports function simultaneously.The MA8601 adapts Single Transaction Translator (STT) and Ganged power management to achieve cost effective solution. Users can also implement multiple Hub configuration options through external EEPROM*.The MA8601 supports SSOP28/SSOP16 package targeting the mainstream standalone 4 ports Hub market.2. Features●Compliant with USB Specification Revision 2.0⏹Upstream Port supports high-speed (480MHz) and full-speed (12MHz) traffic⏹Configurable 4/3/2 downstream ports* support high-speed, full-speed, and low-speed⏹Backward compatible to USB Specification Revision 1.1●Integrated Fast 8051 microprocessor●12MHz Oscillator clock input●Integrated upstream 1.5KΩ pull-up downstream 15KΩ pull-down resistors●Single Transaction Translator (Single TT)●Ganged Power Control and Global Over Current detection for downstream ports●On chip 5V to 3.3V/1.2V regulator●Automatic re-enumeration for switching between self-powered and bus-powered modes*●External EEPROM interface for customized information storage*⏹Customized VID, PID⏹Number of downstream port⏹Product ID⏹Serial number●Two LED port indicator mode*⏹ 4 Downstream port LED (enable green) and one Active/Suspend LED(Red)⏹One joint Downstream port LED for 4 ports (enable green) and one Active/SuspendLED(Red)●Type of package⏹28-pin SSOP⏹16-pin SSOP●Application⏹Standalone USB hub⏹NB / Tablet / Motherboard / Docking Station⏹Gaming console⏹Led monitor hub⏹Any compound device to support USB hub functionNote - * : Only support in 28-pin SSOP3. Ordering Information4. Block DiagramLED1EESCL5. Pin Assignment 5.1 SSOP285.2 SSOP165.3 SSOP28/SSOP16 Pin DescriptionI/O Type Definition:O : Output I : Input B : Bi-directional P : Power6. Electrical Characteristics 6.1 Absolute Maximum Ratings6.2 Operating Conditions6.3 DC Characteristics6.4 Power on SequenceReset TimingN ote: For Vt+ and Vt-, refer to Table 17. Power Consumption Measurements8. Package8.1 SSOP28 Outline8.2 SSOP16 OutlineDisclaimerAll the information in this document is subject to change without prior notice. Prolific Technology Inc. does not make any representations or any warranties (implied or otherwise) regarding the accuracy and completeness of this document and shall in no event be liable for any loss of profit or any other commercial damage, including but not limited to special, incidental, consequential, or other damages.TrademarksThe Prolific logo is a registered trademark of Prolific Technology Inc. All brand names and product names used in this document are trademarks or registered trademarks of their respective holders.CopyrightsCopyright © 2015- 2020 Prolific Technology Inc. All rights reserved.No part of this document may be reproduced or transmitted in any form by any means without the express written permission of Prolific Technology Inc.。
April 07STM32F10x Technical TrainingMCD Application TeamCONTENTSObjectivesSTM32F10x DeviceBlock DiagramMemory mapping and boot modesSystem ArchitectureSTM32F10x PeripheralsMain featuresSTM32F10x USB Developer kitSTM32F10x Firmware LibraryPackage organizationCoding conventionsLibrary structureUsing the LibrarySTM32F10x Technical Training V0.3OBJECTIVESImprove your knowledge on STM32F10x peripheralsIntroduce the STM32F10x Firmware LibraryAt the end of the training you will be able toList the main features of the STM32F10x peripheralsList the main demos of the STM32F10x USB Developer kitConfigure the Firmware library environmentDevelop your applications using the STM32F10x Firmware Library STM32F10x Technical Training V0.3CONTENTSObjectivesSTM32F10x DeviceBlock DiagramMemory mapping and boot modesSystem ArchitectureSTM32F10x PeripheralsMain featuresSTM32F10x USB Developer kitSTM32F10x Firmware LibraryPackage organizationCoding conventionsLibrary structureUsing the LibrarySTM32F10x Technical Training V0.3STM32F10x Technical Training V0.3Up to 20kB SRAM 64kB to come e/o2007F l a s h I /F32kB-128kB Flash Memory 512kB to comee/o 2007CORTEXM3CPU 72 MHzJTAG/SW Debug Nested vect IT Ctrl 1x Systic Timer A R M L i t e H i -S p e e d B u s M a t r i x / A r b i t e r (m a x 72M H z )STM32F10x Series Block DiagramARM 32-bit Cortex-M3 CPUNested Vectored Interrupt Controller (NVIC) w/ 43 maskable IT + 16 prog. priority levels Embedded Memories :FLASH: up 128 Kbytes, 512kB to come e/o 2007SRAM: up 20 Kbytes, 64kB to come e/o 20077 Channels DMAPower Supply with internal regulator and low power modes :2V to 3V6 supply4 Low Power Modes with Auto Wake-upIntegrated Power On Reset (POR)/Power Down Reset (PDR) + Programmable voltage detector (PVD)Backup domain w/ 20B regUp to 72 MHz frequency managed & monitored by the Clock Control w/ Clock Security System Rich set of peripherals & IOsEmbedded low power RTC with V BAT capability Dual Watchdog Architecture5 Timers w/ advanced control features (including Cortex SysTick)9 communications InterfacesUp to 80 I/Os (100 pin package) w/ 16 external interrupts/eventUp to 2x12-bits 1Msps ADC w/ up to 16 channels and Embedded temperature sensor w/ +/-1.5°linearity with T °XTAL oscillators 32KHz + 4~16MHz Int. RC oscillators 32KHz + 8MHzPLL32/49/80 I/OsUp to 16 Ext. ITs2x I 2C1x SPI 2x USART/LIN Smartcard / IrDa Modem Control1x USB 2.0FS 1x bxCAN 2.0B 1x USART/LIN Smartcard/IrDa Modem-Ctrl1x SPI RTC / AWUPower Supply Reg 1.8V POR/PDR/PVDDMA 7 Channels2x 12-bit ADC 16 channels / 1Msps Temp SensorA R M P e r i p h e r a lB u s(m a x 72M H z )Bridge BridgeARM Peripheral Bus(max 36MHz)1x 16-bit PWMSynchronized ACTimer3x 16-bit Timer20B Backup Regs Independent WatchdogWindow Watchdog Reset Clock ControlSTM32F10x Technical Training V0.3Memory Mapping and Boot ModesBOOT Mode Selection Pins Boot Mode AliasingBOOT1BOOT0x0User FlashUser Flash is selected asboot space 01SystemMemory SystemMemory is selectedas boot space 11Embedded SRAMEmbedded SRAM is selected as boot spaceCODESRAMPeripherals0x0000 00000x2000 00000x4000 00000xE010 00000xFFFF FFFF ReservedReservedReservedBit-Band regionBoot modesDepending on the Boot configuration, Embedded Flash Memory, System Memory or Embedded SRAM Memory is aliased at @0x000x0800 00000x0801 FFFF0x1FFF F0000x1FFF F7FF FlashSystemMemoryReservedReservedOption Bytes 0x1FFF F8000x1FFF F9FF Addressable memory space of 4 GBytes RAM : up to 20 kBytes FLASH : up to 128 kBytesSystemMemory : contains the Bootloader used to re-program the FLASH through USART .Boot from SRAM :In the application initialization code you have to Relocate the Vector Table in SRAM using the NVIC Exception Table and Offset registerCortex-M3 internal peripherals0xE000 00000xE00F FFFF ReservedSTM32F10x Technical Training V0.3System ArchitectureMultiply possibilities of bus accesses to SRAM, Flash, Peripherals, DMABusMatrix added to Harvard architecture allows parallel accessEfficient DMA and Rapid data flowDirect path to SRAM through arbiter , guarantees alternating accessHarvard architecture + BusMatrix allows Flash execution in parallel with DMA transferIncrease Peripherals Speed for better performanceDual Advanced Peripheral buses (APB) architecture w/ High Speed APB (APB2) up to 72MHz and Low Speed APB (APB1) up to 36MHzAllows to optimize use of peripherals (18MHz SPI, 4.5Mbps USART , 72MHz PWM Timer , 18MHz toggling I/Os)Buses are not overloaded with data movement tasksBusMatrixSystemD-busI-busCORTEX-M3Master 1GP-DMA Master 2SRAM SlaveFLASHF L I T FAHB-APB2AHB-APB1AHBGPIOA,B,C,D,E -AFIO –USART1-SPI1 -ADC1,2 -TIM1 -EXTI BridgesAPB1APB2Arbiter USART2,3 -SPI2 -I2C1,2 –TIM2,3,4 -IWDG –WWDG –USB –CAN –BKP –PWR –CONTENTSObjectivesSTM32F10x DeviceBlock DiagramMemory mapping and boot modesSystem ArchitectureSTM32F10x PeripheralsMain featuresSTM32F10x USB Developer kitSTM32F10x Firmware LibraryPackage organizationCoding conventionsLibrary structureUsing the LibrarySTM32F10x Technical Training V0.3STM32F10x Technical Training V0.3STM32F10x Series Block DiagramClick on Periph to jump to the corresponding slideCORTEXM3CPU72 MHzUp to 20kB SRAM64kB to come e/o 2007A R M P e r i p h e r a lB u s(m a x 72M H z )2x 12-bit ADC16 channels / 1Msps2x I 2C1x SPI 2x USART/LINSmartcard / IrDa Modem Control32/49/80 I/OsUp to 16 Ext. ITs F l a s h I /F32kB-128kB Flash Memory512kB to come e/o2007Temp Sensor1x USB 2.0FS 1x bxCAN 2.0B 1x 16-bit PWMSynchronized AC TimerIndependent Watchdog 3x 16-bit TimerJTAG/SW Debug XTAL oscillators32KHz + 4~16MHzPower SupplyReg 1.8VPOR/PDR/PVD DMA7 ChannelsNested vect IT Ctrl 1x USART/LINSmartcard/IrDa Modem-Ctrl1x SPI Bridge Bridge1x Systic TimerA R M L i t e H i -S p e e dB u s M a t r i x / A r b i t e r (m a x 72M H z )Int. RC oscillators32KHz + 8MHzPLLReset Clock ControlRTC / AWUARM Peripheral Bus(max 36MHz)20B Backup Regs Window WatchdogEmbedded FLASH STM32F10x Technical Training V0.3Flash Features Overview Flash Features:Up to 128KBytes1 KByte Page sizeEndurance: 1000 cyclesMemory organization:Main memory blockInformation blockAccess time: 35nsWord(32-bit) program time: 20μsPage / Mass Erase Time: 20msFlash interface Features:Read Interface with pre-fetch bufferOption Byte loaderFlash program/Erase operationsTypes of Protection:Access ProtectionWrite ProtectionSTM32F10x Technical Training V0.3Flash OperationsThe Flash program and erase operations are handled by the Flash program and erase controller (FPEC)After reset the FPEC is protected, an unlocking sequence should be performed (write of 2 key values) to unlock the FlashThe Flash can be programmed with 16-bits at a timeFlash can be erased page-wise or completely: Mass EraseThe Read access can be performed with the following configuration: Latency: Number of wait state for a read operation programmable on the flyPrefetch buffer of 2x64bit: For faster CPU execution can be enabled and disabled on the flyHalf Cycle: Flash access can be made on a half cycle of the HCLK to reduce powerconsumption, enabled by softwareSTM32F10x Technical Training V0.3Information BlockThe Information Block consists of:2 KBytes for Big Information block (BIF): contains Bootloader512 Bytes for Small Information block (SIF): contains the user option bytes.6 option bytes (SIF Block) are available:4 for write protection1 for read protection1 for configuration:IWDG HW/SW modeReset when entering STANDBY modeReset when entering STOP modeAfter unlocking the FPEC, the user has to authorize the small info blockprogramming by writing 2 key values then he can program the Option bytesOn every reset, the option bytes loader performs a read of the information block and stores the data into the FPEC registers (when programmed the option bytes are taken into account only after reset).STM32F10x Technical Training V0.3Flash Protection(1/2)Two kind of protections are available:Write protection to avoid unwanted writingsReadout protection to avoid piracyActivated by setting option bytes in the Small Information Block (SIF)Readout protection:The following Flash access are not allowed: read data in Flash memory through DCODE bus (main and information blocks) from others memory, from debugger or from DMA.Pages 0-3 are automatically write protected, to avoid the reprogramming of the Reset Vector to make it jump to RAM to execute untrusted code.Unprotection:Erase the entire Small Information block (User part)The result of Readout protection code (RDP) will be 0xFF, the read protection will be still enableProgram the correct code 0xA5 of RDP to unprotect the memory, this operation will first force a MassErase of the main blockReset the device (System Reset) to re-load the options bytes (and the new RDP code), and disable theReadout protectionSTM32F10x Technical Training V0.3Flash Protection(2/2)Write ProtectionThe write protection is implemented with a choice of protecting 4 pages (4K) at a timeA total of 4 user Options bytes are used to protect all the 128K main FlashAny programming or erase of a protected page is discarded and the Flash will return protection error flag on FSR status registerUnprotection:Erase the entire Small Information block (User part)The result of Readout protection code (RDP) will be 0xFF , the readout protection is enabledProgram the correct code 0xA5 of RDP to disable read protectionReset the device (System Reset) to re-load the options bytes for disabling any write protectionSTM32F10x Technical Training V0.3Direct Memory Access (DMA) STM32F10x Technical Training V0.3DMA Features7 independently configurable channels: hardware requests or software triggeron each channelSoftware programmable priorities: Very high, High, Medium or Low. (Hardware priority in case of equality)Programmable and Independent source and destination transfer data size: Byte, Halfword or Word3 event flags for each channel: DMA Half Transfer, DMA Transfer complete andDMA Transfer ErrorMemory-to-memory, peripheral-to-memory and memory-to-peripheraltransfersFaulty channel is automatically hardware disabled in case of bus access error Programmable number of data to be transferred: up to 65536Support for circular buffer managementSTM32F10x Technical Training V0.3STM32F10x Technical Training V0.3DMA Request MappingD M ASW TRIGGER DMA REQUESTOR ADC1TIM2_CC3TIM4_CC1SW TRIGGER OR USART3_TX SW TRIGGER OR SW TRIGGER OR SW TRIGGER OR SW TRIGGER ORSW TRIGGERORHigh Priority RequestLow Priority RequestThe DMA controller provides access to 7 channelsChannel1Channel2Channel3Channel4Channel5Channel6Channel7TIM1_CC1TIM2_UPTIM3_CC3SPI1_RX USART3_RXTIM1_CC2SPI1_TXTIM3_CC4TIM3_UPSPI2_RXI2C2_TXTIM1_CC4USART1_TXTIM1_CCU TIM1_TRIGTIM4_CC2USART1_RX TIM1_UP SPI2_TX I2C2_RXTIM2_CC1TIM4_CC3USART2_RXTIM1_CC3TIM3_CC1I2C1_TXTIM3_TRIGUSART2_TXTIM2_CC2TIM2_CC4TIM4_UPI2C1_RXSTM32F10x Technical Training V0.3The latency between two DMA transferRequest1 sample & arbitration phaseBus access Address computation Acknowledgement phase1 cycle1 cycle 3 cycle 1 cycleRequest 16 cycles for each request (source and destination on AHB)Request2 sample & arbitration phaseRequest 2If source or destination is a peripheral on APB, Bus access will include more cycles due to the AHB/APB bridge latency depending on the AHB/APB ratio.STM32F10x Technical Training V0.3To improve the DMA performances, a new request can be served while the previous one isrunning : if a request is active and other ones are pending, the new request sample & arbitration phase is performed during AHB bus access of the current request. The winning request AHB bus access will start immediately after the end of the current request…s AHB Bus access.Request 1 sample & arbitration phaseAcknowledgephaseHCLKChannel 1Request 2 sample & arbitration phaseAddresscomputationRequest 1 sample & arbitration phaseAddresscomputationAddresscomputationChannel 2Bus accessBus accessBus accessAcknowledgephaseAcknowledgephaseSTM32F10x Technical Training V0.3DMA and Bus occupationRequest, arbitration and acknowledgement operations are done outside AHB system bus, so the bus is not occupied during those phasesOne DMA access takes 2 cycles: the system Bus can not be totally freeze by DMA as at least one cycle is left to the CPU between two consecutive transactions. So up to 66%of the total bus bandwith available for DMA accesses.Current DMA controller compared to others which permit burst transfer have nearly thesame system bus occupation rate. However , it doesn‟t freeze the bus for many cyclesconsecutively as it is the case with the burst mode: better performance with many small data transfer without blocking the busRead Write Read Write Read WriteRead WriteBus accessBus accessBus free for CPUAHB Control AHB DataQuizHow many DMA Channels are available in the STM32F10x ?____________List the peripherals which have a DMA interface?____________How many interrupts can be generated for each channel?____________Which Channel is able to perform Memory to Memory transfer?____________STM32F10x Technical Training V0.3Power Control (PWR) and Backup Domain (BKP) STM32F10x Technical Training V0.3STM32F10x Technical Training V0.3Power SupplyA/D converter Temp. sensor Reset block PLLV DDAdomainLSE crystal 32K osc BKP registersRCC BDCR register RTCBackup domainCoreMemories DigitalperipheralsV 18domainV DD domainSTANDBY circuitry (Wake-up logic,IWDG, RCC CSR reg)Voltage RegulatorI/O Rings V SS V DDV BAT V DDA V SSAV REF-V REF+Low Voltage DetectorPower Supply SchemesV DD = 2.0 to 3.6 V: External Power Supply for I/Os and the internal regulator .V DDA = 2.0 to 3.6 V: External Analog Power supplies for ADC, Reset blocks, RCs and PLL. ADC working only if V DDA ≥ 2.4 VV BAT = 2.0 to 3.6 V: For Backup domain when V DD is not present.Power pins connection:V DD and V DDA must be connected to the same power sourceV SS , V SSA and V REF-must be tight to ground 0V < V REF+≤ V DDAV REF+and V REF-available only in LQFP100 package, in other packages they are internally connected respectively to V DDA and V SSAPower On Reset (POR)/Power Down Reset (PDR)Integrated POR / PDR circuitry guarantees proper product reset when voltage is not in the product guaranteed voltage range (2V to 3.6V)No need for external reset circuitPOR and PDR have a typical hysteresis of 40mVVDDPORPDR40mv hysteresisResetVtrhVtrlTempo2msVtrl min 1.8V / Vtrh max 2VSTM32F10x Technical Training V0.3STM32F10x Technical Training V0.3Programmable Voltage Detector (PVD)Programmable Voltage DetectorEnabled by softwareMonitor the V DD power supply by comparing it to a thresholdThreshold configurable from 2.2V to 2.9V by step of 100mVGenerate interrupt through EXTI Line16 (if enabled) when VDD < Threshold and/or VDD < ThresholdCan be used to generate a warning message and/or put the MCU into a safe stateVDD100mv hysteresisPVD OutputPVD ThresholdBackup DomainBackup Domain containsRTC (Counter , Prescaler and Alarm mechanism)Separate 32KHz Osc (LSE) for RTC10 x 16-bits user backup registersRCC BDSR register: RTC source clock selection and enable + LSE configReset only by Backup domain RESETV BAT independent voltage supplyAutomatic switch-over to V BAT when V DD goes lower than PDR levelNo current sunk on V BAT when V DD presentT amper detection: resets all user backup registers Configurable level: low/highConfigurable interrupt generationBackup domain32KHz OSC(LSE)RTC10 x 16regANTI_TAMPV BATV DDRCC BDSRregpower switchSTM32F10x Technical Training V0.3STM32F10x Low Power modes: uses CortexM3 Sleep modesWFI, WFE, STOP and STANDBY modesThe reset circuitry, POR/PDR, is active in STANDBY and STOP modesFeature STM32F10x typConsumption in RUN mode w/ execute from Flash on10mAinternal RC and peripherals clock ON36mAConsumption in RUN mode w/ execute from Flash onPLL 72 MHz( internal RC) and peripherals clock ON32mAConsumption in RUN mode w/ execute from SRAM onPLL 72 MHz( internal RC) and peripherals clock ONSTOP w/ Voltage Regulator in low power7µASTANDBY (w/ RTC OFF)2µARTC on VBAT 1.5 µAThe mA/MHz is higher at low frequency because of some static consumption (regulator, oscillator, Flash) SRAM execution is low power than Flash executionSTM32F10x Technical Training V0.3WFI/WFE Modes : Core stopped, peripherals kept runningWFI (Wait For Interrupt)Entry: execute WFI instructionExit: any peripheral interrupt acknowledged by the Nested Vectored Interrupt Controller (NVIC) WFE (Wait For Event)An event can be an interrupt enabled in the peripheral control register but NOT in the NVIC or an EXTIline configured in event modeEntry: execute WFE instructionExit: as soon as the event occurs No time wasted in interrupt entry/exitTwo mechanisms to enter these modesSleep Now: MCU enters Sleep mode as soon as WFI/WFE instruction are executedSleep on Exit: MCU enters Sleep mode as soon as it exits the lowest priority ISR (WFI/WFE instructionsare written in the ISR)To further reduce power consumption you can save power of unused peripherals by gating their clockSTM32F10x Technical Training V0.3STOP Mode: all periph clocks, PLL, HSI and HSE are disabled, SRAM and register contents are preserved.If the RTC and IWDG are running they are not stopped in STOP (either as their clocksources)To further reduce power consumption the Voltage Regulator can be put in Low Power mode Wake-up sources:WFI was used for entry: any EXTI Line configured in Interrupt mode (the corresponding EXTI Interruptvector must be enabled in the NVIC)WFE was used for entry: any EXTI Line configured in event modeEXTI line source can be: one of the 16 external lines, PVD, RTC alarm, USB wake-upAfter resuming from STOP the clock configuration returns to its reset state (HSI used as system clock).STM32F10x typWake-up time from Stop mode on HSI RC at8MHzRegulator in run mode 4 µsRegulator in low power mode9 µsSTM32F10x Technical Training V0.3Low Power Modes (4/4)STANDBY Mode : Voltage Regulator off, the entire V18 domain is powered off.SRAM and register contents are lost except registers in the Backup domain and STANDBY circuitryRTC and IWDG are kept running in STANDBY (if enabled)In STANDBY mode all IO pins are high impedance exceptReset pad (still available)Anti-Tamper pin if configured for tamper or calibration outWKUP pin if enabledWake-up sources:WKUP pin rising edgeRTC alarmExternal reset in NRST pinIWDG resetAfter wake-up from STANDBY mode, program execution will restart in the same way as after a RESET.Wake-up time from STANDBY mode on HSI RC at8MHz STM32F10x typ35 µsSTM32F10x Technical Training V0.3QuizHow many power supply domains are available?____________What is the content of the BKP domain?____________What is the difference between “Sleep Now” and “Sleep on Exit” modes?____________What are the wake-up sources from STOP mode?____________STM32F10x Technical Training V0.3Reset and Clock Control (RCC) STM32F10x Technical Training V0.3RESET Sources System RESETResets all registers except someRCC registers and BKP domain SourcesLow level on the NRST pin (ExternalReset)WWDG end of count conditionIWDG end of count conditionA software reset (through NVIC)Low power management ResetFilterV DDR ONPULSEGENERATOR(min 20µs)SYSTEM NRESET NRSTWWDG RESETIWDG RESETSoftware RESETPOR/PDR RESETLow powermanagement RESET ExternalRESETPower RESETResets all registers except BKP domainSourcesPower On/Power down Reset (POR/PDR)The internal voltage regulator is powered offby the application (this occurs when theMCU enters STANDBY mode)Backup domain RESETResets all BKP domainSourcesSetting BDRST bit in RCC BDCR registerVDD or VBAT power on, if both supplieshave previously been powered off.STM32F10x Technical Training V0.3On Chip OscillatorsMultiple clock sources for full flexibility in RUN/Low Power modesHSE (High Speed External oscillator): 4MHz to 16MHz main osc which can be multiplied by the PLL to provide a wide range of frequencies→Can be bypassed with external clockHSI (High Speed Internal RC): factory trimmed internal RC oscillator 8MHz +/-1% over 0-70°C temp rangeFeeds System clock after reset or exit from STOP mode for fast startup (startup time : 2us max)Backup clock in case HSE osc is failingLSI (Low Speed Internal RC): 32KHz internal RC for IWDG and optionally for the RTCused for Auto Wake-Up (AWU) from STOP/STANDBY modeLSE (Low Speed External oscillator): 32.768kHz osc provides a precise time base with very low power consumption (max 1µA). Optionally drives the RTC for Auto Wake-Up(AWU) from STOP/STANDBY mode.→Can be bypassed with external clockSTM32F10x Technical Training V0.3STM32F10x Technical Training V0.3Clock SchemeSystem Clock (SYSCLK) sources✓HSI ✓HSE ✓PLL Configurable dividers provides AHB, APB1/2, ADC and TIM clocksRTC Clock (RTCCLK) sources✓LSE ✓LSI✓HSE clock divided by 128USB Clock (USBCLK) provided from the internal PLLClock Security System (CSS) to backup clock in case of HSE clock failure (HSI feeds the system clock)Enabled by SW w/ interrupt capability linked to Cortex NMIClock-out capability on the MCO pin (PA.08) / max 50MHzTIMxCLKAPB1 Prescaler /1,2,4,8,16AHB Prescaler /1,2 (512)TIM2,3,4 x1, 2 multPCLK1 up to 36MHz TIM1CLKAPB2 Prescaler /1,2,4,8,16TIM1 x1, 2 multPCLK2 up to 72MHzADC Prescaler /2,4,6,8ADCCLK HCLK up to 72MHzUSB Prescaler /1,1.5USBCLK 48MHzCSSHSE OscOSC_OUT OSC_IN4 -16 MHzup to 72MHzSYSCLK x2...x16 PLLPLLCLK HSI RC/2/28MHzSYSCLK HSIHSE PLLCLKMCO/2LSI RC32.768KHz/128LSE OScOSC32_IN OSC32_OUT~32KHzIWDGCLKRTCCLKQuizHow many types of Reset are available?____________What is the maximum AHB, APB1 and APB2 clock frequencies ?____________What are the clock sources that can feed the PLL input?____________What is the purpose of the CSS?____________STM32F10x Technical Training V0.3General Purpose and Alternate FunctionI/O (GPIO and AFIO)STM32F10x Technical Training V0.3GPIO Features80 multifunction bi-directional I/O ports available: 80% IO ratio80 Standard I/Os (5V tolerant, 20 mA drive)18 MHz TogglingConfigurable Output Speed up to 50 MHzUp to 16 Analog InputsAlternate Functions pins (like USARTx, TIMx, I2Cx, SPIx, CAN, USB…)All I/Os can be set-up as external interrupt (up to 16 lines at time)One I/O can be used as Wake-Up from STANDBY (PA.00)One I/O can be set-up as Tamper Pin (PC.13)All Standard I/Os are shared in 5 ports (GPIOA..GPIOE)Atomic Bit Set and Bit Reset using BSRR and BRR registersLocking mechanism to avoid spurious write in the IO registersWhen the LOCK sequence has been applied on a port bit, it is no longer possible to modify theconfiguration of the port bit until the next reset (no write access to the CRL and CRH registerscorresponding bit).STM32F10x Technical Training V0.3STM32F10x Technical Training V0.3GPIO Configuration ModesB i t S e t /R e s e t R e g i s t e r sI n p u t D a t a R e g i s t e rO u t p u t D a t a R e g i s t e rRead / WriteI /O p i nAnalog InputAlternate Function InputAlternate Function OutputTo On-chip PeripheralsFrom On-chip PeripheralsPush-Pull Open Drain TTL Schmitt TriggerOUTPUT CONTROLON VDD_IOVSSVDD_IOVSS ON/OFFON/OFFP u l l -U PP u l l -D o w nVDD_IO VSS OFFInput DriverOutput DriverReadConfiguration ModeCNF1CNF0MOD1MOD0Input Floating (Reset State)01Input Pull-Up 10Input Pull-Down10Output Push-Pull0000: Reserved 01: 10 MHz 10: 2 MHz 11: 50 MHzOutput Open-Drain01AF Push-Pull 10AFOpen-Drain11Analog Input 0000WriteDisabledAFIO FeaturesEvent Out signal generationPulse generation with SEV instruction: to wake-up an other MCU from low powermode through its Event In signalEach IO can be used as Event OutGPIO Software RemappingSome Alternate function can be remapped in two different pins allowing optimization of the pin outAll SWJ-DP I/O pins can be used as GPIOEXTI Lines ConfigurationEach EXTI line is shared with all GPIO ports: EXTI Linexx GPIO[A..E].xxSTM32F10x Technical Training V0.3QuizHow many ports are in the STM32F10x microcontroller ?____________List all the I/O configuration modes____________How many External interrupts and Wake-up pins, exist in the STM32F10x microcontroller?____________List some of the peripherals that have alternate function pins____________What is the purpose of the Event Out Signal____________STM32F10x Technical Training V0.3External Interrupt/Event Controller (EXTI) STM32F10x Technical Training V0.3STM32F10x Technical Training V0.3EXTI FeaturesUp to 19 Interrupt/Events requestsAll GPIO can be used as EXTI line(0..15)EXTI line 16 connected to PVD output EXTI line 17 connected to RTC Alarm eventEXTI line 18 connected to USB Wake-up from suspend eventIndependent trigger (rising, falling, rising & falling) and mask on each interrupt/event lineDedicated status bit for each interrupt lineGeneration of up to 19 software interrupt/event requestsMinimum Pulse Width : < 1*T PCLK2 (Fast APB)Two Configuration mode:Interrupt mode: generate interrupts with external lines edgesEvent mode: generate pulse to wake-up system from WFE and STOP modesEXTI mapped on High Speed APB (APB2) to save time entering in the External Interrupt routineE X T I [15:0]Interrupt MaskRegisterPending RequestRegisterSoftware Interrupt Event RegisterRising Trigger Selection RegisterTo NVICEdge Detect CircuitSynchro Stage FCLKPulse GeneratorFalling Trigger Selection RegisterEvent Mask Register。
