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IC41SV44052-100J中文资料

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IC41SV44054Document Title4Mx4 bit Dynamic RAM with Fast Page ModeRevision HistoryRevision No History Draft Date Remark0A Initial Draft June 14,2002Preliminary0B Chang working range from V CC=1.9V~2.4V July 31,2002to V CC=1.9V~2.7V, V IH=1.4V to V IH=1.6VThe attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.IC41SV440542Integrated Circuit Solution Inc.FEATURES•Fast Page Mode Access Cycle •TTL compatible inputs and outputs •Refresh Interval:-- 2,048 cycles/32 ms -- 4,096 cycles/64 ms•Refresh Mode: RAS -Only,CAS -before-RAS (CBR), and Hidden •JEDEC standard pinout •Single power supply:1.9V − 2.7VDESCRIPTIONThe ICSI 44052/44054 Series is a 4,194,304 x 4-bit high-performance CMOS Dynamic Random Access Memory. The Fast Page Mode allows 2,048 or 4,096 random accesses within a single row with access cycle time as short as 20 ns per 4-bit word.These features make the 44052/44054 Series ideally suited for digital signal processing, and low power portable audio applications.The 44052/44054 Series is packaged in a 26-pin 300mil SOJ and a 26 pin TSOP-24M x 4 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODEKEY TIMING PARAMETERSParameter-70-100Unit RAS Access Time (t RAC )70100ns CAS Access Time (t CAC )2025ns Column Address Access Time (t AA )3550ns Fast Page Mode Cycle Time (t PC )4560ns Read/Write Cycle Time (t RC )130180nsICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.PIN DESCRIPTIONSA0-A11Address Inputs (4K Refresh)A0-A10Address Inputs (2K Refresh) I/O0-3Data Inputs/Outputs WE Write Enable OE Output Enable RAS Row Address Strobe CAS Column Address Strobe Vcc Power GNDGroundPIN CONFIGURATION 24 (26) Pin SOJ, TSOP -2Preliminary*A11 is NC for 2K Refresh devices.IC41SV44054FUNCTIONAL BLOCK DIAGRAMTRUTH TABLEFunction RAS CAS WE OE Address t R/t C I/O Standby H H X X X High-Z Read L L H L ROW/COL D OUT Write: Word (Early Write)L L L X ROW/COL D IN Read-Write L L H→L L→H ROW/COL D OUT, D IN Hidden Refresh Read L→H→L L H L ROW/COL D OUTWrite(1)L→H→L L L X ROW/COL D IN RAS-Only Refresh L H X X ROW/NA High-Z CBR Refresh H→L L X X X High-Z Note:1.EARLY WRITE only.IC41SV440544Integrated Circuit Solution Inc.Functional DescriptionThe IC41SV44052 and IC41LV44054 are CMOS DRAMs optimized for high-speed bandwidth, low power applications.During READ or WRITE cycles, each bit is uniquely addressed through the 11 or 12 address bits. These are entered 11 bits (A0-A10) at a time for the 2K refresh device or 12 bits (A0-A11) at a time for the 4K refresh device. The row address is latched by the Row Address Strobe (RAS ).The column address is latched by the Column Address Strobe (CAS ). RAS is used to latch the first nine bits and CAS is used the latter ten bits.Memory CycleA memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum t RAS time has expired. A new cycle must not be initiated until the minimum precharge time t RP ,t CP has elapsed.Read CycleA read cycle is initiated by the falling edge of CAS or OE ,whichever occurs last, while holding WE HIGH. The col-umn address must be held for a minimum time specified by t AR . Data Out becomes valid only when t RAC , t AA , t CAC and t OEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters.Write CycleA write cycle is initiated by the falling edge of CAS and WE ,whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE , whichever occurs last.Refresh CycleTo retain data, 2,048 refresh cycles are required in each 32 ms period, or 4,096 refresh cycles are required in each 64ms period. There are two ways to refresh the memory:1.By clocking each of the 2,048 row addresses (A0through A10) or 4096 row addresses (A0 through A11)with RAS at least once every 32 ms or 64ms respectively.Any read, write, read-modify-write or RAS-only cycle refreshes the addressed ing a CAS -before-RAS refresh cycle. CAS -before-RAS refresh is activated by the falling edge of RAS ,while holding CAS LOW. In CAS -before-RAS refresh cycle, an internal 11(12)-bit counter provides the row addresses and the external address inputs are ignored.CAS -before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle.Power -OnAfter application of the V CC supply, an initial pause of 200 µs is required followed by a minimum of eight initializa-tion cycles (any combination of cycles containing a RAS signal).During power-on, it is recommended that RAS track with V CC or be held at a valid V IH to avoid current surges.IC41SV44054ABSOLUTE MAXIMUM RATINGS(1)Symbol Parameters Rating UnitV T Voltage on Any Pin Relative to GND−0.5 to +3.0VV CC Supply Voltage−0.5 to +3.0VI OUT Output Current50mAP D Power Dissipation0.2WT A Commercial Operation Temperature-10 to +70o CT STG Storage Temperature−55 to +125o CNote:1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanentdamage to the device. This is a stress rating only and functional operation of the device at theseor any other conditions above those indicated in the operational sections of this specification isnot implied. Exposure to absolute maximum rating conditions for extended periods may affectreliability.RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.) Symbol Parameter Min.Max.Unit V CC Supply Voltage 1.9 2.7V V IH Input High Voltage 1.6V CC + 0.3V V IL Input Low Voltage−0.30.6V T A Commercial Ambient Temperature-1070o CCAPACITANCE(1,2)Symbol Parameter Max.UnitC IN1Input Capacitance: A0-A105pFC IN2Input Capacitance: RAS, CAS, WE, OE7pFC IO Data Input/Output Capacitance: I/O0-I/O37pFNotes:1. Tested initially and after any design or process changes that may affect these parameters.2. Test conditions: T A = 25o C, f = 1 MHz.IC41SV44054ELECTRICAL CHARACTERISTICS(1)(Recommended Operating Conditions unless otherwise noted.)Symbol Parameter Test Condition Speed Min.Max.UnitI IL Input Leakage Current Any input 0V ≤ V IN≤ Vcc−55µAOther inputs not under test = 0VI IO Output Leakage Current Output is disabled (Hi-Z)−55µA0V ≤ V OUT≤ VccV OH Output High Voltage Level I OH = −2.0 mA 1.6−V V OL Output Low Voltage Level I OL = 2 mA−0.8VI CC1Standby Current: TTL RAS, CAS≥ V IH−1mAI CC2Standby Current: CMOS RAS, CAS≥ V CC− 0.2V0.5mAI CC3Operating Current:RAS, CAS,-70−60mARandom Read/Write(2,3,4)Address Cycling, t RC = t RC (min.)-100−50Average Power Supply CurrentI CC4Operating Current:RAS = V IL, CAS ≥ V IH-70−45mAFast Page Mode(2,3,4)t RC = t RC (min.)-100−35Average Power Supply CurrentI CC5Refresh Current:RAS Cycling, CAS≥ V IH-70−60mARAS-Only(2,3)t RC = t RC (min.)-100−50Average Power Supply CurrentI CC6Refresh Current:RAS, CAS Cycling-70−60mACBR(2,3,5)t RC = t RC (min.)-100−50Average Power Supply CurrentNotes:1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper deviceoperation is assured. The eight RAS cycles wake-up should be repeated any time the t REF refresh requirement is exceeded.2. Dependent on cycle rates.3. Specified values are obtained with minimum cycle time and the output open.4. Column-address is changed once each Fast page cycle.5. Enables on-chip refresh and address counters.6Integrated Circuit Solution Inc.IC41SV44054AC CHARACTERISTICS(1,2,3,4,5,6)(Recommended Operating Conditions unless otherwise noted.)-70-100Symbol Parameter Min.Max.Min.Max.Units t RC Random READ or WRITE Cycle Time130−180−ns t RAC Access Time from RAS(6, 7)−70−100ns t C A C Access Time from CAS(6, 8, 15)−20−25ns t AA Access Time from Column-Address(6)−35−50ns t RAS RAS Pulse Width7010K10010K ns t RP RAS Precharge Time50−70−ns t CAS CAS Pulse Width(23)2010K2510K ns t CP CAS Precharge Time(9)10−10−ns t CSH CAS Hold Time (21)70−100−ns t RCD RAS to CAS Delay Time(10, 20)20502575ns t ASR Row-Address Setup Time0−0−ns t RAH Row-Address Hold Time10−15−ns t ASC Column-Address Setup Time(20)0−0−ns t CAH Column-Address Hold Time(20)15−20−ns t AR Column-Address Hold Time70−100−ns (referenced to RAS)t RAD RAS to Column-Address Delay Time(11)15352050ns t RAL Column-Address to RAS Lead Time35−50−ns t RPC RAS to CAS Precharge Time5−5−ns t RSH RAS Hold Time20−25−ns t CLZ CAS to Output in Low-Z(15, 24)3−3−ns t CRP CAS to RAS Precharge Time(21)5−5−ns t OD Output Disable Time(19, 24)320325ns t OE Output Enable Time(15, 16)-20-25ns t OES OE LOW to CAS HIGH Setup Time5−5−ns t RCS Read Command Setup Time(17, 20)0−0−ns t RRH Read Command Hold Time0−0−ns (referenced to RAS)(12)t RCH Read Command Hold Time0−0−ns (referenced to CAS)(12, 17, 21)t WCH Write Command Hold Time(17)10−15−ns t WCR Write Command Hold Time70−100−ns (referenced to RAS)(17)t WP Write Command Pulse Width(17)10−15−ns t RWL Write Command to RAS Lead Time(17)20−25−ns t CWL Write Command to CAS Lead Time(17, 21)20−25−ns t WCS Write Command Setup Time(14, 17, 20)0−0−ns t DHR Data-in Hold Time (referenced to RAS)50−60−nsIC41SV44054AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)(Recommended Operating Conditions unless otherwise noted.)-70-100Symbol Parameter Min.Max.Min.Max.Unitst ACH Column-Address Setup Time to CAS15−15−ns Precharge during WRITE Cyclet OEH OE Hold Time from WE during20−25−ns READ-MODIFY-WRITE cycle(18)t DS Data-In Setup Time(15, 22)0−0−nst DH Data-In Hold Time(15, 22)15−20−nst RWC READ-MODIFY-WRITE Cycle Time185−240−nst RWD RAS to WE Delay Time during100−130−ns READ-MODIFY-WRITE Cycle(14)t CWD CAS to WE Delay Time(14, 20)45−55−nst AWD Column-Address to WE Delay Time(14)60−85−nst PC Fast Page Mode READ or WRITE45−60−ns Cycle Timet RASP Fast Page Mode RAS Pulse Width70100K100100K nst CPA Access Time from CAS Precharge(15)−40−55nst PRWC Fast Page Mode READ WRITE100−120−ns Cycle Timet OFF Output Buffer Turn-Off Delay from315315ns CAS or RAS(13,15,19, 24)t CSR CAS Setup Time (CBR REFRESH)(20, 25)5−5−nst CHR CAS Hold Time (CBR REFRESH)( 21, 25)10−10−nst ORD OE Setup Time prior to RAS during0−0−ns HIDDEN REFRESH Cyclet REF Auto Refresh Period 2,048 Cycles −32−32ms Auto Refresh Period 4,096 Cycles−64−64mst T Transition Time (Rise or Fall)(2, 3)350350nsAC TEST CONDITIONSOutput load:One TTL Load and 100 pFInput timing reference levels:V IH = 1.6V, V IL = 0.6VOutput timing reference levels: V OH = 1.6V, V OL = 0.8V8Integrated Circuit Solution Inc.IC41SV44054Notes:1.An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper deviceoperation is assured. The eight RAS cycles wake-up should be repeated any time the t REF refresh requirement is exceeded. 2.V IH (MIN) and V IL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V IHand V IL (or between V IL and V IH) and assume to be 1 ns for all inputs.3.In addition to meeting the transition rate specification, all input signals must transit between V IH and V IL (or between V IL and V IH)in a monotonic manner.4.If CAS and RAS = V IH, data output is High-Z.5.If CAS = V IL, data output may contain data from the last valid READ cycle.6.Measured with a load equivalent to one TTL gate and 50 pF.7.Assumes that t RCD≤ t RCD (MAX). If t RCD is greater than the maximum recommended value shown in this table, t RAC will increaseby the amount that t RCD exceeds the value shown.8.Assumes that t RCD≥ t RCD (MAX).9.If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear thedata output buffer, CAS and RAS must be pulsed for t CP.10.Operation with the t RCD (MAX) limit ensures that t RAC (MAX) can be met. t RCD (MAX) is specified as a reference point only; if t RCDis greater than the specified t RCD (MAX) limit, access time is controlled exclusively by t CAC.11.Operation within the t RAD (MAX) limit ensures that t RCD (MAX) can be met. t RAD (MAX) is specified as a reference point only; if t RADis greater than the specified t RAD (MAX) limit, access time is controlled exclusively by t AA.12.Either t RCH or t RRH must be satisfied for a READ cycle.13.t OFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to V OH or V OL.14.t WCS, t RWD, t AWD and t CWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If t WCS≥ t WCS(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If t RWD≥ t RWD (MIN), t AWD≥ t AWD (MIN) and t CWD≥ t CWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to V IH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.15.Output parameter (I/O) is referenced to corresponding CAS input.16.During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, aLATE WRITE or READ-MODIFY-WRITE is not possible.17.Write command is defined as WE going low.TE WRITE and READ-MODIFY-WRITE cycles must have both t OD and t OEH met (OE HIGH during WRITE cycle) in order to ensurethat the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after t OEH is met.19.The I/Os are in open during READ cycles once t OD or t OFF occur.20.Determined by falling edge of CAS.21.Determined by rising edge of CAS.22.These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-MODIFY-WRITE cycles.23.CAS must meet minimum pulse width.24.The 3 ns minimum is a parameter guaranteed by design.25.Enables on-chip refresh and address counters.IC41SV4405410Integrated Circuit Solution Inc.READ CYCLENote:1.t OFF is referenced from rising edge of RAS or CAS , whichever occurs last.IC41SV44054READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)IC41SV44054EARLY WRITE CYCLE (OE = DON'T CARE)12Integrated Circuit Solution Inc.IC41SV44054FAST PAGE MODE READ CYCLEIC41SV44054FAST PAGE MODE EARLY WRITE CYCLE14Integrated Circuit Solution Inc.IC41SV44054FAST PAGE MODE READ WRITE CYCLE (LATE WRITE AND READ-MODIFY-WRITE CYCLE)RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)IC41SV4405416Integrated Circuit Solution Inc.HIDDEN REFRESH CYCLE (1) (WE = HIGH; OE = LOW)CBR REFRESH CYCLE (Addresses; WE , OE = DON'T CARE)Notes:1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.2.t OFF is referenced from rising edge of RAS or CAS , whichever occurs last.IC41SV44054ORDERING INFORMATIONCommercial Range: -10°C to 70°CVoltage: 2.2VSpeed (ns)Order Part No.Package70IC41SV44052-70J300mil SOJ70IC41SV44052-70T300mil TSOP-270IC41SV44052-70JG300mil SOJ Pb-free70IC41SV44052-70TG300mil TSOP-2 Pb-free100IC41SV44052-100J300mil SOJ100IC41SV44052-100T300mil TSOP-2100IC41SV44052-100JG300mil SOJ Pb-free100IC41SV44052-100TG300mil TSOP-2 Pb-freeSpeed (ns)Order Part No.Package70IC41SV44054-70J300mil SOJ70IC41SV44054-70T300mil TSOP-270IC41SV44054-70JG300mil SOJ Pb-free70IC41SV44054-70TG300mil TSOP-2 Pb-free100IC41SV44054-100J300mil SOJ100IC41SV44054-100T300mil TSOP-2100IC41SV44054-100JG300mil SOJ Pb-free100IC41SV44054-100TG300mil TSOP-2 Pb-freeIntegrated Circuit Solution Inc.HEADQUARTER:NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,HSIN-CHU, TAIWAN, R.O.C.TEL: 886-3-5780333Fax: 886-3-5783000BRANCH OFFICE:7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.TEL: 886-2-26962140FAX: 886-2-26962252。

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414J;中文规格书,Datasheet资料

414J;中文规格书,Datasheet资料


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414 J
DC axial compact fan
Product drawing
Web data sheet XI · Page 3 of 4 ebm-papst St. Georgen GmbH & Co. KG · Hermann-Papst-Straße 1 · D-78112 St. Georgen · Phone +49 7724 81-0 · Fax +49 7724 81-1309 · info2@ ·
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414 J
DC axial compact fan
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Web data sheet XI · Page 4 of 4 ebm-papst St. Georgen GmbH & Co. KG · Hermann-Papst-Straße 1 · D-78112 St. Georgen · Phone +49 7724 81-0 · Fax +49 7724 81-1309 · info2@ ·
414 J
DC axial compact ቤተ መጻሕፍቲ ባይዱan
ebm-papst St. Georgen GmbH & Co. KG Hermann-Papst-Straße 1 D-78112 St. Georgen Phone +49 7724 81-0 Fax +49 7724 81-1309 info2@
M52778SP中文资料

M52778SP中文资料

MITSUBISHI ICs (TV)M52778SP VIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCMITSUBISHI ICs (TV)M52778SPVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCABSOLUTE MAXIMUM RATINGSI 2 C BUS DEFAULT CONDITION OF ALL BLOCKS IN M52778SP∗ Please refer to the following sub-address data for each parameter you measure.ELECTRICAL CHARACTERISTICS (Ta=25 ° C, pin8 and pin24:5V supply/pin9 and pin20:8V supply unless otherwise noted.)Symbol ParameterRatings Unit V CC Supply voltage 6.0, 9.0V P d Power dissipation1.69W T opr Operating temperature -20 to +65 ° C T stg Storage temperature -40 to +150 ° C S urgeElectrostatic discharge-200 to +200Vsub address 00H 01H02H03H04H 05H 06H07Hfunction DLA P/N VCOA AVSW4.5/6.0DFA TRF2 DBF TRAP VidG A TTSHARP DEFE CONT DLT A TV/EXT AUTO TINT AllBlocksDATA 20H 20H 00H 40H 00H 20H 02H 40H function 3203200000064003220064sub address 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H12H13Hfunction COLOR SET HP BRI DR MUTE DB CR CG CB V-PO TRF HASUBPO ACL SER HST AFCGACL AllBlocksDATA 20H 40H 20H 20H 20H 10H 10H 10H 60H 00H 40H function 320832320321616160110100SymbolParameterInput signal SWTest conditionsLimitsUnit NoteS 4S 16S 44S 45Sub address function V CCInputSG PINP 1P 3P 4P 12P 13P 16P 18P 19P 46P 48P 5200H 01H03H P 8P 9P 20P24Min.T yp.Max.DL A P/N VC OA AVSWATTSupply current − Default conditions of supply current −− SW 110020H 20H 40H −−−−PIN 320320645V 8V 8V 5VI CC8I CC24 Pin8, 24supply current −− SW 70110 150mA PIN8+PIN24PIN M MI CC9 Pin9supply current −− SW 50 60 70mA PIN MI CC20 Pin20supply current−−SW 5.5 10.0 15.0mAPIN MVIF block−Default conditions of VIF−− SW 110020H 20H 00H −−−− PIN 3203205V 8V 8V 5VVdc NEG Video detector output DC voltage (NEG) −− SW 4.3 4.7 5.1V PINGNDMVdc POS Video detector output DC voltage (POS) −−SW 60H1.62.0 2.4V PINGNDM 1Vo NEG Video detector output AC voltage (NEG) V SG1SW 0 1.9 2.2 2.5V PIN MVo POS Video detector output AC voltage (POS)V SG2SW 060H1.92.2 2.5V PIN M1P/N Video S/N V SG3SW 050 55 − dB PIN MV fVideo frequency characteristicsVSG4SW 04.55.5−MHzPINMMITSUBISHI ICs (TV)M52778SPVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSC ELECTRICAL CHARACTERISTICS (cont.)Symbol Parameter Input signal SWT est conditionsLimitsUnit Note S4S16S44S45Sub address function V CCInput SG PINP1P3P4P12P13P16P18P19P46P48P5200H01H03HP8P9P20P24Min.T yp.Max.DLAP/NVCOAAVSWA TTVin min Input sensitivity V SG5SW0− 47 52dBµPIN MVin max Maximumpermissible inputV SG6SW0102 107−dBµPIN MGR AGC controlrange−−SW50 60−dBµcalcu-late PINV4H Maximum IFAGC voltage−−SW04.0 4.4 4.8VPIN MV4T IF AGC voltage(80dBu)V SG7SW02.2 2.63.0VPIN MV4L Minimum IFAGC voltageV SG8SW01.5 1.92.3VPIN MV1AFT defeatvoltage−−SW3.74.0 4.3VPIN MµAFT N AFT detectorsensitivity (NEG)V SG9SW043 61 79mV/kHz PIN MV1H N Maximum AFTvoltage (NEG)V SG10SW7.2 7.7−VPIN MV1L N Minimum AFTvoltage (NEG)V SG11SW− 0.3 0.8V PIN MV3H Maximum RFAGC voltageV SG3SW7.2 7.7−VPIN MV3L Minimum RFAGC voltageV SG8SW− 0.3 0.8V PIN MCRU Capture range(upper)V SG9SW0.8 1.2−MHzPIN MCRL Capture range(lower)V SG9SW2.2 2.6−MHzPIN MCRT Capture range(total)−−SW3.0 3.8−MHz calcu-late PINIM Intermodulation V SG12SW31 36−dB PIN MDG DG V SG13SW− 3 7% PIN MDP DP V SG13SW− 3 7deg PIN MSPN Sync ratio (NEG)V SG13SW25.028.532.0% PIN MDLPH Maximum delaypoint (NEG/POS)V SG14SW00/40H90 96−dBµPIN M00/1DLPL Minimum delaypoint (NEG/POS)V SG15SW3F/7FH− 70 76dBµPIN M630/1SIF block−Default conditionsof SIF −−SW110020H20H40H−−−−PIN320320645V8V8V5VVAF AF output (DC)S SG21SW2.0 2.4 2.8V PIN MVoAF N AF direct output(4.5M)S SG16SW400 570 740mVrms PIN MVoAF P AF direct output(5.5M)S SG17SW430 570 710mVrms PIN MVoAF S AF direct output(6.0M)S SG18SW440 590 740mVrms PIN MMITSUBISHI ICs (TV)M52778SPVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCELECTRICAL CHARACTERISTICS (C0 to C12:input SG50 at SY IN C13 to C21:input SG60 at SY IN)ELECTRICAL CHARACTERISTICS (cont.)SymbolParameterInput signal SWTest conditionsLimitsUnit NoteS 4S 16S 44S 45Sub address function V CCInputSG PIN P 1P 3P 4P 12P 13P 16P 18P 19P 46P 48P 5200H 01H 03HP 8P 9P 20P24Min.T yp.Max.DL A P/N VC OA AVSWATTVoAF M AF direct output (6.5M)S SG19SW 460 615 770mVrmsPIN MVoAF max Maximum AF output (6.0M)S SG18SW 7FH86011401420mVrmsPIN M 127A TT Maximumattenuation (6.0M)S SG18SW 00H 59 68−dB PIN M 0THD AF AF outputdistortion (6.0M)S SG18SW − 1 3%PIN M LIM Input limiting sensitivity S SG18SW −40 46dB PIN M AMR AMR S SG20SW 49 50−dB PIN M AFSN AF S/NSSG21SW 53 63−dB PIN MGEAuEXT audio GAINEXT SG22SW 60H 48H-2.0 0.0 2.0dBPINM32172SymbolParameterInput signal SWTest conditionsLimitsUnit NoteS 4S 16S 44S 45Sub address function V CCInputSGPINP 1P 3P 4P 12P 13P 16P 18P 23P 41P 42P 4306H07H 09HP 8P 9P 20P24Min.T yp.Max.DL TA TV/EXT AU TOTINTSE TH Pchroma block (PAL)−Default conditions of chroma −−SW 110002H 2FH 40H −−−−PIN 20047085V 8V 8V 5VCn1Output signalamplitude 1:- (B-Y)VI SS4PSW 480 680880mV P-P PIN MCn2Output signalamplitude 2:- (R-Y)VI SS4P SW 390 530670mV P-P PIN M A CC1A CC 1VI VS4PSW -3 0 3dB v=+6dBPIN M A CC2A CC 2VI VS4PSW -3 0 3dB v=-20dBPIN M OV Chroma overload VI VS4PSW1 3 5dB eb=800mV PINM VikP Threshold color killer onVI VS4PSW −-37 -33dBv=variablePIN M killP Residual colorleakage at killer onVI VS4PSW 0 30 60mV P-Pv=-40dBPIN M APC1APC pull in range 1VI VS4PSW +300+550−Hz f=eb =ecf=variablePIN M -300-450−R/BP Ratio of (R-Y/B-Y)VI VS4PSW 0.45 0.60.75−eb=ec+50kHz eb=monochromaPIN M M θR-Y P Demoduration phase θR-Y VIVS4PSW 80 90 100deg eb=ec+50kHzeb=monochromaPIN M MCCResidual carrier leakage VI SS4PSW 0 50 100mV P-PPINMDDHOffset ofdemodulated output by lineVI4.2M SW −−100mVsinwavePIN MVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSC ELECTRICAL CHARACTERISTICS (cont.)Symbol Parameter Input signal SWTest conditionsLimitsUnit Note S4S16S44S45Sub address function V CCInput SG PINP1P3P4P12P13P16P18P23P41P42P4306H07H09HP8P9P20P24Min.T yp.Max.DLTATV/EXTAUTOTINT SE THPchroma block (NTSC)Cn3Output signalamplitude 3:- (B-Y)VI SS3NSW46H470 670870mV P-P PIN M65V8V8V5VCn4Output signalamplitude 4:- (R-Y)VI SS3NSW46H320 480620mV P-P PIN M6VikN Threshold colorkiller onVI VS3N SW46H− -46 -38dB v=variable PIN M6killN Residual colorleakage at killer on VI VS3N SW46H0 30 60mV P-P eb=0mV PIN M6APC2APC pull inrange 2VI VS3N SW46H+350+870−Hzeb=ec+50kHz f=variable PIN M-350-1000−R/BN Ratio of(R-Y/B-Y)VI VS3N SW46H0.4 0.6 0.8−eb=monochroma PIN M6θR-Y N Demodurationphase θR-YVI VS3N SW46H80 95110degeb=monochroma PIN M6TC1Tint control 1VI VS3N SW7FH46H25 45 60deg eb=monochroma PIN M1276TC2Tint control 2VI VS3N SW00H46H25 45 60deg eb=monochroma PIN M06chroma block (others)SRA SECAM refoutput amplitude−−SW41H200 400570mV P-P PIN M15V8V8V5VSRD SECAM ref outputDC voltage −−SW41H3.84.3 4.8VPIN M1AUTO 1Systemidentification 14.43 PALVI SS4PSW25H−0001−busdatareadmode PIN M111AUTO 2Systemidentification 24.43 NTSCVI SS4NSW25H−0101−busdatareadmode PIN M111AUTO 3Systemidentification 33.58 P ALVI SS3PSW25H−1001−busdatareadmode PIN M111AUTO 4Systemidentification 43.58 NTSCVI SS3NSW25H−1101−busdatareadmode PIN M111AUTO 5Systemidentification 5SECAM−−SW25H−0011−busdatareadmode PIN M150µA111AUTO 6Systemidentification 6black & white−−SW25H− --00−busdatareadmode PIN M111VIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCELECTRICAL CHARACTERISTICSVideo & RGB I/F block (∗ input SG50 at SY IN. (Y5 to Y7, Y36 to Y46:input SG60.)/V CC :P8, P24=5V.P9, P20=8V)No.Sub address08H0BH 13Hfunction COLOR DR MUTE ACL SERHST AFCGY 0DA TA 00H 20H47H function3215SymbolParameterInput signal SW Test conditionsLimitsUnit NoteS 4S 16S 44S45Sub address functionInputSGPINP 21P 22P 23P 26P 38P 4002H04H05H06H0A H09H 0C H10HMin.T yp.Max.4.5/6.0DF A TR F2DB F TR AP Vid G SH AR P DE FP CO NT DL TA TV/EX T AU TO BR Y SE T HP DB V-PO TR F HA−Default conditions of video & RGB I/F −−SW 110000H00H 20H02H40H 40H 20H60HPIN 0000000032200640832011YmaxMaximum videoamplitudeVISGASW7F H3.24.1 4.9V P-PPIN M M M127GY Video gainVISGASW40H 8 11 14dBPIN M M M64FBYVideo frequencycharacteristicsVI SGBSW 33H 40H-4 0−dBPINM51642AGY Pin 38 outputamplitudeVI SGA SW 46H 1.5 2.1 2.7V P-PPIN M68CTR1Chroma trapattenuation 1VI SGF SW00/20H33H 46H −− -18dBPIN M M M 0/15168TRF1Chroma trap fine adj. attenuation 1VI SGF SW20/28H33H 46H 00/60HPIN M M M 0/1151680/1DTR1Chroma double trapattenuation 1VI SGF SW30H 33H −− -20dBPIN M M M 1151CTR2Chroma trapattenuation 2VI SGB SW00/20H33H−− -18dBPIN M M M 0/151TRF2Chroma trap fine adj. attenuation 2VI SGB SW20/28H33H00/60HPIN M M M 0/11510/1DTR2Chroma double trap attenuation 2VI SGB SW30H33H −− -20dBPIN M M M 1151YDL1Y delay time 1VI SGA SW00H155240325nsec PIN M M M 0YDL2Y delay time 2VI SGA SW01H135220265nsec PIN M M M 1YDL3Y delay time 3VI SGA SW02H 250380450nsec PIN M M M 2YDL4Y delay time 4VISGASW03H 345500605nsecPIN M M M 3GTnor Video tone 1VI SGB SW20H 32H 1.1 1.6 2.1V P-PPIN M M M3250GTmax Video tone 2VI SGBSW3FH 32H 0 3.6 6.7dBPIN M M M6350GTmin Video tone 3VI SGBSW00H 32H -10 -4 -1dBPIN M M MH50GT2M Video tone 4VI SGBSW20H 32H -2.0 1.0 4.0dBPIN M M M3250VIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCVideo & RGB I/F block (cont.)ELECTRICAL CHARACTERISTICS Video & RGB I/F block (cont.)SymbolParameterInput signal SW Test conditionsLimitsUnit NoteS 4S 16S 44S45Sub address functionInput SGPINP 21P 22P 23P 26P 38P 4002H04H05H06H0A H09H 0C H10HMin.T yp.Max.4.5/6.0DF A TR F2DB F TR AP Vid G SH AR P DE FP CO NT DL TA TV/EX T AU TO BR Y SE T HP DB V-PO TR F HAGT5M Video tone 5VI SGBSW20H 32H -4-1.4 1.2dBPIN M M M3250GYnor Contrast 1VISGB SW40H 2.1 2.5 2.9V P-Pf=100kHzPIN M M M64GYminContrast 2VISGB SW00H −− 50mVf=100kHzPIN M M M 0LumnorBright 1−−SW40H 1.1 1.4 1.8VPIN M M M64Lummax Bright 2−−SW7F H0.6 1.0 1.4VPIN M M M127Lummin Bright 3−−SW00H -1.4-1.0-0.6VPIN M M M 0D (R)Drive R VI SGASW00/3FH2.9 5.5 7.1dBPIN M 0/63D (B)Drive B VI SGASW00/3FH2.9 5.5 7.1dBPIN M0/63EX (R)EXT (R) I/OFB ER SGD SW 07F H00H 4.8 6.0 7.2V P-PPIN M1270EX (G)EXT (G) I/O FB EG SGDSW 07F H00H 4.8 6.0 7.2V P-PPINM1270EX (B)EXT (B) I/O FB EBSGDSW 07F H00H 4.8 6.0 7.2V P-PPIN MM127SymbolParameterInput signal SW Test conditionsLimitsUnit NoteS 4S 16S 44S45Sub address functionInput SGPINP 21P 22P 23P 26P 38P 4002H05H06H08H 0A H 0D H 0E H 0F H13HMin.T yp.Max.4.5/6.0DF A TR F2DB F TR AP Vid G CO NT DL TA TV/EX T AU TO COLO R BR I CR CG CB AC L SE R HS T AFCG OFRGOffset voltage R-G−−SW 40H -1600160mVPIN M64OFBG Offset voltage B-G−−SW 40H -1600160mVPINM M 64C (R)Cut off R −−SW 40H 00/FFH 1.0 1.4 1.8VPIN M640/255C (G)Cut off G −−SW 00/FFH 1.0 1.4 1.8V PIN M 0/255C (B)Cut off B−−SW 00/FFH 1.0 1.4 1.8VPINM0/255VIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCELECTRICAL CHARACTERISTICSVideo & RGB I/F block (cont.)Symbol Parameter Input signal SWTest conditionsLimitsUnit Note S4S16S44S45Sub address functionInput SG PINP21P22P23P26P38P4002H05H06H08H0AH0DH0EH0FH13HMin.T yp.Max.4.5/6.0DFATRF2DBFTRAPVidGCONTDLTATV/EXTAUTOCOLORBRI CR CG CBACLSERHSTAFCGDLF Y delay time〈fine〉VI SGASW02H03H9 45 65nsecPIN M M M13Ccon1Color control 1-R SGE SW117F H48H150310500mV P-P PIN M12772Ccon2Color control 2-R SGE SW1100H48H− 10150mV P-P PIN M072VMF Video mute VI SGBf=4.43M SW−-50 -40dB0BHA0/A7MUTE:0/1 PIN M M MMTXB Matrix 1-B SGE SW1120H32H40H7F H0.5 0.8 1.2V P-P PIN M15064127MTXG Matrix 2-B SGE SW1120H32H40H7F H80190300mV P-P PIN M15064127MTXR Matrix 3-R SGE SW1120H32H40H7F H0.5 0.8 1.2V P-P PIN M15064127MTXG1Matrix 4-R SGE SW1120H32H40H7F H200400600mV P-P PIN M15064127OSD1OSD speed 1ER,EGEB,FB SGDSW00H− 20 90nsec PIN M M M0OSD2OSD speed 2ER,EGEB,FB SGDSW00H− 50160nsec PIN M M M0GYmax1Contrast 3VI SGA SW7F H3.74.6 6.3V P-PPIN M M M 2.9V127GYmin1Contrast 4VI SGA SW7F H− 0 50mV P-P PIN M M M0V127ABR Bright control〈V CC=8.5V at pin20〉−−SW7F H2.0−−V P20=8.5VPIN M127PACL1Peak ACL 1VI SGB SW7F H00H20H20H20H00H1.02.03.0V PIN M12703232320000P ACL2Peak ACL 2VI SGB SW7F H00H20H20H20H40H3.24.25.2V PIN M12703232328000P ACL3Peak ACL 3VI SGB SW7F H00H20H20H20H47H3.44.45.4V PIN M127032323215000VIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCELECTRICAL CHARACTERISTICS Deflection block No.Subaddress06H08Hfunction DLTA TV/EXT AUTO COLOR DDATA 20H00Hfunction0010Symbol Parameter Input signal SWTest conditionsLimitsUnit Note S4S16S44S45Sub address function V CCInput SG PINP12P13P16P18P19P21P22P23P3909H10H11H12H13HP8P9P20P24Min.T yp.Max.SET HPV-POTRF HAVSIZSUBVPOACLSERHSTAFCG−Default conditionsof deflection −−SW110040H60H20H00H47H−−−−PIN08011320150005V8V8V5VISS Sync. sep. inputsensitivity; current −−SW− 0.1 0.2mA PIN MBGP1Burst gate pulsetiming 1 (PAL)SY SGaSW1.52.53.5µsecPIN M MBGP2Burst gate pulsetiming 2 (NTSC)SY SGbSW1.62.63.6µsecPIN M MBGPW Burst gatepulse widthSY SGaSW4.8 6.0 7.2µsecPIN MfH Horizontal free-runningfrequency −−SW15.315.716.1kHzPIN MFPH1Horizontal pull-inrange 1SYSGcf=vari-ableSW+580+780−Hz PIN M MFPH2Horizontal pull-inrange 2SYSGcf=vari-ableSW−-440-220Hz PIN M MHPT1Horizontal pulsetiming 1SY SGaSW7.0 8.1 9.2µsecPIN M MHPT2Horizontal pulsetiming 2SY SGaSW00H-2.0 -1.4-0.8µsec PIN M M0HPT3Horizontal pulsetiming 3SY SGaSW78H0.8 1.4 2.0µsecPIN M M15TH Horizontal pulsewidth−−SW21 25 29µsecPIN M 6.7VH Horizontal pulseamplitude−−SW3 4−VPIN MHSTO Horizontal pulsestop function−−SW57H3 4−VPIN M1AFCG AFG gain SY SGa SW047/67H2.0 4.0 10dB PIN M0/1fV Vertical free-runningfrequency −−SW41 44 47HzPIN MAVER550/60identification 5SYSGdf70HzSW− 70−Hz w-D7=0 PINSW Service switch−−SW3.5 44.5V PIN M MFPV Vertical pull-inrangeSYSGdf=vari-ableSW1100−− 65Hz w-D7=1 PIN MVW Vertical pulsewidth−−SW0.350.520.65msecPIN MVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCELECTRICAL CHARACTERISTICSDeflection block (cont.)Symbol Parameter Input signal SWTest conditionsLimitsUnit Note S4S16S44S45Sub address function V CCInput SG PINP12P13P16P18P19P21P22P23P3909H10H11H12H13HP8P9P20P24Min.T yp.Max.SET HPV-POTRF HAVSIZSUBVPOACLSERHSTAFCGVBLKW Vertical blankingwidth (pin21, 22, 23)−−SW1.35 1.5 1.6msecPIN M M MAVER150/60identification 1SYSGdf63HzSW− 63−Hz w-D7=1 PINAVER250/60identification 2SYSGdf57HzSW− 57−Hz w-D7=1 PINAVER350/60identification 3SYSGdf53HzSW− 53−Hz w-D7=0 PINAVER450/60identification 4SYSGdf47HzSW− 47−Hz w-D7=0 PINWVSS Vertical sync.detectionminimum widthSY SGd SW9.5−−µsecf60Hz widthvariablePIN MRsi1Vertical rampsizeSY SGASW90011001300mV P-P PIN MR∆s1Vertical rampsize controlrangeSY SGASW00/40H 83 93 103%PIN M0/64Rpo1Vertical rampposition controlrangeSY SGASW7F/60H20H120 170 220mV PIN M31/032Rgc Vertical positioncenter adjustment SY SGASW4− 27data PIN M MRpr Vertical ramp outpulse width (PAL)SY SGASW520 545570µsec PIN MVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSC(3) Sub address byte and data byte format:write∗SWread No.Functions BIT SUBADDData byteD7D6D5D4D3D2D1D0IF1DELAY ADJ600H0–A05A04A03A02A01A00 2POS/NEG100H POS/NEG3VCO ADJ601H0–A15A14A13A12A11A10 4AUDIO SW∗101H AUDIO SW5 4.5/6.0∗102H 4.5/6.0 6DEFEAT∗104H DEFEA T7AUDIO ATT703H0A36A35A34A33A32A31A30 36VIDEO OUT GAIN∗102H VIDEOOUT GAINVIDEO8sharpness604H0–A45A44A43A42A41A40 9contrast cont705H0A56A55A54A53A52A51A50 10DL time ADJ∗206H000–––A61A6025DL fineADJ.+50nsec102H0 +0nsec111TV/EXT∗106H TV/EXT14TRAP on/off∗102H TRAP37DOUBLE TRAP∗102H DTRAP38TRAP fine adj. 1∗ 110H FTRAP140TRAP fine adj. 2∗ 102H FTRAP236VIDEO MUTE∗10BHVIDEOMUTECHROMA 15tint cont707H0A76A75A74A73A72A71A70 16color cont708H0A86A85A84A83A82A81A80 17SYSTEM auto∗106H auto18SYSTEM SET∗309H0–––– 3.58NTSC SECAMINTER-FACE 19bright cont70AH0AA6AA5AA4AA3AA2AA1AA0 20drive (R)60BH00AB5AB4AB3AB2AB1AB0 21drive (B)60CH00AC5AC4AC3AC2AC1AC0 22cut off (R)80DH AD7AD6AD5AD4AD3AD2AD1AD0 23cut off (G)80EH AE7AE6AE5AE4AE3AE2AE1AE0 24cut off (B)80FH AF7AF6AF5AF4AF3AF2AF1AF0 31PEAK ACL413H0A136–––A132A131A130DEFLEC-TION 27AFC-2 H phase409H0A96A95A94A93–––29V-SIZE611H00A115A114A113A112A111A120 28V-POSITION510H0––A104A103A102A101A100 30SUB-POSITION∗212H0–––––A121A12033Service SW∗113HServiceSW34H STOP∗113H H STOP35AFC GAIN∗113HAFCGAIN41H fo ADJ∗110H HADJData byteD7D6D5D4D3D2D1D050/60COINCIDENCE AFT1AFT0 3.58NTSC SECAM CONDITION/ killer outVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSC21DATA BYTE CONDITIONS AT SWFunctions DataCondition Initial condition IFPOS/NEG POS/NEG 0NEG NEG 1POS AUDIO SWAUDIO SW 0OFF OFF 1ON DEFEAT DEFEA T 0OFF OFF 1ON 4.5/6.04.5/6.00 6.0 6.01 4.5VIDEO OUT GAINVIDEO OUT GAIN0Normal Normal1gain down VIDEODL time ADJ A71, A700 0120nsec 360nsec0 1280nsec 1 0360nsec 1 1440nsec TV/EXTTV/EXT 0TV TV1EXTVIDEO MUTE MUTE 0VIDEO OUT VIDEO OUT 1VIDEO MUTE TRAP on/off TRAP 0TRAO OFF TRAP OFF 1TRAP ONDOUBLE TRAP DTRAP 0SINGLE TRAP SINGLE TRAP 1DOUBLE TRAP INTERFACETRAP fine adj. 1FTRAP10f 0 down f 0 up 1f 0 up TRAP fine adj. 2FTRAP20f 0 down f 0 down 1f 0 up CHROMASYSTEM autoauto0manual manual1autoSYSTEM SET3.58, NTSC, SECAM0 0 0 4.43 PAL 4.43 PAL1 0 0 3.58 PAL 1 1 0 3.58 NTSC 0 1 0 4.43 NTSC 0 0 1SECAMDEFLECTIONService SW Service SW 0Normal mode normal mode 1Service mode H STOP H STOP 0H OUT H OUT 1H STOP AFC GAINAFC GAIN 0NORMAL NORMAL 1HIGH H fo ADJH to ADJ0Normal Normal1f 0 downSUB-POSITION SUB-POSITION 0 0normal mode normal mode0 1upside mode 1 0downside mode 1 1normal modeVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSC22VIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSC23VIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSC24VIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSC25VIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSC26VIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSC27VIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSC28TYPICAL CHARACTERISTICSAMBIENT TEMPERATURE Ta (°C)02550751001252.0150THERMAL DERATING (MAXIMUM RATING)P O W E R D I S S I P A T I O N P d (m W )650.51.01.51.69VIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSC29VIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSC30VIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSCVIF, SIF, VIDEO, CHROMA, DEFLECTION FOR PAL/NTSC。

MJD41CTF;中文规格书,Datasheet资料

MJD41CTF;中文规格书,Datasheet资料

MJD41CMJD41CDISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:TRADEMARKSThe following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body,or (b) support or sustain life, or (c) whose failure to performwhen properly used in accordance with instructions for useprovided in the labeling, can be reasonably expected to result in significant injury to the user.2. A critical component is any component of a life support device or system whose failure to perform can bereasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.PRODUCT STATUS DEFINITIONS Definition of TermsDatasheet Identification Product Status DefinitionAdvance InformationFormative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.PreliminaryFirst ProductionThis datasheet contains preliminary data, andsupplementary data will be published at a later date.Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.No Identification Needed Full ProductionThis datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.Obsolete Not In ProductionThis datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only.A CEx™Bottomless™CoolFET™CROSSVOLT ™DenseTrench™DOME™EcoSPARK™E 2CMOS™EnSigna™FACT™FACT Quiet Series™FAST ®FASTr™FRFET™GlobalOptoisolator™GTO™HiSeC™ISOPLANAR™LittleFET™MicroFET™MICROWIRE™OPTOLOGIC™OPTOPLANAR™PACMAN™POP™Power247™PowerTrench ®QFET™QS™QT Optoelectronics™Quiet Series™SLIENT SWITCHER ®SMART START™STAR*POWER™Stealth™SuperSOT™-3SuperSOT™-6SuperSOT™-8SyncFET™TruTranslation™TinyLogic™UHC™UltraFET ®VCX™STAR*POWER is used under license分销商库存信息: FAIRCHILDMJD41CTF。

微小电子ZL40202精密LVPECL4 1输出缓冲器数据手册说明书

微小电子ZL40202精密LVPECL4 1输出缓冲器数据手册说明书

1FeaturesInputs/Outputs •Accepts differential or single-ended input •LVPECL, LVDS, CML, HCSL, LVCMOS •Four precision LVPECL outputs •Operating frequency up to 750 MHzPower •Option for 2.5 V or 3.3 V power supply •Core current consumption of 62 mA•On-chip Low Drop Out (LDO) Regulator for superior power supply noise rejectionPerformance •Ultra low additive jitter of 39 fs RMSApplications•General purpose clock distribution •Low jitter clock trees •Logic translation•Clock and data signal restoration•Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC•PCI Express generation 1/2/3 clock distribution •Wireless communications•High performance microprocessor clock distributionApril 2014Figure 1 - Functional Block DiagramZL40202Precision 1:4 LVPECL Fanout BufferData SheetOrdering InformationZL40202LDG1 16 Pin QFN TraysZL40202LDF116 Pin QFN Tape and ReelMatte TinPackage size: 3 x 3 mm-40o C to +85o CTable of ContentsFeatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.0 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63.1 Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63.2 Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113.3 Device Additive Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.4.1 Sensitivity to power supply noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.4.2 Power supply filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.4.3 PCB layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206.0 Typical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217.0 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24List of FiguresFigure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3 - LVPECL Input DC Coupled Thevenin Equivalent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4 - LVPECL Input DC Coupled Parallel Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5 - LVPECL Input AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 6 - LVDS Input DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7 - LVDS Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8 - CML Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9 - HCSL Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 10 - CMOS Input DC Coupled Referenced to VDD/2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 11 - CMOS Input DC Coupled Referenced to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 12 - Simplified Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 13 - LVPECL Basic Output Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 14 - LVPECL Parallel Output Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 15 - LVPECL Parallel Thevenin-Equivalent Output Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 16 - LVPECL AC Output Termination for Externally Terminated LVPECL Inputs . . . . . . . . . . . . . . . . . . . . 13 Figure 17 - LVPECL AC Output Termination for Internally Terminated LVPECL Inputs. . . . . . . . . . . . . . . . . . . . . 13 Figure 18 - LVPECL AC Output Termination for CML Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 19 - Additive Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 20 - Decoupling Connections for Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 21 - Differential Voltage Parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 22 - Input To Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Change SummaryPage ItemChange1Applications Added PCI Express clock distribution.5Pin Description Added exposed pad to Pin Description.6, 7Figure 3 and Figure 413Figure 16Corrected LVPECL interface circuit.18Figure 21Clarification of V ID and V OD .Below are the changes from the February 2013 to the April 2014 issue:Page Item Change7Figure 4Changed text to indicate the circuit is not recommended for VDD_driver=2.5V.7Figure 5Changed pull-up and pull-down resistors from 2kOhm to 100 Ohm.Below are the changes from the November 2012 issue to the February 2013 issue:Removed 22 Ohm series resistors from Figure 3 and 4.These resistors are not required; however there is no impact to performance if the resistors are included.The device is packaged in a 16 pin QFN1416642out3_nvddout3_pN Cc l k _pvddgndout0_no u t 2_no u t 2_po u t 1_n81210o u t 1_pc l k _nN Cout0_pgndFigure 2 - Pin Connections2.0 Pin DescriptionPin # Name Description1, 4clk_p, clk_n,Differential Input (Analog Input). Differential (or singled ended) input signals. For all input signal configuration see “Clock Inputs” on page 615,14, 12, 11, 10, 9, 7, 6out0_p, out0_n out1_p, out1_n out2_p, out2_n out3_p, out3_nDifferential Output (Analog Output). Differential outputs.8, 13vdd Positive Supply Voltage. 2.5 V DC or 3.3 V DC nominal.5, 16gnd Ground. 0 V.2, 3NCNo Connection. Leave unconnected.Exposed PadDevice GND .The ZL40202 is an LVPECL clock fanout buffer with four identical output clock drivers capable of operating at frequencies up to 750MHz.Inputs to the ZL40202 are externally terminated to allow use of precision termination components and to allow full flexibility of input termination. The ZL40202 can accept DC coupled LVPECL or LVDS and AC coupled LVPECL, LVDS, CML or HCSL input signals; single ended input signals can also be accepted. A pin compatible device with internal termination is also available.The ZL40202 is designed to fan out low-jitter reference clocks for wired or optical communications applications while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature range -40°C to +85°C.The device block diagram is shown in Figure 1; its operation is described in the following sections.3.1 Clock InputsThe ZL40202 is adaptable to support different types of differential and singled-ended input signals depending on the passive components used in the input termination. The application diagrams in the following figures allow the ZL40202 to accept LVPECL, LVDS, CML, HCSL and single-ended inputs.Figure 3 - LVPECL Input DC Coupled Thevenin EquivalentFigure 4 - LVPECL Input DC Coupled Parallel TerminationFigure 5 - LVPECL Input AC Coupled TerminationFigure 6 - LVDS Input DC CoupledFigure 7 - LVDS Input AC CoupledFigure 8 - CML Input AC CoupledFigure 9 - HCSL Input AC CoupledFigure 11 - CMOS Input DC Coupled Referenced to GroundVDD_driver R1 (kΩ)R2 (kΩ)R3 (kΩ)RA (kΩ) C (pF) 1.5 1.25 3.075open10101.81 3.8open10102.50.33 4.2open10103.30.75open4.21010Table 1 - Component Values for Single Ended Input Reference to Ground* For frequencies below 100 MHz, increase C to avoid signal integrity issues.3.2 Clock OutputsLVPECL has a very low output impedance and a differential signal swing between 1V and 1.6 V. A simplified diagram for the output stage is shown in Figure 12.The LVPECL to LVDS output termination is not shown since there is a separate device that has the same input and LVDS outputs.out_pout_nFigure 12 - Simplified Output DriverThe methods to terminate the ZL40202 LVPECL drivers are shown in the following figures.Figure 15 - LVPECL Parallel Thevenin-Equivalent Output TerminationF igure 16 - LVPECL AC Output Termination for Externally Terminated LVPECL InputsFigure 17 - LVPECL AC Output Termination for Internally Terminated LVPECL InputsFigure 18 - LVPECL AC Output Termination for CML Inputs3.3 Device Additive JitterThe ZL40202 clock fan out buffer is not intended to filter clock jitter. The jitter performance of this type of device is characterized by its additive jitter. Additive jitter is the jitter the device would add to a hypothetical jitter-free clock as it passes through the device. The additive jitter of the ZL40202 is random and as such it is not correlated to the jitter of the input clock signal.The square of the resultant random RMS jitter at the output of the ZL40202 is equal to the sum of the squares of the various random RMS jitter sources including: input clock jitter; additive jitter of the buffer; and additive jitter due to power supply noise. There may be additional deterministic jitter sources that are not shown in Figure 19.Figure 19 - Additive Jitter3.4 Power SupplyThis device operates with either a 2.5V supply or 3.3V supply.3.4.1 Sensitivity to power supply noisePower supply noise from sources such as switching power supplies and high-power digital components such as FPGAs can induce additive jitter on clock buffer outputs. The ZL40202 is equipped with a low drop out (LDO) power regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise. The LDO regulator on the ZL40202 allows this device to have superior performance even in the presence of external noise sources. The on-chip regulation, recommended power supply filtering, and good PCB layout all work together to minimize the additive jitter from power supply noise.The performance of these clock buffers in the presence of power supply noise is detailed in ZLAN-403, “Power Supply Rejection in Clock Buffers” which is available from Applications Engineering.3.4.2 Power supply filteringFor optimal jitter performance, the device should be isolated from the power planes connected to its power supply pins as shown in Figure 20.•10 µF capacitors should be size 0603 or size 0805 X5R or X7R ceramic, 6.3 V minimum rating•0.1 µF capacitors should be size 0402 X5R ceramic, 6.3 V minimum rating•Capacitors should be placed next to the connected device power pins• a 0.3 ohm resistor is recommended for the filter shown in Figure 20Figure 20 - Decoupling Connections for Power Pins3.4.3 PCB layout considerationsThe power nets in Figure 20 can be implemented either as a plane island or routed power topology without changing the overall jitter performance of the device.Absolute Maximum Ratings*Parameter Sym.Min.Max.Units 1Supply voltage V DD_R-0.5 4.6V 2Voltage on any digital pin V PIN-0.5V DD V 3LVPECL output current I out30mA 4Soldering temperature T260 °C 5Storage temperature T ST-55125 °C 6Junction temperature T j125 °C 7Voltage on input pin V input V DD V 8Input capacitance each pin C p500fF 4.0 AC and DC Electrical Characteristics* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.* Voltages are with respect to ground (GND) unless otherwise statedRecommended Operating Conditions*Characteristics Sym.Min.Typ.Max.Units1Supply voltage 2.5 V mode V DD25 2.375 2.5 2.625V2Supply voltage 3.3 V mode V DD33 3.135 3.3 3.465V3Operating temperature T A-402585°C* Voltages are with respect to ground (GND) unless otherwise statedDC Electrical Characteristics - Current ConsumptionCharacteristics Sym.Min.Typ.Max.Units Notes 1Supply current LVPECL drivers -unloadedI dd_unload62mA Unloaded2Supply current LVPECL drivers - loaded (all outputs are active)I dd_load140mA Including powerto R L = 50DC Electrical Characteristics - Inputs and Outputs - for 3.3 V SupplyCharacteristics Sym.Min.Typ.Max.Units Notes 1Differential input common modevoltageV CM 1.1 2.0V2Differential input voltage difference V ID0.251V3LVPECL output high voltage V OH V DD-1.40V* This parameter is measured from 125 MHz to 750 MHz* This parameter is measured from 125 MHz to 750 MHzFigure 21 - Differential Voltage Parameter* Supply voltage and operating temperature are as per Recommended Operating Conditions4LVPECL output low voltage V OL V DD -1.62V 5LVPECL output differential voltage*V OD0.50.9VDC Electrical Characteristics - Inputs and Outputs - for 2.5 V SupplyCharacteristicsSym.Min.Typ.Max.Units Notes1Differential input common mode voltageV CM 1.1 1.6V 2Differential input voltage difference V ID 0.251V 3LVPECL output high voltage V OH V DD -1.40V 4LVPECL output low voltage V OL V DD -1.62V 5LVPECL output differential voltage*V OD0.40.9VAC Electrical Characteristics* - Inputs and Outputs (see Figure 22) - for 2.5 and 3.3 V supplies.CharacteristicsSym.Min.Typ.Max.Units Notes1Maximum Operating Frequency 1/t p 750MHz 2Input to output clock propagation delay t pd 012ns 3Output to output skew t out2out 50100ps 4Part to part output skewt part2part 80300ps 5Output clock Duty Cycle degradation t PWH / t PWL-2%0%2%Duty Cycle 6LVPECL Output slew rater sl0.75 1.2V/nsDC Electrical Characteristics - Inputs and Outputs - for 3.3 V SupplyCharacteristicsSym.Min.Typ.Max.Units NotesInputt Pt PWL t pdt PWHOutputFigure 22 - Input To Output TimingAdditive Jitter at 2.5 V*Output Frequency (MHz)Jitter MeasurementFilterTypical RMS (fs)Notes112512 kHz - 20 MHz 1122212.512 kHz - 20 MHz 803311.0412 kHz - 20 MHz 70442512 kHz - 20 MHz 65550012 kHz - 20 MHz 566622.0812 kHz - 20 MHz 46775012 kHz - 20 MHz44Additive Jitter at 3.3 V*Output Frequency (MHz)Jitter MeasurementFilterTypical RMS (fs)Notes112512 kHz - 20 MHz 1122212.512 kHz - 20 MHz 823311.0412 kHz - 20 MHz 72442512 kHz - 20 MHz 63550012 kHz - 20 MHz 526622.0812 kHz - 20 MHz 43775012 kHz - 20 MHz395.0 Performance Characterization*The values in this table were taken with an approximate input slew rate of 0.8 V/ns*The values in this table were taken with an approximate input slew rate of 0.8 V/nsAdditive Jitter from a Power Supply Tone*Carrier frequencyParameterTypicalUnitsNotes125MHz 25 mV at 100 kHz 159fs RMS 750MHz25 mV at 100 kHz82fs RMS* The values in this table are the additive periodic jitter caused by an interfering tone typically caused by a switching power supply. For this test, measurements were taken over the full temperature and voltage range for V DD = 3.3 V. The magnitude of the interfering tone is measured at the DUT.6.0 Typical BehaviorTypical Phase Noise at 622.08 MHzTypical Waveform at 155.52 MHzInput Slew Rate versus Additive Jitter Propagation Delay versus TemperatureNote:This is for a single device. For more details see thecharacterization section.V ODversus FrequencyPower Supply Tone Magnitude versus PSRR (at 100 kHz) at 125 MHz Power Supply Tone Magnitude versus Additive Jitter (at 100 kHz) at 125 MHzPower Supply Tone Frequency (at 25 mV) versus PSRR at 125 MHz Power Supply Tone Frequency (at 25 mV) versus Additive Jitter at 125 MHz7.0 Package Thermal Characteristics*Proper thermal management must be practiced to ensure that T jmax is not exceeded.Thermal DataParameterSymbolTest ConditionValue UnitJunction to Ambient Thermal ResistanceΘJAStill Air 1 m/s 2 m/s 67.961.658.1oC/WJunction to Case Thermal Resistance ΘJC Still Air 44.1o C/W Junction to Board Thermal Resistance ΘJB Still Air23.2oC/WMaximum Junction Temperature*T jmax 125o C Maximum Ambient TemperatureT A85oC© 2014 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. 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