40CPQ035中文资料

芯片（2） 元件号码
N/A N/A N/A N/A N/A N/A N/A N/A N/A SC090H045A SC090H150A SC090S045A SC125R015S SC125H045A SC125H045S SC125H100A SC125H100S SC125H150A SC125S030A SC125S045A SC125S045S SC125S060A SC150H045A SC150R015A SC150S045A SC175H045S SC175H100A SC175H100S SC175S045A SC175S045S
熔炉区域的设置将取决于混合物的质量、材料、卡具和带速。肖特基芯片的温度一 定不要超过 400℃，也不能在 350 到 400℃范围内超过 1 分钟。推荐用氢气清理熔炉，尽 管氮气或氮氢混合气体（氮-氢，85%-15%）是可接受的。
采用导电胶安装芯片也是可能的，尽管这不是 IR 公司目前生产中所采用的。 钼片
在焊接中，由于有施加在较大芯片尺寸（200mil/边或更大）的热膨胀应力，IR 公司 建议在阳极和阴极上使用钼或其它热匹配的薄片，必须这样来选择薄片的材料和（或） 镀层，以使它能焊接到顶部和底部金属是银的金属化层上。
IR 公司提供了可焊接到阳极、阴极或两者上的钼片的标准选择，既有圆形的又有方 形形状的，以及各种适合于个别芯片大小的尺寸，这些选项被列在表 2 中。订购带有钼 片的芯片，要把需要选项的后缀号码加到芯片元件号的末尾。 阳极的连接
肖特基整流器芯片用于混合组装，可能导致整个封装尺寸的显著降低，以及性能和 效率的明显改善。此外，几个肖特基芯片可以很容易地安装在同样的散热器上，组成电
路组态或并联器件。因此，IR 肖特基整流器的这种工作优点，能够在非常紧凑的传统封 装组态中实现。

CC4067------16选1模拟开关简要说明：CC4067 是数字控制模拟开关，具有低导通阻抗，低截止漏电流和内部地址译码的特征。

另外，在整个输入信号范围内，导通电阻保持相对稳定。

CC4067是16通道开关，有四个二进制输入端A0～A3和控制端C，输入的任意一个组合可选择一路开关。

C＝1时，关闭所有的通道。

CC4067提供了24引线多层陶瓷双列直插（D）、熔封陶瓷双列直插（J）、塑料双列直插（P）和陶瓷片状载体（C）4种封装形式。

推荐工作条件：电源电压范围…………3V～15V输入电压范围…………0V～V DD工作温度范围M类…………－55℃～125℃E类………….－40℃～85℃极限值：电源电压…...－0.5V～18V输入电压……－0.5V~V DD+0.5V输入电流…………….±10mA储存温度…………－65℃～150℃引出端符号：A0～A3 地址端C 控制端I0/O0～I15/O15输入/输出通道O/I 公共输出/输入端V DD正电源Vss 地逻辑符号：引出端排列（俯视）：逻辑表达式：I I 输入电流（最大）V IN =18V/0V 18 ±0.1±0.1µA t R =t F =20nS;C L =50pFR L =10k Ω t PLHt PHL 传输延迟时间（导通）（最大）A->O/I C->O/I－0 0 0 5.0 10.015.0－650 270 190 nSt R =t F =20nS;C L =50pFRL=300Ωt PLHt PHL 传输延迟时间（截止） （最大）A->O /I C->O/I －0 0 0 5.0 10.015.0－440 180 130 nS控制部分（A0、A1、A2、A3、C） C I 输入电容（最大） A 、C －－ 7.5pF* 峰－峰电压对称值为（V DD-V EE）/2 ** 最坏情况** 两通道的末端逻辑图：。

CD4013：双D触发器CD4013由两个相同的、相互独立的数据型触发器构成。

每个触发器有独立的数据、置位、复位、时钟输入和Q及Q输出，此器件可用作移位寄存器，且通过将Q输出连接到数据输入，可用作计算器和触发器。

在时钟上升沿触发时，加在D输入端的逻辑电平传送到Q输出端。

置位和复位与时钟无关，而分别由置位或复位线上的高电平完成。

图１CD4013引脚图图２CD4013内部电路图图3 CD4013逻辑图Truth Table 真值表功能:Absolute Maximum Ratings 绝对最大额定值:Recommended Operating Conditions 建议操作条件:DC Electrical Characteristics 直流电气特性:AC Electrical Characteristics 交流电气特性:65120tTHL, tTLHTransition Time过渡时间VDD = 5V100200nsVDD = 10V50100VDD = 15V4080tWL, tWHMinimum Clock Pulse Width最小时钟脉冲宽度VDD = 5V100200nsVDD = 10V4080VDD = 15V3265tRCL, tFCLMaximum Clock Rise and Fall Time最大时钟上升和下降时间VDD = 5V15 msVDD = 10V10VDD = 15V5tSUMinimum Set-Up Time 最低设置时间VDD = 5V2040nsVDD = 10V1530VDD = 15V1225fCLMaximum Clock Frequency 最大时钟频率VDD = 5V2.55MHzVDD = 10V6.212.5VDD = 15V7.615.5SET AND RESET OPERATION SET和复位操作tPHL(R),tPLH(S)Propagation Delay Time传递延迟时间VDD = 5V150 300ns VDD = 10V45130 VDD = 15V6590tWH(R), tWH(S)Minimum Set and Reset Pulse Width最低限度和复位脉冲宽度VDD = 5V90180 nsVDD = 10V 40 80VDD = 15V2550CINAverage Input Capacitance 平均输入电容Any Input57.5pF图4 切换时间波形应用电路：置位和复位电路图5（左）和图（右）中的CD4013是CMOS双D触发器，这类电路置位和复位信号是高电平有效，由于开关闭合时电容可视为短路而产生高电平，使RD=1，Q=0；若将此信号加到SD，则SD=1，Q=1;置位、复位过后，电容充电而使RD（SD）变为0，电路可进入计数状态。

Pin Compatibility Between PackagesZynq-7000SoC devices are pin compatible only with other Zynq-7000SoC devices in thesame package. In addition, FB/FBG/FBV and FF/FFG/FFV packages of the same pin-countdesignator are pin compatible. Table1-6 shows the pin compatible devices available foreach Zynq-7000SoC device package. Pins that are available in one device but are notavailable in another device with a compatible package include the other device's name inthe No Connect column of the package file. These pins are labeled as No Connects in theother device's package file.Some FB/FBG/FBV packages include V CCAUX_IO pins, but they are not utilized by the I/O.These pins are placeholders to ensure pin compatibility with FF/FFG/FFV packages. In theFF/FFG/FFV packages, if the high-performance option is chosen for the HP I/O, theV CCAUX_IO pins must be connected to a power supply separate from V CCAUX. Therefore, ifthere are plans to migrate to FF/FFG/FFV packages, V CCAUX_IO must be connected to theappropriate voltage regulator.Table 1-6:Pin CompatibilityPackage Pin Compatible DevicesCL225/CLG2257Z007S7Z010CL400/CLG4007Z007S7Z0107Z014S7Z020CL484/CLG4847Z014S7Z020SB/SBG/SBV485 or7Z012S7Z0157Z030CL/CLG485FB/FBG/FBV484 or RB4847Z030FB/FBG/FBV676 or7Z0307Z0357Z045FF/FFG/FFV676 or RF/RFG676FF/FFG/FFV900 or RF9007Z0357Z0457Z100FF/FFG/FFV1156 or RF11567Z100Notes:1.Pin compatible packages as well as the FB/FBG/FBV and FF/FFG/FFV packages have substantially different decouplingcapacitor recommendations. Refer to the Zynq-7000 SoC PCB Design Guide (UG933) [Ref2].质量等级领域:宇航级IC、特军级IC、超军级IC、普军级IC、禁运IC、工业级IC，军级二三极管，功率管等;应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通信网络、电力工业以及大型工业设备祝您:工作顺利，生活愉快!以深圳市美光存储技术有限公司提供的参数为例，以下为XC7Z035-2FBG676E的详细参数，仅供参考Chapter 1:Package OverviewFlip-Chip PackagesFor larger Zynq-7000SoC devices, Xilinx offers the flip-chip BGA packages, which present a low thermal path. These packages incorporate a heat spreader with additional thermal interface material (TIM), as shown in Figure5-4.3.Preheat dwell 95–180°C for 120–180 seconds4.IR reflow must be performed on dry packagesPb-Free Reflow SolderingXilinx uses SnAgCu solder balls for BGA packages. In addition, suitable material are qualified for the higher reflow temperatures (250°C maximum, 260°C for dry rework only) required by Pb-free soldering processes.Xilinx does not recommend soldering SnAgCu BGA packages with SnPb solder paste using a Sn/Pb soldering process. Traditional Sn/Pb soldering processes have a peak reflow temperature of 220°C. At this temperature range, the SnAgCu BGA solder balls do not properly melt and wet to the soldering surfaces. As a result, reliability and assembly yields can be compromised.The optimal profile must take into account the solder paste/flux used, the size of the board, the density of the components on the board, and the mix between large components and smaller, lighter components. Profiles should be established for all new board designs using thermocouples at multiple locations on the component. In addition, if there is a mixture of devices on the board, then the profile should be checked at various locations on the board. Ensure that the minimum reflow temperature is reached to reflow the larger components and at the same time, the temperature does not exceed the threshold temperature that might damage the smaller, heat sensitive components.Table5-2 and Figure5-7 provide guidelines for profiling Pb-free solder reflow.In general, a gradual, linear ramp into a spike has been shown by various sources to be the optimal reflow profile for Pb-free solders (Figure5-7). SAC305 alloy reaches full liquidus temperature at 235°C. When profiling, identify the possible locations of the coldest solder joints and ensure that those solder joints reach a minimum peak temperature of 235°C for at least 10 seconds. It might not be necessary to ramp to peak temperatures of 260°C and above. Reflowing at high peak temperatures of 260°C and above can damage the heat sensitive components and cause the board to warp. Users should reference the latest IPC/JEDEC J-STD-020 standard for the allowable peak temperature on the component body. The allowable peak temperature on the component body is dependent on the size of the component. Refer to Table5-2 for peak package reflow body temperature information. In any case, use a reflow profile with the lowest peak temperature possible.Table 5-2:Pb-Free Reflow Soldering GuidelinesProfile Feature Convection, IR/ConvectionRamp-up rate2°C/s maximumPreheat Temperature 150°–200°C60–120 secondsTemperature maintained above 217°C60–150 seconds (60–90 seconds typical)Time within 5°C of actual peak temperature30 seconds maximum。