ST72F321J7中文资料
- 格式：pdf
- 大小：2.16 MB
- 文档页数：179
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 6.3 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 24 24 25 25 25 26 26 27 28 28 29 30 30
ST72(F)321J7
48K 1536 (256)
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Device Summary
Features
Program memory - bytes RAM (stack) - bytes Operating Voltage Temp. Range (ROM) Temp. Range (Flash) Packages
4.6.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2 5.3 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ST72(F)321J9
60K 2K (256) 3.8V to 5.5V up to -40°C to +125°C up to -40°C to +125°C TQFP44 10x10 (JxT)
-40°C to +85 °C
Rev. 1.8 July 2003 1/179
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Table of Contents
TQFP44 10 x 10
– 8-bit PWM Auto-reload timer with: 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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3 Communication Interfaces – SPI synchronous serial interface – SCI asynchronous serial interface (LIN compatible) – I2C multimaster interface 1 Analog Peripheral – 10-bit ADC with 12 input pins Instruction Set – 8-bit Data Manipulation – 63 Basic Instructions – 17 main Addressing Modes – 8 x 8 Unsigned Multiply Instruction Development Tools – Full hardware/software development package – In-Circuit Testing capability
6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4 Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.5 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 7.3 7.4 7.5 7.6 7.7
ST72321J
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 5 TIMERS, SPI, SCI, I2C INTERFACEssss
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Memories – 48 to 60K dual voltage High Density Flash (HDFlash) or ROM with read-out protection capability. In-Application Programming and In-Circuit Programming for HDFlash devices – 1.5 to 2K bytes RAM – HDFlash endurance: 100 cycles, data retention: 20 years at 55°C Clock, Reset And Supply Management – Enhanced low voltage supervisor (LVD) for main supply and auxiliary voltage detector (AVD) with interrupt capability – Clock sources: crystal/ceramic resonator oscillators, internal or external RC oscillator, clock security system and bypass for external clock – PLL for 2x frequency multiplication – Four Power Saving Modes: Halt, Active-Halt, Wait and Slow Interrupt Management – Nested interrupt controller – 10 interrupt vectors plus TRAP and RESET – 9 external interrupt lines (on 4 vectors) Up to 32 I/O Ports – 32 multifunctional bidirectional I/O lines – 22 alternate function lines – 12 high sink outputs 5 Timers – Main Clock Controller with: Real time base, Beep and Clock-out capabilities – Configurable watchdog timer – 16-bit Timer A with: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes – 16-bit Timer B with: 2 input captures, 2 output compares, PWM and pulse generator modes
