EDA课程设计-电子钟

EDA 电子钟设计学院班级学号姓名一，设计要求设计一个电子时钟，要求可以显示时、分、秒，用户可以设置时间。

扩展功能要求：跑表功能，闹钟功能，调整数码管的亮度。

二、VHDL代码-------分频------library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fenpin isport (clk : in std_logic;--10m频clk_10000 : out std_logic;--1000分频clk_100 : out std_logic;--100k分频clk_1 : out std_logic--10m分频);end entity;architecture one of fenpin issignal Q_1 : integer range 0 to 500;signal Q_2 : integer range 0 to 50000;signal Q_3 : integer range 0 to 5000000;signal clk10000 : std_logic;signal clk100 : std_logic;signal clk1 : std_logic;beginfen1000:process(clk)beginif clk'event and clk='1' thenif Q_1=500 thenQ_1 <= 0;clk10000 <= not clk10000;else Q_1<=Q_1+1;end if;end if;end process;fen100k:process(clk)beginif clk'event and clk='1' thenif Q_2=50000 thenQ_2 <= 0;clk100<= not clk100;else Q_2<=Q_2+1;end if;end if;end process;fen10m:process(clk)beginif clk'event and clk='1' thenif Q_3=5000000 thenQ_3 <= 0;clk1<=not clk1;else Q_3<=Q_3+1;end if;end if;end process;clk_10000 <= clk10000;clk_100 <= clk100;clk_1 <= clk1;end one;------走表------library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity clock isport(clk_1:in std_logic;key8:in std_logic;hs_set,hg_set,ms_set,mg_set,ss_set,sg_set:in integer range 0 to 9; hs_out,hg_out,ms_out,mg_out,ss_out,sg_out:out integer range 0 to 9); end entity;architecture bhv of clock issignal shi:integer range 0 to 100;signal fen:integer range 0 to 100;signal miao:integer range 0 to 100;beginprocess(clk_1,key8,hs_set,hg_set,ms_set,mg_set,ss_set,sg_set)beginif key8='1' thenshi<=hs_set*10+hg_set;fen<=ms_set*10+mg_set;miao<=ss_set*10+sg_set;elsif clk_1'event and clk_1='1' thenif miao=59 thenmiao<=0;fen<=fen+1;elsif fen>59 thenfen<=0;shi<=shi+1;elsif shi>23 thenshi<=0;else miao<=miao+1;end if;end if;end process;sg_out<=miao rem 10;ss_out<=miao/10;mg_out<=fen rem 10;ms_out<=fen/10;hg_out<=shi rem 10;hs_out<=shi/10;end;---设置时间---library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity set isport(module:in integer range 0 to 4;key4,key1:in std_logic;hs_out,hg_out,ms_out,mg_out,ss_out,sg_out:out integer range 0 to 9);end entity;architecture bav of set issignal a:integer range 0 to 5;signal shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1: integer range 0 to 9; beginprocess(module,key4)beginif module=1 thenif key4'event and key4='1' thenif a < 5 thena<=a+1;else a<=0;end if;end if;end if;end process;process(module,a,key1)beginif module=1 thenif key1'event and key1='1' thencase a iswhen 0 =>if miaoge1 =9 thenmiaoge1<=0;else miaoge1<=miaoge1+1;end if;when 1 =>if miaoshi1 =5 thenmiaoshi1<=0;else miaoshi1<=miaoshi1+1;end if;when 2 =>if fenge1 =9 thenfenge1<=0;else fenge1<=fenge1+1;end if;when 3 =>if fenshi1 =5 thenfenshi1<=0;else fenshi1<=fenshi1+1;end if;when 4 =>if shige1 =9 thenshige1<=0;else shige1<=shige1+1;end if;when 5 =>if shishi1 =2 thenshishi1<=0;else shishi1<=shishi1+1;end if;end case;end if;end if;end process;sg_out<=miaoge1;ss_out<=miaoshi1;mg_out<=fenge1;ms_out<=fenshi1;hg_out<=shige1;hs_out<=shishi1;end;----模式转换----library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity change isport(key7:in std_logic;module:out integer range 0 to 4);end;architecture one of change issignal mo_s:integer range 0 to 4;beginprocess(key7)beginif key7'event and key7='1' thenif mo_s=4 thenmo_s<=0;else mo_s<=mo_s+1;end if;end if;end process;module<=mo_s;end;--------五选一选择器--------library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity xuanze isport(module:in integer range 0 to 4 ;shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9;shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:in integer range 0 to 9;shishi3,shige3,fenshi3,fenge3,miaoshi3,miaoge3:in integer range 0 to 9; fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge:in integer range 0 to 9;a0,a1,a3,a4,a6,a7:out integer range 0 to 9);end entity xuanze;architecture bhv of xuanze isbeginprocess(shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1,shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2,shishi3,shige3,fenshi3,fenge3,miaoshi3,miaoge3,fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge,module)begincase module iswhen 0 => a0<=shishi1;a1<=shige1;a3<=fenshi1;a4<=fenge1;a6<=miaoshi1;a7<=miaoge1;when 1 => a0<=shishi2;a1<=shige2;a3<=fenshi2;a4<=fenge2;a6<=miaoshi2;a7<=miaoge2;when 2 => a0<=fenshi;a1<=fenge;a3<=miaoshi;a4<=miaoge;a6<=xmiaoshi;a7<=xmiaoge; when 3 => a0<=shishi3;a1<=shige3;a3<=fenshi3;a4<=fenge3;a6<=miaoshi3;a7<=miaoge3;when 4 => a0<=8;a1<=8;a3<=8;a4<=8;a6<=8;a7<=8;end case;end process;end;-------秒表-------library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity miaobiao isport(clk_100:in std_logic;module:in integer range 0 to 4;key1,key4:in std_logic;ms_out,mg_out,ss_out,sg_out,sss_out,ssg_out:out integer range 0 to 9);end entity;architecture bhv of miaobiao issignal fen,miao,xmiao:integer range 0 to 99;signal start:std_logic:='0';signal reset:std_logic:='0';beginprocess(clk_100,key1,key4,module,reset,start)beginif module=2 thenif reset='1' thenfen<=0;miao<=0;xmiao<=0;elsif start='1' thenelsif clk_100'event and clk_100='1' then if xmiao=99 thenxmiao<=0;miao<=miao+1;elsif miao>59 thenmiao<=0;fen<=fen+1;elsif fen>23 thenfen<=0;else xmiao<=xmiao+1;end if;end if;end if;end process;process(key4,start)beginif key4'event and key4='1' thenstart<=not start;else start<=start;end if;end process;process(key1,reset)beginif key1'event and key1='1' thenreset<=not reset;else reset<= reset;end if;end process;ssg_out<=xmiao rem 10;sss_out<=xmiao/10;sg_out<=miao rem 10;ss_out<=miao/10;mg_out<=fen rem 10;ms_out<=fen/10;end;--------闹钟时间设置------library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity clockset isport(module:in integer range 0 to 4;key4,key1:in std_logic;hs_out,hg_out,ms_out,mg_out,ss_out,sg_out:out integer range 0 to 9); end entity;architecture bav of clockset issignal a:integer range 0 to 5;signal fenshi1,fenge1,miaoge1: integer range 0 to 9;signal shishi1: integer range 0 to 9:=1;signal shige1: integer range 0 to 9:=2;signal miaoshi1: integer range 0 to 9:=0;beginprocess(module,key4)beginif module=3 thenif key4'event and key4='1' thenif a < 5 thena<=a+1;else a<=0;end if;end if;end if;end process;process(module,a,key1)beginif module=3 thenif key1'event and key1='1' thencase a iswhen 0 =>if miaoge1 =9 thenmiaoge1<=0;else miaoge1<=miaoge1+1;end if;when 1 =>if miaoshi1 =5 thenmiaoshi1<=0;else miaoshi1<=miaoshi1+1;end if;when 2 =>if fenge1 =9 thenfenge1<=0;else fenge1<=fenge1+1;end if;when 3 =>if fenshi1 =5 thenfenshi1<=0;else fenshi1<=fenshi1+1;end if;when 4 =>if shige1 =9 thenshige1<=0;else shige1<=shige1+1;end if;when 5 =>if shishi1 =2 thenshishi1<=0;else shishi1<=shishi1+1;end if;end case;end if;end if;end process;sg_out<=miaoge1;ss_out<=miaoshi1;mg_out<=fenge1;ms_out<=fenshi1;hg_out<=shige1;hs_out<=shishi1;end;------闹钟喇叭输出------library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity clocklaba isport(clk_100:in std_logic;hs1,hg1,ms1,mg1,ss1,sg1:in integer range 0 to 9; hs2,hg2,ms2,mg2,ss2,sg2:in integer range 0 to 9; laba:out std_logic);end entity;architecture bav of clocklaba isbeginprocess(clk_100,hs1,hg1,ms1,mg1,ss1,sg1,hs2,hg2,ms2,mg2,ss2,sg2)beginif hs2=hs1 and hg2=hg1 and ms2=ms1 andmg2=mg1 and ss2=ss1 and sg2=sg1 thenlaba<=clk_100;else laba<='1';end if;end process;end;---------扫描显示---------library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity scan_led isport(clk_10000:in std_logic;key4:in std_logic;module:in integer range 0 to 4;a0,a1,a3,a4,a6,a7:in integer range 0 to 9;sg:out std_logic_vector(6 downto 0);bt:out std_logic_vector(7 downto 0));end;architecture one of scan_led issignal cnt8 :std_logic_vector(2 downto 0);--扫描计数信号signal a :integer range 0 to 15;signal liang: std_logic;signal flash:integer range 0 to 2;signal count1,count2,count3:integer range 0 to 10;beginp1: process(cnt8,liang,a0,a1,a3,a4,a6,a7)begincase cnt8 iswhen "000" => bt<= "0000000"&(liang);a<=a0;when "001" => bt<= "000000"&(liang)&'0';a<=a1;when "010" => bt<= "00000"&(liang)&"00";a<=15;when "011" => bt<= "0000"&(liang)&"000";a<=a3;when "100" => bt<= "000"&(liang)&"0000";a<=a4;when "101" => bt<= "00"&(liang)&"00000";a<=15;when "110" => bt<= '0'&(liang)&"000000";a<=a6;when "111" => bt<= (liang)&"0000000";a<=a7;when others => null;end case;end process p1;p2:process(clk_10000)beginif clk_10000'event and clk_10000 ='1' then cnt8 <= cnt8+1;end if;end process p2;p3:process(a)begincase a is --译码电路when 0 => sg<= "0111111";when 1 => sg<= "0000110";when 2 => sg<= "1011011";when 3 => sg<= "1001111";when 4 => sg<= "1100110";when 5 => sg<= "1101101";when 6 => sg<= "1111101";when 7 => sg<= "0000111";when 8 => sg<= "1111111";when 9 => sg<= "1101111";when 10 => sg<= "1110111";when 11 => sg<= "1111100";when 12 => sg<= "0111001";when 13 => sg<= "1011110";when 14 => sg<= "1111001";when 15 => sg<= "1000000";when others => null;end case;end process p3;process(key4,module) --选择亮度beginif module=4 thenif key4'event and key4='1' thenif flash =2 thenflash<=0;else flash<=flash+1;end if;end if;end if;end process;process(clk_10000,flash) --亮度分频beginif clk_10000'event and clk_10000 ='1' then case flash iswhen 0 => liang<='1';when 1 => if count1=2 thencount1<=0; liang<='1';else count1<=count1+1;liang<='0';end if;when 2 => if count2=4 thencount2<=0; liang<='1';else count2<=count2+1;liang<='0';end if;end case;end if;end process;end;--------例化-------library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity eclock isport(clk:in std_logic; --10m频率key1,key4,key7,key8:in std_logic;--功能键sg:out std_logic_vector(6 downto 0);--段选bt:out std_logic_vector(7 downto 0);--位选laba:out std_logic);--喇叭end entity;architecture bav of eclock iscomponent fenpin isport (clk : in std_logic;--10m频clk_10000 : out std_logic;--1000分频clk_100 : out std_logic;--100k分频clk_1 : out std_logic--10m分频);end component;component clock isport(clk_1:in std_logic;key8:in std_logic;hs_set,hg_set,ms_set,mg_set,ss_set,sg_set:in integer range 0 to 9; hs_out,hg_out,ms_out,mg_out,ss_out,sg_out:out integer range 0 to 9); end component;component scan_led is --扫描显示port(clk_10000:in std_logic;key4:in std_logic;module:in integer range 0 to 4;a0,a1,a3,a4,a6,a7:in integer range 0 to 9;sg:out std_logic_vector(6 downto 0);bt:out std_logic_vector(7 downto 0));end component;component change is --模式转换port(key7:in std_logic;module:out integer range 0 to 4);end component;component xuanze is --五选一选择器port(module:in integer range 0 to 4 ;shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9;shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:in integer range 0 to 9;shishi3,shige3,fenshi3,fenge3,miaoshi3,miaoge3:in integer range 0 to 9; fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge:in integer range 0 to 9;a0,a1,a3,a4,a6,a7:out integer range 0 to 9);end component;component set is --设置当前时间port(module:in integer range 0 to 4;key4,key1:in std_logic;hs_out,hg_out,ms_out,mg_out,ss_out,sg_out:out integer range 0 to 9);end component;component miaobiao is --秒表port(clk_100:in std_logic;module:in integer range 0 to 4;key1,key4:in std_logic;ms_out,mg_out,ss_out,sg_out,sss_out,ssg_out:out integer range 0 to 9);end component;component clockset is --闹钟时间设置port(module:in integer range 0 to 4;key4,key1:in std_logic;hs_out,hg_out,ms_out,mg_out,ss_out,sg_out:out integer range 0 to 9);end component;component clocklaba is --闹钟喇叭输出port(clk_100:in std_logic;hs1,hg1,ms1,mg1,ss1,sg1:in integer range 0 to 9;hs2,hg2,ms2,mg2,ss2,sg2:in integer range 0 to 9;laba:out std_logic);end component;signal moshis:integer range 0 to 4; --信号声明signal shishi1s,shige1s,fenshi1s,fenge1s,miaoshi1s,miaoge1s:integer range 0 to 9; signal shishi2s,shige2s,fenshi2s,fenge2s,miaoshi2s,miaoge2s:integer range 0 to 9; signal shishi3s,shige3s,fenshi3s,fenge3s,miaoshi3s,miaoge3s:integer range 0 to 9; signal fenshis,fenges,miaoshis,miaoges,xmiaoshis,xmiaoges: integer range 0 to 9; signal a0s,a1s,a3s,a4s,a6s,a7s: integer range 0 to 9;signal clk_10000s,clk_100s, clk_1s: std_logic;begin --元件例化u1:clock port map(clk_1=>clk_1s,key8=>key8,hs_set=>shishi2s,hg_set=>shige2s,ms_set=>fenshi2s,mg_set=>fenge2s,ss_set=>m iaoshi2s,sg_set=>miaoge2s,hs_out=>shishi1s,hg_out=>shige1s,ms_out=>fenshi1s,mg_out=>fenge1s,ss_out=>miaos hi1s,sg_out=>miaoge1s);u2:scan_led port map(clk_10000=>clk_10000s,key4=>key4,module=>moshis,a0=>a0s,a1=>a1s,a3=>a3s,a4=>a4s,a6=>a6s,a7=>a7s,sg=>sg,bt=>bt);u3:set port map(module=>moshis,key1=>key1,key4=>key4,hs_out=>shishi2s,hg_out=>shige2s,ms_out=>fenshi2s,mg_out=>fenge2s,ss_out=>miaos hi2s,sg_out=>miaoge2s);u4:change port map(key7=>key7,module=>moshis);u5:xuanze port map(module=>moshis,shishi1=>shishi1s,shige1=>shige1s,fenshi1=>fenshi1s,fenge1=>fenge1s,miaoshi1=>m iaoshi1s,miaoge1=>miaoge1s,shishi2=>shishi2s,shige2=>shige2s,fenshi2=>fenshi2s,fenge2=>fenge2s,miaoshi2=>m iaoshi2s,miaoge2=>miaoge2s,shishi3=>shishi3s,shige3=>shige3s,fenshi3=>fenshi3s,fenge3=>fenge3s,miaoshi3=>m iaoshi3s,miaoge3=>miaoge3s,fenshi=>fenshis,fenge=>fenges,miaoshi=>miaoshis,miaoge=>miaoges,xmiaoshi=>x miaoshis,xmiaoge=>xmiaoges,a0=>a0s,a1=>a1s,a3=>a3s,a4=>a4s,a6=>a6s,a7=>a7s);u6:miaobiao port map(clk_100=>clk_100s,module=>moshis,key1=>key1,key4=>key4,ms_out=>fenshis,mg_out=>fenges,ss_out=>miaoshis,sg_out=>miaoges,sss_out=>xmiaos his,ssg_out=>xmiaoges);u7:fenpin port map(clk=>clk,clk_10000=>clk_10000s,clk_100=>clk_100s,clk_1 =>clk_1s);u8:clockset port map(module=>moshis,key1=>key1,key4=>key4,hs_out=>shishi3s,hg_out=>shige3s,ms_out=>fenshi3s,mg_out=>fenge3s,ss_out=>m iaoshi3s,sg_out=>miaoge3s);u9:clocklaba port map(clk_100=>clk_100s,laba=>laba,hs1=>shishi3s,hg1=>shige3s,ms1=>fenshi3s,mg1=>fenge3s,ss1=>miaoshi3s,sg1=>miaog e3s,hs2=>shishi1s,hg2=>shige1s,ms2=>fenshi1s,mg2=>fenge1s,ss2=>miaoshi1s,sg2=>miaog e1s);end;三，RTL图四，管脚图五，心得体会经过两个多星期的上机实践学习，使我对VHDL语言有了更进一步的认识和了解，要想学好它要重在实践，要通过不断的上机操作才能更好地学习它，通过实践，我也发现我的好多不足之处，首先是自己在指法上还不行，经常按错字母，通过学习也有所改进；再有对VHDL语法还不熟悉，还有对VHDL语言中经常出现的错误也不了解，通过实践，使我在这几个方面的认识有所提高。