En_GreenCompute_ATOMSrv_MotheBoard_Spec_V1.0
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Green Compute Project Intel Atom Mother Board Hardware DesignV1.02011-9-27/Contents1 Scope (4)2 Preface (4)2.1 BackGround (4)2.2 Project Overview (5)2.3 License (5)3 MotherBoard Design (6)3.1 Components Diagram (6)3.2 CPU and Memory (6)3.3 Chipsets(Intel Provided) (7)3.3.1 North Bridge (7)3.3.2 South Bridge/Peripheral Bus Controller (7)3.4 SMBus 2.0 (8)3.5 Network Controller/Interfaces (8)4 Power System (9)4.1 Input Voltage (9)4.1.1 Input Voltage Level (9)4.1.2 Capacitive Load (9)4.1.3 Input Connector (9)4.2 CPU Voltage Regulation Module (VRM) (9)4.2.1 CPU Maximum Power (9)4.2.2 CPU VRM Optimizations (9)4.2.3 CPU VRM Efficiency (10)4.3 Hard Drive Power (10)4.3.1 Power Requirements (10)4.3.2 Output Protection (10)4.3.3 Spin-up Delay (10)4.4 System VRM Efficiency (10)4.5 Power On (11)5 BIOS (11)5.1 BIOS Interface and size (11)5.2 BIOS Socket (11)5.3 BIOS Configuration and Features (11)5.4 BOOT Menu (11)5.5 Console Redirect (12)5.6 PXE Boot (12)5.7 Other Boot Options (12)5.8 Remote BIOS Update (12)5.9 Event Log (13)5.10 Logged Errors (13)5.11 Error Threshold Setting (13)6 BMC/OOB (14)7 Debug Header (14)7.1 POST Error Beep Codes (14)7.2 Serial Console (15)7.3 System Reset (15)8 Hardware Monitoring (15)8.1 Onboard Voltage Monitoring (15)8.2 System Temperature (15)8.3 Fan Speed Control Modes (16)9 Connectors and Headers (16)9.1 Back Panel I/O Ports & Switches (16)9.1.1 LAN Ports / IPMI (17)9.1.2 Universal Serial Bus (USB) (18)9.1.3 VGA Connector (19)9.1.4 Rear UID (Unit ID) Switch (20)9.2 Header Connections (21)9.2.1 Serial Ports (JKCOM/JCOM) (21)9.2.2 Universal Serial Bus (JUSB/JKUSB) (22)9.2.3 Front Panel Accessible Add-on Card Header (JF2) (23)9.2.4 Onboard Speaker (JKSP1/SP1) and TPM Header (JTPM/JKTPM) (24)9.2.5 SMB and SATA DOM power (25)9.3 SATA Ports (25)9.4 Onboard Indicators (26)9.4.1 LAN Port LEDs (26)9.4.2 Unit ID LEDs (LE2/LKE2) (27)9.4.3 Main Power LED (LE1/LKE1) (27)9.4.4 Power/Suspend LED (DP2/DKP2) (27)9.4.5 SATA LED (DKP3/DP3) (28)9.4.6 BMC Heartbeat LED (DKP1/DP1) (28)10 Mechanical (29)10.1 Dimensions (29)10.2 Fixed Locations (29)10.3 Component Placement (29)10.4 PCB Thickness (30)10.5 Heat Sinks (30)10.6 Airflow (30)11 Environmental Requirements (31)12 Prescribed Materials (31)12.1 Disallowed Components (31)12.2 Capacitors and Inductors (32)12.3 Component De-rating (32)13 Appendix A: Front Panel Accessible Add-on Card Design (32)14 Appendix B: Mother Board on Chassis (33)1ScopeThis document defines the technical specifications for the Intel motherboard used in Open Low Power Compute Project servers.2Preface2.1BackGround is the biggest C2C e-commercial website in the world . With the increase of the end-users’ number and data volume, taobao have to involve of thousands of servers to meet the requirements of services development. Especially when the user experience is more and more important for the Internet applications, taobao have deployed the CDN (Content Delivery Network) WebCache servers on the edge of network to accelerate download speed of web pages, which had brought the number of servers to tens of thousands. Such a monster mount of servers are running at the same time, Power is becoming an increasingly large financial and scaling burden for taobao, who have to think about the reduction of the server power consumption for saving Capex and Opex.The simple solution of reducing the power consumption of servers is to replace the traditional server with low power servers. However it is not all the services or applications that fit to run on low power servers. The power consumption of CPU dominates that of the whole server, so low power severs has to adopt a low power CPU whose performance is weaker than that of traditional one. Therefore only the services with tiny CPU utilization are suitable for low power server replacement, which CDN cache service is the right one.Taobao found the low power servers in the market cannot meet the requirements, especially CDN cache servers. CDN cache system as a I/O-intensive application running on traditional server or low-power sever on sale only consume less than 5% CPU utilization with full I/O load. It seems that the art-of-stat server can not satisfy the need of power efficiency.2.2Project OverviewTherefore Taobao customized a green server for the CDN cache application with the support of Intel and SuperMicro. After tens of clusters' deployment, the performance of the server is verified and then the Green Compute project was launched, which not only achieve the energy reduction, high IO performance per chassis, easy operation and maintenance, but also the openness. The CDN cache server should not only one of deliveries in this project, more green servers will be announced in the future.One of most important components in this project is a customized motherboard. This document describes the Open Low Power Compute project Intel Atom motherboard, a dual Intel Atom D525 socket motherboard with 2 DIMM slots. The motherboard is power-effective and barebones, designed to provide the lowest capital and operating costs. Many features found in traditional ATOM motherboards have been removed from the design.2.3LicenseThis work is licensed under the TAPR Open Hardware License V1.0. To view a copy of this license, visit /ohl.htmlTHERE IS NO WARRANTY FOR THE DESIGN MATERIALS, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDETHE DESIGN MATERIALS “AS IS” WITHOUT WARRANTY OF ANY KIND,EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THEIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE DESIGN MATERIALS IS WITH YOU. SHOULD THE DESIGN MATERIALS PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.3MotherBoard Design3.1Components DiagramFigure1 Mother Board BLOCK DIAGRAM3.2CPU and MemoryThe motherboard adopt Intel Embedded CPU, Intel® Atom™D525 (Pineview-D) Dual Core,1.8GHz (13W) processor , which has following featuers:☐TDP (thermal design power) up to13W.☐On die, primary 32-kB instructions cache and 24-kB write-back data cache☐Intel® Hyper-Threading Technology 2-threads per core☐On die 2 x 512-kB, 8-way L2 cache☐Support for IA 32-bit☐Intel® 64 architecture☐Micro-FCBGA (Flip Chip Ball Grid Array) 8 packaging technologies☐Thermal management support via Intel® Thermal Monitor (TM1)☐Supports C0 and C1 states only☐Support 4 lanes in each direction, 2.5 Gbps per lane per direction, point-to-point DMI interface to Intel® NM10 Express Chipset.☐Integrated system memory controller whcih supports DDR2 and DDR3 (SO-DIMM only protocols)with one 64 bit wide channel accessing two DIMMs. The controller supports a maximum of two non-ECC DDR2 DIMMs or two un-buffered DIMMs, single or double sided;thus allowing up to four device ranks. Intel® Fast Memory Access (Intel® FMA) is supported.3.3Chipsets(Intel Provided)3.3.1North BridgeThe north bridge had been integrated into the CPU ,which Support 4 lanes in each direction, 2.5 Gbps per lane per direction, point-to-point DMI interface to Intel® NM10 Express Chipset.3.3.2South Bridge/Peripheral Bus ControllerThe south bridge adopt the Intel ICH9R chipset, which support following features:☐data buffering and interface arbitration required for the system to operate efficiently. I☐provides the bandwidth needed for the system to maintain its peak performance☐Connected with MCH(Memory Controller Hub) by DMI☐Up to 6 PCI-Express lanes☐ 6 Serial ATA (SATA) ports☐Offers the Intel Matrix Storage Technology which provides various RAID options for data protection and rapid data access. S☐Advanced Power Management☐SMBus 2.0 (I2C)☐SST/PECI Fan Speed Control☐SPI (Serial Peripheral interface) Flash☐Low Pin Count (LPC) Interface3.4SMBus 2.0The System Management Bus (SMBus) is a two-wire interface through which various system component chips can communicate with each other and with the rest of the system. It is based on the principles of operation of I2C. SMBus provides a control bus for system and power management related tasks. A system may use SMBus to pass messages to and from devices instead of tripping individual control lines. Removing the individual control lines reduces pin count. Accepting messages ensures future expandability. With System Management Bus, a device can provide manufacturer information, tell the system what its model/part number is, save its state for a suspend event, report different types of errors, accept control parameters, and return its status.SMBus specification defines two classes of electrical characteristics, low power and high power. The first class, originally defined in the SMBus 1.0 and 1.1 specifications, was designed primarily with Smart Batteries in mind, but could be used with other low-power devices. This version 2.0 of the specification introduces an alternative higher power set of electrical characteristics. This class is appropriate for use when higher drive capability is required, for example with SMBus devices on PCI add-in cards and for connecting such cards across the PCI connector between each other and to SMBus devices on the system board.3.5Network Controller/InterfacesTo save power consumption, MB adopts the low power network controller chipset, 2 Intel 82574L, which have following key features:☐PCIe v1.1 (2.5GT/s)☐Single Port☐Low power consumption⏹<750mW S0-Typ (state) 1000Base-T Active 90˚ C (mode) and⏹<300mW S0-Typ (state) 100Base-T Active (mode)☐Message Signal Interrupt Extension (MSI-X) supported☐TCP/UDP, IPv4, and IPv6 checksum offloads; Extended Tx descriptors for more offload capabilities☐TCP Segmentation/Transmit Segmentation Offloading (TSO)☐SMBus pass through, which Enables BMC to configure the Controller’s filters and management-related capabilities☐Preboot eXecution Environment (PXE) flash interface supportTow RJ45 connectors connect with above 2 controllers respectively and one of the controllers enable the “SMBus pass through “ for IPMI.4Power SystemMB accommodates 12V power through its Hot-Plug port.4.1Input Voltage4.1.1Input Voltage LevelThe nominal input voltage delivered by the power supply is 12.5VDC. The motherboard can accept and operate normally with an input voltage tolerance range between 10.8V and 13.2V. The motherboard's undervoltage protection level is less than 10V.4.1.2Capacitive LoadTo ensure compatibility with the system power supply, the motherboard cannot have a capacitive load greater than 8000μF. The capacitive load of the motherboard cannot exceed the maximum value of 8000μF under any operatin g condition listed in section 11, which defines environmental conditions.4.1.3Input ConnectorThe input connector is designed as cable free, which the MB is connected with add-on card through a slot. The adapter card connects the SATA drive, System Power, etc. between the MB and the chassis.4.2CPU Voltage Regulation Module (VRM)4.2.1CPU Maximum PowerThe TDP(Thermal Design Power) of Intel Atom D525 is 13 watts, which the motherboard have to handle.4.2.2CPU VRM OptimizationsCPU VRM is optimized to reduce cost and increase the efficiency of the power conversion system. The design should use only the minimum number of requiredphases to support the maximum CPU power defined in 4.2.1. A PSI (power state indicator) allows the shedding of unused phases, letting the VRM operate at its peak efficiency.4.2.3CPU VRM EfficiencyThe minimum efficiency for the CPU VRM is 91% over the 30% to 90% load, measured from the 12.5V input to the VRM output.4.3Hard Drive PowerThe hard Drives acquire the power from the adapter board(backend board) which connect the power supply with hard drives and mother board. The power connectors of hard drives are standard SATA power connector.4.3.1Power RequirementsSince the power of hard drives come from the back-end boards, the design of mother board can consider little about the power requirements of hard drives.4.3.2Output ProtectionThe 5V disk output power regulator protects against shorts and overload conditions.4.3.3Spin-up DelayWhen a hard drive spins up after the system powers on, it draws excessive current on both 5V and 12V. The peak current may reach the 0.4A-0,5A range in 5V. The system can have up to 6 hard drives installed, so each hard drive must spin up in sequence. The BIOS implements a 5 second delay between each hard drive spinning up.4.4System VRM EfficiencyThe design supplies high efficiency VRMs for all other voltage regulators over 20W not defined in this specification. All voltage regulation modules over 20W have 91% efficiency over the 30% to 90% load range.4.5Power OnThough the motherboard powers on upon application of power to the input connector, the power button is set for power on or off manually. The motherboard always resumes operation upon restoration of power in a power failure event, but the system power off normally, the motherboard has to be powered on by the power button.5BIOS5.1BIOS Interface and sizeThe BIOS interfaces the ICH9R via the SPI bus . To meet the requirements of functionalities for configure the mother board , the size of BIOS should be 32MB or bigger.5.2BIOS SocketThe BIOS chipset is fixed on the mother board, so there is no socket for BIOS chipset.5.3BIOS Configuration and FeaturesThe BIOS is tuned to minimize system power consumption and maximize the HDD IO capacity. It has the following features:⏹C1E power state⏹Unused USB ports disabled⏹Option to disable GPU on OS loaded⏹Active State Power Management Enabled on PCI-E Bus⏹Option to enable or disable the Hyper Threading of cores on CPU.Besides above key features, there are more important ones as below:⏹Watch Dog Enabled which allow the system to reboot when it is inactive for morethan 5 minutes.5.4BOOT MenuThe BIOS has a boot menu that allows its options to be configured before the operating system loads. The BIOS supports USB keyboards for navigating the BIOSmenu. The configuration options available through the boot menu include the following:⏹Boot device selection⏹Boot device priority⏹Enable/disable watchdog timer⏹Restore default settings⏹Enable/disable extended memory test⏹Enable/disable POST (quick boot)5.5Console RedirectThe BIOS detects the setting of GPU. If the setting of GPU is selected as enabled, the BIOS direct its output to the VGA port. If the setting of GPU is selected as disabled, the BIOS direct its output to the board-mounted RS-232 console output.5.6PXE BootThe BIOS supports Intel PXE boot. When PXE booting, the system first attempts to boot from the first Ethernet interface (eth0). If a PXE boot on the first Ethernet interface fails, the BIOS attempts to PXE boot from the second Ethernet interface (eth1).5.7Other Boot OptionsThe BIOS also supports booting from interfaces including SATA, USB and PCI-E.5.8Remote BIOS UpdateThe BIOS can be updated remotely under these scenarios:⏹Scenario 1: Sample/Audit BIOS settings☐Return current BIOS settings, or☐Save/export BIOS settings in a human-readable form that can be restored/imported (as in scenario 2)⏹Scenario 2: Update BIOS with pre-configured set of BIOS settings☐Update/change multiple BIOS settings☐Reboot⏹Scenario 3: BIOS/firmware update with a new revision☐Load new BIOS/firmware on machine and update, retaining current BIOS settings☐RebootAdditionally, the update tools have the following capabilities:⏹Update from the operating system over the LAN – the OS standard is RHEL v5.4 ⏹Can complete the update with a single reboot (no PXE boot, no multiple reboots) ⏹Minimal user interaction (like prompts)⏹Can be scripted and propagated to multiple machines5.9Event LogBased on SMBIOS specification Rev 2.6, the BIOS implements SMBIOS type 15 for an event log; the assigned area is large enough to hold more than 500 event records (assuming the maximum event record length is 24 bytes, then the size will be larger than 12KB), and follow the SMBIOS event log organization format for the event log. The design must provide a system access interface and application software to retrieve and clear the event log from the BIOS, including, at minimum, a Linux application for the RHEL operating system and driver as needed. The event log must be retrieved and stored as a readable text file that is easy to handle by a scripting language under Linux.5.10Logged Errors●CPU: Error categories include DRAM, Link, and L2 Cache.●IOH Error: Any errors that have a status register should be logged into the eventlog.Fatal or non-fatal classification follows the chipset vendor's recommendation. ●DMI error: Any errors that have a status register should be logged into the eventlog. Fatal or non-fatal classification follows the chipset vendor's recommendation.●PCI-E error: Any errors that have a status register should be logged into theevent log,including root complex, endpoint device, and any switch upstream/downstream ports if available. Link disable on errors should also be logged. Fatal, non-fatal, or correctable classification follows the chipset vendor's recommendation.●POST error: All POST errors detected by the BIOS during POST should belogged into the event log.●Miscellaneous errors: Miscellaneous errors include errors listed in the IO hubspecification, such as IOH Configuration Register Parity Error and Persistent SMBUS retry failure. Fatal, non-fatal, or correctable classification follows the chipset vendor's recommendation.5.11Error Threshold SettingAn error threshold setting must be enabled for both correctable and uncorrectable errors. Once the programmed threshold is reached, an event should be triggered andlogged.●DMI Error: Follow the chipset vendor's suggestion.●PCI-E Error: Follow the chipset vendor's suggestion.●IOH Error: Includes Core and Miscellaneous errors. Follow the chipset vendor'ssuggestion.6BMCThe MB adopt the NuvotonSM Baseboard Management Controller (BMC), which supports the 2D/VGAcompatible Graphics Core with the PCI interface, Virtual Media, and Keyboard/Video/Mouse (KVM) Redirection modules.The Nuvoton BMC interfaces with the host system via a PCI interface to communicate with the graphics core. It supports USB 2.0 and 1.1 for remote keyboard/mouse/virtual media emulation. It also provides LPC interface to control Super I/O functions and is connected to the network via an external Ethernet PHY module. It also communicates with onboard components via six SMBus interfaces, fan control,Platform Environment Control Interface (PECI) buses, and General Purpose I/O (T-SGPIO) ports.The Nuvoton WPCM450 (Manufacturer P/N WPCM450RA0BX) has all the features as described above plus IPMI 2.0 support.7Debug HeaderThe motherboard includes a debug header to display POST codes. The POST codes are sent to a board-mounted header in hexadecimal format via two 4-bit hex codes. The hex codes can be driven by either the legacy parallel port (port 80) on the hardware monitor, or 8 GPIO pins. A debug card with two 7-segment displays, two hex-to-7 segment converters, logic level to RS-232 shifter, and an RS-232 connector interfaces the debug header.7.1POST Error Beep CodesThis section lists POST (Power On Self Test) error beep codes for the AMI BIOS.POST error beep codes are divided into two categories: recoverable and terminal. This section lists Beep Codes for recoverable POST errors.When a recoverable type of error occurs during POST, BIOS will display a POST code that describes the problem. BIOS may also issue one of the following beep codes:● 1 long and two short beeps - video configuration error● 1 repetitive long beep - no memory detected● 1 continuous beep with the front panel Overheat LED on - system overheat●8 short beeps - display memory read/write error7.2Serial ConsoleThe output stage of the system's serial console is contained on the debug card. The TX and RX signals from the hardware monitor chip are sent to the debug header at the chip's logic levels (+3.3V). The debug card contains the RS-232 level shifter and the RS-232 D-9 connector.7.3System ResetThe master reset signal is routed to the debug header. If the master reset signal is connected to ground, the motherboard performs a complete system reset.8Hardware MonitoringThe motherboard should have an onboard System Hardware Monitor chip that supports hardware health monitoring.8.1Onboard Voltage MonitoringThe onboard voltage monitor will scan the following voltages continuously: CPU Cores, Chipset Voltage, Memory Voltage (+1.8V), +3.3V, +3.3V standby, +5V, +12V,and Vbat. Once a voltage becomes unstable, it will give a warning or send an error message to the screen. The User can adjust the voltage thresholds to define the sensitivity of the voltage monitor by using SD III.8.2System TemperatureThe CPU thermal technology that reports absolute temperatures (Celsius/Fahrenheit) has been upgraded to a more advanced feature by Intel in its newer processors. The basic concept is that each CPU is embedded by a unique temperature information that the motherboard can read. This ‘Temperature Threshold’ or ‘Temperature Tolerance’ has been assigned at the factory and is the baseline by which the motherboard takes action during different CPU temperature conditions (i.e., by increasing CPU Fan speed,triggering the Overheat Alarm, etc). Since CPUs can have different ‘Temperature Tolerances’, the installed CPU can now send its ‘Temperature Tolerance’ to the motherboard resulting in better CPU thermal management. Designer should have leveraged this feature by assigning a temperature status to certain thermal conditions in the processor (Low, Medium and High). This makes it easier for the user to understand the CPU’s temperature status,C).rather than by just simply seeing a temperature reading (i.e., 25o8.3Fan Speed Control ModesThe CPU temperature and the fan speed are correlative. When the CPU on-die temperature increases, the fan speed will also increase for effective system cooling. The design support following Fan Speed Control Modes:●Full Speed (@100% of PWM Cycle)●Performance (@70% of PWM Cycle)●Balanced (@50% of PWM Cycle)●Energy Saving (@30% of PWM Cycle).Select Full Speed to allow the onboard fans to run at full speed (of 100% Pulse Width Modulation Duty Cycle) for maximum cooling. The Full Speed setting is recommended for special system configuration or debugging. Select Performance for the onboard fans to run at 70% of the Initial PWM Cycle for better system cooling. The Performance setting is recommended for high-power-consuming and high-density systems. Select Balanced for the onboard fans to run at 50% of the Initial PWM Cycle in order to balance the needs between system cooling and power saving. The Balanced setting is recommended for regular systems with normal hardware configurations. Select Energy Saving for the onboard fans to run at 30% of the Initial PWM Cycle for best power efficiency and maximum quietness.9Connectors and Headers9.1Back Panel I/O Ports & SwitchesThe I/O ports are color coded in conformance with the PC 99 specification. See thefigure below for the colors and locations of the various I/O ports.Figure2 Back Panel Connectors and I/O PortsFigure3 I/O Port Locations and Definitions9.1.1LAN Ports / IPMIFor each node: There are LAN ports located on the I/O back panel. Theseports accept RJ45 type cables. There are two Ethernet ports (LAN1 & LAN2)Table2 RJ45/LAN Pin DefinitionsFigure4 Back Panel Connectors for LAN/IPMI9.1.2Universal Serial Bus (USB)For each node: 2 Universal Serial Bus ports (USB0/1) are located on the I/O back panel. Additionally, two USB headers (USB 2/3, 4/5) are also located on the motherboard to provide front chassis access. (Cables are not included).Table3 Back Panel USB 0/1,Pin DefinitionsTable4 Front Panel USB 2/3, USB 4/5 Pin DefinitionsFigure5 Connectors for USB9.1.3VGA ConnectorFor each node: A VGA connector is located next to the LAN Ports on the I/O back panel. This connector is used to provide video display. Refer to the boardTable5 VGA Port/Connector Pin DefinitionsFigure6 Back Panel Connectors for VGA9.1.4Rear UID (Unit ID) SwitchThe Rear UID Switch is used together with the Front Panel UID LED and Rear UID LED (located next to the UID Switch). The Rear UID Switch makes it easier to identify or 'mark' the unit by turning on both the blue UID LED on the back panel and the UID LED on the front panel simultaneously. It enables the user to locate the system from either side of the chassis when the system is installed for example with several units, to pinpoint which system the user wants to work on.Figure7 Back Panel Connectors for rear UID switch9.2Header ConnectionsThis section provides brief descriptions and pin-out definitions for onboard header connectors.9.2.1Serial Ports (JKCOM/JCOM)Two internal serial port headers (COM1,COM2) are located on theTable7 Serial Ports-COM1/COM2/COM3/COM4 Pin DefinitionsFigure8 Serial Ports header position on Mother Board9.2.2Universal Serial Bus (JUSB/JKUSB)For each node, there are two USB headers located on the motherboard to provide front chassis access. (Cables are not included). See the tables on theTable8 Front Panel USB 2/3, USB 4/5 Pin DefinitionsFigure8 USB header position on Mother Board9.2.3Front Panel Accessible Add-on Card Header (JF2)JF2 Add-on card header provides front access to the power supply, Serial ATA and Front Panel Control connections for the motherboard. Plug an Add-On card into this header to use the functions indicated above. This header is designed specifically for this motherboard. Refer to the following figure for details.Figure9 JF2 position on Mother Board9.2.4Onboard Speaker (JKSP1/SP1) and TPM Header(JTPM/JKTPM)An onboard speaker or buzzer is provided for each node. This device provides audible status messages for the mother board.TPM header is used to connect a Trusted Platform Module (TPM), available from a third-party vendor. A TPM is a security device that allows encryption and authentication of hard drives. It enables the motherboard to deny access if the TPM associated with the hard drive is not installed in the system. See theTable9 Trusted Platform Module Header Pin DefinitionsFigure10 speaker and TPM header position on Mother Board9.2.5SMB and SATA DOM powerA System Management Bus (SMB) header is located at JSMB1 for Node 1 and JKSMB1 for Node 2. Connect the appropriate cable here to use the SMB I2C connection on the management system. The pin definition can be find in following table:Table10 SMB Header Pin DefinitionThe SATA DOM Power on JWF1 for Node 1 and JKWF1 for Node 2 is used to supply power to SATA Disk-on-Module (DOM) solid-state storage devices.Figure11 SMB and SATA DOM Power position on Mother Board9.3SATA PortsThere are 4 SATA ports supported on each node. IKSATA1/ISATA1 are located on the motherboard, while the rest are supported through the hot-plug using an add-on card (see JF2,9.2.3). These four SATA ports are supported by。