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74ACT16373TTR资料

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1/10February2003sHIGHSPEED:tPD=5.3ns(TYP.)atVCC=5VsLOWPOWERDISSIPATION:ICC=8µA(MAX.)atTA=25°CsCOMPATIBLEWITHTTLOUTPUTSVIH=2V(MIN.),VIL=0.8V(MAX.)s50ΩTRANSMISSIONLINEDRIVINGCAPABILITYsSYMMETRICALOUTPUTIMPEDANCE:|IOH|=IOL=24mA(MIN)sOPERATINGVOLTAGERANGE:VCC(OPR)=4.5Vto5.5VsIMPROVEDLATCH-UPIMMUNITY

DESCRIPTIONThe74ACT16373isanadvancedhigh-speedCMOS16-BITD-TYPELATCH(3-STATE)fabricatedwithsub-micronsilicongateanddouble-layermetalwiringC2MOStecnology.This16bitD-Typelatchiscontrolledbytwolatchenableinputs(LE)andtwooutputenableinputs(OE).Thedevicecanbeusedastwo8-bitlatchesorone16-bitlatch.WhiletheLEinputisheldatahighlevel,theQoutputswillfollowthedatainputsprecisely.WhentheLEistakenlow,theQoutputswillbelatchedpreciselyatthelevelssetupattheDinputs.Whilethe(OE)inputislow,theoutputswillbeinanormallogicstate(highorlowlogiclevel)andwhileOEisinhighleveltheoutputswillbeinahighimpedancestate.ThisdeviceisdesignedtointerfacedirectlyHighSpeedCMOSsystemswithTTLandNMOScomponents.Allinputsandoutputsareequippedwithprotectioncircuitsagainststaticdischarge,givingthem2KVESDimmunityandtransientexcessvoltage.74ACT16373

16-BITD-TYPELATCHWITH3-STATEOUTPUTS(NONINVERTED)ORDERCODESPACKAGETUBET&RTSSOP

74ACT16373TTRTSSOP

PINCONNECTION元器件交易网www.cecb2b.com74ACT163732/10INPUTANDOUTPUTEQUIVALENTCIRCUIT

PINDESCRIPTION

TRUTHTABLE

X:Don‘tCareZ:HighImpedance*:QoutputsarelatchedatthetimewhentheLEinputistakenlowlogiclevel.IECLOGICSYMBOLSPINNoSYMBOLNAMEANDFUNCTION11OE3StateOutputEnableInput(ActiveLOW)2,3,5,6,8,9,11,121Q0to1Q7

3-StateOutputs

13,14,16,17,19,20,22,232Q0to2Q73-StateOutputs242OE3StateOutputEnableInput(ActiveLOW)252LELatchEnableInput36,35,33,32,30,29,27,262D0to2D7DataInputs

47,46,44,43,41,40,38,371D0to1D7DataInputs

481LELatchEnableInput4,10,15,21,28,34,39,45GNDGround(0V)

7,18,31,42VCCPositiveSupplyVoltage

INPUTSOUTPUTOELEDQHXXZLLXNOCHANGE*LHLLLHHH元器件交易网www.cecb2b.com74ACT163733/10LOGICDIAGRAM

ThislogicdiagramhasnottobeusedtoestimatepropagationdelaysABSOLUTEMAXIMUMRATINGS

AbsoluteMaximumRatingsarethosevaluesbeyondwhichdamagetothedevicemayoccur.Functionaloperationundertheseconditionsisnotimplied.SymbolParameterValueUnitVCCSupplyVoltage-0.5to+7VVIDCInputVoltage-0.5toVCC+0.5VVODCOutputVoltage-0.5toVCC+0.5VIIKDCInputDiodeCurrent±20mAIOKDCOutputDiodeCurrent±20mAIODCOutputCurrent±50mAICCorIGNDDCVCCorGroundCurrent±400mATstgStorageTemperature

-65to+150°CTLLeadTemperature(10sec)300°C元器件交易网www.cecb2b.com74ACT163734/10RECOMMENDEDOPERATINGCONDITIONS

1)VINfrom0.8Vto2.0V

DCSPECIFICATIONS

1)Maximumtestduration2ms,oneoutputloadedattime2)Incidentwaveswitchingisguaranteedontransmissionlineswithimpedancesaslowas50ΩSymbolParameterValueUnitVCCSupplyVoltage4.5to5.5VVIInputVoltage0toVCCVVOOutputVoltage0toVCCVTopOperatingTemperature-55to125°Cdt/dvInputRiseandFallTimeVCC=4.5to5.5V(note1)8ns/V

SymbolParameterTestConditionValueUnitVCC(V)TA=25°C-40to85°C-55to125°CMin.Typ.Max.Min.Max.Min.Max.VIHHighLevelInputVoltage4.5VO=0.1VorVCC-0.1V2.01.52.02.0V5.52.01.52.02.0VILLowLevelInputVoltage4.5VO=0.1VorVCC-0.1V1.50.80.80.85.51.50.80.80.8VVOHHighLevelOutputVoltage4.5IO=-50µA4.44.494.44.45.5IO=-50µA5.45.495.45.44.5IO=-24mA3.863.763.7

V5.5IO=-24mA4.864.764.7VOLLowLevelOutputVoltage4.5IO=50µA0.0010.10.10.15.5IO=50µA0.0010.10.10.14.5IO=24mA0.360.440.55.5IO=24mA0.360.440.5IIInputLeakageCur-rent5.5VI=VCCorGND±0.1±1±1µAIOZHighImpedanceOutputLeakegeCurrent5.5VI=VIHorVILVO=VCCorGND±0.5±5±10µA

ICCTMaxICC/Input5.5VI=VCC-2.1V0.61.51.6mAICCQuiescentSupplyCurrent5.5VI=VCCorGND880160µAIOLDDynamicOutputCurrent(note1,2)5.5VOLD=1.65Vmax7550mAIOHDVOHD=3.85Vmin-75-50mA元器件交易网www.cecb2b.com74ACT163735/10ACELECTRICALCHARACTERISTICS(CL=50pF,RL=500Ω,Inputtr=tf=3ns)

(*)Voltagerangeis5.0V±0.5VCAPACITIVECHARACTERISTICS

1)CPDisdefinedasthevalueoftheIC’sinternalequivalentcapacitancewhichiscalculatedfromtheoperatingcurrentconsumptionwithoutload.(RefertoTestCircuit).Averageoperatingcurrentcanbeobtainedbythefollowingequation.ICC(opr)=CPDxVCCxfIN+ICC/16(percircuit)SymbolParameterTestConditionValueUnitVCC(V)TA=25°C-40to85°C-55to125°CMin.Typ.Max.Min.Max.Min.Max.tPLHPropagationDelayTimeLEtoQ5.0(*)4.26.512.813.7nstPHL5.07.712.213.0tPLHPropagationDelayTimeDtoQ5.0(*)4.16.311.111.8nstPHL5.38.512.313.0tPZLOutputEnableTime5.0(*)5.76.514.215.1nstPZH5.07.712.113.0tPLZOutputDisableTime5.0(*)5.68.29.49.8nstPHZ5.07.010.711.0tW(H)LEMinimumPulseWidthHIGH5.0(*)2.21.72.62.6nstsSetupTimeDtoLE,HIGHorLOW5.0(*)1.2<1.01.41.4nsthHoldTimeDtoLE,HIGHorLOW5.0(*)1.3<1.01.61.6ns

SymbolParameterTestConditionValueUnitVCC(V)TA=25°C-40to85°C-55to125°CMin.Typ.Max.Min.Max.Min.Max.CINInputCapacitance5.03.5pFCOUTOutputCapaci-tance5.011pFCPDPowerDissipationCapacitance(note1)5.0fIN=10MHz31pF元器件交易网www.cecb2b.com

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MC74LCX16373

MC74LCX16373

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

1REV 1© Motorola, Inc. 199611/96Low-Voltage CMOS 16-Bit

Transparent Latch

With 5V-Tolerant Inputs and Outputs

(3-State, Non-Inverting)

The MC74LCX16373 is a high performance, non–inverting 16–bittransparent latch operating from a 2.7 to 3.6V supply. The device is bytecontrolled. Each byte has separate Output Enable and Latch Enableinputs. These control pins can be tied together for full 16–bit operation.High impedance TTL compatible inputs significantly reduce currentloading to input drivers while TTL compatible outputs offer improvedswitching noise performance. A VI specification of 5.5V allowsMC74LCX16373 inputs to be safely driven from 5V devices.The MC74LCX16373 contains 16 D–type latches with 3–state5V–tolerant outputs. When the Latch Enable (LEn) inputs are HIGH, dataon the Dn inputs enters the latches. In this condition, the latches aretransparent, i.e., a latch output will change state each time its D inputchanges. When LE is LOW, the latches store the information that waspresent on the D inputs a setup time preceding the HIGH–to–LOWtransition of LE. The 3–state outputs are controlled by the Output Enable(OEn) inputs. When OE is LOW, the outputs are enabled. When OE isHIGH, the standard outputs are in the high impedance state, but this doesnot interfere with new data entering into the latches.

74LS377中文资料

74LS377中文资料

74LS377中文资料:

54/74377

双 2 位 D 触发器

简要说明：

54/74LS377 为八 D 边沿触发器，其主要电特性的典型值如下（具体厂家有

可能不是完全一至）：

型号 fm PD

54/74LS377 40MHz 85mW

当允许控制端/E 为低电平时，时钟端（CP）脉冲上升沿作用下，输出端 Q

与数据端 D 相一致。当 CP 为高电平或者低电平时，D 对 Q 没影响。

引出端符号：

/E 允许控制端（低电平有效）

D0~D7 数据输入端

Q0~Q7 数据输出端

CP 时钟输入端（上升沿有效）

外接管腿;:逻辑图：功能表：

74FCT162373中文资料

74FCT162373中文资料

16-Bit Latches CY74FCT16373T

CY74FCT162373T

SCCS054 - August 1994 - Revised March 2000Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modified to remove devices not offered.

Copyright © 2000, Texas Instruments IncorporatedFeatures

•FCT-E speed at 3.4 ns

•Power-off disable outputs permits live insertion

•Edge-rate control circuitry for significantly improved

noise characteristics

•Typical output skew < 250 ps

•ESD > 2000V

•TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)

packages

•Industrial temperature range of−40˚C to +85˚C

•V

CC = 5V± 10%

CY74FCT16373T Features:

•64 mA sink current, 32 mA source current

•Typical V

OLP (ground bounce) <1.0V at V

CC = 5V,

T

A = 25˚C

CY74FCT162373T Features:

•Balanced 24 mA output drivers

•Reduced system switching noise

•Typical V

OLP (ground bounce) <0.6V at V

CC = 5V,

T

A= 25˚CFunctional Description

74ALVC16374DTR资料

74ALVC16374DTR资料

© Semiconductor Components Industries, LLC, 2006

June, 2006 − Rev. 11Publication Order Number:

74ALVC16374/D74ALVC16374

Low−Voltage 1.8/2.5/3.3 V

16−Bit D−Type Flip−Flop

With 3.6 V−Tolerant Inputs and Outputs

(3−State, Non−Inverting)

The 74ALVC16374 is an advanced performance, non−inverting

16−bit D−type flip−flop. It is designed for very high−speed, very

low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The

ALVC16374 is byte controlled, with each byte functioning identically,

but independently. Each byte has separate Output Enable and Clock

Pulse inputs. These control pins can be tied together for a full 16−bit

operation.

The 74ALVC16374 consists of 16 edge−triggered flip−flops with

individual D−type inputs and 3.6 V−tolerant 3−state outputs. The

clocks (CPn) and Output Enables (OEn) are common to all flip−flops