1-Welcom and An Overview of the Canadian Life Insurance Industry

REV. 1.0.11.0INTRODUCTIONThis user’s manual is for the XR17V358/354 evaluation board revision 3.x. The XR17V358 and XR17V354 are available in the same package and are pin compatible, therefore they share the same evaluation board. This user’s manual gives an overview of the evaluation board and the jumper settings for testing various modes using the evaluation board. The ordering information for the XR17V358/354 evaluation board is as following:ORDERING INFORMATIONP ART NUMBER D ESCRIPTIONXR17V354IB-0A-EVB Single device XR17V354 is installed on the board.XR17V354IB-E4-EVB Two devices are installed on the board. The master device is XR17V354. The slave device on expansion interface is a XR17V354.XR17V354IB-E8-EVB Two devices are installed on the board. The master device is XR17V354. The slave device on expansion interface is a XR17V358.XR17V358IB-0A-EVB Single device XR17V358 is installed on the board.XR17V358IB-E4-EVB Two devices are installed on the board. The master device is XR17V358. The slave device on expansion interface is a XR17V354.XR17V358IB-E8-EVBTwo devices are installed on the board. The master device is XR17V358. The slave device on expansion interface is a XR17V358.2.0OVERVIEWThis evaluation board has a x1 PCIe connector and will work in any x1, x4 or x16 PCIe slot. Up to 16 UART ports can be tested on this evaluation board when 2 XR17V358 are installed. The PCIe interface of the master device is connected directly to the PCIe connector. The master device communicates with the slave device via Exar’s proprietary expansion interface. The PCIe interface on the slave device is not used. F IGURE 1. PCI E AND E XPANSION I NTERFACEREV. 1.0.1 2.1Evaluation Board Components for Master DeviceThe table below shows all of the components that are on the evaluation board for the master device.T ABLE 1: C OMPONENTS O F T HE XR17V358 E VALUATION B OARD F OR M ASTER D EVICE U NIT P ART F UNCTIONU2XR17V358IB176-FXR17V358 or XR17V354 PCIe UART master device.XR17V354IB176-FU16SP336EEY-L Exar RS-232/RS-485 Transceiver for master device UART channel 0.U11SP336EEY-L Exar RS-232/RS-485 Transceiver for master device UART channel 1.U25SP336EEY-L Exar RS-232/RS-485 Transceiver for master device UART channel 2.U24SP336EEY-L Exar RS-232/RS-485 Transceiver for master device UART channel 3.U28SP336EEY-L Exar RS-232/RS-485 Transceiver for master device UART channel 4.U27SP336EEY-L Exar RS-232/RS-485 Transceiver for master device UART channel 5.U17SP336EEY-L Exar RS-232/RS-485 Transceiver for master device UART channel 6.U22SP336EEY-L Exar RS-232/RS-485 Transceiver for master device UART channel 7.U6SP336EEY-L Exar RS-232/RS-485 Transceiver for master device UART RI# signalschannels 0-3.U13SP336EEY-L Exar RS-232/RS-485 Transceiver for master device UART RI# signalschannels 4-7.U9SP3497EEN-L Exar RS-485 Transceiver for master device UART channel 4. Notinstalled.U10SP3497EEN-L Exar RS-485 Transceiver for master device UART channel 5. Notinstalled.U21SP336EEY-L Exar RS-232/RS-485 Transceiver for master device UART channel 3and 4 for RS-485 full-duplex testing. Not installed.U3HSDL2300IR Transceiver. Not installed.U2693C46 (PDIP)External EEPROM for storing Vendor ID and Device ID. Not installed.U3093C46 (TSSOP)External EEPROM for storing Vendor ID and Device ID. Installed, notprogrammed.2.2Evaluation Board Components for Slave DeviceThe table below shows all of the components that are on the evaluation board for the slave device. If the slave device is not installed, then these components will also not be installed.T ABLE 2: C OMPONENTS O F T HE XR17V358 E VALUATION B OARD F OR S LAVE D EVICE U NIT P ART F UNCTIONXR17V358 or XR17V354 PCIe UART slave device.U1XR17V358IB176-FXR17V354IB176-FU5SP3245EEA-L Exar RS-232 Transceiver for slave device UART channel 0.U4SP3245EEA-L Exar RS-232 Transceiver for slave device UART channel 1.U8SP3245EEA-L Exar RS-232 Transceiver for slave device UART channel 2.REV. 1.0.1T ABLE 2: C OMPONENTS O F T HE XR17V358 E VALUATION B OARD F OR S LAVE D EVICE U NIT P ART F UNCTIONU7SP3245EEA-L Exar RS-232 Transceiver for slave device UART channel 3.U15SP3245EEA-L Exar RS-232 Transceiver for slave device UART channel 4.U14SP3245EEA-L Exar RS-232 Transceiver for slave device UART channel 5.U19SP3245EEA-L Exar RS-232 Transceiver for slave device UART channel 6.U20SP3245EEA-L Exar RS-232 Transceiver for slave device UART channel 7.U12SP3497EEN-L Exar RS-485 Transceiver for slave device UART channel 4.U18SP3497EEN-L Exar RS-485 Transceiver for slave device UART channel 5.U23SP336EEY-L Exar RS-232/RS-485 Transceiver for slave device UART channel 3and 4 for RS-485 full-duplex testing. Not installed.2.3Jumper Settings for Power Sources for Master DeviceThe following table shows the jumper settings for selecting/enabling the power source for the Master Device.T ABLE 3: J UMPER S ETTINGS F OR P OWER S OURCES F OR M ASTER D EVICEJ UMPER F UNCTIONS C OMMENTSJ45 3.3V supply voltage for the 3.3V Core Not installed. Trace between 1&2.J42Enables/Disables Internal Buck Regulator Jumper is not in - Internal buck regulator is enabled(default).J66 3.3V supply voltage for the output stage of buck regulator Not installed. Trace between 1&2.J63 3.3V supply voltage for analog blocks of buck regulator Not installed. Trace between 1&2.J62 1.2V regulated voltage from internal buck Not installed. Trace between 1&2.J67 1.2V supply voltage for 1.2V PHY Not installed. Trace between 1&2.J56 1.2V supply voltage for 1.2V Core Not installed. Trace between 1&2.2.4Jumper Settings for Power Sources for Slave DeviceThe following table shows the jumper settings for selecting/enabling the power source for the Slave Device.T ABLE 4: J UMPER S ETTINGS F OR P OWER S OURCES F OR S LAVE D EVICEJ UMPER F UNCTIONS C OMMENTSJ32 3.3V supply voltage for the 3.3V Core Not installed. Trace between 1&2.J31Enables/Disables Internal Buck Regulator Jumper is not in - Internal buck regulator is enabled(default).J68 3.3V supply voltage for the output stage of buck regulator Not installed. Trace between 1&2.J65 3.3V supply voltage for analog blocks of buck regulator Not installed. Trace between 1&2.J64 1.2V regulated voltage from internal buck Not installed. Trace between 1&2.J70 1.2V supply voltage for 1.2V PHY Not installed. Trace between 1&2.J34 1.2V supply voltage for 1.2V Core Not installed. Trace between 1&2.REV. 1.0.1 2.5Jumper/Switch Settings for RS-232 or RS-485 for Master DeviceThe following table (Table 5) shows the setting for selecting between the RS-232 or RS-485 modes for the master device. The Half-duplex RS-485 mode can be enabled by either setting the FCTR bit-5 to 1 or connecting the EN485# pin to GND.T ABLE 5: S ETTINGS F OR RS-232 OR RS-485 M ODE F OR M ASTER D EVICEREV. 1.0.1T ABLE 5: S ETTINGS F OR RS-232 OR RS-485 M ODE F OR M ASTER D EVICEREV. 1.0.1 T ABLE 5: S ETTINGS F OR RS-232 OR RS-485 M ODE F OR M ASTER D EVICEREV. 1.0.1T ABLE 5: S ETTINGS F OR RS-232 OR RS-485 M ODE F OR M ASTER D EVICEREV. 1.0.1 2.6Jumper Settings for RS-232 or RS-485 for Slave DeviceThe following table shows the setting for selecting between the RS-232 or RS-485 modes for the slave device: T ABLE 6: S ETTINGS F OR RS-232 OR RS-485 M ODE F OR S LAVE D EVICEJ UMPERS/S WITCHF UNCTIONS C OMMENTSJ23 3.3V supply voltage for RS-232 and RS-485 Trans-ceivers for the slave deviceJumper between 1&2J29Enable Auto RS-485 Half-Duplex Direction Control upon power-up Jumper between 1&2 enables this feature for all 8 channels. This feature can be disabled in the software after power-up.J37Enable IR mode upon power-up Jumper between 1&2 enables this feature for all 8channels. This feature can be disabled in the softwareafter power-up.J15Half-Duplex RS-485 control select for DE for UART channel 3Note: SP3497E is not installed.■No jumper installed enables RS-485 driver■Jumper between 2&3 selects RTS# as the half-duplex control output■Jumper between 1&2 disables the RS-485 driverJ18Half-Duplex RS-485 control select for RE# for UART channel 3Note: SP3497E is not installed.■No jumper installed disables RS-485 receiver■Jumper between 1&2 enables the RS-485 receiver■Jumper between 2&3 selects RTS# as the half-duplex control outputJ12Half-Duplex RS-485 control for transmitter andreceiver for UART channel 3Note: SP3497E is not installed.■Not installedJ24Half-Duplex RS-485 control select for DE for UART channel 4Note: SP3497E is not installed.■No jumper installed enables RS-485 driver■Jumper between 2&3 selects RTS# as the half-duplex control output■Jumper between 1&2 disables the RS-485 driverJ28Half-Duplex RS-485 control select for RE# for UART channel 4Note: SP3497E is not installed.■No jumper installed disables RS-485 receiver■Jumper between 1&2 enables the RS-485 receiver■Jumper between 2&3 selects RTS# as the half-duplex control outputJ25Half-Duplex RS-485 control for transmitter andreceiver for UART channel 4Note: SP3497E is not installed.■Not installedREV. 1.0.12.7Pinout for connectorsThe RS232 signals on the evaluation board goes to the SCSI type ultra micro DB68 connector. Figure 2 shows the DB68 connector on the board. Table 7 shows the pinout.F IGURE 2. DB68 CONNECTORT ABLE 7: P INOUT FOR THE DB68P IN NUMBER S IGNALN AMEP IN NUMBERS IGNALN AMEP IN NUMBERS IGNALN AMEP IN NUMBERS IGNALN AME1RXD718RXD335RXD852RXD4 2CT719CT336CT853CT4 3RIN720RIN337RIN854RIN4 4RT721RT338RT855RT4 5DCD722DCD339DCD856DCD4 6DT723DT340DT857DT4 7DS724DS341DS858DS4 8TXD725TXD342TXD859TXD4 9GND26GND43GND60GND 10TXD527TXD144TXD661TXD2 11DS528DS145DS662DS2 12DT529DT146DT663DT2 13DCD530DCD147DCD664DCD2 14RT531RT148RT665RT2 15RIN532RIN149RIN666RIN2 16CT533CT150CT667CT2 17RXD534RXD151RXD668RXD2NOTICEEXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2011 EXAR Corporation Datasheet June 2011.Send your UART technical inquiry with technical details to hotline: ************************.Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.REV. 1.0.1Figure 3 shows the DB9 cnnector. Table 8 shows the DB9 connector pinout. F IGURE 3. DB9 CONNECTORT ABLE 8: DB9 C ONNECTOR P INOUTP IN NUMBER 123456789S IGNALDCDxRXDxTXDxDTxGNDDSxRTxCTxRINx2.8MPIO pinsThe MPIO pins of the both the master and slave devices are connected to LEDs or test points on the evaluation board. Refer to page 6 of the evaluation board schematic for details.3.0DRIVERSSoftware drivers for Windows and Linux are available from Exar. Send an e-mail with your driver request to ************************.。

1300 Henley CourtPullman, WA 99163509.334.6306 FMC-HMI™ Reference ManualRevised September 19, 2012This manual applies to the FMC-HMI rev. BOverviewThe FPGA Mezzanine Card - Human Machine Interface (FMC-HMI) peripheral board enables developers to add a human interface to field-programmable gate array (FPGA) based systems. The FMC-HMI provides a development platform for customers to utilize image capture, touch digitizer and graphical user interface applications.1 Functional DescriptionThe FMC-HMI captures light with the Aptina MT9D112 digital image sensor. This sensor provides a maximum resolution of 1600x1200 at 15 frames per second. The Aptina has a 10-bit raw color depth, an I2C control bus, and can utilize Bayer, RGB, and YCrCb output formats. This image sensor utilizes an automatic exposure, gain, and white balance with powerful image correction algorithms, image scaling, and a FIFO output.1.1 Aptina MT9D112The Aptina MT9D112 is a small (8.5mm x 8.5mm x 5mm) integrated System-on-Chip (SoC) assembly that includes a 2Mp complementary metal–oxide–semiconductor (CMOS) sensor array, a fixed-focus lens with a 3.81mm equivalent focal length, and an image processor. The sensor assembly comes taped to the board and connects through a 23-pin flexible printed circuit (FPC) cable.The FMC-HMI.•Aptina MT9D112 fixed-focus, 2Mp CMOSdigital image sensor•ADI SSM2603 audio codec with 3.5mmline in, microphone in, line out andheadphone out jacks•Shanghai Tianma TM050RBH01 5”800x480 TFT LCD with integrated 4-wiretouch panel•Male FMC LPC connector for digitalsignals•AMS header for analog signals•12-pin female Pmod header•Piezoelectric buzzer•Compatible with wide range of VADJvoltages (1.8V-3.3V)Features include:Users can control the image processor via a standard two-wire interface. The FMC-HMI transfers image data via an 8-bit pixel bus with additional synchronization signals.Note: Operators that desire more information on the Aptina MT9D112 should consult theAptina Imaging product information sheets at:/products/soc/mt9d112d00stc/Or consult the Digilent Inc. VmodCAM product reference manual at:/Data/Products/VMOD-CAM/VmodCAM_rm.pdf1.2 ADI SSM2603The FMC-HMI features an Analog Devices Inc. SSM2603 Low Power Audio Codec thatprovides simultaneous playback and recording capabilities to and from a variety of sources through standard audio jacks. Users control the audio with a standard two-wire interface and an I²S compatible bus presents the digital audio.Note: For more information on the SSM2603 see ADI datasheets available online at:/en/audiovideo-products/audio-codecs/ssm2603/products/product.html1.3 Shanghai Tianma TM050RBH01The Shanghai Tianma TM050RBH01 has a 5” light emitting diode (LED) backlit thin film transistor-liquid crystal display (TFT-LCD) assembly that integrates a resistive touch panel covering the whole active display area.The TFT-LCD assembly arrives taped to the printed circuit board (PCB) and connects through a 45-pin FPC connector. The FPC cable carries both the digital display interface and analog touch panel signals.The display interface is a straight-forward 24-bit RGB pixel bus. The support circuitry on-board the FMC-HMI provides backlight intensity control with pulse width modulation.The four analog signals, X+, X-, Y+, Y- comprise the X and Y plate electrodes. To determine the touch coordinates, users must bias the plates and measure the resistive divider formed by the electrically charged resistive plates using an analog-to-digital converter (ADC) count. When operators use the Shanghai Tianma with system boards that have XADC support, they can use the AMS header to digitalize the analog touch panel signals. An on-board analog multiplexer (MUX) switch helps users select the correct panel electrodes for measurement.Note: For more information on the TM050RBH01 consult the product details for the VmodTFT - Color LCD Touch Screen available online at:/Products/Detail.cfm?NavPath=2,648,979&Prod=VMOD-TFT1.4 FMC SupportThe FMC-HMI uses a Samtec ASP-134604-01 low pin-count male connector as the main connector for digital signals. Everything except for the PCB dimension requirements conforms to the VITA 57.1 specs. The connector supports the full range of 1.8V-3.3V bank supply voltages (VADJ).1.5 AMS HeaderThe AMS header is there to provide support for the XADC feature of seven-series system boards. Operators can use the AMS header signals to bias the touch panel by selecting the analog MUX inputs and carrying the differential analog signal to the FPGA pins for measurement.1.6 12-pin Pmod HeaderA female double Pmod connector offers users the option to connect various Pmods to the system board. Operators can utilize the ADG3308 auto-sensing bidirectional level translator to level shift from 3.3V to VADJ. It is important to note that due to its low drive current this level translation prohibits the use of strong pull resistors (<60kOhm) on data signals.1.7 Piezoelectric BuzzerA Kingstate Electronics Corp. KMTG1603-1 is beneath the screen to provide audible feedback for various frequencies.Note: For more information on the KMTG1603-1 see Kingstate product information at:/Products/Products/ProductItem/tabid/186/rtab/187/Default.aspx?ItemId=399。

电路笔记CN-0105连接/参考器件利用ADI公司产品进行电路设计AD762616位、10 MSPS PulSAR差分ADC 放心运用这些配套产品迅速完成设计。

ADA4932-1低功耗差分ADC驱动器欲获得更多信息和技术支持，请拨打4006-100-006或访问/zh/circuits。

2.7 V、800 µA、80 MHz轨到轨输入/输出放大器AD803116位10 MSPS ADC AD7626的单端转差分高速驱动电路电路功能与优势图1所示电路可将高频单端输入信号转换为平衡差分信号，用于驱动16位10 MSPS PulSAR® ADC AD7626。

该电路采用低功耗差分放大器ADA4932-1来驱动ADC，最大限度提升AD7626的高频输入信号音性能。

此器件组合的真正优势在于低功耗、高性能。

ADA4932-1具有低失真（10 MHz时100 dB SFDR）、快速建立时间（9 ns达到0.1％）、高带宽（560 MHz，-3 dB，G = 1）和低电流（9.6 mA）等特性，是驱动AD7626的理想选择。

它还能轻松设定所需的输出共模电压。

该组合提供了业界先进的动态性能并减小了电路板面积：AD7626采用5 mm × 5mm、32引脚LFCSP封装，ADA4932 -1采用3mm× 3mm、16引脚LFCSP封装），AD8031采用5引脚SOT23封装。

AD7626具有突破业界标准的动态性能，在10 MSPS下信噪比为91.5 dB，实现16位INL性能，无延迟，LVDS接口，功耗仅有136 mW。

AD7626使用SAR架构，主要特性是能够以10 MSPS无延迟采样，不会发生流水线式ADC常有的“流水线延迟”，同时具备出色的线性度。

图1. ADA4932-1驱动AD7626（未显示去耦和所有连接）Rev.0“Circuits from the Lab” from Analog Devices have been designed and built by Analog Devicesengineers. Standard engineering practices have been employed in the design and constructionof each circuit, and their function and performance have been tested and verified in a labenvironment at room temperature. However, you are solely responsible for testing the circuitand determining its suitability and applicability for your use and application. Accordingly, inno event shall Analog Devices be liable for direct, indirect, special, incidental, consequential orOne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: Fax: 781.461.3113©2010 Analog Devices, Inc. All rights reserved.CN-0105电路笔记电路描述ADA4932-1差分驱动器的增益配置约为1（单端输入至差分输出）。

2024年春季学期阶段性学业质量监测九年级英语（全卷满分120分，考试时间120分钟）注意事项：1. 答题前，考生务必将姓名、座位号、考籍号填写在试卷和答题卡上。

2. 考生作答时，请在答题卡上作答(答题注意事项见答题卡) ，在本试卷上作答无效。

3. 考试结束后，将本试卷和答题卡一并交回。

4. 先考听力，在听力开始前有两分钟听力试音时间。

一、听力部分（共30小题，每小题1分，共30分）（一）听句子，选图片。

你将听到五个句子，请选出与所听句子内容相符的图片，有一幅图是多余的。

每个句子读两遍。

A B C D E F1. _______2. _______3. _______4. _______5. _______（二）听句子，选答语。

你将听到五段对话，每段对话后有一个小题，请根据对话内容，选出最佳答案。

每段对话读两遍。

6. What class is the boy in?A. Class One.B. Class Five.C. Class Seven.7. How is the weather today?A. Rainy.B. Cloudy.C. Sunny.8. What does Mary's mother like?A. Chocolate.B. CDs.C. Scarves.9. What are the speakers going to do?A. Go biking.B. Climb mountains.C. Have a picnic.10. Why was the boy late for school this morning?A. Because his bike was broken.B. Because he didn't catch the bus.C. Because he got up late. （三）听长对话，选择最佳答案。

你将听到三段对话，请根据对话内容，选出每个问题的最佳答案。

Energy Measurement ProductsADE Product Family OverviewThe Analog Devices IC (ADE) family combines industry-leading data conversion technology with a fixed function digital signal processor (DSP) to perform the calculations essential to an electronic energy meter. The portfolio includes single-phase products and polyphase products for stepper motor and LCD display meter designs, with five critical measurements available: watt, V rms, I rms, VA, and VAR.With 175 million units deployed in the field, ADI has added to the portfolio the ADE71xx and ADE75xx product families that simplify energy meter design by providing all the features needed for an accurate, reliable, and fully functional energymeter with LCD display in a single IC.ADE Product Family • High accuracy exceeds IEC and ANSI standards • Proprietary 16-bit ADCs and DSP provide high accuracy over large variations in current, environmental conditions, and time • Reliability proven with over 175 million units deployed in the field• On-chip reference with low temperature drift (20 ppm to 30 ppm typ)• On-chip power supply monitoring• On-chip creep protection (no-load threshold)• Single 5 V supply • Low power consumption • Instantaneous active power output for calibration or interface to an MCU • Miswiring or reverse power indication• Tamper detection optionsADE Pulsed Output Products or Stepper Motor Display Meters • Exceeds IEC 61036/62053-21, IEC 60687/62053-22, ANSI C12.16, and ANSI C12.20• Active energy measurement with less than 0.1% error over a dynamic range of 500 to 1 at 25°C• Power consumption as low as 15 mW (typ) for single-phase products and 30 mW (typ) for polyphase products• Built-in current channelamplifier allows the use of low resistance, low cost shunts • Active energy, low frequency outputs directly driveelectromechanical counters • Single 5 V supplyADE Serial Interface Products for LCD Meters• Exceeds IEC 61036/62053-21, IEC 60687/62053-23 (for multifunction products), ANSI C12.16, and ANSI C12.20• Active energy measurement with less than 0.1% error over a dynamic range of 1000 to 1 at 25°C• Active energy and sampled waveform data• Multifunction products provide VAR, VA, V rms, and I rms • User-programmable power quality monitoring features • Digital calibration for power, phase, and offset• Serial peripheral interface (SPI) with interrupt request pin (IRQ)• Single 5 V supplyIntegrated Products for LCD Meters• Exceeds IEC 61036/62053-21, IEC 60687/62053-23 (for multifunction products), ANSI C12.16, and ANSI C12.20• Single chip solution integrates ADE measurement core for watts, VAR, VA, V rms, and I rms• 8052 MCU core with flash memory• 104-segment LCD driver with contrast control for low/high temperature visibility • Low power RTC (1.5 μA typ) with digital compensation for temperature performance • Power fail and batterymanagement with no external components• Reference with low temperature drift (5 ppm/°C typ)• Noninvasive in-circuitemulation/energymeterValue of ADE Products1. Proven TechnologyAnalog Devices is the market leader in sales of energy metering ICs with over 175 million meters deployed worldwide with ADE products.• Quality: Strict quality and test standards applied to ADE products throughout design and manufacturing stages ensure low meter production failure rate and uniform part-to-part characteristics.• Reliability: Accelerated life expectancy tests on ADE products, representing more than 60 years of field usage, reduce probability of meter failure due to IC failure.• Performance: Proprietary Σ-∆ ADCs provide excellent performance with an error of less than 0.1% over an extended current dynamic range.2. Ease of DesignAnalog Devices ADE solutions aim to simplify energy meter design, reduce system cost, and reduce time to market with:• Integration of ADCs and fixed function DSP on a single chip leading to a single IC energy meter• Integration of ADCs and fixed function DSP on a single chip reduces processing requirements, enabling the use of a lower cost MCU • Embedded essential energy calculations to ensure harmonic content is included (up to 233rd harmonics for watt-hour measurement)• Direct and flexible sensor interface without external gain amplifiers• Unparalleled design support including detailed data sheets, reference designs, application notes, evaluation tools, and technical support • Integrated MCU core, and all necessary peripherals, with field proven metering front end • Greater system control with minimized current consumption in battery mode3. Innovation and ChoiceAnalog Devices is committed to continuing its investment in the ADE product family and to enabling very competitive system costs while maintaining a high level of innovation.• 16 patents granted or pending on innovative energy measurement technology• Many energy measurement products currently available for single-phase and polyphase energy meters with more to come4. Quality• Samples from production lots constantly drawn for rigorous qualifications• ADI’s product analysis group continually addresses customer concerns and feedback on the quality of our products • Constant monitoring of electrical ppm failure rate of finished products• Electrical ppm failure rate is largely comprised of marginal parametric rejects that are fully functional but are most likely to experience failure in the field•ADI products have a consistently low ppm failure rate that reflects the stability and high quality of the manufacturing process• TIME DEPENDENT DIELECTRIC BREAKDOWN • ELECTROMIGRATION• HOT CARRIER INJECTION• THERMAL SHOCK SEQUENCE• TEMPERATURE CYCLING SEQUENCE• ELECTRICAL ENDURANCE—HTOL AND LTOL • EARLY LIFE FAILURE CHARACTERIZATION • HIGH TEMPERATURE STORAGE • MOISTURE ENDURANCE TEST • DIE SHEAR TEST• FABRICATION AND ASSEMBLY QUALIFICATION • ELECTRICAL STATIC DISCHARGE (ESD)• LATCH UPPRODUCTION QUALITY CONTROL SUPPLEMENTAL QUALIFICATIONS APPLICATION SPECIFIC QUALIFICATIONEND PRODUCT QUALIFICATIONFABRICATION QUALIFICATIONASSEMBLY QUALIFICATIONANALOG DEVICESSTANDARD QUALIFICATIONS LIST OF QUALIFICATIONSPASSEDPASSEDCUSTOMER FEEDBACK• BOND STRENGTH • BURN-IN SEQUENCE• CONSTANT ACCELERATION • HERMETICITY• HIGH TEMPERATURE STORAGE • INTERNAL WATER VAPOR TEST • LEAD FATIGUE • LID TORQUE• MARKING PERMANENCY • MECHANICAL SHOCK• MOISTURE SENSITIVITY CHARACTERIZATION• MOISTURE ENDURANCE SEQUENCE AND AUTOCLAVE • RESISTANCE TO SOLDERING HEAT • SOLDERABILITY• THERMAL IMPEDANCE• VIBRATION, VARIABLE FREQUENCY • X-RAY INSPECTIONReliabilityAnalog Devices conducted a high temperature operating lifetest (HTOL) to simulate aging of ADE products in the field.Method—ICs subjected to 150°C for 3000 hours:• With acceleration factor of 179×, the life expectancy correlates to 60 years at operating temperature of 60°C.• Four main parameters monitored: reference voltage, gain error, current, and voltage channel offset.Results—parameter distribution over time shows:• Negligible parameter distribution shifts.• Parameters maintain data sheet specifications.• Zero failures.Conclusions from HTOL test:• If other components in electronic meter have the same life expectancy, meter replacement is only needed every 60 years.• Proven stability and accuracy of digital energy measurement.Meter manufacturers must carefully select components to ensure that the overall reliability of electronic energy meter is maximized.10,000125OPERATING TEMPERATURE (°C)A C C E L E R A T I O N F A C T O R10001001010,0001L I F E T I M E (Y e a r s )100010010303540455055606570758085PerformanceThe unsurpassed accuracy of power calculation over a very wide dynamic range, harmonics, and stability over time are the primary reasons why ADE ICs are preferred by many meter manufacturers around the world. The plot to the right highlights the typical performance of ADE ICs over a dynamic range of 1000:1 and temperature range of –40°C to +85°C. Even at a low power factor (PF = 0.5), the ICs maintain their high accuracy.0.4–0.4AMPSE R R O R (%)0.30.20.10–0.1–0.2–0.3Reliability Lifetime PredictionsTypical Performance for ADE ICs"%$"%$"%$&/&3(:.&"463&.&/5%41*/5&3/"- 7 QQN $4*/(-&$:$-& .$66"3541* *$8%53".108&3 4611-:$0/530-108&3 4611-:.0/*503*/(-%0103"%$*/5&3/"-3&4&5"%$5&.1&3"563&4&/403*/5&3/"- 147 ."9$)"3(& 16.1%"$-$% %3*7&3 4&(.&/541--*/5&3/"-$-0$,35$'-"4).&.03:"%& YY "%& YYSelection GuideADE71xx/ADE75xx: Energy Measurement Computing EngineThe ADE71xx/ADE75xx family builds on Analog Devices’ 10 years of experience in energy measurement to provide the best analog-to-digital converters combined with the advanced digital signal processing required to build an accurate, robust, and fully featured energy meter with LCD display.Energy Measurement Key Features:• Exceeds IEC 61036/62053-21,IEC 60687/62053-22, IEC 61268/62053-23, ANSI C12.16, and ANSI C12.20• 4-quadrant power and energy measurement for:• Active, reactive, and apparent• Tampering protection• 2 current inputs for line and neutral • Tampering algorithms integrated • Special energy accumulation modes• Shunt, current transformer, and di/dt current sensor connectivity enabled• 2 high precision pulse outputs for calibration • Power line quality: SAG, period/frequency, peak, zero-crossing• Large phase calibration (5° @ 50 Hz)• Wide measurement frequency bandwidth (14 kHz) for harmonic measurementADE71xx/ADE75xx: LCD DriverThe ADE71xx/ADE75xx family has a unique LCD driver capable of maintainingmaximum contrast on the LCD independently of the power supply level using charge-pump circuitry. This technology combined with the on-chip temperature measurement enables the lowest power operation and maximum readability of the energy meter LCD display.LCD Driver Key Features:• 104-segment LCD driver• Adjustable LCD voltage (5 V max) independent of the power supply (2.7 V min)• LCD freeze and hardware blink functions for low power operation in battery mode • Low offset to minimize LCD fluid biasingRTC Key Features:•1.5 μA current consumption•Low voltage operation: 2.4 V•2 ppm/LSB digital frequency adjustment for calibration and temperature compensation •Alarm and midnight interruptsADE71xx/ADE75xx: Real-Time ClockThe ADE71xx/ADE75xx family provides a low power RTC with nominal and temperature dependent crystal frequency compensation capabilities enabling low drift and high accuracy timekeeping. The RTC functionality is also maintained at low power supply (2.4 V) and over all power supply connections, extending the operating life of the energy meter in battery mode.ADE71xx/ADE75xx: Battery ManagementThe ADE71xx/ADE75xx family has unique battery management features enabling low power consumption in battery mode and optimal power supply management when line voltage is lost.Battery Management Key Features:•No external circuitry for battery switching•Power supply switching based on absolute level•Early warning of power supply collapse with SAG and preregulated power supply monitoring•Internal power supply always valid by hardware controlled switchover to batteryKey Features Maintained in Battery Mode:•Real-time clock for timekeeping•LCD display•Temperature measurement•Meter wake-up events such as RTC alarms, I/O, UART activitiesADE Development ToolsThe ADE71xx and ADE75xx family of products share a common set of tools designedto minimize design time while improving the part understanding. These tools arecomprised of:• Energy meter reference design• 1-pin emulator with isolated USB interface• Isolated USB to UART debugger interface• Downloader software• Evaluation software• Integrated development environment from well-known vendor• Firmware libraries for common and part specific functionsThe energy meter reference design integrates the main functions of an LCD meter withIR port and RS-485 communication, battery backup, two current sensors, antitamperinterface, and EEPROM interface while using the features of the ADE71xx and ADE75xxseries such as battery management, antitamper detection, temperature compensatedreal-time clock, and LCD driver contrast.The reference design is accompanied by code libraries and an example of systemintegration code allowing easy evaluation and further development of solution.Isolated USB communication boards for debugging and emulation provide a safesolution for code development when the meter is connected to the line.The ADE71xx and ADE75xx series can be used with integrated developmentenvironments (IDE) from open market vendors to simulate, compile, debug, anddownload assembly or C code. A free of charge IDE with unlimited assembly codecapability and 4 kB limited C code capability is included in the evaluation kit. Inaddition, the part can be evaluated with a UART interface and a PC by using theversatile evaluation tools and downloader.Single-Phase Energy Metering ICs with Integrated OscillatorThe AD71056, ADE7768, and ADE7769 are single-phase ICs that provide watt-hour information using pulse outputs that directly drive a stepper motor counter.The AD71056, ADE7768, and ADE7769 are pin-reduced versions of the ADE7755, with the enhancement of an on-chip, precisionoscillator circuit that serves as the clock source for the IC. The direct interface to low resistance, low cost shunt resistors also helps to lower the cost of a meter built with AD71056, ADE7768, or ADE7769.These products are pin compatible. The AD71056 and ADE7769 accumulate bidirectional power information, and the ADE7768accumulates power only in the positive direction providing flexibility for various billing schemes. The ADE7769 indicates when the power is below the no-load threshold by holding the calibration frequencypin high. This is useful to indicate a tampering or miswired condition.Single-Phase Energy Metering ICs with Antitamper FeaturesThe ADE7761B detects two common tampering conditions: “fault” condition (when loads are grounded to earth instead of connected to neutral wire or when the meter is bypassed with external wires) and “missing neutral” condition (when the voltage input and return current are missing). The ADE7761B incorporates a novel tampering detection scheme which indicates the fault or missing neutral conditions and allows the meter to continue accurate billing by continuous monitoring of the phase and neutral (return) currents. A fault is indicated when these currents differ by more than 6.25%, and billing continues using the larger of the two currents. The missing neutral condition is detected when no voltage input is present, and billing is continued based on the active current signal. The ADE7761B also includes a power-supply monitoring circuit which ensures that the voltage and current channels are matched,eliminating creep effects in the meter.Polyphase Energy Metering ICs with Pulse OutputThe ADE7752A, ADE7752B, and ADE7762 are polyphase ICs that provide watt-hour information using pulse outputs that can directly drive a stepper motor counter. Compatible with a wide range of 3-phase grid configurations, including 3-wire and 4-wire delta and wye distributions, each of these products can be used for 3-phase commercial and industrial revenue meters or submeters, 3-phase motors or generators, industrial control, and utility automation. The ADE7762 and ADE7752B are optimized for 3-phase, 3-wire applica-tions with no-load threshold and REVP indication based on the sum of the phases.To ensure that energy is billed properly under miswiring or tamper-ing conditions, any of the ICs can be set to accumulate based on the sum of the absolute value in each phase. The active power accumu-lation is signed by default.The ADE7762 has four additional logic output pins. These four pins drive six LEDs for prioritized indication of phase dropout and phasesequence error as well as reverse polarity per phase.ADE7752A and ADE7752B are pin compatible with the legacy ADE7752 and have up to a 50% power consumption reduction from ADE7752. The four additional pins of ADE7762 are located at the top of the package so that the same PCB may be used with an ADE7752A-, ADE7752B-, or ADE7762-based meter.10Single-Phase Energy Metering ICs with Serial InterfaceADI has a range of product offerings for single-phase energy measurement solutions requiring serial interface. The ADE7756 measures active energy and allows digital calibration of phase, offset, and gain through a serial port interface. The ADE7759 has a built-in digital integrator for direct interface with a di/dt sensor such as a Rogowski coil and includes the capability to interface with low resistance shunts and traditional current transformers. The ADE7753 provides active, apparent, and reactive energy measurements, and incorporates a built-in digital integrator to allow direct interface with a Rogowski coil sensor in addition to a low resistance shunt or CT. The ADE7763 provides the same functionality as the ADE7753 but without reactive energy measurement. All four of these ADE single-phase energy metering ICs with SPI are pin compatible for ease of design migration.11Polyphase Energy Metering ICs with Serial InterfaceADI has a selection of product offerings for3-phase energy measurement solutions requiring serial interface. The ADE7758 features second-order sigma-delta ADCs, and is designed formidrange 3-phase energy meters. For each phase, the chip measures active, reactive, and apparent energy, as well as rms voltage and rms current. These measurements are accessed via an SPI that allows a fully automated digital calibration. The ADE7758 interfaces with a variety of sensors, including current transformers and di/dt current sensors, such as Rogowski coils. Additionally, the ADE7758 provides a programmable frequency pulse output for both active and apparent orreactive power.Analog Devices, Inc.Worldwide Headquarters Analog Devices, Inc. One Technology Way P .O. Box 9106Norwood, MA 02062-9106 U.S.A.Tel: 781.329.4700 (800.262.5643, U.S.A. only)Fax: 781.461.3113Analog Devices, Inc. Europe Headquarters Analog Devices, Inc.Wilhelm-Wagenfeld-Str. 6 80807 Munich GermanyTel: 49.89.76903.0 Fax: 49.89.76903.157Analog Devices, Inc. Japan Headquarters Analog Devices, KK New Pier Takeshiba South Tower Building 1-16-1 Kaigan, Minato-ku, Tokyo, 105-6891 JapanTel: 813.5402.8200 Fax: 813.5402.1064Analog Devices, Inc. Southeast Asia Headquarters Analog Devices22/F One Corporate Avenue 222 Hu Bin Road Shanghai, 200021 ChinaTel: 86.21.5150.3000 Fax: 86.21.5150.3222©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.Printed in the U.S.A. BR04915-5-8/07(A)/energymeter。

决胜新高考·名校交流高三年级9月联考卷英语注意事项：1.本试题卷共8页，满分150分，考试时间120分钟。

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1. Where does this conversation take placeA. In a restaurant.B. In a supermarket.C. In a shopping mall.2. What are the speakers doingA. Saving some money.B. Opening a window.C. Setting up an account.3. What does the woman wantA. A stable job.B. The nice hourly wage.C. The pretty flowers.4. What are the speakers talking aboutA. Choosing a university.B. Studying in New York.C. Persuading their moms.5. How much does the cake costA.$2.B.$4.C.$6.第二节(共15小题，每小题分，满分分)听下面5段对话或独白。

加拿大议会演讲稿英文Ladies and gentlemen,。

It is an honor to stand before you today as a representative of the Canadian Parliament. As we gather here, I am reminded of the great responsibility that comes with serving the people of our nation. It is a responsibility that I do not take lightly, and one that I am committed to upholding to the best of my ability.Canada is a country known for its diversity, inclusivity, and commitment to human rights. We are a nation that values the contributions of all its citizens, regardless of their background, and works tirelessly to ensure that everyone has the opportunity to thrive. Our commitment to equality and justice is what sets us apart on the world stage, and it is a legacy that we must continue to uphold.As we look to the future, it is clear that there are many challenges that we must address as a nation. From climate change to economic inequality, we are facing complex and interconnected issues that require thoughtful and decisive action. It is essential that we work together, across party lines and with our international partners, to find solutions that will benefit all Canadians and contribute to a more just and sustainable world.One of the key priorities for our government is addressing the urgent threat of climate change. We have made significant strides in recent years, but there is still much work to be done. We must continue to invest in renewable energy, reduce our carbon emissions, and protect our natural landscapes for future generations. The time for action is now, and we cannot afford to delay any longer.In addition to our environmental commitments, we must also focus on building a strong and inclusive economy. This means creating opportunities for all Canadians to succeed, regardless of their background or circumstances. It means investing in education, healthcare, and infrastructure, and ensuring that no one is left behind as we move forward.Finally, we must continue to champion human rights and democracy both at home and abroad. Canada has a proud tradition of standing up for the rights of all people, andwe must continue to be a voice for those who are marginalized or oppressed. Whether it is advocating for the rights of women and girls, supporting LGBTQ+ communities, or speaking out against authoritarian regimes, we must remain steadfast in our commitment to justice and equality.In closing, I want to reiterate my gratitude for the opportunity to serve the people of Canada. I am confident that by working together, we can overcome the challenges that lie ahead and build a brighter future for all Canadians. Thank you.。

外文资料翻译Overview of adaptable die design for extrusions W.A. Gordon.C.J. Van Tyne.Y.H. MoonABSTRACTThe term ―adaptable die design‖ is used for the methodology in which the tooling shape is determined or modified to produce some optimal propert y in either product or process. The adaptable die design method, used in conjunction with an upper bound model, allows the rapid evaluation of a large number of die shapes and the discovery of the one that produces the desired outcome. In order for the adaptable di e design method to be successful, it is necessary to have a realistic velocity field for the deformation process through extrusion dies of any shape and the velocity field must allow flexibility in material movement to achieve the required material flow description. A variet y of criteria can be used in the adaptable die design method. For example, dies which produce minimal distortion in the product. A double optimization process is used to determine the values for the flexible variables in the velocity fie ld and secondl y to determine the die shape that best meets the given criteria. The method has been extended to the design of dies for non-axisymmetric product shapes.© 2006 Elsevier B.V. All rights reserved.Keywords: Extrusion; Die design; Upper bound approach; Minimum distortion criterion1. IntroductionNew metal alloys and composi tes are being developed to meet demanding applications. Many of these new materials as well as traditional materials have li mited workability. Extrusion is a metalworking process that can be used to deform these diffi cult materials into the shapes ne eded for specific applications.For a successful extrusion proc ess, metalworking engineers and designers need to know how the extrusion die shape can affect the final product. The present work focuses on the design of appropriate extru sion die shapes. A methodology is presented to determine die shapes that meet specific criteria: either shapes which pro-duce product with optimal set of specified properties, such as minimum distortion in the extrudate, or shapes which produce product by an optimized pro cess, such as minimum extrusion pressure. The term ―adaptable die design‖ is used for the method nology in which the die sha pe is determined or modified to produce some optimal proper ty in either product or process. This adaptable die design method, used in conjunction with anupper bound model, allows the r apid evaluation of a large num ber of die shapes and the discove ry of the one that can optimize the desired outcome. There are sever al conditions that need to be met for the adaptable die design method to be viable. First, a generalized but realistic velocit y field is n eeded for use in an upper bound model to mathematically describe the flow of the material during extrusion through dies of any shape. Second, a robust crite-rion needs to be established for the optimiz ation of the die shape. The criterion must be useable within an upper bound model. The full details of the method are presented elsewhere[1–6]. In the present paper, following a review of previous models for extrusion, the flexible velocit y field for the d eformation region in a direct extrusion will be briefl y pr esented. This velocity field is able to characterize the flow through a die of almost any config uration. The adap tableequation, which describes the die shape,is also presented. The constants in this die shape equation are optimized with respect to a criterion. The criterion, which can be used to minimize distortion, i s presented. Finally, the shape of an adaptable die, which produces of an extruded product with minimal distortion, is presented. T he objective of the present paper is to provide a brief overview of the adaptable die design method.2. Background2.1. Axisymmetric extrusionNumerous studies have anal yz ed the axisymmetric extrusion of a cylindrical product from a cylindrical billet. Avitzur[7–10] proposed upper bound models for axisymmetric extru sion through conical dies. Zimerman and Avitzur [11] modeled extrusion using the upper bound method, but with generalized shear boundaries. Finite element methods were used by Chen et al. [12] and Liu and Chung [13] to model axisymmetric extru sion through conical dies. Chen and Ling [14] and Nagpal [15]analyzed other die shapes. They developed velocity fields for axisymmetric extrusion throug h arbitrarily shaped dies. Richmond[16] was the first to propose the concept of a streamlined die shape as a die profile optimized for minimal distortion. Yang et al. [17] as well as Yang and Han [18] developed upper bound models for streamlined dies. Srinivasan et al.[19] proposed a controlled strain rate die as a streamlined shape, which improved the extrusion process for materials with limited workability. Lu and Lo [20] proposed a die shape with an improved strain rate control.2.2. Distortion and die shape analysisNumerous anal ytical and experimental axisymmetric extru sioninvestigations have examined the die shape and resulting distortion. Avitzur [9] showed that distortion increases with increasing reduction and die angle for axisymmetric extrusion through conical dies. Zimerman and Avitzur [11] and Pan et al. [21] proposed further upper bound models, including ones with flexibility in the velocity field to allow the distorted grid to change with friction. They found that increasing friction causes more distortion in the extruded product. Chen et al.[12] con-firmed that distortion increases with increasing reduction, die angle, and friction. Other research work has focused on non-conical die shapes. Nagpal [15] refined th e upper bound approach to study alter-native axisymmetric die shapes. Chen and Ling [14] used the upper bound approach to study the flow through cosine, ellip tic, and hyperbolic dies in an attempt to find a die shape, which minimized force and redundant st rain. Richmond and Devenpeck [16,22,23], instead of assuming a particular type of die shape, decided to design a die based upon some feature of the extruded product. Using slip line analysis and assuming ideal and frictionless conditions, Richmond [16] pro posed a stream-lined sigmoidal die, which has smooth transitions at the die entrance and exit. The streamlined die shape is the basis for many efforts in axisymmetric extrusion die design. Yang et al.[17] , Yang and Han [18] , and Ghulman et al. [24] deve loped upper bound models using streamlined dies. Certain materials, such as metal matrix composites, can be successfull y extruded only in a narrow effective strain rate range, leading to the development of controlled strain rate dies. The control of the st rain rate in the deformation zone came from stud ies that showed fiber breakage during the extrusion of whisker reinforced composites decrease s when peak strain rate was min imized [25] . Initiall y developed by Srinivasan et al. [19] , the streamlined die shape attempts to produce a constant strain rate throughout a large region of the deformation zone. Lu and Lo[20] used a refinedslab method to account for friction and mate rial property changes in the deformation zone. Kim et al. [26]used FEM to design an axisymmetric controlled strain rate die.They used Bezier curves to describe the die shape and minimized the volumetric effective strain rate deviation in the deformation zone.2.3. Three-dimensional non-axisymmetric extrusion analysisBoth the upper bound and finite element techniques have been used to anal yze three-dimensional non-axisymmetric extrusions. Nagpal [27] proposed one of the earliest upper bound analyses for non-axisymmetric extrusion. Upper bound and finite element models were developed Bas ily and Sansome[28] ,Boer et al.[29] , and Boer and Webster [30] . Kiuchi [31] studied non-axisymmetric extrusions through straight converging dies.Gunasekera and Hoshino [32–34] used an upper bound model to study the extrusion of polygonal shapes through converging dies as well as through streamlined dies. Wu and Hsu [35] proposed a flexible velocity field to extrude polygonal shapes through straight converging dies. Han et al. [36] created a velocit y field from their previous axisymmetric upper bound model [37] in order to study extrusion through streamlined dies that produced clover-shaped sections. Yang et al. [37] applied a general upper bound model to study extrusion of elliptic and rectangular sections. Han and Yang [38] modeled the extrusion of trocoidal gears. Yang et al. [39] also used finite element analysis to con-firm the experimental and upper bound anal ysis of the clover sections. Non-axisymmetric three-dimensional extrusions have been studied further by using upper bound elemental technique[40] and spatial elementary rigid zones [41,42] .Streamlined dies have been the proposed die shape for most three-dimensional extrusion. The shape of the die between the entrance and exit has been selected by experience and feel rather than rigorous engin eering principles.Nagpal et al. [43] assumed that the final position of a point that was initially on the billet is determined by ensuring that area reduction of local segments was the same as the overall area reduction. Once the final position of a material point was assumed, a third order polynomial was fit between the die entrance and exit points. Gunasekera et al.[44] refined this metho d to allow for re-entrant geometries. Ponalagusamy et al. [45] proposed using Bezier curves for designing streamlined extrusion dies. Kang and Yang[46] used finite element models to predict the optimal bearing length for an“L‖ shape extrusion. Studies on the design of three-dimensional extrusion dies have been limited.The controlled strain rate con cept has only been applied to axisymmetric extrusions and not to three-dimensional extrusions [19,20,26].3. The adaptable die design methodThe adaptable die design method has been developed and is described in detail in a series of papers [1–5]. The method has been extended to non-axisymmetric three-dimensional extrusion of a round bar to a rectangular shape [6]. The major criterion used in developing the method was to minimize the distortion in the product. The present paper provides a brief overview of the method and results from these previous studies.Fig. 1. Schematic diagram of axis ymme tric e xtrusion using spherical coordinate s yste m thro ugh a die of arbitrar y shape3.1. Velocity fieldAn upper bound analysis of a metal forming problem requires a kin matically admissi ble velocity field. Fig. 1 shows the process parameters in a schematic diagram with a spherical coordinate system (r, θ , φ ) and the three velocity zones that are used in the upper bound anal ysis of axisymmetric extru sion through a die with an arbitrary die shape. The material is assumed to be a perfectly plastic material with flow strength,0σ.he friction, which exists between thedeformation zone in he work piece and the die, is characterized by africtional shear tress, 0mf τσ= mf, can take values from 0 to 1.The material starts as a cylinder of radius Ro and is extruded into a cylindrical product of radius f R . Rigid body flow occurs inzones I and III, with velocities of 0v and f v , respectivel y. Zone II isthe deformation region, where the velocity is fairl y complex. Two spherical surfaces of velocit y discontinuity Γ 1 and Γ 2 separate the three velo cit y zones. The surface Γ 1 is located a distance 0r from the origin and the surface Γ2 is located a distance f r from the origin.The coordinate s ystem is centered at the convergence point of the die. The convergence point is defined by the intersection of the axis of symmetry with a line at angle α that goes through the point where the die begins its deviation from a cylindricalshape and the exit point of the die. Fig. 1 shows the position of the coordinate s ystem origin. The die surface, which is labeled ψ(r) in Fig. 1, is given in the spher ical coordinate system. ψ(r) is the angular position of the die surface as a function of the radial distance from the origin. The die length for the deformation region is given by the parameter L.The best velocity field to describe the flow in the deformation region is the sine-1 velocity field [1,2] . This velocity field uses a base radial velocity, r v , which is modified by an additional term comprised to two functions with each function containingpseudo-independent parameters to determine the radial velocit y component in zone II:r r U v εγ=+ (1) The ε function permits flexibility of flow in the radial, r, direction, and the γ function permits flexib ility of flow in the angular, θ , direction. The value of r v is determined by assuming proportionaldistances in a cylindrical sense from the centreline:2002sin cos sin r r v v r αθψ⎛⎫=- ⎪⎝⎭ (2) This velocit y field was found t o be the best representation of the flow in the deformation region of an extrusion process for an arbitraril y shaped die.The ε f unction is represented as a series of Legendre polynomials that are orthogonal over deformation zone. The representation of ε is:()0an i i i A P x ε==∑ (3)Where ()0002/11/f f R R r x with R R r ρρ--==- i a being the coefficients of the Lengendre polynomials Pi(x)and a n being the order of the representation. There is a restrictionthat:()13a n odd i i A A ==-∑，()02a n even i i A A ==-∑ (4)The remaining higher order coefficients (A2 to A a n ) are the pseudo-independent parameters, with values determined by minimization of the total power. Legendre polynomials are used so that higher order terms can be added to the fun ction without causing significant changes in the coefficients of the lower order polynomials. This feature of the Legendre polynomials occurs because they are orthogonal over a finite distance.The γ function that satisfies the boundary conditions and allows the best description of the flow is:011cos 1cos b in i i B B θγψ=⎛⎫-=+ ⎪-⎝⎭∑ (5) where 011bn i i B B i ==-+∑ and the high order coefficients B1 to B b n are pseudo -independentparameters with values determin ed by minimization of the total power. The order of the representation is b n . It has been shown [3]that a n = 6 and b n = 2 are usuall y sufficient to provide reasonableflexibility for the flow field in the deformation region.3.2. Die shapeThe die shape is described by the functionψ (r). The adaptable die shape is described by a set of Legendre polynomials: ()0cn i i i c p x ψ==∑ (6) where()()0002/11/f f R R r x with r R R ρρ--==-and i c being the coefficients of the Legendre pol ynomials Pi (x). The order of the Legendre polynomial representation is c n . The boundary conditions at the entrance and exit of the deformation region require that:At r = 0r , ψ= αAt r = f r , ψ= α (7)If a streamlined die is used then this function must meet two additional boundary conditions:At r = 0r , 0tan r r ψα∂==-∂ At r = f r , 00tan fR r r R ψα∂==-∂ (8) 3.3. Distortion criteriaThe criterion that was found to minimize the distortion in the extrusion product involves minimizing the volumetric effective strain rate deviation [4,5] . The volumetric effective strain rate deviation in the deformation zone is:Wherewith:(10) andij ε⋅ are the components of the strain rate field.3.4. Determining the adaptable die shapeThe search for the optimal coefficients for the Legendre polynomials representing the die shape is not constrained. A nested optimization routine is used with the velocity field (inside loop) being minimized with respect to the externally supplied power for theprocess, and the die shape (outside loop) being adapted to minimize the distortion criterion. The final shape is called an adaptable die shape, since the shape has adapted to meet the specified criterion.Fig. 2. Streamlined adaptable die shape with no adaptatio n in the rotational directiowith red = 0.60, L/Ro= 1.0,mf= 0.1,Rr/Ro= 0.1 and μ = 1.5. The area reduction ratio is red,Rr is the cornered ra dius of the rectangular product, andμis the height to width ratio o f the rectangular product. (For interpretation of the references to colour in this figure legend, the reader is referred to the web ve rsion of the article.)3.5. Extension to three-dimensional non-axisymmetric shapesIn extending the adaptabl e die design method from axisym metric flow to non-axisymmetric three-dimensional flow in the deformation region requires several special considerations [6]. First, the velocit y field needs to be modified to allow for rotational movement in the deformation region. Second, the bearing region on the exit side of the die needs to be analyzed properly.Third, the functions used to describe the die shape need to have some flexibilit y in the rotational direction (i.e. ψ(r, φ ). This flexibility allows die shape adaptation with respect to the rotational coordinate, φ .4. Die shape to minimize distortionTo illustrate the adaptable die design method a specific three-dimensional example is presented. An extrusion upper bound model was used to determine adaptable die surface shapes,which minimize distortion through minimizin g the volumetric effective strain rate deviation in the deformation zone for the extrusion of a cylindrical billet into a round cornered rectangular product. Two schemes were used. In the first method there was no flexibility allowed in the rotational dire ction, ψ (r), whereas in the second method the die shape was able to adapt in the rotational direction, ψ (r, φ ). In both methods a streamlined con dition was used at the entrance and exit regions of the die. The quarter sections (φ =0 toπ /2) of both die shapes are given in Figs. 2 and 3. Fig. 2is the die shape with no rotational flexibility and in Fig. 3 the die was allowed to adapt its shape in the rota tional direction to reduce distortion. For both of these examples the area reduction was 60% and the rectangular product had a width to height ratio,μ, of 1.5.In Fig. 4, the extrusion die surfac e shape on the two rectangu lar symmetry planes of the product is presented. The adaptable die shape with rotational flexibility is different from the die shape obtained without adaptation in the rotational dire ction especiall y along the φ = π /2 symmetry plane. The adaptable die shape geometry along theφ = π /2 symmetry plane increases the speed of the material in the deformation zone near the exit. Fig. 5shows the resulting distorted grid in the extrudate on the two symmetry planes. The adaptable die shape shows a smaller difference in distortion as compared to the die shape without the rotational flexibility.Fig. 3. Streamlined adaptable die shape with adaptation of the die shape in the rotational directio n with red = 0.60, L/Ro= 1.0,mf= 0.1,Rr/Ro= 0.1 and μ= 1.5.Fig. 4. Streamlined die shape with no adaptation as the rotational d irection compared to streamlined die shape with adaptation as a function of the rotational direction—plotted along rectangular s ymmetr y planes.Fig. 5. Extrudate distorted grid along rectangular symme tr y planes for extrusion through a streamlined die shape with no adaptation as the rotational direction co mpared to a streamlined die shape with adaptation as a function of the rota-tional dire ction—plotted along rectangular s ymmetr y p lanes. Ar is the width of he extr udate and Br is the height of the extrudate.5. SummaryThis paper presented an overview of the ―adaptable die design‖ methodology. The full details of the method are g iven elsewhere[1–6]. In order to use the adaptable die design method in conjunction with an upper bound anal ysis, it is necessary to have a velocity field in the deformation region with sufficient flexibility so that the model can be closer to the real fl ow. The specific criterion of producing a product with minimal distortion involves minimizing the volumetric strain rate deviation. A double optimization process is used (1) to determine the values for the flexible variables in the velocity field and (2) to determine the die shape that best meets the minimum distortion criterion. An example of the method for the design of dies for the extrusion of a cylindrical billet into a round cornered rectangular shape has been presented.AcknowledgementsHelpful discu ssions about this work by Prof. J. Morral of Ohio StateUniversity, along with Prof. L. Shaw and P rof. R. Jeffers of the University of Connecticut, as we ll as the constructive criticis m of Dr. H. Gegel are gratefully acknowledged. The authors are especiall y appreciative of the encouragement and support provided b y Prof. Morral, who allowed the project to be complete d under his auspices a t the University of Connecticut. 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