联想E43L NVD独显 板号 DALE9EMB8D0 REV D LE9E

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AUDIO Amplifier TPA6017A2
RJ45 PAGE 32
25MHz
PCMCIA CONN
IEEE1394 on Daughter/B Memory CardReader
PAGE 29 PAGE 26 PAGE 25 PAGE 26
D
D
PAGE 27
microphone
Audio Jacks
POWER ON TIMING
DNBSWON#
To ICH9m
MEROM Power-up Timing Specifications
S5_ON To ICH9m
B
Td
B
RSMRST# SUSB#,SUSC# SUSON From ICH9m
RESET#
From IT8502 From IT8502 From IT8502
C384 .1U/10V/04
C386 .1U/10V/04
C383 .1U/10V/04
C343 .1U/10V/04
C344 .1U/10V/04
C346 .1U/10V/04 VDDCPU +CK_VDD_MAIN2
16 9 2 61 39 55 12 20 26 45 36 49 48
VDDPLL3 VDD48 VDDPCI VDDREF VDDSRC VDDCPU VDD96I/O VDDPLL3I/O VDDSRCI/O VDDSRCI/O VDDSRCI/O VDDCPU_IO NC X1 X2
03
A
1
1
1
1
1
CLK_MCH_OE# C345 .1U/10V/04 Y3 NEW-CARD_CLK_REQ# PCIE_LANREQ#
R188 R222 R177
2 2 2
1 10K/04 1 10K/04 1 10K/04
2
2
2
2
2
C370 10U/6.3V_8
C388 .1U/10V/04
C355 .1U/10V/04
CK505
CPUCLKT0 CPUCLKC0 CPUCLKT1 CPUCLKC1 CPUT2_ITP/SRCT8 CPUT2_ITP/SRCC8 DOTT_96/SRCT0 DOTC_96/SRCC0
54 53 51 50 47 46 13 14 17 18 21 22 24 25 27 28 38 37 41 40 44 43 30 31 34 35 33 32 1 3 4 5 6
1
2
3
4
5
6
7
8
PCB STACK UP 8L
PAGE 30
LE9E(LE8) BLOCK DIAGRAM
CPU CORE(ISL6266A)
01
14.318MHz
A
LAYER 1 : TOP PAGE 43
LAYER 2 : SGND1
A
CPU Penryn
478P (uPGA)/35W PAGE 4,5
BlueTooth PAGE 33
Finger Printer CONN PAGE 33
SATA - CD-ROM
SATA1 150MB
PCI-E Azalia
X2 Mini PCI-E Card X 2 AUDIO CODEC
(WLAN/ WWAN)
24.576Hz
PAGE 30
C
X1
X1 Express Card
Sheet 1
8
Rev 1A of 44
Tuesday, November 20, 2007
7
1
2
3
4
5
6
5
4
3
2
1
Board Stack up Description
PCB Layers
Layer Layer Layer Layer Layer Layer Layer Layer 1 2 3 4 5 6 7 8
RHCLK_CPU RHCLK_CPU# RHCLK_MCH RHCLK_MCH# CPU_ITP CPU_ITP# R_DOT96 R_DOT96# R_DREFSSCLK R_DREFSSCLK# RSRC_SATA RSRC_SATA#
RP19 4 2 RP23 4 2 RP22 4 2 RP14 2 4 RP13 2 4 RP12 2 4
X1
C
PAGE 19,20,21,22
SYSTEM POWER(ISL6237)
LAN
BROADCOM
BCM 5906M/5784M (10/100/1G LAN)
RICOH R5C847PAGE 4232.7 Nhomakorabea8KHz
(NEW CARD)
LPC MDC CONN PAGE 28
CX20561-12Z
A
+1.05V
Ta=VCC and VCCP asseration to VID[6:0] vaild Tb=VID[6:0] stable to VCC vaild Tc=BCLK stable to PWRGOOD assertion Td=PWRGOOD to RESET# de-assertion time Te=Vcc,boot vaild to PWRGOOD assertion time
5 4 3 2
PROJECT : LE8 Quanta Computer Inc.
Size Document Number Custom Date:
SYSTEM INFORMATION
Sheet
1
Rev 1A 44
Tuesday, November 20, 2007
2
of
1
2
3
4
5
6
7
8
+3V L23 1 2 HI0805R800R-00 +3V +CK_VDD_MAIN
CPU THERMAL SENSOR PAGE 5
CLK_CPU_BCLK,CLK_CPU_BCLK# CLK_MCH_BCLK,CLK_MCH_BCLK# DREFCLK,DREFCLK#
LAYER 3 : IN1 LAYER 4 : IN2 LAYER 5 : VCC LAYER 6 : IN3 LAYER 7 : SGND2 LAYER 8 : BOT
3 4P2R-S-0 1 3 4P2R-S-0 1 3 4P2R-S-0 1 1 *4P2R-S-0@IV 3 1 *4P2R-S-0@IV 3 1 4P2R-S-0 3 1 4P2R-S-0@EV 3 1 4P2R-S-0 3
CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4 CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6 CLK_PCIE_MINI_C 35 CLK_PCIE_MINI_C# 35 DREFCLK 7 DREFCLK# 7 DREFSSCLK 7 DREFSSCLK# 7 CLK_PCIE_SATA 19 CLK_PCIE_SATA# 19 CLK_PCIE_VGA 13 CLK_PCIE_VGA# 13 CLK_PCIE_LAN 31 CLK_PCIE_LAN# 31 PM_STPPCI# 21 PM_STPCPU# 21
TOP GND IN1 IN2 SVCC IN3 GND BOTTOM
Voltage Rails
Voltage Rails
VCC_CORE +1.5V +1.05V 5V_S5/3V_S5 5VSUS/3VSUS/1.5VSUS SMDDR_VTERM/+3V/+5V/+15V/+1.8V +VGACORE/+VGA1.1V LANVCC 3VPCU 5VPCU
C
Tsft_star_vcc Vboot Vid
C
VCC_CORE CPU_UP Vccp Vccp_UP Vccgmch GMCHPWRGD CLK_ENABLE# IMVP6_PWRGD
Tboot Tboot-vid-tr Tcpu_up
Tvccp_up
ACIN
Tgmch_pwrgd ACIN 5VPCU/3VPCU Tcpu_pwrgd NBSWON#
1
1
1
1
1
+3V
B
2
+3V R193 10K/04 PCLK_MINI_LPC 21,31,33 PDAT_SMB R192 2N7002 *4.7K/04 +3V Q11 21 CK_PWG CLK_BSEL1 R215 2.2K FSB
1
27MHz_Nonss/SRCCLK1/SE1 27Mhz_ss/SRCCLC1/SE2 SRCCLKT2/SATACL SRCCLKC2/SATACL SRCCLKT3/CR#_C SRCCLKC3/CR#_D SRCCLKT4 SRCCLKC4
(External MIC)
Head-Phone Jack PAGE 29
FAN PAGE 34
SPI PAGE 36
PAGE 29 PAGE 28
PROJECT : LE8 Quanta Computer Inc.
Size Document Number Custom Date:
BLOCK DIAGRAM
B
2
Q12
R207 10K
R209 10K CGDAT_SMB
CG_XIN CG_XOUT
60 59
1
R_CLK_PCIE_VGA RP17 2 R_CLK_PCIE_VGA# 4 RSRC1_LAN RSRC1_LAN# PM_STPPCI# PM_STPCPU# RSRC_ICH RSRC_ICH# CLK_PCIE_MINI_ CLK_PCIE_MINI_# RSRC_MCH RSRC_MCH# CLK_PCIE_NEW CLK_PCIE_NEW# RP18 4 2 RP21 4 2 RP15 2 4 RP20 2 4 RP16 2 4