逻辑综合synthesis(测试版)

综合复习资料（综合测试版）一、名词解释1、Synthesis:synthesis is the transformation of an idea into a manufacturable device to carry out an intended function.2、SOLD(Synopsys On-Line Documentation): It is a website to provide answers.3、STA(Static Timing Analysis): A method for determining of a circuit meets timing constraints without having to simulate clock cycles.4、Clock skew:To account for varying delays between the clock network branches.5、Jitter:Because some uncertain factors,which leads to the clock happen drift.6、RTL(Register Transfer Level):It is a coding style means describing the register architecture, the circuit topology, and the functionality between registers.7、TCL(Tool Command Language): It is an “open”, industry-standard language, developed at UCA Berkeley.8、PVT: STA scales each cell and net delay based on Process, Voltage, and Temperature variations.9、CTS(Clock Tree Synthesis):Buffer clock timing device in the right place, and avoid the CLOCK to SKEW.10、BDD(Binary Decision Diagram):The binary decision diagram is used to represent the data structure of the Boolean functions.二、填空1、Design objects: Design、Cell、Reference、Port、Pin、Net、Clock2、The advantages of synthesis: reusability、verifiable、portability、prestige、productivity、abstraction、design tricks3、Synthesis is Constraint-Driven, is Path-Based.4、Synthesis=translation + optimization + mapping5、GTECH has nothing to do with technology.三、简答1、Cell-BaBehavioral Level答：1.Behavioral level 2.RTL Level 3.Logic Synthesis 4.Logic Level Design 5.Circuit Level Design yout Level Design 7.Post Verificationsed-Flow2、Logic Synthesis Overview答：1.RTL Design 2.HDLCompiler3.DesignCompiler4.OptimizedGate-level Netlist3、What .synopsys_dc.setup defined答：link_librarytarget_librarysymbol_librarysearch_pathsynthetic_library4、what is .synopsys_dc.setup？答：启动文件（startup files）DC : .synopsys_dc.setupDefined process path to the library and the other for the logic synthesis parameters.定义工艺库的路径和其他用于逻辑综合的参数。

Three distinct files are read and executed when DCis invoked1st. system-wide (do not modify):(e.g. $SYNOPSYS/admin/setup/)2nd. User’s home directory (e.g. ~ccyang/)3rd. User’s current working directory (e.g. ~ccyang/dc/)5、Static Timing Analysis (Design Time)答：A method for determining if a circuit meets timingconstraints without having to simulate clock cycles.1.Designs are broken down into sets of timing paths2．The delay of each path is calculated3.All path delays are checked to see if timing constraintshave been met6、Timing GroupsHow to organize timing paths into group?答：7、Timing Path Exercise答：How many timing paths do you see? 11How many path groups are there? 38、HDL Coding Style for Synthesis答：1.Synthesizable Verilog HDL2.Some tricks in Verilog HDL3.Designware library9、Design Constraints Setting答：1.Setting Design Environment2.Setting Design Constraint10、operating environment答：The operating environment affects the components selected from target library and timing through your design.11、Operating Condition/Input Drive Impedance12、Wire Load Model答：1.Wire load model estimates wire capaon chip area & cell fanout.2.Setting this information during compmodel the design more accurately .13、Sequential Circuit - Specify Clock答：1.Select clock port2.Attributes/Clocks/Specifycreate_clock : define your clock’s waveform &respect the set-up time requirements of all clockedflip-flopsdc_shell>create_clock “clk” -period 50 -waveform {0 25}set_fix_hold : respect the hold time requirementof all clocked flip-flopsdc_shell>set_fix_holdclkset_dont_touch_network : do not re-buffer theclock networkdc_shell>set_dont_touch_networkclk14、group FSM答：To group FSM, use the following dc_shellcommanddc_shell>set_fsm_state_vector {present_State[2],present_State[1], present_State[0]}dc_shell>group -fsm -design_namefsm_name15、What is Setup Time and Hold Time?答：Setup Time: The length of time that data must stabilize before the clock transition. The maximum data path is used to determine if setup constraint is met. Hold Time: The length of time that data must remain stable at the input pin after the active clock transition. The minimum data path is used to determine if hold time is met.16、What is the name of library and what are the functions of library?答：1.Link_library: the library used for interpreting input description.2.Target_library: the ASIC technology that the design is mapped to.3.Symbol_library: used during schematic generation.4.Synthetic_library: designware library to be used.17、Why partition a design?答：Partitioning is driven by many (often competing) needs:1.Separate distinct functions.2.Achieve workable size and complexity.3.Manage project in team environment.4.Design reuse.5.Meet physical constraints.18、How to Partitioning？19、How to constraint ？答：set_max_area 100create_clock–period 10 [get_portsclk]set_dont_touch_network [get_clocksclk]set_input_delay–max 4 –clock clk [get_ports A]set_output_delay–max 5.4 –clock clk [get_port B]20、Timing path答：Design Time breaks designs into sets of signal paths, each path has a startpoint and an endpoint.Startpoints: input ports clock pins of sequential devicesEndpoints: output ports data inputs pins of sequential device21、Set_driving_cell and Set_load答：Set_driving_cell allows the user to specify a realistic external cell driving the input ports.syntax：set_driving_cell–lib_cell and2a0 \ [get_ports IN1]Set_load allows the user to specify the external capacitive load on ports.syntax: set_load 5 [get_ports OUT1]22、Time BudgetingBudget:40% of clock period23、What are virtual clocks?答：Clocks in the environment of the design to be synthesized that:Are defined clock objects within Design Compiler’s memoryDo not clock any sequential devices within the current_designServe as references for input or output delays24、How do I create a virtual clock?答：It is the same as defining a clock, but do not specify a clock pin or port Example: create_clock–name vTEMP_CLK–period 2025、Why to use virtual clocks?Timing Goals for Multiple Clock DesignsMethod is the same as that for single clock designs:1. Define the clock(s), using virtual clocks if necessary2. Specify I/O delays relative to the clock(s)26、Optimization can occur at each of three levels: Architectural、Logic-Level、Gate-Level27、RTL Block Synthesis28、The method to describe a circuit：BDD（二叉决判决图）、HDL（硬件描述语言）、Schematic（电路图）、Netlist（网表）、Boolean expression（布尔表达式）、Gate-level Schematic（门级电路图）、Layout（版图）、Transistor-level schematic（晶体管级电路图）、PCB（PrintedCircuitBoard，印制电路板）29、自己画综合结果答：1.有关阻塞与非阻塞的一个Verilog程序综合2.异步复位与同步复位30、写一段Verilog程序SR锁存器moduleSR_latch(Q,Qbar,Sbar,Rbar); outputQ,Qbar;inputSbar,Rbar;nand n1(Q,Sbar,Qbar);nand n2(Q,Rbar,Q);endmoduleD触发器module DFF（CLK,RST,DFF_DI,DFF_DO); inputCLK，RST，DFF_DI;output DFF_DO;reg DFF_DO;always @ (posedgeCLK or negedge RST) beginif(!RST)DFF_DO<= 0;elseDFF_DO<= DFF_DI;endendmoduleT触发器module TFF( C LK,RST,TFF_DI，TFF_DO);inputCLK,RST,TFF_DI;outputTFF_DO;reg TFF_DO;always @ (posedge CLK or negedge RST)beginif(!RST)TFF_DO <= 0;elseTFF_DO <= TFF_DO_N;endassign TFF_DO_N = (TFF_DI) ? (~TFF_DO) : (TFF_DO); endmodule3-8译码器module DECODE_3_8(CODE, DATA);input [2:0] CODE;output [7:0] DATA;reg [7:0] DATA;always @ (*)begincase(CODE)3'h0 : DATA = 8'b0000_0001;3'h1 : DATA = 8'b0000_0010;3'h2 : DATA = 8'b0000_0100;3'h3 : DATA = 8'b0000_1000;3'h4 : DATA = 8'b0001_0000;3'h5 : DATA = 8'b0010_0000;3'h6 : DATA = 8'b0100_0000;3'h7 : DATA = 8'b1000_0000;default : DATA = 8'bz;endcaseendendmodule加法器module adder(din1,din2，clk，ci，rst_n，dout，co);input din1,din2,inputclk,input ci,inputrst_n,outputregdout,outputreg coalways @ (posedgeclk or negedgerst_n)beginif(!rst_n) {co,dout}<=2'b0;else {co,dout}<=din1+din2+ci;endendmodule由于时间仓促，答案可能存在纰缪之处，如经发现请与作者联系7.3日小开献上。