LPC3250键盘接口模块

第24章LPC3250的I2S音频模块I2S为数字音频接口应用提供了标准的通讯接口。

LPC3250包括2个I2S借口：I2S0和I2S1。

I2S特别定义了一个三线串行总线：一个数据线，一个时钟线，还有一个声音选择信号。

I2S 的连接上有一个主机（并且它一直都是主机）和一个从机。

LPC3250上的I2S接口提供了一个特别的传输和接收通道，每个通道都可以作为主机或者从机来操作。

1.特征[1].I2S输入可以工作在主机和从机模式；[2].I2S输出可以工作在主机和从机模式，但是它与I2S输入没有关系；[3].支持独立的TX和RX时钟，一般时钟是基于TX时钟输入，或者RX时钟输入。

[4].可以处理8，16和32位的声音信号；[5].单声道和立体声音频数据支持；[6].采样频率为16~96KHZ；[7].提供两个8位的声音FIFO数据缓存器，一个用于传输，一个用于接收；[8].当缓存器的电平穿过一个可编程的边界时，会产生一个中断请求；[9].两个DMA请求，由可编程缓存器的电平控制。

它们都连接到通用的DMA模块；[10].对于I2S的输入和输出，控制复位，停止和静音是相互独立的；2.描述I2S通过传输通道将串行数据输出，通过接收通道输入串行数据。

它支持NXP集成电路音频格式，包括8位、16位和32位的音频数据，通用于立体声和单声道模式。

它的配制、数据的访问和控制是由一个APB寄存器操作的。

数据流是由一个带8字节宽度的FIFO缓存的。

I2S接收和传输都是独立操作的主或从模式，对于这两个模式调制的不同在于对语音信号的选择，这个语音信号同时决定数据传输的时间。

一次语音选择改变之后，在下一个传输时钟的下降沿，数据音频就会启动。

在立体声模式，当WS为低时，左边的数据开始传输；当WS为高时，右边的数据开始传输。

在单声道模式，同样的数据会被传输两次，一次是当WS=0，另一次是当WS=1时。

（1）.在主模式（WS-SEL=0），语音信号由系统内部产生，并带有9位计数器。

在单片机应用系统中，存在多种形式的外部数据输入接口界面，例如RS-232C串行通信、键盘输入等[1,4]。

其中利用键盘接口输入数据，是实现现象实时调试、数据调整和控制最常用的方法。

单片机的外围键盘扩展电路有多种实现方式，例如直接利用I/O接口线或外接8255A接口芯片，配合适当的接口管理程序，就可以实现外围键盘扩展功能。

但是，在这些方法中，键盘扩展电路需要占用单片机的资源对按键进行监控和处理，这对要求高实时性处理的单片机系统是不实现的。

为了解决这一问题，可以使用专用键盘接口芯片（例如Intel8279）[2]来组建键盘子系统。

而且，这类专用键盘接口芯片在使用灵活性方面尚有欠缺，尤其当用户需要实现某些特定功能时，其缺点更为明显。

针对上述问题，本文提出一种利用复杂可编程逻辑器件（Complex Programmable Logic Device，CPLD）设计技术[3]实现专用键盘接口芯片的方案。

1 系统原理图1是单片机系统中键盘子系统的构成原理框图。

其中键盘接口芯片KB-CORE是该子系统的核心部分，它应具备如下功能：第一，产生按键扫描时序，并进行硬件去抖动。

如果直按键按下，实现按键编码、中断处理等功能。

第二，可以区分处理数字键和功能键。

数字键钭由接口芯片暂存，而当功能键被按下时申请CPU中断处理；对多个按键同时按下，按一定的编码优先级处理。

第三，提供与MCS-51系列单片机兼容的接口，单片机可以读取芯片中保存的数据或功能代码。

第四，提供数据显示接口，可以直接驱动4位七段LED数码管，并进行动态扫描显示。

按键根据键盘子系统的服务对象拟设置子数字键(0～9)、功能键（ROW、COL、DAT）、清零键（CLR）共14个，排成4×4的矩阵，有两个未定义。

2 专用键盘接口芯片功能结构设计根据上述专用键盘芯片KB-CORE的功能要求，图2示出本芯片内部应有的结构框图。

其工作原理如下：（1）键盘扫描控制及编码电路中内含一个环形计数器。

Lpc3250汇编启动分析在startup.s中首先定义了栈的起始地址C_STACK_BASE EQU 0x81FF0000同时定义了跟中断、用户、任务切换、系统等相关等待任务起始地址和大小。

现在开始启动分析：CODE32AREA vectors,CODE,READONLYENTRY注意这里是代码开始执行的地方，如果用keil编程，自己搭建工程，自己编写汇编的话需要在连接中的Misc controls 中添加--first Startup.o(vectors) 表示从这里开始执行代码，否则就会报错找不到开始执行的地方。

之后就是将pc指针执行复位的地址LDR PC, resetAddr，在下面说说在reseInit中做的事：第一件事关闭看门狗时钟，LDR R0，=TIMCLK_CTRL ;把时钟寄存器加载到R0中MOV R1，#0 ;把要配置的的值加载到r1中STR R1，[R0]；把r1的值赋给r0的地址第二件事，关闭MMU,cache和写缓存，在这里被注释掉了，因为cortex-m3没有协处理器p15;第三件事，就是中断管理（vic管理初始化）；周立功为中断管理重新建立了一个目录vicControl.s;LDR R2，=MIC_ER ;加载中断寄存器地址MOV R3，#3 ;把3载入r3中ORR R3，R3，R3，LSL #30 ；r3 = r3 |(r3<<30) 配置了0,1，30,31STR R3，[R2]；同时使能了中断低优先级和高优先级BIC R3，R3,#3 ;R3 &=~(3) 把r3的低两位清0LDR R2, =MIC_ITR ;加载配置中断类型的寄存器STR R3,[R2] ；这里配置成irq,不配置成fiqMOV R3,#0LDR R2,=MIC_APR ;配置主中断的的产生方式为低电瓶或下降沿STR R3,[R2]LDR R2,=MIC_ATR ；配置成电瓶触发STR R3,[R2]MVN R1,R3 ; R1 = ~R3; r1 = 0xffffffffLDR R2,=MIC_RSRSTR R1,[R2]/*下面是配置sub interrupt*/........./*首先定义一个变量*/AREA vicAddr, DATA,ALIGN = 2 ；4字节对齐的数据段，有就是int型__GulVicEntry SPACE 32*3*4 + 4 ；申请388字节的空间，并初始化/*插入点资料*/AREA语法格式：AREA 段名属性1 ，属性2 ，……AREA 伪指令用于定义一个代码段或数据段。

LPC3250采用ARM926EJ-S内核，运行频率可高达208MHz；支持矢量浮点协处理器；32kB 指令高速缓存和32kB 数据高速缓存;高达256kB 的内部SRAM（IRAM）；可选择从不同的外部设备中启动：NAND Flash、SPI 存储器、USB、UART 或静态存储器；多层 AHB 系统为每个AHB 主机单独提供总线，包括CPU 的指令总线和数据总线、DMA 控制器的两条数据总线和USB 控制器的另一条总线，两条数据总线一条用于LCD、另一条用于以太网MAC。

一般情况下没有仲裁延迟，除非出现2 个主机同时访问同一个从机的情况。

DDR 和SDR SDRAM 以及静态设备的外部存储器控制器；2 个NAND Flash 控制器。

一个支持单级NAND Flash 器件，另一个支持多级NANDFlash 器件；1 个主机中断控制器（MIC）和2 个从机中断控制器（SIC），支持74 个中断源；1 个8 路通用AHB DMA 控制器（GPDMA），可与SD 卡端口、高速UART、I2S端口和SPI 接口一同使用，来实现存储器到存储器之间的传输；串行接口：－带有特定 DMA 控制器的10/100 以太网MAC；－USB 接口支持设备、主机（遵循OHCI）或On-The-Go（OTG），带有相关的DMA 控制器，由特定的PLL 来提供所需的48MHz USB 时钟；－4 个标准UART，带有小数波特率发生器和64 字节FIFO，其中一个标准的UART支持IrDA；－3 个其它的高速UART，在13MHz 的主振荡器作用下可支持高达921,600bps的板内通信；所有高速UART 都提供64 字节FIFO；－2 个SPI 控制器；－2 个SSP 控制器；－2 个独立的主机I2C 接口，具有标准开漏管脚。

I2C 总线接口支持单主机、从机和多主机的I2C 配置；－2 个I2S 接口，每个具有独立的输入（RX）和输出（TX）通道。

文件标识：R&DNXPLPC3250_EK 平台当前版本：v1.00 作 者：林鸿飞 文件状态：[√] 草稿 [ ] 正式发布 [ ] 正在修改完成日期：2009-11-30EMC基本开发文档（BD）日 期：2009-11-30 作 者：林鸿飞版本/状态作者参与者起止日期修改内容v1.00 林鸿飞 2009-09-08/2009-11-30初始版本目录第1章 LPC32x0 外部存储器控制器 (EMC)1.1 介绍LPC32x0 外部存储器控制器是一个 ARM PrimeCell 多端口存储器控制器外设，用于异步静态存储器外设如：RAM、ROM 和 flash，以及动态粗存储器如单数据速率（SDR）和双数据速率（DDR）SDRAM。

EMC是一种遵循先进微控制器总线结构（AMBA）的外设。

1.2 EMC 的特性z动态存储器接口支持包括单一数据传输率和双数据传输率的 SDRAM；z支持 1.8 V I/O 接口的移动 SDRAM 设备；z异步静态存储器设备支持包括 RAM、ROM 和 Flash，可选用或者不选用异步页模式；z低传输等待时间（transaction latency）；z带有读写缓冲区以减少延迟提高性能；z支持8位，16位和32位宽度的静态存储器；z支持 16位，32位宽度片选型 SDRAM 存储器；z静态存储器的特点包括：支持异步页模式读取；可编程的等待状态；总线循环延迟（turnaround delay）；输出使能和写使能延迟；扩展的等待时间。

z多重省电模式，可动态控制到 SDRAM 的 CKE 和 CLKOUT 信号；z控制器可支持 2K、4K 和 8K 行地址同步存储器设备，也就是典型的 512 Mbit、256 Mbit 以及和 128 Mbit 设备，每个设备的数据可以为4、8、16 或 32 位；z如果需要，独立的复位域允许通过芯片复位进行自动刷新；z带有 4 个静态存储器设备选择信号；z带有 2 个同步存储器设备选择信号。

ClareOne 16 Zone Wired Input Module Installation SheetLast modified: 09/30/20Part number: CLR-C1-WD16DescriptionThe ClareOne 16 Zone Wired Input Module allows the takeover of hardwired security zones making them compatible with the ClareOne panel. The input module has 16 wired zone inputs each with LED status, a tamper switch input, a back-up battery charging terminal, and 2 auxiliary power outputs for poweredsensors,********************************** module supports powered and unpowered sensors, including contact zones (open/close), motion sensors, and glass break detectors. Input zones 1 and 2 have an optional 2-minute communication time delay which can be enabled to prevent repeated signals from motion sensors being sent to the panel. Once all sensors are wired to the module, the modules and each zone can be paired to the ClareOne panel. Follow the steps in this installation sheet for module and sensor connection to the panel.Notes•This wireless module works with most wired sensors that do not require a smoke loop.•Sensors/zones must be in their normally closed state when added to the module. Important safety instructions•Before you install this module, be sure to read, keep, and follow all instructions.•When using a supervised back up battery, if the battery is low, replace it with a compatible lead-acidrechargeable battery.InstallationUse the included screws for installation. The included antennas should be used regardless of location, for optimal RF communication.Note: If the module is being installed in a metal container or equipment rack, the antennas must extend outside the container to ensure that the RF communication is not interrupted.To install the module:1. Carefully select the mounting location, verifying that themodule is vertical, and secure it in position using theprovided screws.Note: The module should be within 1000 ft (304.8 m) ofthe panel, however walls and other construction materials may lessen that distance.2. Attach each of the antennas to the module, one in each ofthe ANT terminals on the top of the module.Note: The antennas should be clear of obstructions and if in a metal enclosure, should extend outside of it.3. Wire the sensors/leads to the desired terminals markedZone 1 through 16.Wiring notes:•The module requires 4.7kΩ of end of line (EOL) resistance on each zone. Some existing installationsmay already have EOL resistors installed; it isimportant to determine if this is the case and makeappropriate adjustments as needed. How the EOLresistor is installed depends on if the sensor isnormally open (N/O) or normally closed (N/C). Referto Determining EOL resistance and sensor type for© 30SEP20 Clare Controls, LLC. 1 / 6 DOC ID – 1987 • Rev 02details on determining EOL resistance and if a sensoris N/O or N/C.•Install one of the included 4.7k Ω resistors on each zone that has a sensor attached. Install the resistor inparallel for N/O and in series with N/C sensors.•For any powered sensors, such as motion sensors and glass break sensors, wire the Positive andNegative leads from the sensor to the “AUX” (+) and“GND” (-) terminals for device power. See Figure 1:Wiring diagram on page 3.4. Wire the tamper switch input.Notes•If using a tamper switch, wire it directly to the tamper terminals without the need for an EOL resistor.•If not using a tamper switch, simply connect a short piece of wire across the tamper input.5. (Recommended) For any security system that issupervised, a battery should be connected to the CLR-C1-WD16. To provide an independent battery back up to the module, connect the included battery leads to a 12V, 5Ah lead acid rechargeable battery (battery not included). This battery type is common with most traditional hardwiredsecurity panels, otherwise it is recommended that youconnect the module to an auxiliary 16-volt power supplywith its own battery backup. Connect the power supplyleads from the provided power supply to the terminalslabeled +16.0V and GND on the wired input module.Note: The dashed wire is positive.6. Plug the power supply into a 120VAC outlet.Note: Do not plug the module into a receptacle controlled by a switch.ProgrammingThe following instructions step through pairing the module to the ClareOne panel.To add the module to the panel:1. Once the module is plugged in, open the front cover.2. Put the ClareOne panel into sensor pairing mode, andthen select "Wired Input Module" as the device type. For detailed programming instructions, refer to the ClareOneWireless Security and Smart Home Panel User Manual(DOC ID 1871).3. After setting the ClareOne panel to “Add mode”, press andhold the Pair button on the module for two seconds. Allzone LEDs flash and then extinguish. The Pairing LEDilluminates, i ndicating that the module is in “Pair Mode”. 4. Trip the tamper input, either by opening the tamper switchor removing the wire across the inputs. Once complete,close the tamper switch or replace the wire across theinputs.5. Follow the ClareOne panel on-screen prompts to completethe process.Note: If you are not adding a battery backup(recommended), disable the low battery notifications bysetting “Low Battery Detection" to Off under the WiredInput Module's sensor settings.To pair the zones to the module:Note: Each zone must be paired individually, one at a time. 1. Verify that the module’s Pairing LED is still illuminated.Note: If the LED is no longer illuminated, press and holdthe Pair button for two seconds.2. Put the ClareOne panel into sensor Pairing mode.3. Trip the desired hardwired zone.Note: Once a zone is tripped, its module LED illuminates and remains lit until the module exits Pairing mode.4. Follow the ClareOne panel on-screen prompts to completethe process.Note: If using a motion sensor, it is recommended toconnect them to Zone 1 or 2, and then enable thecommunication delay for that zone. To enable/disable this feature, see Buttons and LEDs – Memory Reset, on page2. If using more than 2 hardwired motions, allocate themost active areas on these zones. If using motions in anoccupancy detection mode for automation, disable thissetting.5. Repeat steps 1-4 for each zone.6. Once all zones are paired, press the Pair button.The Pairing LED extinguishes.Buttons and LEDsThe following section details the buttons and LEDs found on the module.ButtonsPair: The Pair button, when pressed, puts the module in/out of “Pair Mode”.Memory Reset: The Memory Reset button clears the module’s memory and returns it to the factory default settings. The Memory Reset button is also used to enable/disable the communication timer delay for Zones 1 and 2.To clear the memory:1. Remove power from the module.2. Press and hold the Memory Reset button.3. Reapply power while continuing to hold the Memory Resetbutton.4. After 3 seconds, release the Memory Reset button.The Processor, RF XMIT, and Pairing LEDs flash,indicating the module is reset.To enable communication timer delay on zones 1 or 2: 1. Pair a sensor to zone 1 or 2.2 / 6 DOC ID – 1987 • R ev 02Note: Complete the next step before adding anothersensor.2. Press the Memory Rese t button.The zone’s yellow LED illuminates, signifying that the2-minute communication timer delay is enabled for thatzone.To disable communication timer delay on zones 1 or 2:1. Enter Pairing Mode.2. Trip the sensor on zone 1 or 2, and then immediatelypress the Memory Reset button.The zone’s yellow DLY LED extinguishes signifying thatthe lockout delay is disabled for the zone.LEDsPairing: The Pairing LED illuminates when the module is in “Pair Mode” and is off when the module is in “Normal Operation Mode”. If there are no zones learned the Pairing LED flashes.Processor LED: This LED flashes when the module is in “Normal Operation Mode”.RF XMIT LED: The RF XMIT LED illuminates when RF transmission is sent.Zone LEDs: During "Normal Operation Mode" each LED remains off until its representative zone is opened, then the LED illuminates. At the beginning of "Pair Mode" all Zone LEDs flash briefly, after which each Zone LED remains off until the zone is learned in and then it turns on and remains on until "Pair Mode" is complete.DLY LEDs: Zones 1 and 2 each have a DLY LED. When a zone’s DLY LED is illuminated yellow, that zone has the2-minute communication timer delay enabled. When the DLY LED is off, that zone’s communication timer delay is disabled. When the DLY LED is flashing, the associated zone is tripped, and the 2-minute communication timer delay is in effect. All additional triggers from that sensor are ignored for 2 minutes. Testing the moduleVerify that the module and zones are working correctly.To test the module/zones:1. Set the panel to the sensor test mode.2. Trip each zone on the module one at a time. Monitor thesystem after tripping the zones.Refer to the ClareOne Wireless Security and Smart Home Panel User Manual (DOC ID 1871) for specific testinformation. Determining EOL resistance andsensor typeIn some instances, it is not visually apparent what is physically connected to a zone in terms of any pre-existing EOL resistors and whether the sensor is N/O or N/C. Use a multimeter to learn this information.With a sensor in its active state (i.e. door/window contact is separated from its magnet), take a multimeter set to measure resistance and connect the multimeter across the zone wires. If the multimeter reads a value of 10kΩ or less, the sensor isN/O, if the multimeter reads an open or extremely high resistance (1Ω or higher) than the sensor is N/C. The table below provides guidance for using the measurements to determine the EOL resistance value, as well as the line resistance for N/O sensors. This is the case regardless of the number of sensors connected to a single zone, so long as all sensors on the same zone are in series or in parallel with one another.Note: The module will not work if there is a combination of series and parallel sensors connected to the same input zone.Multimeter reads forN/OMultimeter reads forN/CSensors active(sensor away fromthe magnet)Value for EOL resistor OpenSensors inactive(Sensors connectedto the magnet)Value of line resistance(10Ω or less)Value of EOL resistorplus line resistanceEOL resistance on existing installations typically ranges from1kΩ - 10kΩ while line resistance should be 10Ω or less. However, there may be some installations that do not have any EOL resistors installed and the measured EOL resistance may be the same as the line resistance. If there is no EOL resistor installed than simply installing the provided 4.7kΩ resistor is all that is needed. Ideally, any existing EOL resistors would be removed and replaced with a 4.7kΩ resistor. If that is not an option, additional resistors must be appropriately added, to get the EOL resistance to 4.7kΩ. For more information, refer to the ClareOne 16 Zone Wired Input Manual (DOC ID 1992).DOC ID - 1987 • R ev 02 3 / 6WiringThe graphic below details the module wiring. Figure 1: Wiring diagram(1) 12 VDC Backup battery connection(1.a) Negative wire (-)(1.b) Positive wire (+)(2) 16 VDC Power supply connection(2.a) Positive wire (+)(2.b) Negative wire (-)(3) 12VDC Auxiliary Power Output 1(3.a) Positive wire (+)(3.b) Negative wire (-) (4) 12VDC Auxiliary Power Output 2(4.a) Positive wire (+)(4.b) Negative wire (-)(5) Tamper input(6) Wired zone N/O loop(7) Wired zone N/C loopNote: When wiring a sensor that also has a tamper output, the alarm output and tamper output should be wired in series so that the zone will trigger on either a motion or tamper event.4 / 6 DOC ID – 1987 • R ev 02SpecificationsCompatible panel ClareOne (CLR-C1-PNL1)Input voltage 16 VDC Plug-in transformer Auxiliary voltage output 12 VDC @ 500 mAEOL supervision 4.7K (resistors included)Battery backup 12 VDC 5Ah (optional)Input zones 16Zone type N/O or N/C compatibleTamper zone Use external switch or wire to short Dimensions 5.5 × 3.5 in. (139.7 × 88.9 mm) Operating environmentTemperature Relative humidity 32 to 122°F (0 to 50°C) 95%Regulatory informationManufacturer Clare Controls, Llc.7519 Pennsylvania Ave, Suite 104Sarasota, FL 34243North American standards FCC: 15.109 Class B 15.231, Industry Canada: ICES-003, RSS-210FCC compliance FCC / IC StatementThis equipment has been tested and found tocomply with the limits for a Class B digital device,pursuant to Part 15 of the FCC Rules. Theselimits are designed to provide reasonableprotection against harmful interference in aresidential installation.Per FCC 15.19 (a) (3) and (a) (4), This devicecomplies with part 15 of the FCC Rules.Operation is subject to the following conditions:(1) this device may not cause harmfulinterference, and (2) this device must accept anyinterference received, including interference thatmay cause undesirable operation.Per FCC 15.21, The user manual or instructionmanual for an intentional or unintentional radiatorshall caution the user that changes ormodifications not expressly approved by the partyresponsible for compliance could void the user'sauthority to operate the equipment. Thisequipment generates, uses and can radiate radiofrequency energy and, if not installed and used inaccordance with the instructions, may causeharmful interference to radio communications.However, there is no guarantee that interferencewill not occur in a particular installation.If this equipment does cause harmful interferenceto radio or television reception, which can bedetermined by turning the equipment off and on,the user is encouraged to try to correct theinterference by one or more of the followingmeasures:•Reorient or relocate the receiving antenna. •Increase the separation between the equipment and receiver.•Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.•Consult the dealer or an experienced radio/TV technicianfor help. This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.Cet appareil est conforme avec Industrie Canada exempts de licence standard RSS (s). Son fonctionnement est soumis aux deux conditions suivantes: (1) cet appareil ne doit pas provoquer d'interférences et (2) cet appareil doit accepter toute interférence, y compris celles pouvant causer un mauvais fonctionnement de l'appareil. In accordance with FCC requirements of human exposure to radio frequency fields, the radiating element shall be installed such that a minimum separation distance of 20 cm is maintained from the general population.FCCID: 2ABBZ-RF-CHW16-433IC: 11817A-CHW16433This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. This Class B digital apparatus complies with Canadian ICES-3B. Cet appareil numérique de la classe B est conforme à la norme NMB-003 du Canada. MANUFACTURER HEREBY DISCLAIMS ALL WARRANTIES AND REPRESENTATIONS, WHETHER EXPRESS, IMPLIED, STATUTORY OR OTHERWISE INCLUDING (BUT NOT LIMITED TO) ANY WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THESE PRODUCTS AND ANY RELATED SOFTWARE. MANUFACTURER FURTHER DISCLAIMS ANY OTHER IMPLIED WARRANTY UNDER THE UNIFORM COMPUTER INFORMATION TRANSACTIONS ACT OR SIMILAR LAW AS ENACTED BY ANY STATE. (USA only) SOME STATES DO NOT ALLOW THE EXCLUSION OF IMPLIED WARRANTIES, SO THE ABOVE EXCLUSION MAY NOT APPLY TO YOU. THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSO HAVE OTHER LEGAL RIGHTS THAT VARY FROM STATE TO STATE.DOC ID - 1987 • R ev 02 5 / 6MANUFACTURER MAKES NO REPRESENTATION, WARRANTY, COVENANT OR PROMISE THAT ITS ALARM PRODUCTS AND/OR RELATED SOFTWARE (I) WILL NOT BE HACKED, COMPROMISED AND/OR CIRCUMVENTED; (II) WILL PREVENT, OR PROVIDE ADEQUATE WARNING OR PROTECTION FROM, BREAK-INS, BURGLARY, ROBBERY, FIRE; OR (III) WILL WORK PROPERLY IN ALL ENVIRONMENTS AND APPLICATIONS.Environmental class UL: Indoor dry IEC: 3K5EU complianceEN 54 EN 54-00:0000European Union directives 1999/5/EC (R&TTE directive): Hereby, Clare Controls declares that this device is in compliance with the essential requirements andlocal supplier upon the purchase of equivalentnew equipment, or dispose of it at designatedcollection points. For more information see:.battery information. The battery is marked withthis symbol, which may include lettering toindicate cadmium (Cd), lead (Pb), or mercury(Hg). For proper recycling, return the battery toyour supplier or to a designated collection point.For more information see: .Warranty informationClare Controls offers a two (2) year limited warranty on originalClare Controls components, from the date of shipment fromClare Controls.Contact informationClare Controls, LLC.7519 Pennsylvania Ave, Suite 104Sarasota, FL 34243General: 941.328.3991Fax: 941.870.9646Integrator/Dealer Support: 941.404.1072******************************Homeowner Support (ClareCare): 941.315.2273 (CARE)**********************6 / 6 DOC ID – 1987 • R ev 02。

88DC Input specificationTransistor specificationWiring(XBE-DN32A)XBE-DN32ADC 6V or less / 1mA or less About 5.6AC 560Vrms / 3 Cycle (altitude 2000m)10or more by Megohmmeter 16 point / COM 0.360(When all inputs and outputs are on)Input On, LED On 1/3/5/10/20/70/100(set by CPU parameter) Default:3TVS Diode 1or less 1or less (Rated load, resistive load)32 point / COM 0.360mA (when all point On)DC12/24V 10% (ripple voltage 4 Vp-p or less)89SpecificationNames and FunctionsXBF-AD04AXBF-AD04CWiring 0~100001/16000(0~5V)-10000~10000(10V)APPLICSTION90SpecificationNames and Functions WiringXBF-DV04AXBF-DV04CXBF-DC04C911.25mV (DC 1~5V, 0~5V),2.5mV (DC 0~10V)5(DC 4~20mA, 0~20mA)SpecificationNames and FunctionsWiring XBF-AH04AAPPLICSTION92SpecificationWiring XBF-RD04ANames and Functions93SpecificationNames and Functions Wiring XBF-TC04SAPPLICSTION94-200.0 ~ 1300.00.0 ~ 500.0-200.0 ~ 1200.00.0 ~ 500.0-200.0 ~ 800100ppm/(0.01%/)Automatic compensation by RJC sensing2.0500ms/ 4 loopPID CONTROL, ON/OFF CONTROL20 minutes or above0.5 /min (30 /hour) or less16 point terminal (10 point terminal 1ea, 6 point terminal 1ea)Fixed: 64 points0.2% or less (25 , normal temperature,except -200~-100 for the T type)Insulation resistor: 500V DC, 10 M or aboveSpecificationXBF-TC04TT95-200.0 ~ 850.0 -200.0 ~ 600.0 0.2% or less (25 , normal temperature)100ppm/ (0.01%/ )500ms/ 4 loop PID CONTROL, ON/OFF CONTROL SpecificationXBF-TC04RT Insulation resistor: 500V DC, 10 M or aboveAPPLICSTION962 Channel (Insulation between Channels)5VDC 5%, (8 per 350load cell channel)Four-wire or Six-wire1/400000.0~6.00.125(when the rated output of the load cell is 0.0 ~ 1.0/ V)5V, DC 24Internal DC5V : 110External DC24V : 2805SpecificationXBF-LD02S0.01% or below (nonlinear accuracy, 25)Zero Drift: 0.25Gain Drift: 15ppm//DC500 V,10 M orabove Insulation Insulation Voltage Resistance(Internal Test Specifications)97APPLICSTIONSpecificationNames and Functions XBF-PD02ATerminal98Switching controlSpecificationXBF-PN08B-214748364.8~214748364.7()-21474.83648~21474.83647-214748364.8~214748364.7()-21474.83648~21474.83647-214748364.8~214748364.7()-21474.83648~21474.8364799APPLICSTIONNames and FunctionsTerminal100SpecificationXBF-HO02AXBF-HD02ANames and Functions101APPLICSTIONTerminal (XBF-HO02A)A+A-A+A-B+B-B+B-P 24VP 12VA phase differentiation input +A phase differentiation input -A phase differentiation input +A phase differentiation input -B phase differentiation input +B phase differentiation input -B phase differentiation input +B phase differentiation input -Terminal (XBF-HD02A)102Ethernet (XBL-EMTA)RAPIEnet (XBL-EIMT)XBL-C21AXBL-C41ARS-232C, RS-422 / 485103APPLICSTIONEthernet/IP (XBL-EIPT)Main unit scan 2 + Data receive time + Communication module scan XG5000 (setting station and high-speed link parameter block)Profibus-DP Module (XBL-PMEC, XBL-PSEA)104Thin Cable Terminal resistance ()125 kbps 250 kbpsCSMA/NBA Poll type Up to 64 (including master) MAC IDs (MAC Identifier)Insertion and removal of nod available in voltage On status Terminal resistance ()Master/Slave operation Data Processing unit XG5000 : High Speed Link Monitoring 110(5%), 1/2W Only available as Master Byte Rnet (XBL-RMEA)DeviceNet Module (XBL-DSEA)Trunk/drop line Power/Signal cable inside the identical network cable105APPLICSTIONCANopen Module (XBL-CMEA, XBL-CSEA)106Smart linkConnection cable Terminal board Option modules107APPLICSTION Program editing & Engineering software Windows-based easy operation Multi-PLC, Multi-programming support Various monitoring and diagnosis functions Convenient network settingExtended monitoring function for network system and communication modules Fast interface with CPU by effective network managementVarious built-in diagnosis, functions(CPU condition, Link conditon, Service condition, Frame monitoring)Trend monitor Special module monitor Ladder monitor Forced I/O Variable monitor Parameter setting Service conditionmonitoringNetwork scan Frame monitoring XGT PanelLink monitoringFast ethernetSmart I/O Other PLCOther netdevicsLS Inverter XG5000(Programming software)XG-PD (Network setting software)108Main SpecificationAluminum body frame, responsive touch screen.Easy-to-use Multi-touch, gesture, dual screen, portrait mode. Multi connected with 1Gbits 2ch. Ethernet between PC to PLC.Various interfaces : USB host /device, SD card, HDMI. High resolution : 1024 X 768IP66, UL type 4x, NEMA 4x standardsDate/Hour data, Logging/Alarm/Recipe data and nonvolatile device Approx. 3 years (Operating ambient temperature of 2577)109APPLICSTIONMain Specification1GHz 32bit RISC Embedded CPU 16,777,216 TFT color LCD128MB display data and1MB back-up memory Ethernet 1ch, RS-232C 2ch, RS-422/485 1ch USB host 3ch and device 1chSD memory card interfaceMain FunctionsPLC ladder monitoring (XGK/XBC PLC only)Web Server/Data Server Path through XP-Remote :Remote controlling and monitoringDate/Hour data, Logging/Alarm/Recipe data and nonvolatile device Approx. 3 years (Operating ambient temperature of 25)and USB memory driver is available)110Main SpecificationTFT LCD-applied wide typeLED Backlight adopted for enhanced contrast ratio and low-powerPLC Ladder monitoring function: Only XGK/XBC supports*Web Server* / Data Server* / Path-Through Function*Remote Viewer Function*Screen editor : XP-BuilderFunctions that support only the TTA modelDate/Hour data, Logging/Alarm/Recipe data and nonvolatile deviceApprox. 3 years (Operating ambient temperature of 50)Time error Approx. 3 sec/1day(Operating ambient temperature of 25)1 channel, USB 2.0 Host (mouse, keyboard, printer and USB memory driver is available)4.6W7.2W 6.5W10W12810232165.0132.536.1165.0132.536.1156.0123.5208.0154.044.4192.0138.0276.0218.044.4260.0202.01 channel, IEEE802.1a, 10Base-T/100Base-TX111APPLICSTIONGraphic type XP30/XP40/XP50/XP70/XP80/XP90High and vivid distinction with 65,536 colors High quality raster and vector symbolsVarious BMP JPG GIF graphic file support: BMP, JPG, GIF, WMF, etc Simple animation effects: animated GIF 10/100BASE-T Ethernet interface Convenient and easy screen editingStrengthened data management: Logging, Recipe, and Alarm Read function of a controller’s state information: Monitoring and maintenanceMulti-lingual display: up to 8 languagesOffline and concurrent simulation with XG5000 Easy to change the address of the graphic objects: Tag function with XGT PanelUSB host for peripheral devices: USB Drive, Mouse, keyboard, printer, etcSufficient memory for screen data: 10MB112Text type XP10Screen: 192 64 Graphic STN LCDSystem RAM: 1000 wordsFlash memory: Program/Parameter back upCommunication: Half-duplex comm.- Baud rate: 1200~115200 bps - Master/slave setting available- RS-232C/RS-485 2 CH separate to usePower reguirements - 24 V input or 5 V direct input by LS PLC Various function key - ESC, ALM, SET, ENT, F1~F4, Arrow keys Panel Editor - Easy programming and H/W settingKey to control PLC device and screen ESC key Alarm historyData input and Screen change PLC data setting Enter keyDC24V input terminalRS-232C port to download a project Brightness adjustment RS-422 port115,200bps12 Keys (F1~F4, ESC, ALM, ,113APPLICSTIONProduct list114Product list。

LPC3250与S3C2440A性能及功能参数对比1．性能/功能参数对比表续上表2．芯片的用户手册下载地址LPC3250用户手册下载地址：/support/documents/microcontrollers/pdf/user.manual.lpc3220.01.lpc3230.01.lpc3240.01.lpc3250.01.pdfS3C2440A用户手册下载地址：/global/business/semiconductor/productInfo.do?fmly_id=229&part num=S3C2440&xFmly_id=2293．结合WinCE系统分析LPC3250的优势优势（一）——AHB矩阵总线结构由于LPC3250内部采用了先进的矩阵总线结构，使得LPC3250即使主频比S3C2440A 低了近200MHZ，但是整体的性能差距却不大。

优势（二）——LCD分辨率LPC3250支持1024*768的分辨率，而对系统性能几乎不会产生影响；而S3C2440A数据手册中支持最高640*480的分辨率，实际应用最高也只能到800*480。

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USB-DIO-32 - Buffered Digital I/O, Three Counter/Timers FEATURES•High-speed USB 2.0 device, USB 1.1 compatible•Small, portable 32-channel digital I/O module•Four 8-bit ports independently selectable for inputs or outputs•All 32 I/O lines buffered with Sink 64mA / Source 32mA current capabilities•Removable screw terminal adaptor for easy wiring•Standard 50-pin IDC connector with key•Custom high-speed function driver•PC/104 module size and mounting compatibility•Small (4" x 4" x 1.25") rugged industrial enclosureFACTORY OPTIONS•Three 82C54 counter/timers•External power for high current capabilities•DIN rail mounting provision•Economy "E" version also available without the screw terminal board•OEM (board only) version with PC/104 mounting holes and PCB footprint foradded flexibility in embedded applicationsFUNCTIONAL DESCRIPTIONThe USB-DIO-32 is an ideal solution for adding portable, easy-to-install digital I/O and counter capabilities to any computer with a USB port. The USB-DIO-32 is a USB 2.0 high-speed device, offering the highest speed available with the USB bus. It is fully compatible with both USB 1.1 and USB 2.0 ports. The unit is plug-and-play allowing quick connect or disconnect whenever you need additional I/O on your USB port.The USB-DIO-32 features 32 bits of TTL-compatible digital I/O with high-current capabilities and three optional 82C54 counters. Each digital port can be pro-grammed to accept inputs or to drive outputs on four 8-bit ports, designated as port A, B, C, and D. Power is supplied to the board via the USB cable or for higher current capabilities, external power may be used. The I/O wiring connections for USB-DIO-32 are via an industry standard 50-pin connector. For exter-nal circuits, fused +5VDC power is available at the connector. This resettable fuse is rated at 0.5A.All I/O lines are buffered by a type 74ABT245 tri-state buffer transceiver capable of sinking 64 mA or sourcing 32 mA. The buffers are configured under pro-gram control for input or output. Jumper selectable pull-ups (to +5 VDC) or pull-downs (to ground) on the board allow for contact monitoring and assure that there are no erroneous outputs at power-up until the board is initialized by system software.The USB-DIO-32 is designed to be used in rugged industrial environments but is small enough to fit nicely onto any desk or testing station. The board isPC/104 sized (3.550 by 3.775 inches) and ships inside a steel powder-coated enclosure with an anti-skid bottom.COUNTER/TIMERSThree 82C54 chips each include three 16-bit counter/timers factory configured in an optimal module for use as event counters, frequency output, pulse width, and frequency measurement (see the Block Diagram).OEM USB/104 FORM FACTORThe OEM (board only) version is perfect for a variety of embedded applications. What makes the OEM option unique is that its PCB size and mounting holes match the PC/104 form factor (without the bus connections). This allows our rugged digital board to be added to any PCI-104 or PC/104 stack by connecting it to a simple USB port usually included on-board with embedded CPU form factors such as EBX, EPIC, and PC/104. This is especially important since many newer CPU chipsets do not support ISA and have plenty of USB ports. The USB-DIO-32 OEM board can also be installed using standoffs inside other enclo-sures or systems.ACCESSORIESThe USB-DIO-32 is available with optional cable assemblies and screw terminal board. The pin connections are also compatible with industry standard I/O racks such as ACCES A24A, OPTO22, Gordos, Potter & Brumfield, etc. with optional cable.SOFTWAREThe USB-DIO-32 is plug-and-play which allows quick connect or disconnect whenever you need additional I/O on your USB port. The module utilizes a high-speed custom function driver optimized for a maximum data throughput that is 50-100 times faster than the USB human interface device (HID) driver used by many competing products. This approach maximizes the full functionality of the hardware along with capitalizing the advantage of high-speed USB 2.0. The USB-DIO-32 is supported for use in most USB supported operating systems and includes a free Linux and Windows 98se/Me/2000/XP/2003 compatible soft-ware package. This package contains sample programs and source code in Visual Basic, Delphi, C++ Builder, and Visual C++ for Windows. Also incorporated is a graphical setup program in Windows. Third party support includes a Windows standard DLL interface usable from the most popular application programs. Embedded OS support include Windows XPe.BLOCK DIAGRAM CONNECTOR PIN ASSIGNMENTSUSB-DIO-32 has a 50-pin connector . provided for I/O connectionsSpecificationsDigital Inputs (TTL Compatible)Logic High: 2.0 to 5.0 VDCLogic Low: -0.5 to +0.8 VDCDigital OutputsLogic High: 2.0 VDC minimum source 32 mALogic Low: 0.55 VDC maximum sink 64 mAOptional Counter/TimersType: 82C54-10 programmable interval countersOutput Drive: 2.0 VDC minimum source 32 mA0.55 VDC maximumInput Gate: TTL/CMOS compatibleClock: On-boardActive Count Edge: Negative EdgeMinimum Clock Pulse Width: 30 nS high 40 nS lowTimer Range: 16 bitsMaximum Input Frequency: 10MHzBus TypeUSB 2.0 High-speed USB 1.1 Full-speed compatibleEnvironmentalOperating Temperature Range: 0° to 70°C (extended temp available)Storage Temperature Range: -40° to +85°CHumidity: 5% - 95%, non-condensingBoard Dimension: 3.550 x 3.775 inchesBox Dimension: 4.00 x 4.00 x 1.25 inchesPower+5VDC provided via USB bus up to 500mA**Basic Unit with Three Counters: 100mA typical (no load)+5VDC resettable fuse at 0.5A located on connector** Optional on-board external power circuitry and AC/DC adapter can be ordered (“-P” option) if current use is expected to be greater than what can be supplied by the USB bus. Please check to see how much current your USB port can supply and how much current you anticipate using.Ordering GuideUSB-DIO-32 Enclosure, module and screw terminal boardOptions-OEM Board only version (no enclosure and screw terminal board)-E Economy model (no screw terminal board)-DIN DIN rail mounting provision-P External power and AC/DC adapter-Cx Number of counters (where x = 1, 2 or 3 counters)AccessoriesUTBK-50 External plug-in screw terminal board。

第10章LCD模块1.LCD控制器介绍LCD控制器给单色或者彩色LCD板提供所有必须的控制信号，LCD控制器只有在LPC3250中拥有。

2.特征[1].AHB总线主接口可以访问帧缓冲区[2].通过不同的AHB总接口来设置和控制[3].双16字节可编程的64位宽的FIFO用于缓存将要显示的数据[4].支持4或8位接口的单面板或双面板单色STN显示[5].支持单面板或双面板彩色STN显示[6].支持TFT彩色显示[7].可编程的显示分辨率，包括但不限于320*200，320*240，640*200，640*240，800*600，1024*768。

[8].硬件光标支持单板显示[9].支持15灰度级单色，3375彩色STN以及32K彩色可调色的TFT[10].对于单色STN，1、2和4BPP调色显示（BPP位每像素）[11].对于彩色STN、TFT，1、2、4和8BPP调色彩色显示[12].16BPP真实彩色非调色，用与彩色STN、TFT[13].24BPP真实彩色非调色，用与彩色TFT[14].对于不同的显示板，可以编程定时[15].256项16位调色RAM用作一个128*32位的RAM[16].帧，行，像素时钟信号[17].交流偏置信号用于STN板，数据使能信号用于TFT板[18].支持大、小端，WINDOWS CE数据格式[19].通过外设时钟，或者由一个时钟输入引脚来提供LCD板的时钟3.可编程参数下面重要的显示和控制器参数可以被编程4.硬件光标支持硬件光标接口降低了软件开销，这个软件涉及到要维持LCD帧缓冲区的光标图像。

如果没有这个结构，软件需要：[1].在下一个光标位置节约一个图像区域[2].更新带光标图形的区域[3].用一个预先节约的图像来修复一个光标位置。

此外，LCD控制器必须核实图像操作是否覆盖光标，如果覆盖了，需要纠正。

光标尺寸为64*64的24位彩色形式，每一个光标的移动都要涉及到读和写，大约75KB的数据。

A F TA F TD R AF TD RA F TD R A F TD R A F T D R A F A F TD R A F TDRAF TDRAF TD R A F T DA F TD R A F TDRAF TDRA F T D RA F TDRA F T D R A1.General descriptionNXP Semiconductor designed the LPC3250 for embedded applications requiring high performance and low power consumption.NXP achieved their performance goals using NXP Semiconductor's state-of-the-art 90 nanometer process technology to implement an ARM926EJ-S CPU core with a Vector Floating Point co-processor and a large set of standard peripherals including USBOn-The-Go. Figure 1 shows a block diagram of the LPC3250. The LPC3250 operates at CPU frequencies exceeding 200 MHz. The basic ARM926EJ-S CPU Core implementation uses a Harvard architecture with a 5-stage pipeline. The ARM926EJ-S core also has an integral Memory Management Unit (MMU) to provide the virtual memory capabilities needed to support the multi-programming demands of modern operating systems. The basic ARM926EJ-S core also includes a set of DSP instruction extensions including single cycle MAC operations and native Jazelle Java Byte-code execution in hardware. The NXP implementation has one 32 kB Instruction Cache and one 32 kB Data Cache.For low power consumption, the LPC3250 takes advantage of NXP Semiconductor's advanced process and technology development to optimize Intrinsic Power, and uses software controlled architectural enhancements to optimize Power Management. The LPC3250 also includes 256 kB of on-chip static RAM, a NAND Flash interface, an Ethernet MAC, an LCD controller that supports STN and TFT panels, and an external bus interface that supports SDR and DDR SDRAM as well as static devices. In addition, the LPC3250 includes a USB 2.0 Full Speed interface, seven UARTs, two I2C interfaces, two SPI/SSP ports, two I2S interfaces, two multi-channel PWMs, four general purpose timers with capture inputs and compare outputs, a Secure Digital (SD) interface, and a 10-bit A/D converter with a touch screen sense option.2.FeaturesARM926EJS processor, running at CPU clock speeds up to 208 MHz A Vector Floating Point coprocessor.A 32 KB instruction cache and a 32 KB data cache.Up to 256 KB of internal SRAM.Selectable boot-up from various external devices: NAND Flash, SPI memory, USB, UART, or static memory.A Multilayer AHB system that provides a separate bus for each AHB master, includingboth an instruction and data bus for the CPU, two data busses for the DMA controller, and another bus for the USB controller, one for the LCD and a final one for the Ethernet MAC. There are no arbitration delays in the system unless two masters attempt to access the same slave at the same time.LPC325016/32-bit ARM microcontroller; hardware floating-pointcoprocessor, USB On-The-Go, and SDRAM memory interfaceRev. XX.xx — 26 February 2008Objective data sheetA F T D R A F A F TDR AF TD R A F T D AF TDRA F T D R A F T DR A F T DR AAn External memory controller for DDR and SDR SDRAM, as well as static devices.The address bus provides up to 16 MB for each of the 4 static chip selects.Two NAND Flash controllers. One for single level NAND Flash devices and the otherfor multi-level NAND Flash devices.An Interrupt Controller, supporting 73 interrupt sources.An eight channel General Purpose AHB DMA controller (GPDMA) that can be usedwith the SD card port, the high-speed UARTs, I2S ports, and SPI interfaces, as well as memory-to-memory transfers. Serial Interfaces:A 10/100 Ethernet MAC with dedicated DMA Controller.A USB interface supporting either Device, Host (OHCI compliant), or On-The-Go (OTG) with an integral DMA controller and dedicated PLL to generate the required 48 MHz USB clock.Four standard UARTs with fractional baud rate generation and 64 byte FIFOs. One of the standard UART’s supports irDA.Three additional high-speed UARTs intended for on-board communications that support baudrates up to 921,600 bps when using a 13 MHz main oscillator.All high-speed UARTs provide 64-byte FIFOs Two SPI controllers. Two SSP controllersTwo I2C-bus Interfaces with standard open drain pins. The I2C-bus Interfaces support single master, slave and multi-master I2C configurations.Two I2S interfaces, each with separate input and output channels. Each channel can be operated independently on 3 pins, or both input and output with one I2S interface can be done on only 4 pins.Additional Peripherals:LCD controller supporting both STN and TFT panels, with dedicated DMA controller. Programmable display resolution up to 1024x768. Secure Digital (SD) memory card interface.General purpose input, output, and I/O pins. Includes 12 GP input pins, 24 GP output pins, and 51 GP I/O pins.10 bit, 400kHz A/D Converter with input multiplexing from 3 pins. Optionally, the A/D Converter can operate as a touch screen controller.Real Time Clock (RTC) with separate power pin. This RTC has a dedicated 32 kHz oscillator. NXP implemented the RTC in an independent on-chip power domain so it can remain active while the rest of the chip is not powered. The RTC also Includes a 32 byte scratchpad memory.A 32-bit general purpose high speed timer with a 16-bit pre-scaler. This timerincludes one external capture input pin and a capture connection to the RTC clock. Interrupts may be generated using 3 match registers.Four enhanced Timer/Counters which are identical except for the peripheral base address. A minimum of two Capture inputs and two Match outputs are pinned out for all four timers, with a choice of several pins for each. Timer 1 brings out a third Match output, while Timers 2 and 3 bring out all four Match outputs.A 32-bit Millisecond timer driven from the RTC clock. This timer can generate Interrupts using 2 match registers.A Watchdog Timer. The watchdog timer is clocked by PERIPH_CLK.A F T D R A F A F TDR AF TD R A F T D AF TDRA F T D R A F TDR A F T DR ATwo versatile PWM blocks with 6 and 4 outputs respectively, programmable resolution, and an external clock capability. Two additional single output PWM blocks.Keyboard scanner function allows automatic scanning of up to an 8x8 key matrix. Up to 18 external interrupts.Standard ARM Test/Debug interface for compatibility with existing tools. Emulation Trace Buffer with 2K x 24 bit RAM allows trace via JTAG.Stop mode saves power, while allowing many peripheral functions to restart CPU activity.On-chip crystal oscillator.An on-chip PLL allows CPU operation up to the maximum CPU rate without the requirement for a high frequency crystal. Another PLL allows operation from the 32 kHz RTC clock rather than the external crystal. Boundary Scan for simplified board testing.320 pin LFBGA package, 280 pin TFBGA, and 100 pin TFBGA packages.Drop-in backward compatibilty with the LPC3180.3.Applications3.1Application Type3.2Another Application Type4.Ordering information[1]<Temperature Range>.Table 1.Ordering informationType numberPackage NameDescriptionVersion<BASIC_TYPE>TFBGA296plastic thin fine-pitch ball grid array package; 296 balls; body 15 x 15 x 0.7 mmSOT1048-1<BASIC_TYPE>TFBGA100plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.8 mmSOT598-1A F TDR A F A F TDRA F T D R A F T DAF TDR A F T D RA F T D R AF T D R A5.Block diagramFig 1.Block diagram of LPC3250A F TDR A F A F TDRA F T D R A F T DAF TDR A F T D RA F TTD R A6.Pinning information6.1PinningA4I2S1TX_CLK / MAT3.0A5I2C1_SCLA6MS_BS / MAT2.1 / PWM3.6A7MS_DIO1 / MAT0.1 / PWM3.2A8MS_DIO0 / MAT0.0 / PWM3.1A9SPI2_DATIO / MOSI1 /LCD[20]A10SPI2_DATIN / MISO1 / LCD[21]A11GPIO_01A12GPIO_00A13GPO_21 / U4_TX / LCD[3]A14GPO_15 / PWM3.3 / LCDFPA15GPO_07 / LCD[2]A16GPO_06 / PWM4.3 / LCD[18]Row BB2GPO_20B3GPO_05B4I2S1TX_WS / CAP3.0B5P0.0 / I2S1RX_CLKB6I2C1_SDAB7MS_SCLK / MAT2.0 / PWM3.5B8MS_DIO2 / MAT0.2 / PWM3.3B9SPI1_DATIO / MOSI0B10SPI2_CLK / SCK1 / LCD[23]B11GPIO_04 / SSEL1 / LCD[22]B12GPO_12 / PWM3.5 / LCDLE B13GPO_13 / PWM3.4 / LCDCP B14GPO_02 / MAT1.0 / LCD[0]B15GPI_19 / U4_RXB16GPI_08 / KEY_COL6/SPI2_BUSY / ENET_RX_DV B17N.C.Row C C1FLASH_RD_N C2GPO_19C3GPO_00 / TST_CLK1C4USB_ATX_INT_N C5USB_SE0_ VM / U5_TXC6TST_CLK2C7GPI_06 / HSTIM_CAP / I2S1RX_SDAC8MS_DIO3 / MAT0.3 / PWM3.4C9SPI1_CLK / SCK0A F TDR AFA F TDRAF T DRA F T D AF TDR AF T DR A F T D RAF T D R A C10SPI1_DATIN / MISO0C11GPIO_03 / KEY_ROW7 /ENET_MDIO C12GPO_09 / PWM4.1 / LCD[9]C13GPO_08 / PWM4.2 / LCD[8]C14GPI_02 / CAP2.0 /ENET_RXD3C15GPI_01 / SERVICE_N C16GPI_00 / ENET_RXD2C17KEY_ROW4 / ENET_TXD0C18KEY_ROW5 / ENET_TXD1Row D D1FLASH_RDY D2FLASH_ALED3GPO_14D4GPO_01D5USB_DAT_VP / U5_RXD6USB_OE_TP_ND7P0.1 / I2S1RX_WSD8GPO_04D9GPIO_02 / KEY_ROW6 / ENET_MDC D10GPO_16 / PWM3.2 /LCDAC D11GPO_18 / PWM3.1 / LCDLP D12GPO_03 / LCD[1]D13GPI_07 / PCAP3.0D14PWM_OUT1 / LCD[16]D15PWM_OUT2 / LCD[19]D16KEY_ROW3 / ENET_TX_EN D17KEY_COL2 / ENET_RX_ER D18KEY_COL3 / ENET_CRS Row E E1FLASH_IO[03]E2FLASH_IO[07]E3FLASH_CE_N E4I2C2_SDAE5USB_I2C_SCL E6USB_I2C_SDA E7I2S1TX_SDA / MAT3.1E8GPO_11E9GPIO_05 / SSEL0E10GPO_22 / U7_HRTS / LCD[14]]E11GPO_10 / PWM3.6 /LCDPWR E12GPI_09 / KEY_COL7 / ENET_COL E13GPI_04 / SPI1_BUSY E14KEY_ROW1 / ENET_TXD2E15KEY_ROW0 / ENET_TX_ER E16KEY_COL1 /ENET_RX_CLK/ENET_REF_CLK E17U7_RX / CAP0.0 / LCD[10]E18U7_TX / MAT1.1 / LCD[11]Row F F1FLASH_IO[02]F2FLASH_WR_N F3FLASH_CLE F4GPI_03F5VSS_IOC F6VSS_IOB F7VDD_IOCF8VDD_IOBF9VDD_IODF10VSS_IOD F11VSS_IODF12VSS_IODF13VDD_IODF14KEY_ROW2 / ENET_RXD3F15KEY_COL0 / ENET_TX_CLK F16KEY_COL5 / ENET_RXD1F17U6_IRRX F18U5_RX Row G G1EMC_DYCS1_N G2FLASH_IO[05]G3FLASH_IO[06]G4RESOUT_N G5VSS_IOC G6VDD_IOC G7VDD_CORE12G8VSS_COREG9VDD_CORE12G10VSS_COREG11VDD_CORE12G12VSS_COREG13U7_HCTS / CAP0.1 /LCDCLKIN G14DBGENG15KEY_COL4 / ENET_RXD0G16U6_IRTX G17SYSCLKEN / LCD[15]G18JTAG_TMS Row H H1EMC_OE_N H2FLASH_IO[00]H3FLASH_IO[01]H4FLASH_IO[04]H5VSS_IOCH6VDD_IOCH7VSS_COREH12VSS_IODH13VDD_IOAH14JTAG_TCK H15U5_TX H16HIGHCORE / LCD[17]H17JTAG_NTRSTH18JTAG_RTCKTable 2.Pin Allocation Table SOT1048-1 (TFBGA296)PinSymbolPinSymbolPinSymbolA F TDR AF A F TDRAF T D RAF T D AF TDR AF T DR A F T D R A F T D R ARow JJ1EMC_A[20] / P1.20J2EMC_A[21] / P1.21J3EMC_A[22] / P1.22J4EMC_A[23] / P1.23J5VDD_IOCJ6VDD_EMC J7VDD_CORE12J12VDD_CORE12J13VDD_IOA J14U3_RX J15JTAG_TDOJ16JTAG_TDI J17U3_TXJ18U2_HCTS / U3_CTS Row KK1EMC_A[19] / P1.19K2EMC_A[18] / P1.18K3EMC_A[16] / P1.16K4EMC_A[17] / P1.17K5VSS_EMCK6VDD_EMCK7VDD_EMCK12VSS_COREK13VSS_IOA K14VDD_RTC K15U1_RX / CAP1.0K16U1_TX K17U2_TX / U3_DTRK18U2_RX / U3_DSRRow L L1EMC_A[15] / P1.15L2EMC_CKE1L3EMC_A[00] / P1.0L4EMC_A[01] / P1.1L5VSS_EMCL6VDD_EMCL7VSS_COREL12VDD_COREFXDL13VDD_RTCCOREL14VSS_RTCCOREL15P0.4 / I2S0RX_WS / LCD[6]L16P0.5 / I2S0TX_SDA / LCD[7]L17P0.6 / I2S0TX_CLK / LCD[12]L18P0.7 / I2S0TX_WS / LCD[13]Row M M1EMC_A[02] / P1.2M2EMC_A[03] / P1.3M3EMC_A[04] / P1.4M4EMC_A[08] / P1.8M5VSS_EMC M6VDD_EMC M7VDD_CORE12M8VDD_EMCM9VSS_COREM10VSS_CORE M11VDD_CORE12M12 VSS_CORE M13VDD_COREFXDM14RESET_NM15ONSWM16GPO_23 / U2_HRTS / U3_RTS M17P0.2 / I2S0RX_SDA / LCD[4]M18P0.3 / I2S0RX_CLK / LCD[5]Row N N1EMC_A[05] / P1.5N2EMC_A[06] / P1.6N3EMC_A[07 / P1.7N4EMC_A[12] / P1.12N5VSS_EMC N6 VSS_EMC N7VDD_EMCN8VDD_EMCN9VDD_EMCN10VDD_EMC N11VDD_EMC N12VDD_AD N13VDD_ADN14VDD_FUSE N15VDD_RTCOSC N16GPI_05 / U3_DCD N17GPI_28 / U3_RI N18GPO_17Row P P1EMC_A[09] / P1.9P2EMC_A[10] / P1.10P3EMC_A[11] / P1.11P4EMC_DQM[1]P5EMC_DQM[3]P6VSS_EMC P7VSS_EMCP8 VSS_EMC P9VSS_EMCP10 VSS_EMC P11 VSS_EMC P12EMC_BLS[3]P13VSS_ADP14VSS_OSCP15VDD_PLLUSBTable 2.Pin Allocation Table SOT1048-1 (TFBGA296)Pin SymbolPin SymbolPin SymbolA F TDR AFA F TDRAF T DRA F T D AF TDR AF T DR A F T D RAF T D R A6.2Pin descriptionP16RTCX_IN P17RTCX_OUT P18VSS_RTCOSC Row R R1EMC_A[13] / P1.13R2EMC_A[14] / P1.14R3EMC_DQM[0]R4EMC_WR_N R5EMC_CAS_N R6EMC_DYCS0_NR7EMC_D[01]R8EMC_D[07]R9EMC_D[17]/ DDR_DQS1R10EMC_D[24] / P2.5R11EMC_CS1_N R12EMC_BLS[2]R13TS_XOUT R14PLL397_LOOP R15SYSX_OUT R16VSS_PLLUSB R17VDD_PLLHCLK R18VSS_PLLHCLK Row T T1EMC_DQM[2]T2EMC_RAS_N T3EMC_CLK T4EMC_CLKIN T5EMC_D[02]T6EMC_D[06]T7EMC_D[11]T8EMC_D[14]T9EMC_D[20] / P2.1T10EMC_D[23] / P2.4T11EMC_D[27] / P2.8T12EMC_CS2_N T13EMC_BLS[1]T14ADIN1T15VSS_PLL397T16VDD_PLL397T17SYSX_IN T18VDD_OSC Row UU2N.C.U3EMC_CKE0U4EMC_D[00]U5EMC_D[03]U6EMC_D[09]U7EMC_D[12]U8EMC_D[15]U9EMC_D[19] / P2.0U10EMC_D[22] / P2.3U11EMC_D[26] / P2.7U12EMC_D[30] / P2.11U13EMC_CS0_N U14EMC_BLS[0]U15ADIN0U16TS_YOUT U17N.C.Row VV3EMC_D[04]V4EMC_D[05]V5EMC_D[08]V6EMC_D[10]V7EMC_D[13]V8EMC_D[16]/ DDR_DQS0V9EMC_D[18]/ DDR_NCLKV10EMC_D[21] / P2.2V11EMC_D[25] / P2.6V12EMC_D[28] / P2.9V13EMC_D[29] / P2.10V14EMC_D[31] / P2.12V15EMC_CS3_NV16ADIN2Table 2.Pin Allocation Table SOT1048-1 (TFBGA296)PinSymbolPinSymbolPinSymbolTable 3.Pin descriptionSymbol Pin Type Reset state Description ADIN0U15analog in input ADC input 0ADIN1T14analog in input ADC input 1ADIN2V16analog in input ADC input 2DBGENG14I : PD input Device test input (JTAG select)EMC_A[00] / P1.0L3I/O LEMC address bit 0I/OPort 1 bit 0A F TDR A F A F TDRA F T D R AF T D AF TDR A F T D RAF T DR A F T D R AEMC_A[01] / P1.1L4I/O L EMC address bit 1I/O Port 1 bit 1EMC_A[02] / P1.2M1I/O L EMC address bit 2I/O Port 1 bit 2EMC_A[03] / P1.3M2I/O L EMC address bit 3I/O Port 1 bit 3EMC_A[04] / P1.4M3I/O L EMC address bit 4I/O Port 1 bit 4EMC_A[05] / P1.5N1I/O L EMC address bit 5I/O Port 1 bit 5EMC_A[06] / P1.6N2I/O L EMC address bit 6I/O Port 1 bit 6EMC_A[07 / P1.7N3I/O L EMC address bit 7I/O Port 1 bit 7EMC_A[08] / P1.8M4I/O L EMC address bit 8I/O Port 1 bit 8EMC_A[09] / P1.9P1I/O L EMC address bit 9I/O Port 1 bit 9EMC_A[10] / P1.10P2I/O L EMC address bit 10I/O Port 1 bit 10EMC_A[11] / P1.11P3I/O L EMC address bit 11I/O Port 1 bit 11EMC_A[12] / P1.12N4I/O L EMC address bit 12I/O Port 1 bit 12EMC_A[13] / P1.13R1I/O L EMC address bit 13I/O Port 1 bit 13EMC_A[14] / P1.14R2I/O L EMC address bit 14I/O Port 1 bit 14EMC_A[15] / P1.15L1I/O L EMC address bit 15I/O Port 1 bit 15EMC_A[16] / P1.16K3I/O L EMC address bit 16I/O Port 1 bit 16EMC_A[17] / P1.17K4I/O L EMC address bit 17I/O Port 1 bit 17EMC_A[18] / P1.18K2I/O L EMC address bit 18I/O Port 1 bit 18EMC_A[19] / P1.19K1I/O L EMC address bit 19I/O Port 1 bit 19EMC_A[20] / P1.20J1I/O LEMC address bit 20I/OPort 1 bit 20Table 3.Pin description …continuedSymbolPin Type Reset state DescriptionA F TDR A F A F TDRA F T D R AF T D AF TDR A F T D RAF T DR A F T D R AEMC_A[21] / P1.21J2I/O L EMC address bit 21I/O Port 1 bit 21EMC_A[22] / P1.22J3I/O L EMC address bit 22I/O Port 1 bit 22EMC_A[23] / P1.23J4I/O L EMC address bit 23I/O Port 1 bit 23EMC_BLS[0]U14O H Static memory byte lane 0 select EMC_BLS[1]T13O H Static memory byte lane 1 select EMC_BLS[2]R12O H Static memory byte lane 2 select EMC_BLS[3]P12O H Static memory byte lane 3 select EMC_CAS_N R5O H SDRAM column addr strobe out, active lowEMC_CKE0U3O L Clock enable out for SDRAM bank 0EMC_CKE1L2O L Clock enable out for SDRAM bank 1EMC_CLK T3O L/R SDRAM clock out EMC_CLKIN T4I input SDRAM clock feedbackEMC_CS0_N U13O H EMC static memory chip select 0EMC_CS1_N R11O H EMC static memory chip select 1EMC_CS2_N T12O H EMC static memory chip select 2EMC_CS3_N V15O H EMC static memory chip select 3EMC_D[00]U4I/O [1]input EMC data bit 0EMC_D[01]R7I/O [1]input EMC data bit 1EMC_D[02]T5I/O [1]input EMC data bit 2EMC_D[03]U5I/O [1]input EMC data bit 3EMC_D[04]V3I/O [1]input EMC data bit 4EMC_D[05]V4I/O [1]input EMC data bit 5EMC_D[06]T6I/O [1]input EMC data bit 6EMC_D[07]R8I/O [1]input EMC data bit 7EMC_D[08]V5I/O [1]input EMC data bit 8EMC_D[09]U6I/O [1]input EMC data bit 9EMC_D[10]V6I/O [1]input EMC data bit 10EMC_D[11]T7I/O [1]input EMC data bit 11EMC_D[12]U7I/O [1]input EMC data bit 12EMC_D[13]V7I/O [1]input EMC data bit 13EMC_D[14]T8I/O [1]input EMC data bit 14EMC_D[15]U8I/O [1]input EMC data bit 15EMC_D[16]/ DDR_DQS0V8I/O [1]input EMC data bit 16,DDR data strobe 0 I/O EMC_D[17]/ DDR_DQS1R9I/O [1]inputEMC data bit 17,DDR data strobe 1 I/OTable 3.Pin description …continuedSymbolPin Type Reset state DescriptionA F TDR A F A F TDRA F T D R AF T D AF TDR A F T D RAF T DR A F T D R AEMC_D[18]/ DDR_NCLK V9I/O input EMC data bit 18,DDR inverted clock out EMC_D[19] / P2.0U9I/O inputEMC data bit 19I/O parallel I/O bit 0EMC_D[20] / P2.1T9I/O input EMC data bit 20I/O parallel I/O bit 1EMC_D[21] / P2.2V10I/O input EMC data bit 21I/O parallel I/O bit 2EMC_D[22] / P2.3U10I/O input EMC data bit 22I/O parallel I/O bit 3EMC_D[23] / P2.4T10I/O input EMC data bit 23I/O parallel I/O bit 4EMC_D[24] / P2.5R10I/O input EMC data bit 24I/O parallel I/O bit 5EMC_D[25] / P2.6V11I/O input EMC data bit 25I/O parallel I/O bit 6EMC_D[26] / P2.7U11I/O input EMC data bit 26I/O parallel I/O bit 7EMC_D[27] / P2.8T11I/O input EMC data bit 27I/O parallel I/O bit 8EMC_D[28] / P2.9V12I/O input EMC data bit 28I/O parallel I/O bit 9EMC_D[29] / P2.10V13I/O input EMC data bit 29I/O parallel I/O bit 10EMC_D[30] / P2.11U12I/O input EMC data bit 30I/O parallel I/O bit 11EMC_D[31] / P2.12V14I/O input EMC data bit 31I/O parallel I/O bit 12EMC_DQM[0]R3O L SDRAM data mask 0 out EMC_DQM[1]P4O L SDRAM data mask 1 out EMC_DQM[2]T1O L SDRAM data mask 2 out EMC_DQM[3]P5O L SDRAM data mask 3 out EMC_DYCS0_N R6O H SDRAM active low chip select 0EMC_DYCS1_N G1O H SDRAM active low chip select 1EMC_OE_N H1O H EMC static memory output enable EMC_RAS_N T2O H SDRAM row address strobe, active lowEMC_WR_N R4O H EMC write strobe, active low FLASH_ALE D2O L Flash address latch enable FLASH_CE_N E3O H Flash chip enableFLASH_CLEF3OL Flash command latch enableTable 3.Pin description …continuedSymbolPin Type Reset state DescriptionA F TDR A F A F TDRA F T D R AF T D AF TDR A F T D RAF T DR A F T D R AFLASH_IO[00]H2I/O [1]input Flash data bus, bit 0FLASH_IO[01]H3I/O [1]input Flash data bus, bit 1FLASH_IO[02]F1I/O [1]input Flash data bus, bit 2FLASH_IO[03]E1I/O [1]input Flash data bus, bit 3FLASH_IO[04]H4I/O [1]input Flash data bus, bit 4FLASH_IO[05]G2I/O [1]input Flash data bus, bit 5FLASH_IO[06]G3I/O [1]input Flash data bus, bit 6FLASH_IO[07]E2I/O [1]input Flash data bus, bit 7FLASH_RD_N C1O H Flash read enableFLASH_RDY D1I input Flash ready (from Flash device)FLASH_WR_N F2O HFlash write enable GPI_00 / ENET_RXD2C16I inputGP input 00IEthernet receive data 2GPI_01 / SERVICE_N C15I input GP input 01Iboot select input GPI_02 / CAP2.0 / ENET_RXD3C14I input GP input 02I Timer 2 Cap 0IEthernet receive data 3GPI_03F4I input GP input 03GPI_04 / SPI1_BUSY E13I input GP input 04ISPI1 busy input GPI_05 /U3_DCD N16I input GP input 05IUart 3 data carrier detect input GPI_06 /HSTIM_CAP / I2S1RX_SDA C7I input GP input 06I HS timer capture input II2S1 receive data GPI_07 / PCAP3.0D13I input GP input 07Iinput PWM3 capture/clock input GPI_08 / KEY_COL6 /SPI2_BUSY / ENET_RX_DV B16I input GP input 08I keyscan column 6 input I SPI2 busy inputIEthernet receive data valid input GPI_09 / KEY_COL7 / ENET_COL L2I input GP input 09I keyscan column 7 input IEthernet collision input GPI_19 / U4_RX B15I input GP input 10IUart 4 receive GPI_28 / U3_RIN17I input GP input 11IUart 3 ring indicator inputTable 3.Pin description …continuedSymbolPin Type Reset state DescriptionA F TDR A F A F TDRA F T D R AF T D AF TDR A F T D RAF T DR A F TD R AGPIO_00A12I/O input GP I/O 00GPIO_01A11I/O input GP I/O 01GPIO_02 /KEY_ROW6 / ENET_MDC D9I/O input GP I/O 02O keyscan row 6 outputOEthernet PHY interface clock GPIO_03 / KEY_ROW7 / ENET_MDIO C11I/O input GP I/O 03I/O keyscan row 7 output I/OEthernet PHY interface data GPIO_04 / SSEL1 / LCD[22]B11I/O inputGP I/O 04I/O SSP1 Slave Select I/OLCD data bit 22GPIO_05 /SSEL0E9I/O input GP I/O 05I/O SSP0 Slave Select GPO_00 / TST_CLK1C3O L GP out 00, test clock 1 out GPO_01D4O L GP out 01GPO_02 / MAT1.0 / LCD[0]B14O L GP out 02O L Timer 1 Match 0OL LCD data bit 0GPO_03 / LCD[1]D12O HGP out 03O LCD data bit 1GPO_04D8O L GP out 04GPO_05B3O H GP out 05GPO_06 / PWM4.3 / LCD[18]A16O L GP out 06O PWM4 out 3OLCD data bit 18GPO_07 / LCD[2]A15O H GP out 07O LCD data bit 2GPO_08 / PWM4.2 / LCD[8]C13O L GP out 08O PWM4 out 2OLCD data bit 8GPO_09 / PWM4.1 / LCD[9]C12O L GP out 09O PWM4 out 1OLCD data bit 9GPO_10 / PWM3.6 / LCDPWR E11O L GP out 10O PWM3 out 6OLCD panel power enable GPO_11E8OL GP out 11Table 3.Pin description …continuedSymbol Pin TypeReset stateDescriptionA F TDR A F A F TDRA F T D R A F T DAF TDR A F T D RA F T D R AF T D R AGPO_12 / PWM3.5 / LCDLE B12O LGP out 12O PWM3 out 5OLCD line end signal GPO_13 / PWM3.4 / LCDCP B13O L GP out 13O PWM3 out 4OLCD clock output GPO_14D3O L GP out 14GPO_15 / PWM3.3 / LCDFP A14O L GP out 15OPWM3 out 3O LCD frame/sync pulseGPO_16 / PWM3.2 /LCDAC D10O L GP out 16O PWM3 out 2OLCD STN AC bias / TFT data enable GPO_17N18O L GP out 17GPO_18 / PWM3.1 / LCDLP D11O L GP out 18O PWM3 out 1OLCD line sync / horizontal sync GPO_19C2O L GP out 19GPO_20B2O H GP out 20GPO_21 / U4_TX / LCD[3]A13O L GP out 21O Uart 4 transmit OLCD data bit 3GPO_22 /U7_HRTS / LCD[14]]E10O L GP out 22O HS Uart 7 RTS out OLCD data bit 14GPO_23 / U2_HRTS / U3_RTSM16OL GP out 23O HS Uart 2 RTS out OUart 3 RTS out HIGHCORE / LCD[17]H16O LCore voltage control out O LCD data bit 17I2C1_SCL A5I/O T I2C1 serial clock input./output I2C1_SDA B6I/O T I2C1 serial data input/output I2C2_SCL A3I/O T I2C2 serial clock input/output I2C2_SDA E4I/O T I2C2 serial data input/output I2S1TX_CLK / MAT3.0A4I/O L I2S1 transmit clock I/O Timer 3 Match 0I2S1TX_SDA / MAT3.1E7I/O input I2S1 transmit data I/OTimer 3 Match 1Table 3.Pin description …continuedSymbol Pin Type Reset state DescriptionA F TDR A F A F TDRA F T D R AF T D AF TDR A F T D RAF T DR A F T D R AI2S1TX_WS / CAP3.0B4I/O inputI2S1 transmit word select I/O Timer 3 Cap 0JTAG_NTRST H17I : PU input JTAG1 reset input JTAG_RTCK H18O L JTAG1 return clock out JTAG_TCK H14I inputJTAG1 clock input JTAG_TDI J16I : PU input JTAG1 data input JTAG_TDO J15O L JTAG1 data outJTAG_TMS G18I : PU input TAG1 test mode select input KEY_COL0 / ENET_TX_CLK F15I input Keyscan column 0 input I Ethernet transmit clock KEY_COL1 / ENET_RX_CLK / ENET_REF_CLK E16I input Keyscan column 1 input, I Ethernet receive clock (MII mode)IEthernet reference clock (RMII mode)KEY_COL2 / ENET_RX_ER D17I input Keyscan column 2 input I Ethernet receive error input KEY_COL3 / ENET_CRS D18I input Keyscan column 3 input I Ethernet carrier sense input KEY_COL4 / ENET_RXD0G15I input Keyscan column 4 input I Ethernet receive data 0KEY_COL5 / ENET_RXD1F16I input Keyscan column 5 input I Ethernet receive data 1KEY_ROW0 / ENET_TX_ER E15I/O H Keyscan row 0 out I/O Ethernet transmit error KEY_ROW1 / ENET_TXD2E14I/O H Keyscan row 1 out I/O Ethernet transmit data 2KEY_ROW2 / ENET_RXD3F14I/O H Keyscan row 2 out I/O Ethernet transmit data 3KEY_ROW3 / ENET_TX_EN D16I/O H Keyscan row 3 out I/O Ethernet transmit enable KEY_ROW4 / ENET_TXD0C17I/O H Keyscan row 4 out I/O Ethernet transmit data 0KEY_ROW5 / ENET_TXD1C18I/O H Keyscan row 5 out I/O Ethernet transmit data 1MS_BS / MAT2.1 / PWM3.6A6I/O L MS/SD card command out I/OTimer 2 Match 1I/O PWM3.6 outputMS_DIO0 / MAT0.0 / PWM3.1A8I/O input MS/SD card data 0I/OTimer 0 Match 0I/O PWM3.1 outTable 3.Pin description …continuedSymbolPin Type Reset state DescriptionA F TDR A F A F TDRA F T D R AF T D AF TDR A F T D RAF T DR A F TD R AMS_DIO1 / MAT0.1 / PWM3.2A7I/O inputMS/SD card data 1I/OTimer 0 Match 1I/O PWM3.2 outMS_DIO2 /MAT0.2 / PWM3.3B8I/O input MS/SD card data 2I/OTimer 0 Match 2I/O PWM3.3 outMS_DIO3 / MAT0.3 / PWM3.4C8I/O input MS/SD card data 3I/O Timer 0 Match 3I/OPWM3.4 outMS_SCLK / MAT2.0 / PWM3.5B7I/O L MS/SD card clock out I/OTimer 2 Match 0I/O PWM3.5 outputN.C.B17pin not connected N.C.U17pin not connected N.C.U2pin not connectedONSW M15O L RTC match out for external powercontrol P0.0 /I2S1RX_CLK B5I/O input Port 0 bit 0I/O I2S1 receive clock P0.1 /I2S1RX_WS D7I/O input Port 0 bit 1I/O I2S1 receive word select P0.2 /I2S0RX_SDA / LCD[4]M17I/O input Port 0 bit 2I/O I2S0 receive data I/OLCD data bit 4P0.3 /I2S0RX_CLK / LCD[5]M18I/O input Port 0 bit 3I/O I2S0 receive clock I/OLCD data bit 5P0.4 /I2S0RX_WS / LCD[6]L15I/O input Port 0 bit 4I/O I2S0 receive word select I/OLCD data bit 6P0.5 /I2S0TX_SDA / LCD[7]L16I/O input Port 0 bit 5I/O I2S0 transmit data I/OLCD data bit 7P0.6 /I2S0TX_CLK / LCD[12]L17I/O input Port 0 bit 6I/O I2S0 transmit clock I/OLCD data bit 12P0.7 /I2S0TX_WS / LCD[13]L18I/O input Port 0 bit 7I/O I2S0 transmit word select I/OLCD data bit 13PLL397_LOOPR14analog filterPLL397 loop filter(for external components)Table 3.Pin description …continuedSymbolPin Type Reset state DescriptionA F TDR A F A F TDRA F T D R AF T D AF TDR A F T D RAF T DR A F T D R APWM_OUT1 /LCD[16]D14O LPWM1 out OLCD data bit 16PWM_OUT2 / LCD[19]D15O L PWM2 out O internal irq/fiq status OLCD data bit 19RESET_N M14I input Reset input, active lowRESOUT_N G4O L/H Reset out. Reflects external & WDT resetRTCX_IN P16analog in input RTC oscillator input RTCX_OUT P17analog outoutput RTC oscillator output SPI1_CLK / SCK0C9O input SPI1 clock out O SSP0 clock out SPI1_DATIN /GPI_25/ MISO0C10I/OinputSPI1 data inI/O GPI bit 25I/O SSP0 MISOSPI1_DATIO / MOSI0B9I/OinputSPI1 data out (and opt. input)I/O SSP0 MOSI SPI2_CLK / SCK1 / LCD[23]B10I/O input SPI2 clock out I/O SSP1 clock outI/OLCD data bit 23SPI2_DATIO / MOSI1 / LCD[20]A9I/O inputSPI2 data out (and opt. input)I/O SSP1 MOSI I/OLCD data bit 20SPI2_DATIN / GPI_27/ MISO1 / LCD[21]A10I/O inputSPI2 data in I/O GPI bit 27I/OLCD data 21SYSCLKEN / LCD[15]G17I/O HClock request out for external clock source I/OLCD data bit 15SYSX_IN T17analog in input System clock oscillator input SYSX_OUT R15analog out output System clock oscillator output TS_XOUT R13I/O T Touchscreen X output TS_YOUT U16I/O T Touchscreen Y output TST_CLK2C6O L Test clock 2 out U1_RX / GPI_15 / CAP1.0K15I/O inputHS Uart 1 receive I/O GPI bit 15I/OTimer 1 Cap 0U1_TXK16OHHS Uart 1 transmitTable 3.Pin description …continuedSymbolPin Type Reset state Description。

LPC3000系列ARM…………………………………………4-02LPC2900系列ARM…………………………………………4-06LPC2800系列ARM…………………………………………4-08LPC1000系列ARM…………………………………………4-10LPC2400/2300系列ARM…………………………………4-13LPC2200/2100系列ARM………………………………4-20LPC2103/02/01ARM………………………………………4-27LPC700系列单片机………………………………………4-30LPC9001系列单片机………………………………………4-31LPC900系列单片机………………………………………4-3280C51系列单片机…………………………………………4-38嵌入式系统智能开发平台…………………………………4-39技术支持电话： (020) 22644383 22644384技术支持邮箱：ARM@ LPC2300@LPC3000系列ARM—数据传输及处理能力不同凡响LPC3000系列ARM采用了带有矢量浮点协处理器的ARM926EJ-S CPU内核，与LPC2000系列相比，数据处理能力大幅提升；工作频率可高达266MHz，这为USB、以太网、LCD控制器等外设同时运行提供了强有力的后盾，将各种高速外设性能发挥到淋漓尽致。

LPC3000系列采用了多重AHB总线架构，各个高速外设同时运行，没有速度瓶颈。

超强的浮点和DSP数据处理能力、超高的数据传输速度和丰富的片内高速外设使得LPC3000系列ARM成为数据处理和通信等应用场合的首选。

功能特性:● ARM926EJ-S内核○ LPC3200：266MHz； LPC3100：180MHz。

● 矢量浮点协处理器(仅适用于LPC3200)○ 单精度浮点数计算一个周期完成；○ 双精度浮点数计算两个周期完成。

● 大容量Cache○ LPC3200：32KB指令和32KB数据；○ LPC3100：16KB指令和16KB数据。

第32章LPC3250通用I/O口1.特征[1].在LPC3250里存在4个口来描述通用的输入口，输出口，以及输出输出口；[2].位电平设置和清除寄存器允许一个单指令可以设置或者清除一个P口的任何位数；[3].个别支持输入和输出模式的位的方向控制；[4].对于I/O口，可编程的输出状态和真实口状态都可以读出来；[5].总共22个通用输入口，24个通用输出口，6个通用I/O口（P3口）；[6].如果16位的SDRAM接口被使用了，那么13个外部寄存器控制器EMC数据线（P2口）就被作为GPIO使用了；[7].如果信号共享的外设没有使用，那么8个额外的GPIO线就被使用了。

2.应用[1].通用的I/O口[2].驱动LED或者其它指示器[3]控制片外装置或者与之通讯[4].感测静态输入3.GPIO功能简介通用的I/O口模块控制输出口状态，并且允许访问输入口。

有的口被定义为GPO，有的定义为GPI，有的是GPIO。

在系统复位时，所有的输出信号都有一个定义值，这些定义值在PACKAING，PINOUT，和PIN复用口中找到。

通过FAB总线访问GPIO模块，由PERIPH-CLK提供时钟信号。

下面四组分别介绍了四个I/O口的连接：P0，P1，P2，P3。

其中P0，P1，P2口是GPIO口，而P2口含有三种不同类3.1P0，1，2，3双向口[1].作为输入口，寄存器P[3~0]-INT-STATE反应了当前GPIO输入口的电平。

[2].作为输出口，寄存器P[3~0]-OUTP-SET和P[3~0]-OUTP-CLR控制通讯的GPIO口的电平。

[3].P[2~0]-DIR-CLR寄存器控制GPIO口的方向，其中GPIO口方向的选择在P P[2~0]-DIR-STATE寄存器中读取。

[4].可编程的输出信号的电平可以在寄存器P[3~0]-OUTP-STATE中读取。

3.1.1P1口和P2口的EMC总线GPIO当使用一个16位SDRAM总线时，或者没有SRAM连接的时候，一些或者所有的EMC-D[31~19]和EMC[23~0]-A口可以用做GPIO口。