T73YE10TR100中文资料

TONGLINGNC00001PCB 继电器JQC-3FF●10A switching capability●Small footprint●Sealed type available●Class B/F available●Conform to RoHS,ELV directive19.2*15.4*15.4mm■Nominal Voltage额定电压(VDC) 3 5 6 9 12 18 24 48Coil Resistance线圈阻值 (Ω±10%) 25 69 100 225 400 900 1600 6400Rated Current额定电流(mA) 120 71.4 60 40 30 20 15 7.5 0.36W Max Operate Voltage 最大吸合电压(VDC) 2.25 3.75 4.5 6.75 9 13.5 18 36Min Release Voltage最小释放电压(VDC) 0.15 0.25 0.3 0.45 0.6 0.9 1.2 2.4Max ApplicableVoltage 最大过载电压70℃时额定电压的130%，23℃时额定电压的170%■Contact Form触点形式1H/1ZContact Material触点材料Silver AlloyLoad负载Resistive load(COSФ=1)Contact Ratings触点负载1H:10A 240VAC 1Z: 7A 240VAC 12A 120VAC 10A 120VACMinimum load 最小负载100mA 5VDCMax Switching Voltage最大转换电压250VAC/30VDCMax Switching Current最大转换电流15AMax Switching Power 最大转换功率2770VA/240WContact Resistance接触电阻100mΩMax at 6VDC 1ALife Expectancy寿命Electrical 电气寿命: 100,000 Operations(at30Operations/minute)Mechanical机械寿命: 10,000,000 Operations(at300Operations/minute)■CHARACTERISTICS DATA性能参数Insulation Resistance绝缘阻值100MΩMin at 500VDC Dielectric Strength Between Open Contacts触点间耐压750VAC(50/60Hz for one minute) Between Contacts and coil触点与线圈间耐压1500VAC(50/60Hz for one minute) Operate Time吸合时间10msRelease Time释放时间5msTemperature Range环境温度-40℃to+85℃Shock Resistance冲击Operating Extremes动作极限: 10G Damage Limits破坏极限: 100GVibration Resistance振动10-55Hz, 1.5mmMax. switching frequency最大转换频率Mechanical: 18,000 operations/hr Electrical: 1,800 operations/hrHumidity湿度40-85% Weight重量Approx 10g Safety Standard安全标准CE■ENGINEERING DATA设计参数1510531000500300100705030■OVERALL AND MOUNTING DIMENSIONS安装图安装图接线图4 513 2Form C513 2Form AREMARK（备注）：1、产品部分外形尺寸中未注尺寸公差：当外形尺寸≤1mm 时，公差为±0.2mm；当外形尺寸在 1~5mm 时，公差为±0.3mm；当外形尺寸＞5mm时，公差为±0.4mm。

TX Buffering, Phase Alignment, and TX Skew Reductionor TXRESET (see “FPGA TX Interface,” page 120). Assertion of GTXRESET triggers a sequence that resets the entire GTX_DUAL tile.Using the TX Phase-Alignment Circuit to Minimize TX SkewTo use the phase-alignment circuit to force the XCLK phase of multiple lanes to match the common TXUSRCLK phase, follow these steps.Initial conditions when TX_BUFFER_USE is TRUE:♦Set TX_BUFFER_USE_0 and TX_BUFFER_USE_1 to TRUE.♦Set TXRX_INVERT0 and TXRX_INVERT1 to 011.♦Set TX_XCLK_SEL0 and TX_XCLK_SEL1 to TXOUT.♦Set PMA_TX_CFG0 and PMA_TX_CFG1 to 20'h80082.1.Set TX_XCLK_SEL0 and TX_XCLK_SEL1 to TXUSR .2.Wait for all clocks to stabilize, then drive TXENPMAPHASEALIGN High.Keep TXENPMAPHASEALIGN High unless the phase-alignment procedure must be repeated. Driving TXENPMAPHASEALIGN Low causes phase alignment to be lost.3.Wait 32 TXUSRCLK2 clock cycles, and then drive TXPMASETPHASE High.4.Wait the number of required TXUSRCLK2 clock cycles as specified in Table 6-11, and then drive TXPMASETPHASE Low. The phase of the PMACLK is now aligned with TXUSRCLK.5.Set TX_XCLK_SEL0 and TX_XCLK_SEL1 back to TXOUT.6.Assert and deassert TXRESET synchronously to TXUSRCLK. In this use mode,TXRESET must be deasserted simultaneously to all GTX Transceivers on which the deskew operation is being performed.The phase-alignment procedure must be redone if any of the following conditions occur:•GTXRESET is asserted•PLLPOWERDOWN is deasserted •The clocking source changedFigure 6-20 shows the TX phase-alignment procedure. TXENPMAPHASEALIGN(0/1) and TXPMASETPHASE(0/1) are independent for each GTX transceiver. Thisimplementation is different from the GTP_DUAL tile where TXENPHASEALIGN and TXPMASETPHASE are shared tile pins. The procedure is always applied to each GTX transceiver’s TXENPMAPHASEALIGN(0/1) signal on the tile. TXOUTCLK cannot be the source for TXUSRCLK when the TX phase-alignment circuit is used. See “FPGA TX Interface,” page 120 for details.Table 6-11:Number of Required TXUSRCLK2 Clock CyclesPLL_DIVSEL_OUT_0PLL_DIVSEL_OUT_1TXUSRCLK2 Wait Cycles18,192216,384432,767Chapter 6:GTX Transmitter (TX)TX PRBS GeneratorOverviewPseudo-random bit sequences (PRBS) are commonly used to test the signal integrity of high-speed links. These sequences appear random but have specific properties that can be used to measure the quality of a link.The GTX PRBS block can generate several industry-standard PRBS patterns. Table 6-13 lists the available PRBS patterns and their typical uses.Ports and AttributesTable 6-14 defines the TX PRBS generator ports.There are no attributes in this section.DescriptionEach GTX transceiver includes a built-in PRBS generator. This feature can be used inconjunction with other test features, such as loopback and the built-in PRBS checker, to run tests on a given channel.To use the PRBS generator, the PRBS test mode is selected using the TXENPRBSTST port. Table 6-14 lists the available settings.Table 6-13:Pseudo-Random Bit Sequences Name Polynomial Length of Sequence (bits)Consecutive ZerosTypical UsePRBS-71+X 6+X 7 (inverted)27–17Used to test channels with 8B/10B.PRBS-231+X 18+X 23 (inverted)223–123ITU-T Recommendation O.150, Section 5.6. One of therecommended test patterns in the SONET specification.PRBS-311+X 28+X 31 (inverted)231–131ITU-T Recommendation O.150, Section 5.8. A recommended PRBS test pattern for 10 Gigabit Ethernet. See IEEE 802.3ae-2002.Table 6-14:TX PRBS Generator PortsPortDirectionClock DomainDescriptionTXENPRBSTST0[1:0]TXENPRBSTST1[1:0]InTXUSRCLK2Transmitter test pattern generation control. A pseudo-random bit sequence (PRBS) is generated by enabling the test pattern generation circuit.00: Test pattern generation off (standard operation mode)01: Enable 27–1 PRBS generation 10: Enable 223–1 PRBS generation 11: Enable 231–1 PRBS generationBecause PRBS patterns are deterministic, the receiver can check the received data against a sequence of its own PRBS generator.TX Out-of-Band/Beacon SignalingChapter 6:GTX Transmitter (TX)Parallel In to Serial OutParallel In to Serial OutOverviewThe Parallel In to Serial Out (PISO) block is the heart of the GTX TX datapath. It serializes parallel data from the PCS using a high-speed clock from the shared PMA PLL.The PISO block serializes 16 or 20 bits per parallel clock cycle, depending on the internal data width for the tile (INTDATAWIDTH). The clock rate is determined by the shared PMA PLL rate, divided by a local TX divider.Ports and AttributesTable 6-15 defines the TX PISO ports.Table 6-16 defines the TX PISO attributes.DescriptionEquation 6-5 shows how to calculate the TX line rate when operating without oversampling (OVERSAMPLE_MODE = FALSE).Equation 6-5When oversampling is activated, use Equation 6-6 to calculate the line rate.Equation 6-6See “Oversampling,” page 185 for more information about oversampling.Table 6-15:TX PISO PortsPortDirectionClock DomainDescriptionINTDATAWIDTH In AsyncSpecifies the width of the internal datapath for the entire GTX_DUAL tile. This shared port is also described in “Shared PMA PLL,” page 86.0: Internal datapath is 16 bits wide 1: Internal datapath is 20 bits wideTable 6-16:TX PISO AttributesAttributeTypeDescriptionOVERSAMPLE_MODEBooleanThis shared attribute activates the built-in 5x digital oversampling circuits in both GTX transceivers. Oversampling must be enabled when running the GTX transceivers at line rates between 150Mb/s and 750Mb/s.TRUE: Built-in 5x digital oversampling enabled for both GTX transceivers on the tileFALSE: Digital oversampling disabledSee “Oversampling,” page 185 for more details about 5x digital oversampling.PLL_TXDIVSEL_OUT_0 PLL_TXDIVSEL_OUT_1IntegerSets the divider for the TX line rate for the individual GTX transceiver. The divider can be set to 1, 2, or 4.Tx Line Rate PLL Clock Rate 2×PLL_TXDIVSEL_OUT----------------------------------------------------------=Tx Line Rate PLL Clock Rate 2×PLL_TXDIVSEL_OUT 5×---------------------------------------------------------------------=。

4脚 DIP
PC815XNNSZ0F*5, *6 复 合 光 晶 PC81510NSZ0X 体 管 5, 6 输 PC852XNNSZ0F* * 出 PC853XNNSZ0F*5, *6
*1 *2 *3 *4 *5 *6 *7 *8 *9
–
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50
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600
1
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100
⅜ ⅜ ⅜
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页码 40 40 40 40 40 40 41 41 41 41 41 41 41 42 42 42 42 42 42 43 43
<OPIC 输出型>
封装类型 输出类型 特点 型号 （系列） PC400J00000F／PC456L0NIP0F／ PC410S0NIP0F ／PC410L0NIP0F ／ PC4D10SNIP0F PC457S0NIP0F ／PC457L0NIP0F 页码
PC714V0NSZXF PC724V0NSZXF
高绝缘电压 高绝缘电压， 大输入电流 高绝缘电压， 带基底端子 高绝缘电压， 高灵敏度 高绝缘电压， 高灵敏度, 高集电极发射极电压， 大功率
PC3HU7xYIP0B
PC3H2J00000F （小扁平型4脚）
注意： 未经元器件规格说明书确认，便在设备中使用产品目录、数据手册等所刊载的任何夏普元器件，由此引起的故障或损害，夏普公 司将不负任何责任。 除非特别说明，本页所列的型号均符合 RoHS （有害物质限制）标准* 。详情请与夏普公司联系。 *RoHS （有害物质限制）标准：禁止使用铅、镉、六价铬、汞和特定溴系阻燃剂 （PBB 和 PBDE） ，除特别情况外。 因此，在使用任何夏普元器件之前，务请与夏普公司联系以获取最新的元器件规格说明书。

Dimensions of CNY70 in mm95 11345www.vishay.Document Number 83751Ozone Depleting Substances Policy StatementIt is the policy of Vishay Semiconductor GmbH to1.Meet all present and future national and international statutory requirements.2.Regularly and continuously improve the performance of our products, processes, distribution and operatingsystems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment.It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs).The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances.Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents.1.Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively2.Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the EnvironmentalProtection Agency (EPA) in the USA3.Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Vishay Telefunken products for any unintended or unauthorized application, the buyer shall indemnify Vishay Telefunken against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use.Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, GermanyTelephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423Document Number 83751。