PLL DesignGuide December 2003NoticeThe information contained in this document is subject to change without notice. Agilent Technologies makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Agilent Technologies shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing, performance, or use of this material.WarrantyA copy of the specific warranty terms that apply to this software product is available upon request from your Agilent Technologies representative.Restricted Rights LegendUse,duplication or disclosure by the ernment is subject to restrictions as set forth in subparagraph (c) (1) (ii) of the Rights in Technical Data and Computer Software clause at DFARS252.227-7013for DoD agencies,and subparagraphs(c)(1) and (c) (2) of the Commercial Computer Software Restricted Rights clause at FAR 52.227-19 for other agencies.Agilent Technologies395 Page Mill RoadPalo Alto, CA 94304 U.S.A.Copyright © 1998-2003, Agilent Technologies. All Rights Reserved. AcknowledgmentsMentor Graphics is a trademark of Mentor Graphics Corporation in the U.S. and other countries.Microsoft®, Windows®, MS Windows®, Windows NT®, and MS-DOS® are U.S. registered trademarks of Microsoft Corporation.Pentium® is a U.S. registered trademark of Intel Corporation.PostScript® and Acrobat® are trademarks of Adobe Systems Incorporated.UNIX® is a registered trademark of the Open Group.Contents1PLL QuickStart GuideUsing DesignGuides.................................................................................................1-1 Basic Procedures.....................................................................................................1-3 Selecting Appropriate Configurations.......................................................................1-7 Phase Margin and Unity Gain Bandwidth...........................................................1-8 Phase Noise Response......................................................................................1-10 T ransient Time Response...................................................................................1-12 2PLL DesignGuide ReferenceUsing the PLL DesignGuide.....................................................................................2-1 PLL Configurations...................................................................................................2-2 Frequency Synthesizer (SYN)............................................................................2-2 Frequency Modulator (FMD)..............................................................................2-3 Frequency Demodulator (FDM)..........................................................................2-4 Phase Modulator (PMD).....................................................................................2-5 Phase Demodulator (PDM)................................................................................2-6 Phase Detectors.......................................................................................................2-6 Detector T ypes....................................................................................................2-6 RFIC PLL Examples.................................................................................................2-8 Synthesizers.......................................................................................................2-8 Phase Detectors.................................................................................................2-8 Prescalars..........................................................................................................2-9 Reference.................................................................................................................2-10 T emplate Reference Guide.................................................................................2-10 T emplate Example: SYN_CP_FQ_A3P..............................................................2-11 T emplate Example: SYN_CP_PN_A3P............................................................2-13 T emplate Example: SYN_CP_TN_A3P............................................................2-14 Parameter Definitions.........................................................................................2-15 Encoded Subcircuits...........................................................................................2-18 Bibliography........................................................................................................2-20Chapter 1: PLL QuickStart GuideThis PLL QuickStart Guide is intended to help you get started using thePhase-Locked Loop Design Guide effectively.For detailed reference information,refer to Chapter 2, PLL DesignGuide Reference.Note This manual is written describing and showing access through the cascading menu preference. If you are running the program through the selection dialog box method, the appearance and interface will be slightly different.The PLL DesignGuide has many simulation setups and data displays that are very useful for designing a phase-locked loop. The simulation set-ups are categorized by the PLL configuration,simulation technique,and type of phase detector and low-pass filter. The simulation set-ups are for analysis.Note This DesignGuide is not a complete solution for all phase-locked loop techniques, but covers the most common approaches. Subsequent releases of this DesignGuide will include an expanded range of features.Using DesignGuidesAll DesignGuides can be accessed in the Schematic window through either cascading menus or dialog boxes. You can configure your preferred method in the Advanced Design System Main window. Select the DesignGuide menu.The commands in this menu are as follows:DesignGuide Studio Documentation>Developer Studio Documentation is only available on this menu if you have installed the DesignGuide Developer Studio. It brings up the DesignGuide Developer Studio documentation. Another way to access the Developer Studio documentation is by selecting Help>Topics and Index > DesignGuides>DesignGuide Developer Studio(from any ADS program window). DesignGuide Developer Studio >Start DesignGuide Studio is only available on this menu if you have installed the DesignGuide Developer Studio.It launches the initial Developer Studio dialog box.PLL QuickStart GuideAdd DesignGuide brings up a directory browser in which you can add a DesignGuide to your installation. This is primarily intended for use with DesignGuides that are custom-built through the Developer Studio.List/Remove DesignGuide brings up a list of your installed DesignGuides. Select any that you would like to uninstall and choose the Remove button.Preferences brings up a dialog box that allows you to:•Disable the DesignGuide menu commands (all except Preferences) in the Main window by unchecking this box. In the Schematic and Layout windows, thecomplete DesignGuide menu and all of its commands will be removed if this box is unchecked.•Select your preferred interface method (cascading menus vs. dialog boxes).Close and restart the program for your preference changes to take effect.Note On PC systems, Windows resource issues might limit the use of cascading menus. When multiple windows are open, your system could become destabilized. Thus the dialog box menu style might be best for these situations.Basic ProceduresThe features and content of the PLL DesignGuide are accessible from the DesignGuide menu found in the ADS Schematic window.To access the documentation for the DesignGuide, select either of the following:•DesignGuide >PLL>PLL DesignGuide Documentation(from ADS Schematicwindow)•Help>Topics and Index >DesignGuides>PLL (from any ADS program window) You have the option of selecting a PLL Configuration or choosing to examine one of the various RFIC PLL examples. The RFIC examples are subsets of the various PLL configurations, whereby device level components replace the phase detector and prescalar model components.PLL QuickStart GuideUsing a dialog box of Phase-Locked Loop schematics, you select your desired PLL configuration, as shown here.You select one of the available PLL configurations shown.Having identified the type of PLL structure, you then select one of the three simulations available from the Simulation tab, as shown here. The simulations include•Closed and Open Loop frequency response•Phase Noise response•Transient responseYou then need to identify the phase detector and low-pass filter used in your design. Some combinations are unavailable at this time but are expected to be available in future upgrades.PLL QuickStart GuideThe selection box for phase detectors is shown here.Shown here is the selection box for loop filters. The grayed-out selections are not available at this time. Right- click one of the available selections. For a detailed description of the loop filter selections, refer to the Chapter 2, PLL DesignGuide Reference.Selecting Appropriate ConfigurationsThe Phase-Locked Loop DesignGuide is broken up into different sub-categories, as shown in the previous section. The specifications that you select depend on your desired simulation and the type of PLL structure that your system can utilize.If,for example,you are designing a synthesizer,you can start with the loop frequency response configurations shown in the section“Phase Margin and Unity Gain Bandwidth”on page1-8.The output parameters will be used for evaluating the phase noise and transient responses.Most of the information on the data display for this design simulation and others is in a format that engineers can easily understand. The visibility of equation syntaxes is rmation about items on a data display that you will want to modify is enclosed in red boxes.PLL QuickStart GuidePhase Margin and Unity Gain BandwidthThe optimization procedure based on achieving a desired Phase margin and Unity Gain Bandwidth is shown here. Enter your desired values, as well as your VCO tuning parameter, the divide ratio, and the Phase Detector characteristics. (Enter this data in the area of the schematic encircled in this illustration.)In the data display results shown here, the resultant Phase Margin and Unity Gain Frequency are displayed, along with the optimized loop filter parameters. If the objectives have not been met,you should adjust the loopfilter parameters to alter the initial conditions of the optimization and re-run the simulation.PLL QuickStart GuidePhase Noise ResponseThe parameters derived from the Loop Frequency Response schematic should be entered into the Phase Noise Response schematic.The phase noise characteristics of each component should be set on each subcircuit block. The F and L parameters that describe the noise versus frequency characteristics are depicted in the schematic.The data display corresponding to the Phase Noise schematic is shown here.The graph on the left displays the individual noise source’s contributions and the graph on the right shows the overall noise performance of the PLL.PLL QuickStart GuideTransient Time ResponseShown here is the schematic for evaluating the transient time response of a synthesizer.The loop filter parameters derived from the Loop Frequency response need to be entered into this schematic, along with the VCO and Phase Detector constants. The transient response requires additional parameters such as the Reference Frequency and the stop and delay time, as well as the Divider Ratio step change.The Transient response data display has several figures that will describe the PLL performance as a function of time. From this display, you can evaluate the settling time and use the results to debug the phase-locked loop.PLL QuickStart GuideChapter 2: PLL DesignGuide ReferenceThe sections that follow provide a basic reference on the use of the PLL DesignGuide.Using the PLL DesignGuideThe Phase-Locked Loop (PLL) DesignGuide is integrated into Agilent EEsof’s Advanced Design System environment, working as an interactive handbook for the creation of useful designs.The Guide contains many templates to be used in the ADS software environment. These templates can assist the PLL developer in designing a phase-locked loop to meet performance specifications. You can use the optimization templates to define the loop performance, then proceed to evaluate the phase noise response and transient response. The DesignGuide provides a complete tool kit to interactively explore dynamic PLL systems at the top level as part of an integrated design process.In addition to the requirements of the ADS EEsof software, the PLL DesignGuide requires approximately 10 MB of additional storage space.Note This manual assumes that you are familiar with all of the basic ADS program operations. For additional information, refer to the ADS Schematic Capture and Layout manual.The primary features of the PLL DesignGuide are:•Complete PLL synthesis capability•Frequency synthesizer design•Phase modulator design•Frequency modulator design•Phase demodulator design•Frequency demodulator design•RFIC PLL examples•Open and closed loop frequency response•Phase noise simulationPLL DesignGuide Reference•Time domain transient simulation•Four distinct phase detectors•Seven loop filter configurations•Opamp, VCO, phase detector, reference characterization•Easy modification to user-defined configurationsPLL ConfigurationsFollowing are diagrams and basic descriptions of the PLL configurations included in this DesignGuide. To access these tools, select DesignGuide >PLL DesignGuide > Select PLL Configuration from the ADS Schematic window, and make appropriate selections in the tabs of the dialog box.Frequency Synthesizer (SYN)A block diagram of the basic phase-locked synthesizer is shown in Figure2-1.Figure2-1. Frequency SynthesizerThe voltage controlled oscillator frequency is divided by N and then compared in a phase detector with the reference oscillator. The accuracy and long-term stability of the output frequency are controlled by the reference oscillator. The short-term stability is N times the reference inside the loop bandwidth and that of the VCO outside of the loop bandwidth. This allows a means of generating several highly accurate output frequencies. Frequency selection is performed by changing the divider ratio N.Frequency Modulator (FMD)Frequency modulation of the phase-locked loop is produced by adding a baseband voltage into the VCO tuning terminal along with the output of the loop filter, as shown in Figure2-2.Figure2-2. Frequency ModulationThe loop bandwidth must be smaller than the smallest modulation frequency to avoid linear distortion. The VCO characteristics must be linear to avoid nonlinear distortion of the modulation.PLL DesignGuide ReferenceFrequency Demodulator (FDM)The frequency modulated reference signal is applied to the PLL. For the loop to remain in lock, the VCO frequency must track the incoming frequency, as shown in Figure2-3.Figure2-3. Frequency DemodulatorThe frequency of the VCO is proportional to the tuning voltage.Therefore,the tuning voltage must be a close replica of the modulation of the signal.The recovered signal is equivalent to the original signal filtered by the closed loop transfer function of the PLL.To avoid distortion,the VCO control characteristics must be linear and the loop bandwidth must be large compared to the input modulation.Phase Modulator (PMD)Phase modulation of the phase-locked loop is produced by adding a baseband voltage into the VCO tuning terminal along with the output of the loop filter, as shown in Figure2-4.Figure2-4. Phase ModulatorAnother alternative is to add the phase modulator input before the loop filter, thereby, eliminating the need for the differentiator. The loop bandwidth must be smaller than the smallest modulation frequency to avoid linear distortion. The VCO and phase detector characteristics must be linear to avoid nonlinear distortion of the modulation. Phase modulation of the phase-locked loop is produced by adding a baseband voltage into the VCO tuning terminal along with the output of the loopfilter. Another alternative is to add the phase modulator input before the loop filter, thereby eliminating the need for the differentiator. The loop bandwidth must be smaller than the smallest modulation frequency to avoid linear distortion. The VCO and phase detector characteristics must be linear to avoid nonlinear distortion of the modulation.PLL DesignGuide ReferencePhase Demodulator (PDM)The frequency modulated reference signal is applied to the PLL. For the loop to remain in lock, the VCO frequency must track the incoming frequency, as shown in Figure2-5.Figure2-5. Phase DemodulatorThe frequency of the VCO is proportional to the tuning voltage. Therefore, the integral of the tuning voltage must be a close replica of the phase modulation of the signal. The recovered signal is equivalent to the derivative of the original frequency modulated signal after it has been filtered by the closed loop transfer function of the PLL.To avoid distortion,the VCO control characteristics must be linear and the loop bandwidth must be large compared to the input modulation.Phase DetectorsThis section provides detailed information on the phase detectors used in the PLL DesignGuide.Detector Types•Phase/Frequency Detector•Charge Pumped Detector•Mixer •Exclusive ORPhase/Frequency DetectorThe digital behavior is modelled as a common D flip-flop.Phase correction is provided by pulse width modulation of the output.(2-1)Charge Pumped DetectorThe charge pumped detector is identical to the Phase/Frequency detector except thatthe output is a single-ended current source.(2-2)MixerMixers having wide bandwidths of operation but also have a limited locking rangeand therefore tend to require help during start-up.(2-3)Exclusive ORAn exclusive OR consists of basic logic components. When combined, they obey the Truth Table shown here. They provide only phase-error information.(2-4)d KLogic 1Logic 0–2π---------------------------------------------……V radian --------------------=K d Id 2π------……Amps radian -------------------- =K d MixerGain ……V V ----=K d Logic 1Logic 0–π2-----------------------------------------------……V radian --------------------=PLL DesignGuide ReferenceRFIC PLL ExamplesThis section provides a few examples of RFIC configurations that are used in the PLL DesignGuide.SynthesizersThree RFIC Synthesizer examples are demonstrated•Active 3 Pole PLL configuration using a RFIC MOSFET Phase Frequency Detector •Active 3 Pole PLL configuration using a RFIC MOSFET Charge Pumped Detector •Active 3 Pole PLL configuration using a RFIC MOSFET Prescalar and Phase DetectorPhase DetectorsFour RFIC phase detector configurations are examined:•MOSFET Phase/Frequency Detector •MOSFET Charge Pumped DetectorTable 2-1.Input #1Input #2Output #1Output #2000101101010111XORInput #1Input #2Output #2Output #1•BJT Mixer Detector•BJT Exclusive OR Detector.Each configuration is measured to determine its Phase Detector Sensitivity (amps/radian or volts/radian). Also included are selectable subcircuit components. PrescalarsTwo RFIC prescalar configurations are examined:•MOSFET Divide by 2•BJT Divide by 2Each configuration demonstrates the divider ratio with its transient response. Also included are selectable subcircuit components.PLL DesignGuide ReferenceReferenceThis section provides some useful reference information on the use of the PLL DesignGuide.Template Reference GuideTo access the templates listed here, select DesignGuide >PLL DesignGuide > Select PLL Configuration from the ADS Schematic window, and make appropriate selections in the tabs of the dialog box.Circuit TypesSYN (Synthesizer)FMD (Frequency Modulator)PMD (Phase Modulator)PDM (Phase Demodulator)FDM (Frequency Demodulator)SimulationsFQ (Loop Frequency Response)PN (Phase Noise Response)TN (Transient Time Domain Response)Phase DetectorsPF (Phase/Frequency)CP (Charge Pump)MX (Mixer)XR (Exclusive OR)Loop FiltersP3P (Passive 3-pole PLL integrator)P4P (Passive 4-pole PLL integrator)A2P (Active 2-pole PLL integrator)A2PLG (Active 2-pole PLL integrator for Low Gain Opamps)A3P (Active 3-pole PLL integrator)A3PPF (Active 3-pole PLL integrator with passive pre-filtering)A4PPF (Active 4-pole PLL integrator with passive pre-filtering)Possible Template ConfigurationsFollowing are two possible template configurations. The sections that follow provide more detailed template examples.SYN_CP_FQ_P4PClosed and Open Loop Response of Frequency Synthesizer with charge pump detector and using a 4-pole passive PLL integrator.PMD_PF_TN_A3PPFTransient Response of a Phase Modulator with a Phase/Frequency Detector using an active 3-pole PLL integrator with a pre-filter.Template Example: SYN_CP_FQ_A3PThis example is of a phase-locked loop frequency synthesizer that uses acharge-pumped phase detector and has an active3-pole PLL integrator.The template SYN_CP_FQ_A3P identifies the fact that we are interested in the closed- andopen-loop frequency response. This template also contains an optimization for determining the best resistor and capacitor values in the integrator based on the desired loop bandwidth and phase margin. There are three distinct circuits in this template:•Closed Loop Response•Open Loop Response•Loop Filter ResponseActive 3-Pole IntegratorThe active 3-pole PLL integrator is a second-order filter.This combines with the VCO’s pole to create a 3-pole PLL. The loop bandwidth must be significantly lowerPLL DesignGuide Referencethan the reference frequency to ensure proper sideband suppression. The loop filter consists of two capacitors(Clpf1and Clpf2)as well a resistor(Rlpf1).The operational amplifier used has ideal characteristics.PLL Input ParametersYou need to identify various parameters before simulating.The VCO gain constant or tuning sensitivity parameter is identified as Kv(MHz/volt). The-charge pumped phase detector uses current Id (amps). The divider ratio N0 is the ratio between the VCO center frequency and the reference frequency. The other parameters are the Loop filter component values. The filter parameters are optimized from an initial guess value.Optimization ParametersThe optimization criteria are the desired PLL loop filter bandwidth and the corresponding phase margin. The goals of the optimization process are to vary the loopfilter component values until the loopfilter bandwidth and the phase margin are within the error bounds specified in the Goal item.The frequency range and number of data points for the simulation are set in AC. The type of optimization and considerations are identified in the Nominal Optimization item. The measurement equations assist in the collection and plotting of the data results.Closed Loop ResponseThe closed loop frequency response is simulated based on the optimized loop filter component values.Simulation ResultsThe initial guess values of the loop filter components can be altered if the optimization results do not meet the desired design constraints. Once the Simulate button is chosen, the optimizer begins to adjust the loop filter components to obtain the desired loop filter bandwidth and phase margin. The New Data Display Window button corresponding to the design schematic is then chosen. Open the data set corresponding to the template name. In this example, open SYN_CP_FQ_A3P.dds. The Optimized filter bandwidth and Phase Margin are identified, as well as the corresponding loop filter component values. The plots of the open and closed loop frequency responses are displayed.Template Example: SYN_CP_PN_A3PThis example is of a phase-locked loop frequency synthesizer that uses a charge pumped phase detector and has an active 3-pole PLL integrator. The templateSYN_CP_PN_A3P identifies the fact that we are interested in the phase noise response. The optimized loop filter parameters generated from the frequency response template SYN_CP_FQ_A3P can be used in this template. The PLL parameters and the desired AC frequency sweep range need to be specified. The opamp noise characteristics can be altered to reflect your opamp.PLL ParametersThe PLL parameters consist of the VCO tuning sensitivity Kv (MHz/volt), phase detector current Id (amps), inner loop frequency divider N0, reference frequency divider N0ref (if applicable), and the loop filter components.Simulation Frequency SweepThe sweep range of the AC simulator is set by the start and stop frequency,as well as the grid on the logarithmic plot.Phase Noise CharacteristicsIn modeling the phase noise of the various phase-locked loop components, three distinct frequencies (F3,F2,F1) are defined at which the phase noise characteristics exhibit single sideband slopes of(-30,-20,-10dBc/Hz),respectively.These frequencies (F3,F2,F1) correspond to the phase noise values of (L3,L2,L1), respectively. L0defines the broadband noise floor.Simulation ResultsThe Simulate button is then chosen and once the simulation is complete, the New Data Display Window button corresponding to the design schematic is chosen. The data set corresponds to the template name. In this example, openSYN_CP_PN_A3P.dds. The plot on the left depicts the phase noise contribution versus frequency of the various components of the PLL in the locked state. The plot on the right shows the overall PLL phase noise performance, where we expect to see system phase noise characteristics to track the reference oscillator inside the loop bandwidth, then track the phase noise of the VCO outside the loop bandwidth. The table demonstrates the PLL phase noise at different frequencies.PLL DesignGuide ReferenceTemplate Example: SYN_CP_TN_A3PThis example is of a phase-locked loop frequency synthesizer that uses acharge-pumped phase detector and has an active3-pole PLL integrator.The template SYN_CP_TN_A3P identifies the fact that we are interested in the transient time domain response.The optimized loopfilter parameters generated from the frequency response template SYN_CP_FQ_A3P can be used in this template. The PLL parameters need to be set up. An Envelope Simulation is performed, where the fundamental frequency is that of the reference oscillator.PLL ParametersThe PLL parameters consist of the individual loop filter component resistor and capacitor values. These values are typically derived form the optimized frequency response simulation template. In addition, the parasitic capacitance (C_vco) and resistance (R_vco) can be included in the transient simulation. The PLL parameters are specified VCO tuning sensitivity Kv, initial divider ratio N0, reference frequency Fref, and charge pump maximum current Id. The transient parameters are then specified: the loop divider step change N_Step, the delay time before the step occurs Delay_Time,the step time of the simulation Step_Time, and the stop time of the simulation Stop_Time. The delay time is used to allow the simulation conditions to stabilize before the divider step change occurs. The step time refers to the resolution accuracy of the simulation.The stop time identifies the length of time the simulation results progress, this time should be long enough to observe the step change stabilizing.The initial divider ratio N0needs to be entered in two places:the variable equation and the measurement equation.Simulation SchematicThe individual components of the PLL transient simulation are identified. Note that the reference oscillator is a sawtooth waveform, allowing for better accuracy in the phase detector.Simulation ResultsThe Simulate button is then chosen. Upon completion of the simulation, the New Data Display Window button corresponding to the design schematic is chosen. The data set corresponding to the template name. In this example, openSYN_CP_TN_A3P.dd s. The upper left plot depicts the tuning voltage that controls the VCO. The corresponding VCO frequency tracks the tuning voltage in the lower。
adisimpll锁相环设计过程锁相环（Phase-Locked Loop，PLL）是一种常用于时钟和信号恢复的电子电路。
它可以将输入信号的频率、相位和幅度与参考信号进行比较，然后通过调整其内部振荡器的频率和相位来保持与参考信号的同步。
在现代电子系统中，锁相环已成为许多应用的核心部件，例如通信系统、数据转换和数字信号处理等。
锁相环的设计过程通常包括以下几个主要步骤：1.确定锁相环的规格要求：首先需要确定系统的特定需求，包括输入和输出信号的频率范围、带宽、相位噪声要求以及抖动限制等。
这些规格要求将直接影响锁相环的设计参数和性能。
2.选择合适的锁相环架构：根据系统的特定需求，选择适合的锁相环架构。
常见的锁相环架构包括基于电压控制振荡器（Voltage-Controlled Oscillator，VCO）的基本锁相环、带自由运行振荡器（Free-Running Oscillator）的环-环（Ring-Oscillator）锁相环和数字控制振荡器（Digital-Controlled Oscillator，DCO）的混合锁相环等。
3.设计相位频率检测器：锁相环中的相位频率检测器（Phase-Frequency Detector，PFD）用于比较参考信号和反馈信号的相位和频率差异，并将其转化为控制信号。
常见的PFD电路包括EXOR门和带有多频偏的PFD等。
4.设计环路滤波器：设计环路滤波器用于平稳化锁相环的控制信号。
环路滤波器通常采用低通滤波器结构，能够滤除高频噪声和不稳定性。
5.设计振荡器：根据系统的频率范围和性能要求，设计合适的振荡器。
常见的VCO设计包括压控晶体振荡器（Voltage-Controlled Crystal Oscillator，VCXO）和频率可调振荡器（Voltage-Controlled Oscillator，VCO）。
6.设计控制电路：根据锁相环的设计需求，设计合适的控制电路。
电子英语证书考试(PEC)-集成电路术语解释Acquisition Time (采集时间):与采样A/D相关，在输入端使用跟踪/保持(T/H)放大器来采集和保持(以特定的容差)模拟输入信号。
采集时间是T/H放大器被置于跟踪模式后稳定到其终值所需要的时间。
Active Filter (有源滤波器):有源滤波器采用有源器件(例如运算放大器)来产生滤波器响应。
这种技术在高速应用中具备优势，因为不需要使用电感(高频率特性差)。
ADIsimADC™ (模数转换器(ADC)设计工具):ADIsimADC工具可以帮助用户选择模数转换器(ADC)、执行评估以及排除故障。
它使用典型数据值，通过数学方式模拟所选ADC的一般行为，允许用户施加输入信号、设置编码（采样）速率以及在选定的ADC上仿真FFT。
这款工具对于检查所选ADC的SNR、SFDR、SINAD、THD、ENOB等非常有用。
注意：这款工具不能完全模拟模数转换的各方面特性，不应用来代替实际硬件测试。
下载并使用这款工具的全功能版本，可以发现其它功能。
（更多信息请参考应用笔记AN-737 pdf）Adjacent Channel Leakage Ratio (ACLR) :A ratio in dBc between the measured power within a channel relative to an adjacent channel.Adjacent Channel Power Ratio (ACPR) :See Adjacent Channel Leakage Ratio (ACLR).Aliased Imaging (混叠镜像):这是一种利用故意混叠作为高频信号的技术，通常用于直接数字频率合成器(DDS)。
Aliasing (混叠):在一个数据采样系统中，为了避免损失数据，必须以FS>2FA的速率对模拟输入进行采样(Nyquist定理)。
MT-086TUTORIALFundamentals of Phase Locked Loops (PLLs)FUNDAMENTAL PHASE LOCKED LOOP ARCHITECTUREA phase-locked loop is a feedback system combining a voltage controlled oscillator (VCO) and a phase comparator so connected that the oscillator maintains a constant phase angle relative to a reference signal. Phase-locked loops can be used, for example, to generate stable output high frequency signals from a fixed low-frequency signal.Figure 1A shows the basic model for a PLL. The PLL can be analyzed as a negative feedback system using Laplace Transform theory with a forward gain term, G(s), and a feedback term, H(s), as shown in Figure 1B. The usual equations for a negative feedback system apply.(B) STANDARD NEGATIVE FEEDBACKCONTROL SYSTEM MODEL(A) PLL MODEL ERROR DETECTOR LOOP FILTER VCOFEEDBACK DIVIDER PHASE DETECTOR CHARGEPUMP F O = N F REFFigure 1: Basic Phase Locked Loop (PLL) ModelThe basic blocks of the PLL are the Error Detector (composed of a phase frequency detector and a charge pump ), Loop Filter , VCO , and a Feedback Divider . Negative feedback forces the error signal, e(s), to approach zero at which point the feedback divider output and the reference frequency are in phase and frequency lock, and F O = N FREF .Referring to Figure 1, a system for using a PLL to generate higher frequencies than the input, the VCO oscillates at an angular frequency of ωO . A portion of this signal is fed back to the error detector, via a frequency divider with a ratio 1/N. This divided down frequency is fed to one input of the error detector. The other input in this example is a fixed reference signal. The error detector compares the signals at both inputs. When the two signal inputs are equal in phase and frequency, the error will be constant and the loop is said to be in a “locked” condition.PHASE FREQUENCY DETECTOR (PFD)Figure 2 shows a popular implementation of a Phase Frequency Detector (PFD), basically consisting of two D-type flip flops. One Q output enables a positive current source; and the other Q output enables a negative current source. Assuming that, in this design, the D-type flip flop is positive-edge triggered, the possible states are shown in the logic table.+IN −IN CP (A) OUT OF FREQUENCY LOCK AND PHASE LOCK (B) IN FREQUENCY LOCK, BUTSLIGHTLY OUT OF PHASE LOCK 0+I +I0UP 100DOWN 010CP OUT + I −I 0+IN −IN OUT 0+I −I (C) IN FREQUENCY LOCK AND PHASE LOCKFigure 2: Phase/Frequency Detector (PFD) Driving Charge Pump (CP)Consider now how the circuit behaves if the system is out of lock and the frequency at +IN is much higher than the frequency at –IN, as shown in Figure 2A. Since the frequency at +IN is much higher than that at –IN, the UP output spends most of its time in the high state. The first rising edge on +IN sends the output high and this is maintained until the first rising edge occurs on –IN. In a practical system this means that the output, and thus the input to the VCO, is driven higher, resulting in an increase in frequency at –IN. This is exactly what is desired. If the frequency on +IN were much lower than on –IN, the opposite effect would occur. The output at OUT would spend most of its time in the low condition. This would have the effect of driving the VCO in the negative direction and again bring the frequency at –IN much closer to that at +IN, to approach the locked condition.Figure 2B shows the waveforms when the inputs are frequency-locked and close to phase-lock. Since +IN is leading –IN, the output is a series of positive current pulses. These pulses will tend to drive the VCO so that the –IN signal become phase-aligned with that on +IN. When this occurs, if there were no delay element between U3 and the CLR inputs of U1 and U2, it would be possible for the output to be in high-impedance mode, producing neither positive nor negative current pulses. This would not be a good situation.The VCO would drift until a significant phase error developed and started producing either positive or negative current pulses once again. Over a relatively long period of time, the effect of this cycling would be for the output of the charge pump to be modulated by a signal that is a sub-harmonic of the PFD input reference frequency. Since this could be a low frequency signal, it would not be attenuated by the loop filter and would result in very significant spurs in the VCO output spectrum, a phenomenon known as the "backlash" or "dead zone" effect.The delay element between the output of U3 and the CLR inputs of U1 and U2 ensures that it does not happen. With the delay element, even when the +IN and –IN are perfectly phase-aligned, there will still be a current pulse generated at the charge pump output as shown in Figure 2C. The duration of this delay is equal to the delay inserted at the output of U3 and is known as the anti-backlash pulse width.Note that if the +IN frequency is lower than the −IN frequency and/or the +IN phase lags the −IN phase, then the output of the charge pump will be a series of negative current pulses—the reverse of the condition shown in (A) and (B) in Figure 2.PRESCALERSIn the classical Integer-N synthesizer, the resolution of the output frequency is determined by the reference frequency applied to the phase detector. So, for example, if 200 kHz spacing is required (as in GSM phones), then the reference frequency must be 200 kHz. However, getting a stable 200 kHz frequency source is not easy. A sensible approach is to take a good crystal-based high frequency source and divide it down. For example, the desired frequency spacing could be achieved by starting with a 10 MHz frequency reference and dividing it down by 50. This approach is shown in Figure 3A.(A)(B)REFERENCEDIVIDER÷R REFERENCEDIVIDER÷RPRESCALER÷PFigure 3: Adding an Input Reference Divider and a Prescaler to the Basic PLLThe "N counter," also known as the N divider, is the programmable element that sets the relationship between the input and output frequencies in the PLL. The complexity of the N counter has grown over the years. In addition to a straightforward N counter, it has evolved to include a prescaler, which can have a dual modulus. This structure has grown as a solution to the problems inherent in using the basic divide-by-N structure to feed back to the phase detector when very high-frequency outputs are required. For example, let’s assume that a 900 MHz output is required with 10 Hz spacing. A 10 MHz reference frequency might be used, with the R-Divider set at 1000. Then, the N-value in the feedback would need to be of the order of 90,000. This would mean at least a 17-bit counter capable of dealing with an input frequency of 900 MHz. To handle this range, it makes sense to precede the programmable counter with a fixed counter element to bring the very high input frequency down to a range at which standard CMOS will operate. This counter, called a prescaler, is shown in Figure 3B.However, note that using a standard prescaler as shown reduces the system resolution to F1×P. This issue can be addressed by using a dual-modulus prescaler which has the advantages of a standard prescaler, but without loss of resolution. A dual-modulus prescaler is a counter whose division ratio can be switched from one value to another by an external control signal. It's use is described shown in Figure 4.=, THEREFOREFigure 4: Adding a Dual Modulus Prescaler to the PLLBy using the dual-modulus prescaler with an A and B counter, one can still maintain output resolution of F1. However, the following conditions must be met:1.The output signals of both counters are High if the counters have not timed out.2.When the B counter times out, its output goes Low, and it immediately loads bothcounters to their preset values.3.The value loaded to the B counter must always be greater than that loaded to the Acounter.Assume that the B counter has just timed out and both counters have been reloaded with the values A and B. Let’s find the number of VCO cycles necessary to get to the same state again.As long as the A counter has not timed out, the prescaler is dividing down by P + 1. So, both the A and B counters will count down by 1 every time the prescaler counts (P + 1) VCO cycles. This means the A counter will time out after ((P + 1) × A) VCO cycles.At this point the prescaler is switched to divide-by-P. It is also possible to say that at this time the B counter still has (B – A) cycles to go before it times out. How long will it take to do this: ((B – A) × P).The system is now back to the initial condition where we started.The total number of VCO cycles needed for this to happen is :N = [A × (P + 1)] + [(B – A) × P]= AP + A + BP – AP= BP + A.Therefore, F OUT = (F REF/R) × (BP + A), as in Figure 4.There are many specifications to consider when designing a PLL. The input RF frequency range and the channel spacing determine the value of the R and N counter and the prescaler parameters.The loop bandwidth determines the frequency and phase lock time. Since the PLL is a negative feedback system, phase margin and stability issues must be considered.Spectral purity of the PLL output is specified by the phase noise and the level of the reference-related spurs.Many of these parameters are interactive; for instance, lower values of loop bandwidth lead to reduced levels of phase noise and reference spurs, but at the expense of longer lock times and less phase margin.Because of the many tradeoffs involved, the use of a PLL design program such as the Analog Devices' ADIsimPLL™ allows these tradeoffs to be evaluated and the various parameters adjusted to fit the required specifications. The program not only assists in the theoretical design, but also aids in parts selection and determines component values.OSCILLATOR/PLL PHASE NOISEA PLL is a type of oscillator, and in any oscillator design, frequency stability is of critical importance. We are interested in both long-term and short-term stability. Long-term frequencystability is concerned with how the output signal varies over a long period of time (hours, days, or months). It is usually specified as the ratio, Δf/f for a given period of time, expressed as a percentage or in dB.Short-term stability, on the other hand, is concerned with variations that occur over a period of seconds or less. These variations can be random or periodic. A spectrum analyzer can be used to examine the short-term stability of a signal. Figure 5 shows a typical spectrum, with random and discrete frequency components causing a broad skirt and spurious peaks.o mOUTPUTFREQUENCYFigure 5: Oscillator Phase Noise and SpursThe discrete spurious components could be caused by known clock frequencies in the signal source, power line interference, and mixer products. The broadening caused by random noise fluctuation is due to phase noise. It can be the result of thermal noise, shot noise, and/or flicker noise in active and passive devices.The phase noise spectrum of an oscillator shows the noise power in a 1 Hz bandwidth as a function of frequency. Phase noise is defined as the ratio of the noise in a 1 Hz bandwidth at a specified frequency offset, fm, to the oscillator signal amplitude at frequency f o.It is customary to characterize an oscillator in terms of its single-sideband phase noise as shown in Figure 6, where the phase noise in dBc/Hz is plotted as a function of frequency offset, f m, with the frequency axis on a log scale. Note the actual curve is approximated by a number of regions, each having a slope of 1/f X, where x = 0 corresponds to the "white" phase noise region (slope = 0 dB/decade), and x = 1, corresponds to the "flicker" phase noise region (slope = –20 dB/decade). There are also regions where x = 2, 3, 4, and these regions occur progressively closer to the carrier frequency.PHASE NOISE (dBc/Hz)FREQUENCY OFFSET, f m , (LOG SCALE)f OUTPUTFigure 6: Phase Noise in dBc/Hz Versus Frequency Offset from Output FrequencyNote that the phase noise curve is somewhat analogous to the input voltage noise spectral density of an amplifier. Like amplifier voltage noise, low 1/f corner frequencies are highly desirable in an oscillator.In some cases, it is useful to convert phase noise into time jitter. This can be done by basically integrating the phase noise plot over the desired frequency range. (See Tutorial MT-008, Converting Oscillator Phase Noise to Time Jitter ). The ability to perform this conversion between phase noise and time jitter is especially useful when using the PLL output to drive an ADC sampling clock. Once the time jitter is known, its effect on the overall ADC SNR can be evaluated. The ADIsimPLL™ program (to be discussed shortly) performs the conversion between phase noise and time jitter.FRACTIONAL-N PHASE LOCKED LOOPSFractional-N PLLs have been utilized since the 1970s. As has been discussed, the resolution at the output of an integer-N PLL is limited to steps of the PFD input frequency as shown in Figure 7A, where the PFD input is 0.2 MHz.Fractional-N allows the resolution at the PLL output to be reduced to small fractions of the PFD frequency as shown in Figure 7B, where the PFD input frequency is 1 MHz. It is possible to generate output frequencies with resolutions of 100s of Hz, while maintaining a high PFD frequency. As a result the N-value is significantly less than for integer-N."N" = N INTEGER + N FRACTIONN MODULUS= 900 +N FRACTION5Figure 7: Integer-N Compared to Fractional-N SynthesizerSince noise at the charge pump is multiplied up to the output at a rate of 20logN, significant improvements in phase noise are possible. For a GSM900 system, the fractional-N ADF4252 offers phase noise performance of –103 dBc/Hz, compared with –93 dBc/Hz for the ADF4106 integer-N PLL.Also offering a significant advantage is the lock-time improvement made possible by fractional-N. The PFD frequency set to 20 MHz and loop bandwidth of 150 kHz will allow the synthesizer to jump 30 MHz in less than 30 µs. Current base stations require two PLL blocks to ensure that LOs can meet the timing requirements for transmissions. With the super-fast lock times of fractional-N, future synthesizers will have lock time specs that allow the two “ping-pong” PLLs to be replaced with a single fractional-N PLL block.The downside of fractional-N PLLs is higher spurious levels. A fractional-N divide by 900.2 (See Figure 7B) consists of the N-divider dividing by 900 80% of the time, and by 901 20% of the time. The average division is correct, but the instantaneous division is incorrect. Because of this, the PFD and charge pump are constantly trying to correct for instantaneous phase errors. The heavy digital activity of the sigma-delta modulator, which provides the averaging function, creates spurious components at the output. The digital noise, combined with inaccuracies in matching the hard-working charge pump, results in spurious levels greater than those allowable by most communications standards. Only recently have fractional-N parts, such as the ADF4252, made the necessary improvements in spurious performance to allow designers to consider their use in traditional integer-N markets.SIMPLIFYING PLL DESIGN USING ADIsimPLL™The ADIsimPLL™ software is a complete PLL design package which can be downloaded from the Analog Devices' website. The software has a user-friendly graphical interface, and a complete comprehensive tutorial for first-time users.Traditionally, PLL Synthesizer design relied on published application notes to assist in the design of the PLL loop filter. It was necessary to build prototype circuits to determine key performance parameters such as lock time, phase noise, and reference spurious levels. Optimization was accomplished by "tweaking" component values on the bench and repeating lengthy measurements.ADIsimPLL both streamlines and improves the traditional design process. Starting with the “new PLL wizard,” a designer constructs a PLL by specifying the frequency requirements of the PLL, selecting an integer-N or fractional-N implementation, and then choosing from a library of PLL chips, library or custom VCO, and a loop filter from a range of topologies. The program designs a loop filter and displays key parameters including phase noise, reference spurs, lock time, lock detect performance, and others.ADIsimPLL operates with spreadsheet-like simplicity and interactivity. The full range of design parameters such as loop bandwidth, phase margin, VCO sensitivity, and component values can be altered with real-time updates of the simulation results. This allows the user to easily optimize the design for specific requirements. Varying the bandwidth, for example, enables the user to observe the tradeoff between lock time and phase noise in real-time, and with bench-measurement accuracy.ADIsimPLL includes accurate models for phase noise, enabling reliable prediction of the synthesizer closed-loop phase noise. Users report excellent correlation between simulation and measurement. If required, the designer can work directly at the component level and observe the effects of varying individual component values.The basic design process using ADIsimPLL can be summarized as follows:1.Choose reference frequency, output frequency range, and channel spacing2.Select PLL chip from list3.Select VCO4.Select loop filter configuration5.Select loop filter bandwidth and phase margin6.Run simulation7.Evaluate time and frequency domain results8.OptimizeADIsimPLL works for integer-N or fractional-N PLLs, but does not simulate fractional-N spurs. Phase noise prediction for fractional-N devices assumes the device is operating in the "lowest phase noise" mode.REFERENCES1.Mike Curtin and Paul O'Brien, "Phase-Locked Loops for High-Frequency Receivers and Transmitters"Part 1, Analog Dialogue, 33-3, Analog Devices, 1999Part 2, Analog Dialogue, 33-5, Analog Devices, 1999Part 3, Analog Dialogue, 33-7, Analog Devices, 19992.Roland E. Best, Phase Locked Loops, 5th Edition, McGraw-Hill, 2003, ISBN: 0071412018.3.Floyd M. Gardner, Phaselock Techniques, 2nd Edition, John Wiley, 1979, ISBN: 0471042943.4.Dean Banerjee, PLL Performance, Simulation and Design, 3rd Edition, Dean Banerjee Publications, 2003,ISBN: 0970820712 .5.Bar-Giora Goldberg, Digital Frequency Synthesis Demystified, Newnes, 1999, ISBN: 1878707477.6.Brendan Daly, "Comparing Integer-N and Fractional-N Synthesizers," Microwaves and RF, September2001, pp. 210-215.7.Adrian Fox, "Ask The Applications Engineer-30 (Discussion of PLLs)," Analog Dialogue, 36-3, 2002.8.Hank Zumbahlen, Basic Linear Design, Analog Devices, 2006, ISBN: 0-915550-28-1. Also available asLinear Circuit Design Handbook, Elsevier-Newnes, 2008, ISBN-10: 0750687037, ISBN-13: 978-0750687034. Chapter 4.9.Walt Kester, Analog-Digital Conversion, Analog Devices, 2004, ISBN 0-916550-27-3, Chapter 6. Alsoavailable as The Data Conversion Handbook, Elsevier/Newnes, 2005, ISBN 0-7506-7841-0, Chapter 6.10.Walt Kester, "Converting Oscillator Phase Noise to Time Jitter," Tutorial MT-008, Analog Devices11.Design Tool: ADIsimPLL, Analog Devices, Inc.12.Analog Devices PLL Product Portfolio: /pllCopyright 2009, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of customers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property of their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices Tutorials.。
