quartus ii 中常见warning 及解决方法(转载)（Quartus II中常见警告及解决方法（转载））Support original! I reprinted, you can download free1.Found clock-sensitive, change, during, active, clock, edge, at, time, <time>, on, register, <name>"Reason: vector, source, file, clock sensitive signals (such as data, allowing, clearing, synchronization, loading, etc.) change simultaneously on the edge of the clock. A clock sensitive signal cannot change at the edge of the clock. The consequence is that the result is incorrect.Measures: edit vector source file2.Verilog, HDL, assignment, warning, at, <location>: truncated, value, with, size, <number>, to, match,, size, of, target (<number>Reason: in HDL design, the number of targets is set, such as: reg[4:0] a, and default to 32 bits, the number of digits to the right sizeMeasure: if the result is correct, it needs no correction. If you don't want to see this warning, you can change the number of settings3.All, reachable, assignments, to, data_out (10), assign,'0', register, removed, by, optimizationReason: after the optimizer has been optimized, the output port is no longer functional4.Following 9, pins, have, nothing, GND, or, VCC, driving, datain, port - changes, to, this,, connectivity, may, change, results, fittingReason: ninth feet, empty or grounded or connected to the power supplyMeasures: sometimes the output port is defined, but the output is directly assigned to '0', which will be grounded and assigned '1' to the power supply. If these ports are used in your design, you can ignore these warning5.Found, pins, functioning, as, undefined, clocks, and/or, memory, enablesReason: you have no constraint information as the PIN of the clock. You can set the settings for the corresponding PIN. Mainly refers to some of your pin in the circuit played a role in the clock tube, such as the flip-flop CLK pin, and this pin has no clock constraint, so QuartusII CLK as undefined clock.Measures: if CLK is not a clock, can add "not clock" constraint; if it is, can be added in clock setting; in some of the clock requirements are not very high, you can ignore this warning or modified here: Assignments>Timing analysis settings... Individual clocks > >.....6.Timing, characteristics, of, device, EPM570T144C5, are,preliminaryReason: because MAXII is a relatively new component, the timing in QuartusII is not a formal version. Wait for Service PackMeasure: only affects Quartus's Waveform7.Warning:, Clock, latency, analysis, for, offsets, is, supported, for, the, current, device, family, but, is, PLL, not, enabledMeasure: change the on in setting, Requirements&Option-->More, Timing, Setting-->setting-->Enable, Clock, Latency, timing to OFF8.Found, clock, high, time, violation, at,, NS, on, register, |counter|lpm_counter:count1_rtl_0|dffs[11]"Reason: violated the steup/hold time, should be after the simulation, to see whether the waveform settings and the clock edge in line with steup/hold timeMeasure: adding a register in the middle can solve the problem9.warning:, circuit, may, not, operate.detected,non-operational,, paths, clocked, by, clock, clk44, with, clock,, skew, larger, delay, than, dataReason: clock jitter is greater than data delay, when the clock is very fast, and if and other classes of excessive levels of this problem will occur, but this problem is mostly in thedevice's highest frequency will appear措施：设置-->选项-->需要定时要求和改小一些违约，如改到50mhz10。
