stmf库函数笔记

STM32之FATFS文件系统(SPI方式)笔记BY:T7Date:20171202At:YSU_B307开发环境：uVision : V5.12.0.0 STM32F103V8T6库版本 : STM32F10x_StdPeriph_Lib_V3.5.0FATSF : ff13a工程版本：FATFS_V1 日期：20171130硬件连接：SPI1_CS -> PA4 SPI1_CLK -> PA5 SPI1_MISO -> PA6 SPI1_MOSI -> PA7工程功能：建立在SPI_SD的基础上，完成文件系统的初步接触。

一、FATFS文件系统1.使用开源的FAT文件系统模块，其源代码的获取从官网：目前最新版本是：ff13a2.解压后得到两个文件：其中，documents相当于STM32的固件库使用手册，介绍FATFS系统的函数使用方法，source 中则是需要用到的源代码。

因为FATFS使用SD卡，所以FATFS的基础是SD卡的正常读写，这里采用SPI模式。

二、STM32之SD卡_SPI模式1.硬件连接：SPI1_CS -> PA4 SPI1_CLK -> PA5 SPI1_MISO -> PA6 SPI1_MOSI -> PA72.SPI模式下STM32读写SD卡的工程结构在确定STM32使用SPI模式读写SD卡没有问题后，进入FATSF文件系统的实验，另源代码在文档最后。

三、FATSF文件系统移植1.配置工程环境1)STM32读写SD卡-SPI模式成功2)将解压后的ff13a整个文件夹赋值到工程目录下，如图：3)返回到MDK界面下，添加ff13a项目组,并把ff13a\source\目录下ff.c，diskio.c，ffunicode.c，ffsystem.c添加到项目组中，如下图：4)在Target Options的C++编译器选项中添加文件包含路径，如下图四、为FATSF文件系统添加底层驱动（一）在diskio.c中添加函数代码1.DSTATUS disk_status (BYTE pdrv); 添加完成后如下图2.DSTATUS disk_initialize (BYTE pdrv); 添加完成后如下图3.DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);4.DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);5.DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);6.DWORD get_fattime (void);注意：在diskio.c中 DEV_MMC的宏定义要为0，如下图（二）打开Ffconf.h函数1.改变FF_CODE_PAGE的值如下2.改变FF_USE_LFN的值如下五、Main主函数Main.c函数如下代码：#include "main.h"#define ONE_BLOCK 512#define TWO_BLOCK 1024uint8_t sd_RxBuf[TWO_BLOCK];//SD卡数据j接收缓存区uint8_t sd_TxBuf[TWO_BLOCK] = {0};//SD卡数据j接收缓存区FRESULT res; //读写文件的返回值FIL FileSyatemSrc,FileSystemDst; //文件系统结构体，包含文件指针等成员UINT br,bw; //Fil R/W countBYTE FileRxBuffer[ONE_BLOCK]; //FILE COPY BUFFER//BYTE TxFileBuffer[] = "This is the FATFS System!\r\n";BYTE TxFileBuffer[] = "中文文件系统实验！\r\n";static const char * FR_Table[]={"FR_OK：成功", /* (0) Succeeded */"FR_DISK_ERR：底层硬件错误", /* (1) A hard error occurred in the low level disk I/O layer */"FR_INT_ERR：断言失败", /* (2) Assertion failed */"FR_NOT_READY：物理驱动没有工作", /* (3) The physical drive cannot work */"FR_NO_FILE：文件不存在", /* (4) Could not find the file */"FR_NO_PATH：路径不存在", /* (5) Could not find the path */"FR_INVALID_NAME：无效文件名", /* (6) The path name format is invalid */"FR_DENIED：由于禁止访问或者目录已满访问被拒绝", /* (7) Access denied due to prohibited access or directory full */"FR_EXIST：由于访问被禁止访问被拒绝", /* (8) Access denied due to prohibited access */"FR_INVALID_OBJECT：文件或者目录对象无效", /* (9) The file/directory object is invalid */"FR_WRITE_PROTECTED：物理驱动被写保护", /* (10) The physical drive is write protected */"FR_INVALID_DRIVE：逻辑驱动号无效", /* (11) The logical drive number is invalid */"FR_NOT_ENABLED：卷中无工作区", /* (12) The volume has no work area */"FR_NO_FILESYSTEM：没有有效的FAT卷", /* (13) There is no valid FAT volume */"FR_MKFS_ABORTED：由于参数错误f_mkfs()被终止", /* (14) The f_mkfs() aborted due to any parameter error */"FR_TIMEOUT：在规定的时间无法获得访问卷的许可", /* (15) Could not get a grant to access the volume within defined period */ "FR_LOCKED：由于文件共享策略操作被拒绝", /* (16) The operation is rejected according to the file sharing policy */"FR_NOT_ENOUGH_CORE：无法分配长文件名工作区", /* (17) LFN working buffer could not be allocated */"FR_TOO_MANY_OPEN_FILES：当前打开的文件数大于_FS_SHARE", /* (18) Number of open files > _FS_SHARE */"FR_INVALID_PARAMETER：参数无效" /* (19) Given parameter is invalid */};int main(void){int i = 0;FATFS fs; //记录文件系统盘符信息的结构体LED_Init();USARTx_Init();/* 调用f_mount()创建一个工作区，另一个功能是调用了底层的disk_initialize()函数，进行SDIO借口的初始化 */res = f_mount(&fs, "0:", 1 );if (res != FR_OK){printf("挂载文件系统失败 (%s)\r\n", FR_Table[res]);}else{printf("挂载文件系统成功 (%s)\r\n", FR_Table[res]);}/* 调用f_open()函数在刚刚开辟的工作区的盘符0下打开一个名为Demo.TXT的文件，以创建新文件或写入的方式打开(参数"FA_CREATE_NEW | FA_WRITE"),如果不存在的话则创建这个文件。

《STM32Cube高效开发教程》读书笔记目录一、前言 (2)1.1 书籍简介 (3)1.2 编写目的 (4)二、STM32Cube概述 (5)2.1 STM32Cube的意义 (6)2.2 STM32Cube的主要特点 (7)三、安装与配置 (9)3.1 STM32Cube的安装 (10)3.2 开发环境的配置 (11)四、创建项目 (12)4.1 新建项目 (13)4.2 项目设置 (14)五、HAL库介绍 (15)5.1 HAL库简介 (16)5.2 HAL库的主要组件 (18)六、STM32最小系统 (19)6.1 STM32最小系统的组成 (21)6.2 STM32最小系统的应用 (22)七、GPIO操作 (24)7.1 GPIO的基本概念 (25)7.2 GPIO的操作方法 (26)八、中断系统 (28)8.1 中断的基本概念 (29)8.2 中断的处理过程 (31)九、定时器 (33)9.1 定时器的功能介绍 (34)9.2 定时器的操作方法 (36)十五、文件系统 (37)一、前言随着科技的飞速发展，嵌入式系统已广泛应用于我们生活的方方面面，从智能手机到自动驾驶汽车，其重要性不言而喻。

而STM32作为一款广泛应用的微控制器系列，以其高性能、低功耗和丰富的外设资源赢得了广大开发者的青睐。

为了帮助开发者更好地掌握STM32系列微控制器的开发技巧，提升开发效率，我们特别推出了《STM32Cube 高效开发教程》。

本书以STM32Cube为核心，通过生动的实例和详细的讲解，全面介绍了STM32系列微控制器的开发过程。

无论是初学者还是有一定基础的开发者，都能从中找到适合自己的学习内容。

通过本书的学习，读者将能够更加深入地理解STM32的内部结构和工作原理，掌握其编程方法和调试技巧，从而更加高效地进行嵌入式系统的开发和应用。

在科技日新月异的今天，STM32系列微控制器将继续扮演着举足轻重的角色。

使用STM32F4XX自带数学库“arm使用STM32F4XX自带数学库"arm_math.h"STM32-F4属于Cortex-M4F构架，这与M0、M3的最大不同就是具有FPU（浮点运算单元），支持浮点指令集，因此在处理数学运算时能比M0/M3高出数十倍甚至上百倍的性能，但是要充分发挥FPU的数学性能，除了#include “arm_math.h”（而非用编译器自带的math.h）以外，（arm_math.h位于\Libraries\CMSIS\Include文件夹）还需要进行设置。

1、代码设置如果没有启动FPU而使用数学函数运算时，CPU执行时认为遇到非法指令而跳转到HardFault_Handler()中断函数中死循环。

因此，需要在系统初始化时开启FPU。

在system_stm32f4xx.c中的SystemInit()函数中添加如下代码：/* FPU settings ------------------------------------------------------------*/#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */#endif2、编译控制从上面的代码可以看出，当__FPU_PRESENT=1且__FPU_USED=1时，编译时就加入了启动FPU的代码，CPU也就能正确高效的使用FPU进行简单的加减乘除了。

但是对于复杂运算要充分发挥M4F的浮点功能，就需要使用固件库自带的arm_math.h而非编译器自带的math.h，这个文件根据编译控制项（__FPU_USED ==1）来决定是使用哪一种函数方法：如果没有使用FPU，那就调用keil的标准math.h头文件中定义的函数；如果使用了FPU，那就是用固件库自带的优化函数来解决问题。

stm32f4 自然对数自然对数是数学中的一个重要概念，它在数学和工程领域中有着广泛的应用。

在本文中，我们将探讨一下stm32f4中自然对数的一些相关知识。

让我们来了解一下自然对数的定义。

自然对数以常数e为底，它是一个无理数，约等于 2.71828。

自然对数的定义可以用以下公式表示：ln(x) = loge(x)，其中ln表示自然对数，e表示常数，x表示一个正实数。

在stm32f4中，我们可以利用数学库函数来计算自然对数。

通过使用这些函数，我们可以方便地计算任意正实数的自然对数。

不过，在编程中，我们需要注意一些细节。

首先，我们需要在代码中包含适当的头文件，以便使用数学库函数。

其次，我们需要提供一个合适的变量来存储计算结果。

最后，在使用自然对数函数之前，我们需要确保输入的参数是一个正实数，否则函数可能会返回错误的结果。

在stm32f4中，我们可以使用log函数来计算自然对数。

该函数的原型如下：float log(float x)，其中x表示一个正实数。

该函数返回x 的自然对数。

下面我们来看一个例子，展示如何在stm32f4中计算自然对数。

```c#include <math.h>int main() {float x = 2.71828; // 输入一个正实数float result = log(x); // 计算自然对数// 打印结果printf("ln(%f) = %f", x, result);return 0;}```在上面的例子中，我们输入了一个正实数2.71828，并使用log函数计算了它的自然对数。

最后，我们将结果打印出来。

当我们运行这段代码时，输出结果应该是ln(2.71828) = 1.00000。

通过上面的例子，我们可以看到，在stm32f4中计算自然对数是非常简单的。

只需要使用合适的数学库函数，我们就可以方便地进行计算。

这对于许多工程和科学应用来说是非常有用的。

STM32F20xxx_21xxx单⽚机硬件开发⼊门笔记AN3320Application noteGetting started with STM32F20xxx/21xxx MCUhardware developmentIntroductionThis application note is intended for system designers who require a hardwareimplementation overview of the development board features such as the power supply, theclock management, the reset control, the boot mode settings and the debug management. It shows how to use the high-density performance line STM32F20xxx/21xxx product familiesand describes the minimum hardware resources required to develop anSTM32F20xxx/21xxx application.Detailed reference design schematics are also contained in this document with descriptionsof the main components, interfaces and modes.August 2011Doc ID 18267 Rev 21/29/doc/20ec15b314791711cd7917a6.htmlContents AN3320Contents1Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.1.1Independent A/D converter supply and reference voltage . . . . . . . . . . . . 71.1.2Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.1.3Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.2Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.3Reset & power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.3.1Power on reset (POR) / power down reset (PDR) . . . . . . . . . . . . . . . . . . 91.3.2Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 101.3.3System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.1HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.1.1External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.1.2External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 132.2LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.2.1External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.2.2External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 142.3Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.1Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.2Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.3Embedded boot loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.2SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 184.3Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.3.1SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.3.2Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.3.3Internal pull-up and pull-down resistors on JT AG pins . . . . . . . . . . . . . . 194.3.4SWJ debug port connection with standard JTAG connector . . . . . . . . . 20 2/29 Doc ID 18267 Rev 2AN3320Contents5Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.1Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.2Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.3Ground and power supply (V SS, V DD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.4Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.5Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.6Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1.1Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1.2Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1.3Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1.4SWJ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1.5Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.2Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Doc ID 18267 Rev 23/29List of tables AN3320 List of tablesTable 1.Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 2.Debug port pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 3.SWJ I/O pin availability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 4.Mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 5.Optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 6.Reference connection for all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 7.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4/29 Doc ID 18267 Rev 2AN3320List of figures List of figuresFigure 1.Power supply overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2.Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3.Power-on reset/power-down reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4.PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5.Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6.HSE external clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7.HSE crystal/ceramic resonators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 8.LSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 9.LSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10.Boot mode selection implementation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 11.Host-to-board connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12.JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 13.Typical layout for V DD/V SS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 14.STM32F207IG(H6) microcontroller reference schematic. . . . . . . . . . . . . . . . . . . . . . . . . . 25Doc ID 18267 Rev 25/29Power supplies AN33206/29 Doc ID 18267 Rev 21 Power supplies1.1 IntroductionThe device requires a 1.8V to 3.6V operating voltage supply (V DD ), excepted the WLCSPpackage witch requires 1.65V to 3.6V. An embedded regulator is used to supply the internal 1.2V digital power.The real-time clock (RTC) and backup registers can be powered from the V BAT voltage when the main V DD supply is powered off.1.V DDA and V SSA must be connected to V DD and V SS , respectively.2.The voltage on V REF ranges from 1.65V to V DDA for WLCSP64+2 packages.AN3320Power suppliesDoc ID 18267 Rev 27/291.1.1 Independent A/D converter supply and reference voltageTo improve conversion accuracy, the ADC has an independent power supply that can be filtered separately, and shielded from noise on the PCB.●the ADC voltage supply input is available on a separate V DDA pin ●an isolated supply ground connection is provided on the V SSA pinWhen available (depending on package), V REF– must be tied to V SSA .On 100-pin package and above and on WLCSP64+2To ensure a better accuracy on low-voltage inputs, the user can connect a separate external reference voltage ADC input on V REF+. The voltage on V REF+ may range from 1.8V to V DDA . On WLCSP64+2, the V REF- pin is not available, it is internally connected to the ADC ground (V SSA ).On 64-pin packagesThe V REF+ and V REF- pins are not available, they are internally connected to the ADC voltage supply (V DDA ) and ground (V SSA ).1.1.2 Battery backupTo retain the content of the Backup registers when V DD is turned off, the V BAT pin can beconnected to an optional standby voltage supplied by a battery or another source.The V BAT pin also powers the RTC unit, allowing the RTC to operate even when the main digital supply (V DD ) is turned off. The switch to the V BAT supply is controlled by the power down reset (PDR) circuitry embedded in the Reset block.If no external battery is used in the application, it is highly recommended to connect V BAT externally to V DD .1.1.3 Voltage regulatorThe voltage regulator is always enabled after reset. It works in three different modesdepending on the application modes.●in Run mode, the regulator supplies full power to the 1.2V domain (core, memories and digital peripherals)●in Stop mode, the regulator supplies low power to the 1.2V domain, preserving the contents of the registers and SRAM●in Standby mode, the regulator is powered down. The contents of the registers and SRAM are lost except for those concerned with the Standby circuitry and the Backup domain.Note:Depending on the selected package, there are specific pins that should be connected either to V SS or V DD to activate or deactivate the voltage regulator. Refer to section "Voltage regulator" in STM32F20xxx/21xxx datasheet for details .Power supplies AN33208/29 Doc ID 18267 Rev 21.2 Power supply schemesThe circuit is powered by a stabilized power supply, V DD .●Caution:–The V DD voltage range is 1.8V to 3.6V (and 1.65V to 3.6V for WLCSP64+2 package)●The V DD pins must be connected to V DD with external decoupling capacitors: one single T antalum or Ceramic capacitor (min. 4.7µF typ.10µF) for the package + one 100nF Ceramic capacitor for each V DD pin.●The V BAT pin can be connected to the external battery (1.65V < V BA T < 3.6V). If no external battery is used, it is recommended to connect this pin to V DD with a 100nF external ceramic decoupling capacitor.●The V DDA pin must be connected to two external decoupling capacitors (100nF Ceramic + 1µF Tantalum or Ceramic).●The V REF+ pin can be connected to the V DDA external power supply. If a separate, external reference voltage is applied on V REF+, a 100nF and a 1µF capacitors must be connected on this pin. In all cases, V REF+ must be kept between 1.65V and V DDA .●Additional precautions can be taken to filter analog noise:–V DDA can be connected to V DD through a ferrite bead.–The V REF+ pin can be connected to V DDA through a resistor (typ. 47Ω).●For the voltage regulator configuration, there are specific pins (REGOFF and IRROFF depending on the package) that should be connected either to VSS or VDD to activate or deactivate the voltage regulator specific. Refer to section "Voltage regulator" in STM32F20xxx/21xxx datasheet for details .●When the voltage regulator is enabled, V CAP1 and V CAP2 pins must be connected to 2*2.2µF Ceramic capacitor.AN3320Power suppliesDoc ID 18267 Rev 29/291.Optional. If a separate, external reference voltage is connected on V REF+, the two capacitors (100 nF and1µF) must be connected.2.V REF + is either connected to V REF or to V DDA .3.N is the number of V DD and V SS inputs.4.Refer to section "Voltage regulator" in STM32F20xxx/21xxx datasheet to connect REGOFF and IRROFFpins.1.3Reset & power supply supervisor1.3.1Power on reset (POR) / power down reset (PDR)The device has an integrated POR/PDR circuitry that allows proper operation starting from 1.8V .The device remains in the Reset mode as long as V DD is below a specified threshold, V POR/PDR , without the need for an external reset circuit. For more details concerning the power on/power down reset threshold, refer to the electrical characteristics in STM32F20xxx/21xxx datasheets.On WLCSP66 package if IRROFF pin is set to V DD (in that case REGOFF pin must not be activated, refer to section "Voltage regulator" in STM32F20xxx/21xxx datasheet for details ), the PDR is not functional. Then the V DD can lower below 1.8V , but the external circuitry must ensure that reset pin is activated when V DD /V DDA becomes below 1.65V .Power suppliesAN332010/29 Doc ID 18267 Rev 21.t RSTTEMPO is approximately2.6ms. V POR/PDR rising edge is 1.74V (typ.) and V POR/PDR falling edge is1.70V (typ.). Refer to STM32F20xxx/21xxx datasheets for actual value.1.3.2 Programmable voltage detector (PVD)Y ou can use the PVD to monitor the V DD power supply by comparing it to a thresholdselected by the PLS[2:0] bits in the Power control register (PWR_CR).The PVD is enabled by setting the PVDE bit.A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicatewhether V DD is higher or lower than the PVD threshold. This event is internally connected to EXTI Line16 and can generatean interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when V DD drops below the PVD threshold and/or when VDD rises above the PVD threshold depending on the EXTI Line16 rising/falling edge configuration. As an example the service routine can perform emergency shutdown tasks.AN3320Power suppliesDoc ID 18267 Rev 211/291.3.3 System resetA system reset sets all registers to their reset values except for the reset flags in the clockcontroller CSR register and the registers in the Backup domain (see Figure 1).A system reset is generated when one of the following events occurs:1. A low level on the NRST pin (external reset)2. window watchdog end-of-count condition (WWDG reset)3. Independent watchdog end-of-count condition (IWDG reset)4. A software reset (SW reset)5.Low-power management resetThe reset source can be identified by checking the reset flags in the Control/Status register, RCC_CSR.The STM32F20xxx/21xxx does not require an external reset circuit to power-up correctly. Only a pull-down capacitor is recommended to improve EMS performance by protecting the device against parasitic resets. See Figure 5.Charging and discharging a pull-down capacitor through an internal resistor increases the device power consumption. The capacitor recommended value (100nF) can be reduced to 10nF to limit this power consumption;Clocks AN332012/29 Doc ID 18267 Rev 22 ClocksThree different clock sources can be used to drive the system clock (SYSCLK):●HSI oscillator clock (high-speed internal clock signal)●HSE oscillator clock (high-speed external clock signal)●PLL clockThe devices have two secondary clock sources:●32kHz low-speed internal RC (LSI RC) that drives the independent watchdog and, optionally, the RTC used for Auto-wakeup from the Stop/Standby modes.●32.768kHz low-speed external crystal (LSE crystal) that optionally drives the real-time clock (RTCCLK)Each clock source can be switched on or off independently when it is not used, to optimize the power consumption.Refer to the STM32F20xxx/21xxx reference manual RM0033 for the description of the clock tree.2.1 HSE OSC clockThe high-speed external clock signal (HSE) can be generated from two possible clock sources:●HSE external crystal/ceramic resonator (see Figure 7)●HSE user external clock (see Figure 6)1.The value of R EXT depends on the crystal characteristics. Typical value is in the range of 5 to 6 R S(resonator series resistance).2.Load capacitance C L has the following formula: C L = C L1 x C L2 / (C L1 + C L2) + C stray where: C stray is the pincapacitance and board or trace PCB-related capacitance. Typically, it is between 2pF and 7pF. Please refer to Section 5: Recommendations on page 21 to minimize its value.Figure 6.HSE external clockFigure 7.HSE crystal/ceramicAN3320ClocksDoc ID 18267 Rev 213/292.1.1 External source (HSE bypass)In this mode, an external clock source must be provided. It can have a frequency from 1 to 16MHz (refer toSTM32F20xxx/21xxx datasheets for actual max value).The external clock signal (square, sine or triangle) with a duty cycle of about 50%, has to drive the OSC_IN pin while the OSC_OUT pin must be left in the high impedance state (see Figure 7 and Figure 6).2.1.2 External crystal/ceramic resonator (HSE crystal)The external oscillator frequency ranges from 4 to 26MHz.The external oscillator has the advantage of producing a very accurate rate on the mainclock. The associated hardware configuration is shown in Figure 7. Using a 25MHz oscillator frequency is a good choice to get accurate Ethernet, USB OTG high-speed peripheral, and I 2S.The resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The load capacitance values must be adjusted according to the selected oscillator.For C L1 and C L2 it is recommended to use high-quality ceramic capacitors in the 5pF-to-25pF range (typ.), designed for high-frequency applications and selected to meet the requirements of the crystal or resonator. C L1 and C L2, are usually the same value. Thecrystal manufacturer typically specifies a load capacitance that is the series combination of C L1 and C L2. The PCB andMCU pin capacitances must be included when sizing C L1 and C L2 (10 pF can be used as a rough estimate of the combined pin and board capacitance).Refer to the electrical characteristics sections in the datasheet of your product for more details.Clocks AN332014/29 Doc ID 18267 Rev 22.2 LSE OSC clockThe low-speed external clock signal (LSE) can be generated from two possible clocksources:●LSE external crystal/ceramic resonator (see Figure 9)●LSE user external clock (see Figure 8)1.“LSE crystal/ceramic resonators” figure:To avoid exceeding the maximum value of C L1 and C L2 (15pF) it is strongly recommended to use a resonator with a load capacitance C L ≤7pF. Never use a resonator with a load capacitance of 12.5pF.2.“LSE external clock” and “LSEcrystal/ceramic resonators” figures:OSC32_IN and OSC32_OUT pins can be used also as GPIO, but it is recommended not to use them as both RTC and GPIO pins in the same application.3.“LSE crystal/ceramic resonators” figure:The value of R EXT depends on the crystal characteristics. A 0Ω resistor would work but would not be optimal. To fine tube R S value, refer to AN2867 - Oscillator design guide for ST microcontrollers.2.2.1 External source (LSE bypass)In this mode, an external clock source must be provided. It can have a frequency of up to 1MHz. The external clock signal (square, sine or triangle) with a duty cycle of about 50% has to drive the OSC32_IN pin while the OSC32_OUT pin must be left high impedance (see Figure 8).2.2.2 External crystal/ceramic resonator (LSE crystal)The LSE crystal is a 32.768kHz low-speed external crystal or ceramic resonator. It has theadvantage of providing a low-power, but highly accurate clock source to the real-time clock peripheral (RTC) forclock/calendar or other timing functions.The resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The load capacitance values must be adjusted according to the selected oscillator.Figure 8.LSE external clockFigure 9.LSE crystal/ceramicAN3320ClocksDoc ID 18267 Rev 215/292.3 Clock security system (CSS)The clock security system can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.●If a failure is detected on the HSE oscillator clock, the oscillator is automaticallydisabled. A clock failure event is sent to the break input of the TIM1 advanced control timer and an interrupt is generated to inform the software about the failure (clocksecurity system interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex?-M3 NMI (non-maskable interrupt) exception vector.●If the HSE oscillator is used directly or indirectly as the system clock (indirectly means that it is used as the PLL input clock, and the PLL clock is used as the system clock), a detected failure causes a switch of the system clock to the HSI oscillator and thedisabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too.For details, see the STM32F20xxx/21xxx (RM0033) reference manuals available from the STMicroelectronics website /doc/20ec15b314791711cd7917a6.html .Boot configuration AN332016/29 Doc ID 18267 Rev 23 Boot configuration3.1 Boot mode selectionIn the STM32F20xxx/21xxx, three different boot modes can be selected by means of theBOOT[1:0] pins as shown in Table 1.The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set the BOOT1 and BOOT0 pins after reset to select the required boot mode.The BOOT pins are also resampled when exiting the Standby mode. Consequently, they must be kept in the required Boot mode configuration in the Standby mode. After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, and starts code execution from the boot memory starting from 0x0000 0004.3.2 Boot pin connectionFigure 10 shows the external connection required to select the boot memory of the STM32F20xxx/21xxx.1.Resistor values are given only as a typical example.Table 1.Boot modesBOOT mode selection pinsBoot mode AliasingBOOT1BOOT0x 0Main Flash memory Main Flash memory is selected as boot space01System memory System memory is selected as boot space11Embedded SRAMEmbedded SRAM is selected as boot spaceAN3320Boot configuration3.3 Embedded boot loader modeThe Embedded boot loader mode is used to reprogram the Flash memory using one of theavailable serial USART1(PA9/PA10), USART3(PB10/11 & PC10/11), CAN2(PB5/13) or USBOTG FS(PA11/12) in Device mode (DFU: device firmware upgrade).The USART peripheral operates with the internal 16MHz oscillator (HSI). The CAN andUSB OTG FS, however, can only function if an external clock (HSE) multiple of 1 MHz(between 4 and 26 MHz)is present.This embedded boot loader is located in the System memory and is programmed by STduring production.For additional information, refer to AN2606.Doc ID 18267 Rev 217/29Debug management AN332018/29 Doc ID 18267 Rev 24 Debug management4.1 IntroductionThe Host/Target interface is the hardware equipment that connects the host to theapplication board. This interface is made of three components: a hardware debug tool, a JTAG or SW connector and a cable connecting the host to the debug tool.Figure 11 shows the connection of the host to the evaluation board STM3220G-EVAL.Figure 11.Host-to-board connection 4.2 SWJ debug port (serial wire and JTAG)The STM32F20xxx/21xxx core integrates the serial wire / JT AG debug port (SWJ-DP). It is an ARM? standard CoreSight? debug port that combines a JTAG-DP (5-pin) interface and a SW-DP (2-pin) interface.●The JTAG debug port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-AP port●The serial wire debug port (SW-DP) provides a 2-pin (clock + data) interface to the AHP-AP portIn the SWJ-DP , the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG pins of the JTAG-DP .4.3 Pinout and debug port pinsThe STM32F20xxx/21xxx MCU is offered in various packages with different numbers of available pins. As a result, some functionality related to the pin availability may differ from one package to another.4.3.1 SWJ debug port pinsFive pins are used as outputs for the SWJ-DP as alternate functions of general-purpose I/Os (GPIOs). These pins, shown in Table 2, are available on all packages.%VALUATION BOARD(OST 0#0OWER SUPPLY*4!' 37 CONNECTOR$EBUG TOOLAI BAN3320Debug managementDoc ID 18267 Rev 219/294.3.2 Flexible SWJ-DP pin assignmentAfter reset (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as dedicated pins immediately usable by the debugger host (note that the trace outputs are not assigned except if explicitly programmed by the debugger host).However, some of the JTAG pins shown in Table 3 can be configured to an alternate function through the GPIOx_AFRx registers.Table 3 shows the different possibilities to release some pins.For more details, see the STM32F20xxx/21xxx (RM0033) reference manual, available from the STMicroelectronics website /doc/20ec15b314791711cd7917a6.html .4.3.3 Internal pull-up and pull-down resistors on JTAG pinsThe JTAG input pins must not be floating since they are directly connected to flip-flops to control the debug mode features. Special care must be taken with the SWCLK/TCK pin that is directly connected to the clock of some of these flip-flops. Table 2.Debug port pin assignmentSWJ-DP pin nameJTAG debug portSW debug portPinassignment TypeDescription Type Debug assignment JTMS/SWDIO I JTAG test mode selection I/O Serial wire data input/output PA13JTCK/SWCLK I JTAG test clock I Serial wire clock P A14JTDII JTAG test data input --P A15JTDO/TRACESWO O JTAG test data output -TRACESWO if async traceis enabled PB3JNTRSTIJTAG test nReset。

第一：软件的安装：第二：阅读《STM32F4开发指南-寄存器版本_V1.1》的第三章主要是MDK的使用技巧。

第三：新建项目工程和下载：寄存器的就先参考我提供的例程，后面讲述库函数的时候咱们再从官方提供的库文件里面去拷贝。

1.新建文件夹STM32_Demo，在这个文件夹里面新建3个文件夹：USER，SYSTEM，HARDWAR。

USER：用来保存工程文件；SYSTEM：用来存放一些官方提供的一些内核文件，以及一些常用的模块文件；HARDWARE：存放和硬件相关的模块文件；2.从我提供的程序代码里面拷贝文件到上面新建的文件夹里面；从1.STM32F4_LED工程文件里面拷贝资料文件到上面新建的文件夹里面：把1.STM32F4_LED--->SYSTEM拷贝到STM32_Demo---->SYSTEM；把1.STM32F4_LED--->HARDWAR拷贝到STM32_Demo---->HARDWARE；把1.STM32F4_LED--->USER--->main.c拷贝到STM32_Demo---->USER里面；3.新建项目工程：新建工程文件并保存到USAR里面；选择芯片如下：STM32F407ZG把文件里面的.c和.s文件添加到项目工程，可以先对其进行分组；最终出现的效果如下（组的名称随意命名）：在文件里面还有很多.h文件，咱们要在工程里面知名路径；编译会出现问题，咱们需要添加1个宏定义；STM32F40_41xxx这样编译就没有问题了。

先让ST-Link和STM32开发板连接，并连接到计算机；咱们需要使用ST-Link下载，所以要配置如下：点击上图中“Settings”，进入如下界面：下载工程文件到STM32开发板：配置注意的几点：第四：项目工程的分析：USER：main.c；HARDWARE：led.c和led.h；相关LED灯的操作文件；SYSTEM：sys文件夹：startup_stm32f40_41xxx.s：官方提供的启动代码文件；stm32f4xx.h：官方提供的STM32F4系列芯片的头文件，类似reg51.h。

STM32F4 DSP库学习笔记5-复数FFT的实现方法我们会用了ST官方的汇编FFT库，那些库函数在没有带FPU浮点运算的32芯片上也可以用的不错。

然后今天我们就用一下F4的DSP库。

在该目录下包含了图中所示的源文件复数FFT函数支持三种数据类型，分别是浮点，Q31和Q15，待会就拿浮点数来做例子。

先介绍下函数：void arm_cfft_f32(const arm_cfft_instance_f32 * S,float32_t * p1,uint8_t ifftFlag,uint8_t bitReverseFlag);arm_cfft_instance_f32 * S是一个结构体指针这个结构体包含FFT运算的旋转因子和位反转表，就相当于一个常量，我们不用去管它。

float32_t * p1，是输入复数数组的地址，长度应该是运算点数的两倍，注意的是输入和输出共用一块缓存uint8_t ifftFlag,是运算的正反标志ifftFlag=1是反变换。

ifftFlag=0是正变换uint8_t bitReverseFlag，是flag that enables (bitReverseFlag=1) or disables (bitReverseFlag =0) bit好，然后就只要这一句话就可以计算复数的FFT正变换arm_cfft_f32(&arm_cfft_sR_f32_len1024,testInput,0, 1);计算出结果后，用下面语句就可以求出幅值了；arm_cmplx_mag_f32(testInput, testOutput, 1024);关于arm_cmplx_mag_f32(testInput, testOutput, 1024)，它的原型是：void arm_cmplx_mag_f32(float32_t * pSrc,float32_t * pDst,uint32_t numSamples);这个函数是求复数的模值float32_t * pSrc,是输入数组地址float32_t * pDst,是输出数组地址uint32_t numSamples是运算点数当然上面语句中testInput数组的长度是testOutput数组的两倍。

BiLSTM-CRF学习笔记（原理和理解）维特⽐BiLSTM-CRF 被提出⽤于NER或者词性标注，效果⽐单纯的CRF或者lstm或者bilstm效果都要好。

根据pytorch官⽅指南()，实现了BiLSTM-CRF⼀个toy级别的源码。

下⾯是我个⼈的学习理解过程。

1. LSTMLSTM的原理前⼈已经解释的⾮常清楚了：BiLSTM-CRF中，BiLSTM部分主要⽤于，根据⼀个单词的上下⽂，给出当前单词对应标签的概率分布，可以把BiLSTM看成⼀个编码层。

⽐如，对于标签集{N, V, O}和单词China，BiLSTM可能输出形如(0.88,-1.23,0.03)的⾮归⼀化概率分布。

这个分布我们看作是crf的特征分布输⼊，那么在CRF中我们需要学习的就是特征转移概率。

2. CRF主要讲⼀下代码中要⽤到的CRF的预测（维特⽐解码）维特⽐算法流程:1.求出位置1的各个标记的⾮规范化概率δ1(j)δ1(j)δ1(j)=w∗F1(y0=START,yi=j,x),j=1,2,…,mδ1(j)=w∗F1(y0=START,yi=j,x),j=1,2,…,m2.由递推公式（前后向概率计算）δi(l)=max(1≤j≤m){δi−1(j)+w∗Fi(yi−1=j,yi=l,x)},l=1,2,…,lδi(l)=max(1≤j≤m){δi−1(j)+w∗Fi(yi−1=j,yi=l,x)},l=1,2,…,l每⼀步都保留当前所有可能的状态ll 对应的最⼤的⾮规范化概率，并将最⼤⾮规范化概率状态对应的路径（当前状态得到最⼤概率时上⼀步的状态yiyi）记录Ψi(l)=argmax(1≤j≤m){δi−1(j)+w∗Fi(yi−1=j,yi=l,x)}=argmaxδi(l),l=1,2,…,mΨi(l)=arg m ax(1≤j≤m){δi−1(j)+w∗Fi(yi−1=j,yi=l,x)}=argmaxδi(l),l=1,2,…,m就是PijPij的取值有m*m个，对每⼀个yjyj，都确定⼀个（⽽不是可能的m个）能最⼤化概率的yiyi状态3.递推到i=ni=n时终⽌这时候求得⾮规范化概率的最⼤值为maxy{w∗F(y,x)}=max(1≤j≤m)δn(j)=max(1≤j≤m){δn−1(j)+w∗Fn(yn−1=Ψn−1(k),yi=l,x)},l=1,2,…,mmaxy{w∗F(y,x)}=max(1≤j≤m)δn(j)=max(1≤j≤m) {δn−1(j)+w∗Fn(yn−1=Ψn−1(k),yi=l,x)},l=1,2,…,m最优路径终点y∗n=argmax(1≤j≤m)δn(j)yn∗=arg m ax(1≤j≤m)δn(j)4.递归路径由最优路径终点递归得到的最优路径（由当前最⼤概率状态状态对应的上⼀步状态，然后递归）y∗i=Ψi+1(y∗i+1),i=n−1,n−2,…,1yi∗=Ψi+1(yi+1∗),i=n−1,n−2,…,1求得最优路径：y∗=(y∗1,y∗2,…,y∗n)Ty∗=(y1∗,y2∗,…,yn∗)T3. 损失函数最后由CRF输出，损失函数的形式主要由CRF给出在BiLSTM-CRF中，给定输⼊序列X，⽹络输出对应的标注序列y，得分为S(X,y)=∑ni=0Ayi,yi+1+∑ni=1Pi,yiS(X,y)=∑i=0nAyi,yi+1+∑i=1nPi,yi（转移概率和状态概率之和）利⽤softmax函数，我们为每⼀个正确的tag序列y定义⼀个概率值p(y│X)=eS(X,y)∑y'∈YXeS(X,y')p(y│X)=eS(X,y)∑y′∈YXeS(X,y′)在训练中，我们的⽬标就是最⼤化概率p(y│X) ，怎么最⼤化呢，⽤对数似然（因为p(y│X)中存在指数和除法，对数似然可以化简这些运算）对数似然形式如下：log(p(y│X)=loges(X,y)∑y∈YXes(X,y′)=S(X,y)−log(∑y′∈YXes(X,y′))log(p(y│X)=log e s(X,y)∑y∈YXes(X,y′)=S(X,y)−log(∑y′∈YXes(X,y′))最⼤化这个对数似然，就是最⼩化他的相反数：￥−log(p(y│X))=log(∑y′∈YXes(X,y′))−S(X,y)−log(p(y│X))=log(∑y′∈YXes(X,y′))−S(X,y)$(loss function/object function)最⼩化可以借助梯度下降实现在对损失函数进⾏计算的时候，前⼀项S(X,y)S(X,y)很容易计算，后⼀项log(∑y′∈YXes(X,y′))log(∑y′∈YXes(X,y′))⽐较复杂，计算过程中由于指数较⼤常常会出现上溢或者下溢，由公式 log∑e(xi)=a+log∑e(xi−a)log∑e(xi)=a+log∑e(xi−a)，可以借助a对指数进⾏放缩，通常a取xixi的最⼤值（即a=max[Xi]a=max[Xi]），这可以保证指数最⼤不会超过0，于是你就不会上溢出。

STM32F103学习笔记（五）外部中断首先是外部中断基本的概念：STM32 的每个IO 都可以作为外部中断的中断输入口，这点也是STM32 的强大之处。

STM32F103 的中断控制器支持19 个外部中断/事件请求。

每个中断设有状态位，每个中断/事件都有独立的触发和屏蔽设置。

STM32F103 的19 个外部中断为：线0~15：对应外部IO 口的输入中断。

线16：连接到PVD 输出。

线17：连接到RTC 闹钟事件。

线18：连接到USB 唤醒事件。

线16~18还没有学到只看了线0~15。

每个中断线对应着7个GPIO口，形成映射关系，以线0 为例：它对应了GPIOA.0、GPIOB.0、GPIOC.0、GPIOD.0、GPIOE.0、GPIOF.0、GPIOG.0。

而中断线每次只能连接到1 个IO 口上，这样就需要通过配置来决定对应的中断线配置到哪个GPIO 上了。

下面我们看看GPIO 跟中断线的映射关系图：根据映射关系，就开始配置按键对应GPIO口和中断的映射了：[csharp] view plain copy &lt;pre name="code" class="csharp"&gt;&lt;prename="code" class="html"&gt;void EXTIX_Init(void){ EXTI_InitTypeDef EXTI_InitStructure;NVIC_InitTypeDef NVIC_InitStructure; KEY_Init(); // 按键端口初始化RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO,EN ABLE); //使能复用功能时钟//GPIOE.2 中断线以及中断初始化配置下降沿触发GPIO_EXTILineConfig(GPIO_PortSourceGPIOE,GPIO_Pi nSource2);EXTI_InitStructure.EXTI_Line=EXTI_Line2; //KEY2 EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;EXTI_InitStructure.EXTI_LineCmd = ENABLE;EXTI_Init(&amp;EXTI_InitStructure); //根据EXTI_InitStruct中指定的参数初始化外设EXTI寄存器//GPIOE.3 中断线以及中断初始化配置下降沿触发//KEY1GPIO_EXTILineConfig(GPIO_PortSourceGPIOE,GPIO_Pi nSource3);EXTI_InitStructure.EXTI_Line=EXTI_Line3;EXTI_Init(&amp;EXTI_InitStructure); //根据EXTI_InitStruct中指定的参数初始化外设EXTI寄存器//GPIOE.4 中断线以及中断初始化配置下降沿触发//KEY0GPIO_EXTILineConfig(GPIO_PortSourceGPIOE,GPIO_Pi nSource4);EXTI_InitStructure.EXTI_Line=EXTI_Line4;EXTI_Init(&amp;EXTI_InitStructure); //根据EXTI_InitStruct中指定的参数初始化外设EXTI寄存器//GPIOA.0 中断线以及中断初始化配置上升沿触发PA0 WK_UPGPIO_EXTILineConfig(GPIO_PortSourceGPIOA,GPIO_Pi nSource0);EXTI_InitStructure.EXTI_Line=EXTI_Line0;EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; EXTI_Init(&amp;EXTI_InitStructure); //根据EXTI_InitStruct中指定的参数初始化外设EXTI寄存器NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn;//使能按键WK_UP所在的外部中断通道NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x02; //抢占优先级2，NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x03; //子优先级3NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; //使能外部中断通道NVIC_Init(&amp;NVIC_InitStructure);NVIC_InitStructure.NVIC_IRQChannel = EXTI2_IRQn;//使能按键KEY2所在的外部中断通道NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x02; //抢占优先级2，NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x02; //子优先级2NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; //使能外部中断通道NVIC_Init(&amp;NVIC_InitStructure);NVIC_InitStructure.NVIC_IRQChannel = EXTI3_IRQn;//使能按键KEY1所在的外部中断通道NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x02; //抢占优先级2NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01; //子优先级1NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; //使能外部中断通道NVIC_Init(&amp;NVIC_InitStructure); //根据NVIC_InitStruct中指定的参数初始化外设NVIC寄存器NVIC_InitStructure.NVIC_IRQChannel = EXTI4_IRQn;//使能按键KEY0所在的外部中断通道NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x02; //抢占优先级2NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x00; //子优先级0NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; //使能外部中断通道NVIC_Init(&amp;NVIC_InitStructure); //根据NVIC_InitStruct中指定的参数初始化外设NVIC寄存器} //外部中断0服务程序voidEXTI0_IRQHandler(void) { delay_ms(10);//消抖if(KEY3==1) //WK_UP按键{ BEEP=!BEEP; } EXTI_ClearITPendingBit(EXTI_Line0); //清除LINE0上的中断标志位} //外部中断2服务程序voidEXTI2_IRQHandler(void) { delay_ms(10);//消抖if(KEY2==0) //按键KEY2{ LED0=!LED0; }EXTI_ClearITPendingBit(EXTI_Line2); //清除LINE2上的中断标志位} //外部中断3服务程序voidEXTI3_IRQHandler(void) { delay_ms(10);//消抖if(KEY1==0) //按键KEY1{ LED1=!LED1; }EXTI_ClearITPendingBit(EXTI_Line3); //清除LINE3上的中断标志位} void EXTI4_IRQHandler(void){ delay_ms(10);//消抖if(KEY0==0) //按键KEY0 { LED0=!LED0;LED1=!LED1; }EXTI_ClearITPendingBit(EXTI_Line4); //清除LINE4上的中断标志位} [html] view plain copy。

STM32自学笔记作者：忙碌的小姚新浪微博：@忙碌的小姚新浪博客：/mlxiaoyao222目录STM32 自学笔记 (1)第一章 (3)我与STM32 的那些日子 (3)第二章 (4)使用固件库建立一个工程 (4)1、了解STM32F103的固件库 (4)2、创建第一个工程 (4)3、接下来就是管理工程文件了 (9)4、编写main.c 和文件路径 (10)第三章 (14)STM32点亮第一个LED 使用keil for ARM MDK 软件仿真 (14)1、Main.c 函数代码： (14)2、代码分析： (15)3、软件仿真介绍： (16)第四章 (19)串口的使用 (19)1、为什么要用串口？ (19)2、STM32跟PC机（也就是电脑）如何连接 (19)3、代码分析 (20)4、仿真及调试 (23)5、串口接收数据 (25)第五章 (27)通用定时器的使用 (27)1、STM32F103内部定时器有哪些？ (27)2、如何进行程序编写 (27)3仿真结果观察 (30)4对第四章串口的补充 (31)5工程代码 (35)第一章我与STM32 的那些日子STM32这块板子是在阿莫上跟一个老师买的，砍了半天100块钱。

包括一个Jlink v8仿真器（好像65块左右），和一块STM32系统板。

那已是一年前的事了。

那时我刚大三，刚学了半年51，于是想学点更高级的。

但我好像属于三分钟热度的这种人，买回来学了一个星期，就学不动了，寄存器操作，固件库的使用根本就没明白是怎么一回事，之后就没有然后了。

现在看到那块板子，总有一种说不出的滋味，要是当时能咬牙切齿努力学习，说不定现在也不会安静地坐在电脑前一字一句敲打这篇激励性文章了。

对于STM32我没用任何基础，唯一有的也只是一年前学的那一个星期，不过那已不重要了，我现在仍是一个小白。

作为一个初学者，也许是坐井观天，看的是片面的，可能有很多观点是错误的，希望读者朋友能勇于指出来。