Application Note

AN1009APPLICATION NOTE “Negative Undershoot” NVRAM Data CorruptionMiniaturisation in microelectronics has led, inevitably, to the inadvertent appearance of parasitic devices. Adjacent conducting paths end up being separated by a gap that is so narrow that it ceases to isolate them properly from each other. Parasitic tunnelling devices, bipolar transistors, and thyristors end up being formed, with each one causing its own distinctive misbehaviour.The occurrence of parasitic SCRs (silicon controlled rectifiers) causes the well-studied problem of latch-up. The occurrence of parasitic bipolar transistors, such as the one shown in Figure 1, is normally less serious, but leads to a particular type of problem in battery-powered circuits. It is this problem that is ad-dressed in this document.The problem manifests itself in battery-powered memory as data corruption: the unintentional flipping from 1 to 0, or from 0 to 1, of bits of data in the memory array. It is caused when a negative pulse is inadvertently applied to the emitter of an inadvertently formed parasitic bipolar transistor, causing it to go into conduction mode, and to connect two otherwise isolated signal lines.ANATOMY OF A PARASITIC BIPOLAR TRANSISTORFigure 1 shows the cross section of a CMOS gate, with one MOSFET formed directly in the N-type sub-strate, and the other in a P-well. Under certain conditions, the P-well can start to behave as the base re-gion of a parasitic bipolar NPN transistor, with the N-type substrate as its collector region, and the N+ diffusion contact of the MOSFET as its emitter region.Figure 1. Cross-Section of an NPN Parasitic Bipolar TransistorDecember 19981/4AN1009 - APPLICATION NOTE 2/4The P-well is held at ground, so the parasitic NPN transistor should never turn on. If, though, a negative pulse is applied to the pad, and hence to the emitter of the parasitic NPN transistor, the transistor would be put into its conducting mode. Once the pad is taken to -V be , the parasitic bipolar transistor turns on,and pulls current from the substrate.When the memory device is being powered by the external power source, the effect of this extra parasitic current will be negligible, and will be compensated for by the external power source. When the memory device is being powered from the internal battery, though, the battery is unable to compensate for the extra current, and so the supply voltage will fall. As soon as the supply voltage falls below a critical value, SRAM cells in the memory array will cease to hold their stored data reliably.The parasitic bipolar transistor starts to turn on when the pad is taken to about -0.6 V. In battery mode, the impact on the substrate will start to be felt once the current drain through the bipolar transistor is approx-imately -0.6mA. The substrate will be pulled to approximately 1.0V once the current through the bipolar transistor reaches -1.5mA. As the magnitude of the negative current increases, it directly reduces the lev-el of internal V CC (the substrate voltage). A current drain of approximately -2.0mA will bring internal V CC to ground, thus leaving the SRAM array completely unpowered.Figure 2. Substrate Vversus Negative UndershootsFigure 2 superimposes three pairs of curves: three negative undershoot pulses of 100, 500 and 1000ns duration; and the corresponding effects that are felt by the V CC substrate voltage.Thus, we see that the effect on the substrate voltage is proportional to the duration of the negative under-shoot pulse. It is also proportional to its magnitude (its amplitude). It is also proportional to the number of pins that receive the negative undershoot pulse (the example, above, is the effect of just one pin on the chip going negative).3/4AN1009 - APPLICATION NOTEREMEDIESST is continually making design and process modifications to improve the performance of its products.Immunity to negative undershoot will be improved over time, but only where it does not have a negative impact on other performance measures, such as operating speed.The application designer is, therefore, advised to take steps to avoid negative undershoot pulse from be-ing introduced. The first step is to improve the cleanliness of each of the signals. Table 1 lists the pins of ST’s NVRAMS that are affected (those that consist of an N+ diffusion in a P-well on an N-type substrate).All pins that are connected to N+ diffusion are susceptible to negative undershoot, but special attention should be given to the V CC pin. This is connected to internal circuitry that increases the pin’s sensitivity to negative undershoots, to the extent that pulses of greater than -0.3V may affect the substrate voltage.The second step, therefore, is to clamp the power lines (V CC and V SS ) with a Schottky diode, to short out any attempt by them to go negative. Its effectiveness depends on its speed of operation set against the speed and energy content of the negative-going pulse (the current sink capability of the pulse). An off-the-shelf diode with a V be of approximately 0.32V, and a current rating of 100mA, will generally reduce the occurrence of the problem to negligible proportions. However, the higher the current sink capability of the negative pulse, the more likely an RF Schottky diode is required.The Schottky diode should be placed as close to the device pin as possible.V CC can be subject to mechanical noise, the switching of V CC on and off, and to negative spikes coming from the power supply during initial power up. The third step, then, is to clean up the power supply, par-ticularly its behaviour at power-on and power-off, where the memory device is expected to continue to power itself from its internal battery. Particular care should be taken when working with programmable power supplies. Forcing a programmable power supply from a positive voltage to 0 volts without taking care to step down the voltage can generate a negative undershoot pulse.The fourth step is to protect each of the pins, mentioned in Table 1, by its own individual Schottky diode.No pin should exceed -0.3V, and their collective reverse current should not be allowed to exceed -1.0mA,especially when the memory device is being battery-powered.Table 1. List of the Pins on Devices that are Affected by the Problem Device Substrate Type PIns Connected to N+ DiffusionM40Z111 N-13, 16M40Z300 N-4, 10, 13, 16, 20, 22, 23M48Z02, M48Z12 N-AllM48Z08, M48Z18 P-none (not applicable)M48Z58, M48Z59 N-1, 11-13, 19-15, 26, 28M48Z35 N-AllM48T02, M48T12 N-AllM48T08, M48T18 P-none (not applicable)M48T58, M48T59, M48T559N-1, 11-13, 15-19, 26, 28M48T35 N-AllM48T37 N-1, 4-10, 13, 15-20, 22-26, 30,31,33-39AN1009 - APPLICATION NOTE 4/4If you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses:***************** (for application support)***************** (for general enquiries)Please remember to include your name, company, location, telephone number and fax number.Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.© 1998 STMicroelectronics - All Rights ReservedThe ST logo is a registered trademark of STMicroelectronics.All other names are the property of their respective owners.STMicroelectronics GROUP OF COMPANIESAustralia - Brazil - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore -Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.。

AN2452Application note STW8110x evaluation board and graphical user interfaceApplication and scopeThis application note describes the evaluation board (EVB) and the graphical user interface(GUI) of the STW81101, STW81102 and STW81103 multi-band RF frequency synthesizers(with integrated VCOs).The STW8110x GUI software allows the STW81101, STW81102 and STW81103synthesizers to be programmed via an I2C/SPI control interface.Three evaluation boards are available depending on the output matching network optimalfrequency range:■EVB1G (single output - 1GHz - output divider by 4)■EVB2G (single output - 2GHz - output divider by 2)■EVB4G (single output - 4GHz - direct output)February 2008 Rev 31/21Contents AN2452Contents1Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.1Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2Main form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3T utorial operation mode form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.4Waveform viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.1Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.2Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.2.1Top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.2.2Bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.3Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.4Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.5Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202/21AN2452Software3/211 Software1.1 InstallationThe STW8110x GUI software is built on the Microsoft (R) .NET Framework (see/net/default.mspx ). It may require the installation of the Microsoft (R) .NET Framework version 2.0, which may require the installation of Windows Installer 3.0 (see /library/default.asp?url=/library/en-us/msi/setup/windows_installer_start_page.asp ). Administrator privileges are required to install Microsoft (R) .NET Framework and Windows Installer.Follow these steps to install the STW8110x GUI:1.If an old version of the GUI is already installed, uninstall it.2. Run setup.exe (datasheets, programming configuration files and desktop/quick launchshortcuts are optional components installed by default).3. Run STW8110xGUI.exe 4.The default starting operation mode is Tutorial. The starting operation mode can bemodified by means of the radio buttons in the tutorial form:a) T utorial: a brief tutorial on the features of the GUI.b) Basic: only the main options are enabled.c)Advanced: all the available options are enabled.1.2 Main formThis section details the items on the main form. See Figure 1: Main form on page 4.1.Pressing this button shows the About STW8110xGUI screen.2.Pressing this button opens the datasheet of the selected device.3. H elp4. Device selection (STW81101/2/3).5.GUI operation modes:Tutorial : A brief tutorial on the basic features of the GUI. An inner default configurationis loaded.Basic : only the main options are enabled. Frequency values must be set in the following order:a) Input reference frequency F ref . b) Output frequency step F step .c)Output frequency F out .The calibrator is always ON. VCO and output divider are set automatically.Advanced : all the available options are enabled. Any F vco or F out are allowed. Amessage will warn if the inserted values are beyond the frequency limits of the VCOs. Frequency values must be set in the following order:a) Input reference frequency F ref .b) Output frequency step F step or F pfd .c)Output frequency F out or F vco .Waveform Viewer : a form is opened displaying the bit sequence sent to the device.Software AN24524/21Figure 1.Main form6. Swallow counter A: 5-bit counter.7. VCO calibrator:–Last calibration F vco: contains the last calibration data (VCO and frequency of calibration).–Calibrator ON/OFF.–The maximum allowed F pfd during calibration is 1MHz. If F pfd > 1MHz, the device is programmed in two steps:a) Device is programmed forcing calibration with the maximum F pfd≤1MHz(F pfd = F ref / R ≤ 1MHz ==> R ≥ F ref / 106).b) Device is programmed with the desired F pfd.Example with F ref = 76.8MHz:Desired values:- F pfd = 1200kHz- R = F ref / F pfd = 64Forced values:- R' = ⎡F ref / 106⎤ = ⎡76.8⎤ = 77- F'pfd = F ref / R' = 997.403kHzDevice programming in two steps:a) Device is programmed with F pfd = 997.403kHz and Calibrator ON.b) Device is programmed with F pfd = 1200kHz and Calibrator OFF.1234 56789101112131615141718192021AN2452Software8. Output divider:–Direct output.–Divider by 2.–Divider by 4.9. Configurations:–Load/Save: load/save a configuration file.–Load default/Save default: load/save a default configuration.10. Program counter B: 12-bit counter.11. VCO. VCO settings:–Output frequency range/VCOs frequency range: press this button to showinformation on the limits of F out/F vco (only for the embedded VCOs).–VCO selection (enabled only in Advanced mode):- EXT: external VCO. The external VCO buffer is able to manage a signal comingfrom an external VCO in order to build a synthesizer using the STW8110x only asPLL IC. The external VCO signal can range from 625MHz up to 5GHz. Itsminimum power level must be -10dBm.- VCO A/VCO B: embedded VCOs.12. Parallel port address. Hex value of the parallel port base address:–278: normally assigned to LPT2.–378: normally assigned to LPT1.–3BC–FILE: output is saved to a text file.13. Prescaler modulus:–P=16–P=1914. Reference divider. The 10-bit programmable reference counter allows the inputreference frequency to be divided to produce the input clock to the phase frequencydetector (PFD):F pfd = F ref / Rwhere–F pfd: PFD input frequency–F ref: input reference frequencyLimits: 2 ≤ R ≤ 102315. Frequency settings:–F ref: input reference frequency (MHz)- Limits: 10MHz ≤ F ref≤ 200MHz–F pfd: phase frequency detector (PFD) input frequency (kHz)F pfd = F ref / R, where R is the reference divider factor.–-/+: finds a lower/higher rational value for F pfd.–F vco: VCO oscillating frequency (MHz)F vco = N · F pfd.–N: PLL division ratioN = B · P + A.5/21Software AN24526/2116. Output frequency settings:–F out: output frequency (MHz)F out = F vco / DIV, where DIV is the output division ratio.–F step: output frequency step (kHz)F step = F pfd / DIV, where DIV is the output division ratio.–-/+: finds a lower/higher rational value for F step.17. Charge pump current. The nominal value of the output current is controlled by anexternal resistor (R ext) and can be varied over 8 levels by means of 3 dedicatedprogramming bits:–CPSEL[2:0]: bits controlling the charge pump current–R ext: the minimum value of the current is:I min = 2 V bg / R ext where V bg = 1.17V.–I cp: charge pump current (mA)I cp = (CPSEL + 1) · I min18. VCO voltage amplitude. The voltage swing of the VCOs can be adjusted over 4 levelsby means of two dedicated programming bits:–PLL_A[1:0]: bits controlling the voltage swing of the VCO.This setting trades current consumption with the VCO’s phase noiseperformances. Higher amplitudes provide better phase noise, whereas loweramplitudes save power.19. Two digital interfaces are available:–I2C- ACK: if checked and the acknowledge is not received, read and write operationsfail. Uncheck this if the board is not enabled to read.- Read: read the read-only register.- Write: write the 6 write-only registers.- A[2:0]: the device address (1100A2A1A0) must be set.–SPIShow sent data: the programming sequence is shown on the message list.20. Device programming:–Device programming modes:- Device ON: device on with output buffer control disabled.- Out Buffer CTRL: device on with output buffer control enabled. This control modeallows to enable/disable the output stage by a hardware control pin (EXT_PD, pin23) while the PLL stays locked at the desired frequency; in such a way a very fastswitching time is achieved. This feature can be useful in designing a ping-pongarchitecture saving the cost of an external RF switch.- Power Down: 'Power Down' mode enabled (device off).–SEND: press this button to program the device.AN2452Software21. Message list: displays information, warnings and errors:–CLEAR: press this button to delete all the messages.Clicking the right mouse button on the message list shows a menu:–Copy: copy the selected messages to the clipboard.–Copy to File: copy the selected messages to a file.–Append Mode: file is opened in append mode when 'Copy to File' is used.–Select All: all messages are selected (double-clicking the left mouse button has the same effect).–Deselect All: no message is selected.–Clear after Send: clears the message list after pressing the Send button.7/21Software AN2452 1.3 Tutorial operation mode formFigure 2.Tutorial operation mode form13241.Help for the current GUI operation mode.2. Start next session with: select the operation mode for the next session.3. Always on top:–Red: enabled–Gray: disabled4. The tutorial form shows a description of the evaluation board.8/21AN2452Software9/211.4 Waveform viewerFigure 3.Waveform viewerThe digital signals used to program the device can be displayed on a waveform viewer:●I 2C - the following are shown:–SCL (clock) signals sent to the device –SDA (data) signals sent to the device –ACK signals sent from the device ●SPI - the following signals are shown:–Clock –Data –Load1.Traces can be arranged by means of the vertical sliders, or in two default positions(separated or superimposed traces) by means of a button.2. The checkboxes allow you to display or hide the traces and bit descriptions that become visible when zooming in.3.The mouse buttons have the following functions on the waveform display:–Left: zoom in –Right: zoom out –Middle: pan1231Evaluation board AN245210/212 Evaluation board2.1 Setup1.Connect the evaluation board to the PC parallel port via the cable included in the kit.2. Choose which digital bus is used: the SPI or I 2C.3. If the I 2C is set, the device address must be chosen by connecting ADD [2:0] to VCC(1) or GND (0). The default is 000.4.Connect a signal generator to the REF_CLK connector (external reference clock).Set the frequency as desired (13MHz, 19.2MHz, 76.8MHz,…) and set the level to 10dBm.5. Connect the RF OUT connector to a spectrum analyzer.6.Make sure that the device is not in hardware power-down (that is, ensure the switch is not in the off position).The lock detector LED is turned on when the device is locked.The nominal value of the charge pump output current is controlled by the external resistor R15 (4.7k Ω on the evaluation board).The loop filter components are: C28, R17, R18, R18, C25, C30.The output matching network can be adjusted, depending on the application.AN2452Evaluation board11/212.2 Description2.2.1 Top viewFigure 4.STW8110x EVB (1G/2G/4G): top view1.Digital interface connector: connect to the PC parallel port through the supplied cable.2. Power supply (5V).3. Hardware power down: turn on/off the device.4. Digital interface selection between I 2C and SPI.5. I 2C device address (default: 000).6.Identification label. Two ID labels are present on the board network (see also 2.2.2 - 1):single output EVB top: STW8110x-EVBy, bottom: aaaaaaaaxyzzz, where:aaaaaaaa = internal ST codex = 1,2,3 depending on the device (STW81101/2/3)y = 1,2,4 depending on the board (EVB1G/2G/4G)zzz = progressive board number7. RF output.8.Single output EVB: RF output matching network (see also 2.2.2 - 3 and Figure 6).Differential output EVB: RF output de-coupling capacitors (C46 and C47).9. Reference clock input.10. STW8110x.11. Loop filter and external resistor controlling the charge pump current (R15).12. Lock detector LED.53mm57mm123456789101112Evaluation board AN245212/212.2.2 Bottom viewFigure 5.STW8110x evaluation board bottom viewThe bottom view (with the exception of the SMA connectors) is common to both the singleand the differential output evaluation boards.1.Identification label (see 2.2.1 - 6).2. The R5 short enables the I 2C read mode.3.RF output matching network (L1, R13, L2, R12) - (see 2.2.1 - 8 and Figure 6).Figure 6.Output matching network (single output top and bottom views)123Single output topBottomAN2452Evaluation board 2.3 SchematicsFigure 7.Main schematic13/21Evaluation board AN245214/21Figure 8.Digital interfaceFigure 9.Low noise voltage regulator+3.3V low noise+3.3V low noiseAN2452Evaluation board15/21Figure 10.Voltage regulator+5V+5V+3.3VEvaluation board AN245216/212.4 Layout2.5 Bill of materialsFigure 11.Top layerFigure 12.Bottom layerFigure 13.Ground layerFigure 14.Power layerTable 1.Bill of materials common to all the EVBs (EVB1G/2G/4G)QuantityReferencePart Part number - manufacturer 3R1, R3, R4330 Ω0603 - PHICOMP 5R2, R6, R7, R8, R17 2.2 k Ω 0603 - PHICOMP 1R50 Ω0603 - PHICOMP 3R9, R10, R11100 Ω0603 - PHICOMP 1R1451 Ω0603 - PHICOMP 1R154.7 k Ω0603 - PHICOMPAN2452Evaluation board17/211R16270 Ω 0603 - PHICOMP 1R188.2 k Ω 0603 - PHICOMP 1R1910 k Ω 0603 - PHICOMP 1R204 k Ω 0603 - PHICOMP 9C8, C13, C22, C25, C33, C34,C35, C36, C40, C35, C36, C4010 F GRM188 - 0603 - Murata 5C1, C2, C3, C4, C3810 pF GRM188 - 0603 - Murata 3C6, C7, C1115 pF GRM188 - 0603 - Murata 3C5, C26, C39100 nF GRM188 - 0603 - Murata 5C10, C18, C20, C23, C4522 pF GRM188 - 0603 - Murata 6C9, C12, C14, C21, C24, C44 1 nF GRM188 - 0603 - Murata 1C19 1.8 nF GRM188 - 0603 - Murata 1C28270 pF GRM188-COG - 0603 - Murata 1C3068 pF GRM188-COG - 0603 - Murata 1C29 2.7 nF GRM188-COG - 0603 - Murata 1C2747 F 1210 - AVX TPS Series III 3C31, C37, C4210 nF GRM188 - 0603 - Murata 1C32100 pF GRM188 - 0603 - Murata 2C41, C43 1 F GRM188 - 0603 - Murata 2L3,L4220 nH 0805HT - R22T B - Coilcraft 3U2, U3, U40 Ω0603 - PHICOMP1D1LED 1Q1BC847C ST 1U6STW8110xST1U7LT1962EMS8-3.3Linear T echnology 1U8LK112M33TR ST 1U974LCX07TTR ST1SMA (1.6mm)SMA REF Freq 1SMA (1.6mm)SMA Band 21J110 pole connector1J2+5VOLT 1J3GND 3S1, S2, S3SwitchTable 1.Bill of materials common to all the EVBs (EVB1G/2G/4G) (continued)QuantityReferencePart Part number - manufacturerEvaluation board AN245218/21Table 2.EVB1G output matching networkQuantity Reference Part Part number - manufacturer 1Cs20.5 pF GRM1555C1HR50C - MURA TA 1XS1 2.1 nH0403HQ-2N1XJL - COILCRAFT Cs3NCCs1NCCs4NCCs5NC1C1622 pF GRM1555C1H220J - MURA TA 1U50900BL150900BL15C050 - JOHANSON 2C15, C178.2 pF GRM1555C1H8R2D - MURA TA 2R12, R1324.9 Ω2L1, L218 nH0403HQ-18NXJL- COILCRAFT Table 3.EVB2G output matching networkQuantity Reference Part Part number - manufacturer Cs2NC1XS1 1.9 nH0402P A-1N9X B - COILCRAFT 1Cs3 1.2 pF GRM1555C1H1R2C - MURA TA Cs1NCCs4NCCs5NC1C1622 pF GRM1555C1H220J - MURA TA 1U51600BL151600BL15B100 - JOHANSON 2C15, C1722 pF GRM1555C1H220J - MURA TA 2R12,R1351Ω2L1, L2 5.5 nH0403HQ-5N5XJL - COILCRAFTAN2452Evaluation boardTable 4.EVB4G output matching networkQuantity Reference Part Part number - manufacturer 1Cs2 1.2 pF GRM1555C1H1R2C - MURA TA1XS1 4.7 pF GRM1555C1H4R7C - MURA TA1Cs3 1.2 pF GRM1555C1H1R2C - MURA TACs1NC1Cs4 1 pF GRM1555C1H1R0C - MURA TA1Cs5 1 pF GRM1555C1H1R0C - MURA TA1C1612 pF GRM1555C1H120J - MURA TA1U53700BL153700BL15B100 - JOHANSON2C15, C1712 pF GRM1555C1H120J - MURA TA2R12, R1351 Ω1L1, L2 5.5 nH0403HQ-5N5XJL - COILCRAFT19/21Revision history AN245220/213 Revision historyTable 5.Document revision historyDate RevisionChanges17-Jul-20071Initial release.13-Aug-20072Updated item 6 in Section 2.2.1: Top view .15-Feb-20083Modified Section 1.2: Main form and Section 1.3: Tutorial operationmode form .Added Section 1.4: Waveform viewer .AN2452Please Read Carefully:Information in this document is provided solely in connection with ST products. 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AuthorsTanja Heimberger1,Steffi Sandke1, Tanja Weis1, and Eva Graf21Heidelberg CardioBiobank, Department of Internal Medicine III, University Hospital, Heidelberg Germany2Agilent Technologies AbstractThis Application Note demonstrates the use of the Agilent 4150 TapeStation system as a quality control (QC) tool to analyze DNA samples stored at the Heidelberg CardioBiobank (HCB). An important quality control step is performed immediately after DNA extraction from blood samples to ensure the storage of only high-quality DNA samples. Subsequently, the QC step can be repeated for previously frozen DNA samples before using them for research purposes. This Application Note focuses on a retrospective analysis of the quality and quantity of stored DNA samples. Analysis of a subset of samples was taken as representative of the DNA quality after nine years of storage at –80 °C without any freeze thaw cycles.Within this timeframe, different DNA extraction methods were used at the HCB, and resulted in varied sample quality levels. Post QC analysis was able to verify the efficiency of the sample extraction and handling processes previously implemented. Retrospective Quality Analysis of DNA Samples from the Heidelberg CardioBiobank2IntroductionThe HCB is one of the largest biobanks in Germany, with a strong focus on Cardiovascular Diseases. It operates as a hospital-integrated biobank as well as a core biobank for several national and international clinical trials andresearch projects (Figure 1). The Biobank started with a cluster of standard –80 °C freezers in which biologicalsamples (predominantly liquid samples) were stored in a study-specific way.Therefore, the collection of the biological samples was performed according to study-specific guidelines. In 2014, the HCB was restructured to establish a large, fully automated –80 °C-storage system with a capacity of up to1.2 million samples (custom-built by Liconic AG, Liechtenstein). To ensure that biosamples are “fit for purpose”, we evaluated and optimized theentire workflow for sample collection,Figure 1.Scheme Heidelberg CardioBiobank (HCB).Core Biobank:National/International Studies Core Biobank:University Hospital HeidelbergStandardized shipping/storage Human and animal sampling/storageFigure 2. Workflow of whole blood sample processes including DNA extraction. For all pre-analytical processes, SOPs weredeveloped and time standards were set. The SOPs are related to the collection process of biological samples, its transportation, and, if applicable, the automated DNA extraction (Tecan/Promega Freedom EVO HSM workstation). The liquid samples are aliquoted automatically (Tecan Freedom EVO system) and stored in an automated –80 °C freezer system (customized Liconic STC store).Precise documentation of each processing step is done with the LIMS software CentraXX (Kairos) which records not only the sample data, but also the time stamps of each process.Research Study Whole blood sample Automated DNA extractionQuality and quantity controlAutomated aliquotingDocumentationLIMS Automated storage Research interestSOP SOPSOPSOPprocessing, logistics, and storage. It was then possible to develop and implement additional and specificstandard operating processes (SOPs) for all pre-analytical processes to achieve the highest quality of samples, which ismandatory for cutting-edge translational research (Figure 2). To investigate the impact of these processes in biobanks, we analyzed the quality and quantity of DNA samples from a series of randomly selected samples from the3nine consecutive years between 2010 and 2018 with other established quality management (QM) analysis tools. Additionally, the 4150 TapeStation system was evaluated as a QC tool for quantification and integrity assessment for genomic DNA by automatedelectrophoresis, and the results were compared.ExperimentalDNA extractionFor the analysis of long-term stored DNA, a random selection of 20 samples per year, from 2010 until 2018, was performed. Before 2015, the blood sampling processes were operatedpartly under slightly different conditions, for example, in some studies there was no time specification for storage of blood samples at 4 °C before DNA extraction. The following DNA extraction was performed manually with the NucleoSpin Blood XL column kit (Macherey-Nagel, Düren, Germany) using a silica membrane columnsystem for the extraction of DNA from EDTA whole blood (volume 9 mL). As of 2015, the DNA extraction was executed by an automated extraction system (Tecan/Promega Freedom EVO HSM workstation, Tecan, Männedorf, Switzerland) using the ReliaPrep Large Volume HT gDNA Isolation system,which uses a resin bead based extraction technology. The EDTA whole blood samples (volume 9 mL) were stored at 4 °C until sample processing, with a maximum storage time of seven days before starting the automatic extraction of DNA samples. Due to the switch to automated hardware systems, it was also necessary to switch to labware (storage tubes for biological samples) optimized for the automated processes starting in 2014. To exclude possible effects of storage tubes on the quality of the stored samples, we analyzedFigure 3. Workflow of DNA quality and quantity analysis.Analysis •Agilent 4150 TapeStation system•Application of Agilent Genomic DNA Screen Tape assay •Analyses of 20 samples per year from 2010–2018•Three replicates per sampletwo groups of samples from the year 2014. Samples of group 1 from 2014 were stored in tubes from Micronic, and group 2 from 2014 represents samples stored in FluidX tubes. In parallel with the implementation of automated systems, improved SOPs were developed and implemented for all processes related to the handling, processing, and logistics of biological samples.DNA analysisThe selected DNA samples underwent an identical thawing procedure (18 hours at 4 °C) before an aliquot from each sample was taken for further processing. First, the sample concentration was measured by NanoDrop spectrophotometer (Thermo Fisher, Waltham, USA) tocompare the value of the concentration with the measurement taken before freezing in 2010 to 2018. An additional measurement was performed with the Quantus fluorometer (Promega, Madison, USA), which is a fluorescence-based nucleic acid quantification method.The results from Quantus were used to adjust the final concentration of the DNA samples to the quantitative range of the Agilent Genomic DNA ScreenTape assay of the 4150 TapeStation system (10 to 100 ng/µL). In general, the process was in concordance with the instruction manual. Therefore, all kit components were equilibrated at room temperature for 30 minutes. After dilution of the selected DNA, 10 μL genomic DNA sample buffer and 1 μL genomic DNA sample were carefully aliquoted, vortexed for 1 minute, spun down, and then loaded on the genomic DNA ScreenTape 1.Typically, all available sample positions on 4150 TapeStation controller software were selected. The experiments were performed in triplicates, as displayed with the whole workflow in Figure 3. The Agilent TapeStation analysis software was used to evaluate the DNA sample concentration and the DNA integrity number (DIN).4Results and DiscussionQualityThe DIN algorithm is included in the TapeStation analysis software and provides a quality assessment of the DNA sample by assigning a numerical score from 1 to 10. A high DIN indicates intact gDNA, and a low DIN degraded gDNA 2. The DNA analysis revealed that the tested DNA samples are of high and consistent quality (DIN >9) from 2014 to the present when automated processes and improved SOPs were in place. By contrast, samples collected before 2014 show higher variation of DNA integrity (Figure 4). Figure 5 shows the comparison of representative samples taken between 2010 and2018 with the TapeStation gel view and electropherogram overlay. In 2014, the20105YearsDNA QualityDI N6789102011201220132014/12014/22015201620172018Figure 4. Comparison of sample quality over a period of nine years. For each year, 20 DNA samples were analyzed with the Agilent Genomic DNA ScreenTape assay. In 2014, two groups were analyzed due to the change of labware.ABSize (bp)(L)20102011201220132014/12014/2201520162017201820102011201220132014/12014/22015201620172018100DIN 8.1DIN 8.6DIN 8.2DIN 9.0DIN 8.8DIN 8.9DIN 9.4DIN 9.7DIN 9.6DIN 9.52504006009001,2001,5002,0002,5003,0004,0007,00015,00048,50010S a m p l e i n t e n s i t y (n o r m a l i z e d F U )254060901,201,502,002,503,004,007,0015,0048,50Figure 5. Comparison of representative samples harvested between 2010 and 2018. The DNA sample 2014/1 represent tubes from Micronic and sample 2014/2 tubes from FluidX. The sample integrity increased after 2015, reflected by higher DIN values. A) TapeStation gel view B) Overlay of the electropherograms of 10 samples. Both views enable visual comparison of the sample integrity.type of storage tubes was changed due to the implementation of the automated storage and robotics handling systems and their respective requirements. Accordingly, two different sets ofsamples (2014/1 and 2014/2) were analyzed. The change from the tube manufacturer Micronic to FluidX had no influence on the quality of the DNA samples.5QuantityThe concentration of DNA was routinely measured by a NanoDrop spectrophotometer directly after DNA extraction at the HCB. DNA samples from the years 2010 to 2014 had been extracted manually (see material and methods) and obtained an average DNA concentration of approximately 120 ng/µL. The implementation of improved SOPs and the automatedDNA extraction method in 2015 resulted in a significant increase of average DNA yield to about 300 ng/µL. In this study, after thawing the samples, the DNA quantification by NanoDrop was repeated. The storage at –80 °C did not lead to altered sample concentration independent of the storage time (Figure 6). The samples were also measured by Quantus, which fluorometrically evaluates the DNA quantity, as the TapeStation system uses a fluorescence-based approach to determine DNA concentration. All tested samples showed an equivalent DNA concentration on both systems (Figure 7).Figure 7. Determination of DNA quantity by Quantus fluorometer and the Agilent 4150 TapeStation system. The increase of the DNA concentration between 2014 and 2015 is a result of the conversion from manual to automated DNA extraction.Figure 6. Overview of DNA concentration as measured by NanoDrop spectrophotometer. Theincrease of DNA concentration was a result of the change from manual to automated DNA extraction methods from 2014 to 2015. All DNA concentrations (conc.) remained stable throughout the years of storage at –80 °C.Yearsn g /µLYearsn g /µL/genomics/ tapestationFor Research Use Only. Not for use in diagnostic procedures.This information is subject to change without notice.© Agilent Technologies, Inc. 2019 Printed in the USA, April 9, 2019 5994-0811ENConclusionFrom 2010 to 2014, the collection of biological samples at the HCB was performed in some studies under less stringent SOPs compared to 2015 to 2018 (for example, the storage timeuntil processing of blood samples varied from two hours up to several days study dependently). As a result, the quality of the analyzed DNA samples differed from 2010 to 2014.Because of significant improvements made to processes in 2015, we evaluated workflows such ascollection, transportation, and sample preparation procedures. The influence of preprocessing parameters likeincubation time and storage modalities on DNA quality was investigated and resulted in the development and implementation of advanced SOPs. In addition to the standardized processes, we implemented automated hardware systems for DNA extraction, which also improved the outcome of the performedwork. Hence, by automating the DNA extraction process, the quantity, quality, and variability of quality of extracted DNA could be significantly increased. The analysis with the Agilent Genomic DNA ScreenTape assay enablescomparison of DNA quality by using DIN. The improvements to sample handling and extraction are also reflected in the DNA integrity, leading to DIN values being more consistent at a significantly higher level. Nowadays, the need for personalized and precision medicine is highly apparent, requiring translational research according to best practices (“garbage in equals garbage out”). We showed that the implementation ofstandardized and almost fully automated sample processing systems leads to the highest quality of biological samples. The use of the Genomic DNA ScreenTape assay with the Agilent 4150 TapeStation system could be smoothly integrated into our workflow as a reliable QC tool in biobanking processes to verify the quality of DNA samples important for downstream applications.References1. Agilent Genomic DNA ScreenTapeSystem Quick Guide for 4200 TapeStation System, AgilentTechnologies , publication number G2991-90040, 2015. 2. Gassman, M.; McHoull, B. DNAIntegrity Number (DIN) with the Agilent 2200 TapeStation System and the Agilent Genomic DNA ScreenTape Assay, Agilent Technologies Technical Overview , publication number 5991-5258EN, 2015.。

March 2012Doc ID 022842 Rev 11/13AN4057Application noteSPC560Pxx, SPC56APxx power up HW guidelineINTRODUCTIONThis application note is addressed to system hardware designers usingSTMicroelectronics ® SPC560Pxx/SPC56APxx microcontrollers It gives design references to ensure a reliable microcontroller power up sequence also in the condition of an offset voltage on the high voltage regulator supply pin V DD_HV_REG at power up.The use of the SPC560Pxx/SPC56APxx internal voltage regulator requires a specific design ST approved ballasts with the recommended supporting network described in the latest revision of the device data sheet (for further details see Section Appendix A: Additional information ). It is important to respect the power on sequence conditions, ensuring a monotonic supply ramp starting at ground level and respecting the min and max slew rate on V DD_HV_REG .This application note covers:■Recommended power on sequence conditions ■Possible deviations injecting an offset voltage on V DD_HV_REG and its impact on microcontroller power up ■Optional proposals to eliminate the effect of offset voltage on V DD_HV_REG pinContents AN4057Contents1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.1Power up sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Offset voltage on V DD_HV_REG and voltage regulator circuitry . . . . . . . 62.1Offset voltage on V DD_HV_REG: problem description . . . . . . . . . . . . . . . . . 62.1.1Possible application paths to induce a V DD_HV_REG offset voltage . . . . . 62.1.2Battery short to pin on connector of microcontroller board . . . . . . . . . . . 62.2HW guidelines for high/low voltage supply of the internal regulator with offsetvoltage on V DD_HV_REG 72.2.1Resistors partition network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.2.2V DD_HV_REG pin active path to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3SPC560Pxx/SPC56APxx devices affected . . . . . . . . . . . . . . . . . . . . . . 10Appendix A Additional information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11A.1Reference document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122/13Doc ID 022842 Rev 1AN4057List of tables List of tablesTable 1.Resistor partition network values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2.SPC560Pxx/SPC56APxx device affected from V DD_HV_REG offset issue . . . . . . . . . . . . . 10 Table 3.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Doc ID 022842 Rev 13/13List of figures AN4057 List of figuresFigure 1.Offset voltage on V DD_HV_REG from SPC560Pxx/SPC56APxx input pin . . . . . . . . . . . . . . . 6 Figure 2.Battery short to pin on connector of microcontroller board. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3.Resistors partition network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4.Active path to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4/13Doc ID 022842 Rev 1AN4057Overview Doc ID 022842 Rev 15/131 OverviewThese SPC560Pxx /SPC56APxx microcontrollers are members of a new microcontrollerfamily built on the Power Architecture ®. The device is supplied externally with a singlevoltage supply, which can be either 5V or 3.3V depending on application requirements.Internally the chip operates with 2 supply voltages, namely the main supply (5V or 3.3V)and the core logic supply (1.2V).This document provides guideline for the recommended configuration of the high and lowvoltage supply for the internal regulator in order to ensure the correct power up sequence ofthe microcontroller.The note describes application fault conditions that may offset V DD_HV_REG significantly andmitigating circuitries to ensure reliable power up in case of these fault conditions. Thestandard supply circuitry and sequence that use in the recommended conditions of initialpower up on V DD_HV_REG pin starting from ground level are described in theSPC560Pxx/SPC56APxx data sheet (for further details see Section Appendix A: Additionalinformation ).Possible causes of fault conditions injecting an offset voltage on V DD_HV_REG pin aredescribed in the following list:●Supply microcontrollers I/O V IN while the microcontroller is switched off with shorted supply for V DD_HV_REG and V DD_HV_IO pins ●Offset voltage injected on V DD_HV_REG by external signal(s) shorted to battery.1.1 Power up sequencingPreventing an overstress event or a malfunction within and outside the device, theSPC560Pxx/SPC56APxx implements a specific power up sequence, as described in thedata sheet, to ensure each module is started only when all conditions for switching it ON areavailable.In case of a fault condition on the application board, that sequence may not be respected,causing the device not to exit the power up.Two possible fault conditions are described in the following sections. However, if the faultcause is removed, the device (while within the absolute maximum ratings) works again,without getting damaged, powering up properly.2 Offset voltage on V DD_HV_REG and voltage regulatorcircuitry2.1 Offset voltage on V DD_HV_REG: problem descriptionV DD_HV_REG offset on the devices SPC560Pxx/SPC56APxx, before the module is poweredup, may in some cases prevent the power up device correctly.A V DD_HV_REG offset before a correct power up supply sequence can set the POR devicelogic to an undefined state, preventing the internal logic to switch correctly and initialize theinternal V DD_LV circuitry. The internal regulator remains in power down. The consequence isthat the microcontroller is not able to exit reset.application paths to induce a V DD_HV_REG offset voltage2.1.1 PossibleFigure1 describes a GPIO configuration with the pin connected to an externally suppliedsignal (V batt).If V batt is powered while MCU V DD is not yet provided, GPIO protection circuitry (diode)induces a voltage on V DD_HV_IO.In the case V DD_HV_IO is directly connected to V DD_HV_REG, the induced voltage ispropagated to the internal regulator. The same consideration is done when using anexternal diode, D1 in Figure1, connecting GPIO V IN to V DD.2.1.2 Battery short to pin on connector of microcontroller boardAnother possible cause of an initial offset on V DD_HV_REG is battery short to any pin of theboard connector.6/13Doc ID 022842 Rev 1The short to battery can be propagated through various components (ASSP, ASICs, ComDrivers) to the V DD_HV_REG as these components typically share the same supply.2.2 HW guidelines for high/low voltage supply of the internalregulator with offset voltage on V DD_HV_REGIn general an offset voltage must be avoided to pre-charge V DD_HV_REG through parasiticpaths. The MCU supply must power on from GND to power supply with a monotonic ramprate, minimum and maximum value as described in the data sheet (T vdd). In case of a faultcondition, injecting an offset to V DD_HV_REG while the MCU is not supplied, the followingmodifications on the module can prevent the device to remain in reset. The supply voltageconditions are still respected.Possible HW solutions on the supplying circuitry of the microcontroller to allow a correctpower up sequence, in case of an offset build up on V DD_HV_REG pin are:●Resistive network between V DD_HV_REG, V DD_LV_REG and GND●Active discharge on V DD or V DD_HV_REG at power up●Other application means to prevent the presence of an offset on V DD_HV_REG duringpower upnetwork2.2.1 ResistorspartitionThis solution with two partitioning resistors, shown in Figure3, enables V DD_LV_REG to bepre- conditioned and the internal V DD_LV_REG to be forced into a defined state as soon asthe ballast regulator turns-on.Doc ID 022842 Rev 17/138/13Doc ID 022842 Rev 1Static consumption has to be considered into the board voltage regulator design.2.2.2 V DD_HV_REG pin active path to groundAnother solution is to add a controlled active path to ground on V DD_HV_REG /V DD_HV_IO thatforces these pins to ground when the microcontroller is switched off or discharges theV DD_HV_REG at start up.Figure 4 describes a generic configuration that uses the enable signal of an externalregulator, VIGN, to drive the gate of NFET to force V DD_HV_REG /V DD_HV_IO pin to ground.When the external regulator is off there is a discharge path of the current from theV DD_HV_REG /V DD_HV_IO .It has to be granted that the V DD rises with the required monotonic slew rate before any faultcondition can build up an offset on V DD_HV_REG , prior to the release of the active dischargecircuit.Table 1.Resistor partition network valuesSymbolParameter Value Unit V DD_HV_REG @ 5V R1Resistor between V DD_HV_REG /ballastemitter and ballast collector910ΩR2Resistor between ballast emitter andground300ΩV DD_HV_REG @ 3.3V R1Resistor between V DD_HV_REG /ballastemitter and ballast collector510ΩR2Resistor between ballast emitter andground 300ΩDoc ID 022842 Rev 19/13SPC560Pxx/SPC56APxx devices affected AN405710/13Doc ID 022842 Rev 13 SPC560Pxx/SPC56APxx devices affectedTable 2 lists the STMicroelectronics SPC560Pxx/SPC56APxx devices and revisions that areaffected by the previously described phenomenon.Table 2.SPC560Pxx/SPC56APxx device affected from V DD_HV_REG offset issuePart number Package devicemarking mask identifierand silicon versionMIDR1 register SPC560P34xx/P40xx AB -cut 1.1 (and older)MAJOR_MASK[3:0]: 4'b0000MINOR_MASK[3:0]: 4'b0001SPC560P50xx/P44xx BD -cut 3.4 (and older)MAJOR_MASK[3:0]: 4’b0001MINOR_MASK[3:0]: 4’b0101SPC560P60xx/P54xx SPC56AP60xx/AP54xxAA -cut 1.0 MAJOR_MASK[3:0]: 4’b0000MINOR_MASK[3:0]: 4’b0000AN4057Additional information Doc ID 022842 Rev 111/13Appendix A Additional informationA.1 Reference document●32-bit Power Architecture ® based MCU with 1088 KB Flash memory and 80 KB RAMfor automotive chassis and safety applications (SPC560P54x, SPC560P60L3,SPC56AP54L3, SPC56AP60x, Doc ID 18340)●32-bit Power Architecture ® based MCU with 320 KB Flash memory and 20 KB RAM forautomotive chassis and safety applications (SPC560P34L1, SPC560P34L3,SPC560P40L1, SPC560P40L3, Doc ID 16100)●32-bit Power Architecture ® based MCU with 576 KB Flash memory and 40 KB SRAMfor automotive chassis and safety applications (SPC560P44L3, SPC560P44L5,SPC560P50L3, SPC560P50L5, Doc ID 14723)Revision history AN4057 Revision historyTable 3.Document revision historyDate Revision Changes01-Mar-20121Initial release.12/13Doc ID 022842 Rev 1AN4057Please Read Carefully:Information in this document is provided solely in connection with ST products. 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Versatile Link Application Note 1035IntroductionThis application note describes how fiber optics can be used to solve many different types of application prob-lems, introduces Avago Technologies’ Versatile Link plas-tic fiber optics, and shows how to design a fiber-optic link using the Versatile Link. Below is an outline of this application note.I. IntroductionII. Example ApplicationsIII. Versatile Link DescriptionIV. System Specifications and Link DesignV. Pulse-Width DistortionVI. Additional Circuit RecommendationsVII. AppendixOptical fiber is typically made from either plastic or glass. Because both plastic and glass are electrical insu-lators, there is no direct electrical connection between the transmitter and the receiver of a fiber-optic link. This helps to alleviate ground-loop and common-mode noise problems, as well as to isolate large common-mode volt-ages. Another useful property of optical fiber is that it does not emit radiation and is not susceptible to elec-tromagnetic interference (EMI). This prevents an optical fiber from interfering with neighboring wires and also gives it inherent immunity to induced or coupled noise from adjacent wires.Fiber optics can protect equipment from excessive volt-ages, reduce EMI, increase safety by eliminating the haz-ard of generating sparks, and ensure data integrity in environments with large amounts of noise or with high common-mode voltages.Example ApplicationsDifferent applications have different requirements and, therefore, different reasons for using fiber optics. The fol-lowing paragraphs discuss some examples of common fiber-optic applications and why fiber optics are used in those applications.The first type of application utilizes the EMI immunity of fiber-optics for data transmission in electrically noisy environments. A good example is data transmission be-tween a programmable logic controller (PLC) and the computer that is directing it, illustrated in Figure a. The two computers might be in a factory containing ma-chinery that generates large amounts of electrical noise. Data transmission lines commonly run alongside lines that supply power to the machinery. There may be large amounts of electrical noise present on the power lines caused by the machinery. This noise can couple electro-magnetically into any adjacent lines. If one of those adja-cent lines is a twisted-pair or coax line carrying data, the coupled electrical noise may significantly interfere with the data transmission. The noise may cause only periodic errors, or it might completely corrupt all of the data be-ing sent. Because optical fiber is not susceptible to EMI, it can eliminate the undesirable coupling of noise from the power lines onto the data lines and ensure error-free data transmission.Figures b, c and d illustrate other applications whichutilize the EMI immunity of fiber optics. Figure b showshow fiber can connect a robot controller with the cellcontroller and the robot. The fiber eliminates the largeamounts of noise generated by the motors, solenoids,etc. that are part of the robot. Figure c illustrates howfiber is used to network point-of-sales terminals (cashregisters) in a retail store. Fiber optics ensures that salesinformation is not corrupted or lost due to noise gener-ated inside the building. Figure d shows fiber opticsconnecting two HPIB (IEEE-488) data buses. The HPIBdata bus is commonly used to connect test instrumentsin manufacturing automated test systems. Again, fiberoptics eliminates the noise that is commonly present ina factory and ensures that correct test data is transferredto the test system controller.Figure 1b. Robot Controller.Figure 1c. Point of Sales TerminalsFigure 1d. HPIB (IEEE-488) Bus Extender.Figure 2b. Medical Equipment – Heart Monitor.Figure 2c. X-Ray Machine.Figure 2d. Lightning Protection.The second type of application uses fiber-optics for volt-age isolation. A digital voltmeter, illustrated in Figure a, is a good example. There is typically some circuitry at the input of the voltmeter that converts the analog voltage across the input terminals into a digital signal; this circuitry is called an analog-to-digital converter (ADC). The output of the ADC is then sent to processing circuitry that displays the information on the front panel or, perhaps, sends the information to an external com-puter. A problem arises, however, when the signal to be measured has a very high common-mode voltage com-ponent. An example of this is measuring the difference between two very high voltages. The ADC will also be at the same common-mode voltage, causing a problem in safely sending information from the ADC to the digital control circuitry at ground potential. Because of its insu-lating properties, an optical fiber is not affected by such high voltages and does not conduct any current that might interfere with or damage the circuitry to which it is connected. Fiber optics allow data to be transmitted and still maintain a high degree of voltage isolation.Figures b, c and d also illustrate the use of fiber in voltage-isolation applications. Figure b is a simple block diagram of an electrocardiograph, which is used to mon-itor a patient’s heart. If the heart were to stop beating, a defibrillator might be used to restart it. The fiber protects the electrocardiograph from the very high voltages that are generated by the defibrillator. Figure c shows the use of fiber in a clinical X-ray machine. The fiber isolates the high voltages used to power the X-ray tube and pro-vides EMI immunity from the noise generated by switch-ing high voltages and currents. Figure d illustrates how fiber can protect electronic equipment from the high voltages generated by nearby lightning strikes.Figure 3b. Telephone Switching Network.Figure 3c. Tempest Applications.Another type of application reduces the amount of un-wanted electromagnetic radiation emitted by a transmis-sion line. This type of application is the converse of the first type; the idea is to minimize the amount of EMI that is radiated from the transmission line itself, rather than being concerned with the susceptibility of the transmis-sion line to external interference. An example is high speed video transmission from a workstation computer to a high resolution video monitor, shown in Figure a. As the resolution of a video monitor increases, the num-ber of pixels (dots) on the screen also increases. If the computer is updating the screen with the same number of frames per second, the computer must send more pix-els per second as the resolution increases. Therefore, the bandwidth of the video transmission link must increase as well. If a coaxial cable is used to transmit the video information, it becomes more and more difficult (and expensive) to shield the cable and reduce unwanted ra-diation as the frequency of the transmitted information increases. Because an optical fiber does not emit radia-tion, it can significantly reduce the amount of EMI gener-ated in transmitting information at very high data rates or when there are many transmission lines.Figures b and c show two additional applications that use fiber optics to reduce the amount of unwanted emis-sions. Figure b illustrates the use of fiber in the tele-phone switching network of a central office switch. Fiber helps to minimize the amount of unwanted radiation generated by the large number of interconnects in the network. Figure c illustrates how fiber might be used in Tempest applications. Tempest is a federal government specification that restricts the amount of radiation that can be emitted by “secure” electronic equipment. Be-cause fiber does not emit any radiation, it is well suited for Tempest applications. Figure c shows how fiber is used to connect a secure personal computer (i.e., a com-puter constructed to limit the amount of emissions) with a secure central computer. The fiber also connects the secure central computer with a non-secure personal computer, located inside of a secure room (i.e., a room specifically designed to limit unwanted emissions).The above examples illustrate how the features of fiber optics can be used to solve problems found in many dif-ferent types of applications.Figure 4. Versatile Link Family.Figure 5. Exploded View.Guaranteed Minimum Link Length Typical Link LengthMetres Metres 0°C - 70°C 25°C 25°CVersatile Link Standard Improved Standard Improved Standard ImprovedCable Cable Cable Cable Cable Cable High Performance MBd 7 7 4 40High Performance MBd 4 4 0 4 0 6 Low Current Link 40 kBd 8 - - 0 Extended Distance 40 kBd 60 8 6 90 00Link Standard MBd 7 0 40Photo Interrupter 00 kHz N.A. N.A. N.A. N.A. N.A. N.A.Evaluation Kit MBd C ontents: Horizontal transmitter, horizontal receiver packages; metres of (Standard) simplex cable with simplex and simplex latching connectors installed; individual connectors: simplex, duplex, simplex latching, bulkhead adapter; polishing tool, abrasive paper, literature.Versatile Link DescriptionThe Avago Technologies HFBR-0 0 Z series low-cost fiber-optic system, the Versatile Link, was designed for ease of use, versatility, and reliability. Table summariz-es the data rate and distance capabilities of the Versatile Link family. Typical distances at room temperature are also shown. The maximum data rates for Versatile Link components range from 40 kBd to MBd, with even higher data rates available in the future.Avago Technologies guarantees minimum and maxi-mum specifications of its components both at room temperature and over the full operating temperature range (0 to 70°C). These guaranteed specifications were obtained from extensive characterizations of the Versa-tile Link components and cover the full range of manu-facturing process variations. This ensures reliable circuit operation and allows Avago Technologies to guarantee minimum link distances.The Versatile Link family, shown in Figure 4, is intended for use with mm plastic optical flber. No optical design is required because the specifications include any con-nector losses at the transmitter and at the receiver. The compact, low-profile package is color coded to distin-guish transmitters from receivers; connectors are also color coded. Both horizontal and vertical package styles are available with standard 8-pin DIP pinouts. The pack-ages can also be interlocked or stacked (“n-plexed”) to decrease the required amount of PC-board space.Figure shows an exploded view of the Versatile Link horizontal style package. The package was designed for improved performance and ease of manufacturing. The active components are attached to a lead frame which is then transfer molded with clear plastic to form the insert. A precision lens is molded into the insert to optimize the optical coupling from the package to the fiber. The insert is held in the main part of the housing by a snap-on cap on the back of the package.Figure 6. Connector Alignment.-ment system to ensure proper coupling between the connector and the package. Figure 6 illustrates how the alignment system operates. The precision-molded lens on the insert is located at the bottom of a depression in the shape of a truncated cone. When the connector is inserted into the package, the jaws of the housing force the beveled end of the connector into the cone-shaped depression. This accurately centers the fiber directly above the molded lens on the insert and ensures reliable and repeatable connections.The gray transmitter modules contain 660 nm large-area LEDs that can be easily interfaced to all standard logic families. The blue receiver modules contain monolithic integrated optical detectors with TTL/CMOS-compatible outputs.Four connector options are available for use with the Versatile Link:. Simplex connector, which is compatible with our pre-vious Snap-In Link family,. Latching simplex connector, for applications that re-quire increased connector pullout force,. Duplex connector, which incorporates a lockout fea-ture that ensures correct orientation of the connector when used with interlocked packages,4. Latching duplex connector.Avago Technologies offers simplex and duplex cables with two grades of attenuation, standard and improved. Cable with connectors is offered in one meter increments of length; unconnectored cable is available in lengths of , 00, and 00 meters. These cables are UL-recognized and pass UL VW- flame-retardancy specifications.An evaluation kit is available which contains a standard MBd transmitter and receiver, m of connectored cable, individual simplex, simplex latching, and duplex connec-tors, a bulkhead adapter, polishing tools and literature.The data sheet for the Versatile Link family contains com-plete guaranteed specifications for entire links and indi-vidual components, electrical pinouts, interface circuits, connectoring information, mechanical dimensions, part number and ordering information.Reliability Data Sheets are available which provide com-plete reliability information for all Versatile Link compo-nents.System Specifications and Link DesignTo obtain optimum performance under a variety of dif-ferent conditions, it is helpful to understand some of the basic specifications of the Versatile Link and how to use them in designing a fiber optic link. This section will first discuss how Avago Technologies specifies its transmit-ters, receivers, and plastic fiber-optic cable, then explain how to use those specifications in determining proper operating conditions. This section will also explain what a link operating diagram is and how to use it to quickly determine transmitter drive current or link length.A basic fiber-optic system is very simple: an LED trans-mitter couples light into a fiber, the light travels down the fiber to an optical detector, and the detector con-verts the light into a digital output signal. The important specifications of the fiber-optic data link are:. How much light is coupled into the fiber by the transmitter, . How much light the receiver needs to function prop-erly,. How much light is lost on the way to the receiver.For a brief explanation of how optical power is specified in “dB” and “dBm”, see the Appendix.Figure 8. Normalized Typical Output Power vs. Drive Current.Transmitter SpecificationsThe primary transmitter specification is P T , the amount of optical power coupled into the fiber at a specified LED drive current. P T specifies how much power is ac-tually coupled into the fiber; this eliminates the need to calculate the loss in coupling light from the LED to the fiber. Due to normal process variations, Avago Tech-nologies specifies a range of coupled power for each type of transmitter. Figure 7 shows the coupled power specifications for each of the Versatile Link transmitters. Guaranteed specifications over the full operating range are shown in Figure 7 because these values typically are used in “worst-case” designs and are also used in our ex-amples.The amount of coupled power can be easily adjusted by changing the LED forward drive current, I F , as indicated in Figure 8. Notice that the coupled power is normalized to the value at I F = 60 mA. The graph, therefore, repre-sents the CHANGE in output power for different drive currents. For example, operating the transmitter at a drive current of 0 mA will drop the output power by about dB. There is an approximately linear relationship between drive current and output power; therefore, the output power will drop approximately in half (i.e., about dB) when the drive current is cut in half.Figure 9 shows thc recommended transmitter drive cir-cuits. You should note that for the MBd and 40 kBd drive circuits, an input-high level turns the LED on; for the MBd circuit, an input-high level turns the LED off. The capacitor in the MBd circuit slows the falling edge of the optical waveform and allows the receiver to op-erate up to the maximum output power of the MBd transmitter. The value of R can be determined from the equations in the figure. Typical values for the forward voltage of thc LED, V F , and the output low voltage of the gate, V OL , are .6 V and 0. V respectively.Additional transmitter drive circuits will be covered later in the application note.Figure 10. Receiver Specifications.The Versatile Link receivers function somewhat as optical inverters: high input power causes a low output voltage, and low input power causes a high output voltage.There are two primary receiver specifications:. P R(L) specifies the input power required for a LOW out-put voltage, . P R(H) specifies the input power required for a HIGH out-put voltage.Figure 0 shows the ranges of P R(L) and P R(H) for each of the receivers over the full operating temperature range.Typically, both a minimum and a maximum are specified for P R(L). For proper operation, the received optical power must be between the minimum and the maximum P R(L). If no maximum is specified, the corresponding transmitter (i.e., the HFBR- X Z transmitter for the HFBR- X Z re-ceiver) is not capable of overdriving the receiver for drive currents up to the recommended maximum value of 60 mA, and you need ensure only that the input power is greater than the minimum P R(L). If the maximum P R(L) is ex-ceeded, the receiver may exhibit excessive pulse-width distortion (discussed later) or multiple edge transitions.Only a maximum P R(H) is specified for each receiver. When the transmitter LED is in the off state, the received opti-cal power must be less than the maximum P R(H) for proper receiver operation.The minimum P R(L) is called the sensitivity of the receiver. A receiver with good sensitivity (lower minimum P R(L)) will allow longer link lengths or lower transmitter drive current. The difference between the minimum and maxi-mum P R(L) is called the dynamic range of the receiver. A receiver with a large dynamic range can handle a wider variation in received power and therefore more variation in the length of the link. Note that the 40 kBd receiver has very good sensitivity and a large dynamic range. The 40 kBd link can therefore handle long link lengths and large variations in the length of the link. Also note that the maximum P R(L) for the MBd receivers is determined by the maximum coupled power of the MBd transmit-ters.Because the receiver switching threshold is between the minimum P R(L) and the maximum P R(H), the receiver input power should be within this region only very briefly dur-ing signal transitions. Very slow rise or fall times of the input optical waveform may cause multiple transitions on the output of the receiver.Figure shows how simple the receiver interface circuits are, requiring only one or two external components. The 0. µF bypass capacitor is mandatory and must be locat-ed close to the receiver; the total lead length between the ends of the capacitor and the receiver power supply pins should not exceed 0 mm. The external pull-up re-sistor is optional. The MBd and MBd receivers have an internal K ohm pull-up resistor, and the 40 kBd receiver has an internal 0 µA pull-up current source. All data sheet specifications for propagation delay and rise/fall time use an external pull-up resistor, a 60 ohm resistor for the MBd and MBd receivers, and a . K ohm resis-tor for the 40 kBd receiver.Figure 12. Cable Attenuation.Figure 11. Receiver Interface Cirsuits.Optical LossesThere are two primary causes of optical loss in a fiber-optic link: losses due to cable attenuation and connector coupling efficiency.Attenuation is defined as loss per unit length of fiber, expressed in dB/m. To obtain the optical loss in a fiber, simply multiply the length of the fiber by the attenua-tion. Figure shows the range of attenuation for the two grades of fiber, standard and improved, that Avago Technologies offers.For a given length and type of fiber, there will be a range of optical loss due to the range of attenuation of the fiber. For our standard fiber, Figure illustrates how the range of loss, as well as the magnitude of the loss, in-creases as the length of the fiber increases. You can see that for a 40 m length of fiber, the losses due to attenu-ation will be between 7.6 dB and 7. dB, a range of al-most 0 dB. A fiber optic receiver must be able to handle the range of loss as well as the magnitude of the loss. Therefore, receivers with both large dynamic range and good sensitivity are required for long link lengths.Connector losses at the transmitter and receiver are al-ready included in the transmitter and receiver specifi-cations. However, connector losses due to connectionsthrough bulkhead adaptors need to be determined. T here should be a minimum and a maximum loss specified for the bulkhead connection. Avago Technologies specifies the loss of a bulkhead connection as a minimum of 0.7 dB and a maximum of .8 dB. As you increase the num-ber of bulkhead connections, the range of loss increases as does the magnitude of the losses. It is important to remember that the range of loss is just as important as the magnitude of the loss.The total loss in a system is the sum of the individual losses due to attenuation and connectors. It is important to calculate both the minimum and the maximum losses of the system due to attenuation and connectors. A wide range of losses results in a wide range of input power at the receiver. This places greater requirements on the dynamic range of the receiver.Table shows the results of calculating the minimum and maximum losses for a m link of standard cable with two bulkhead connections.You can see that even for this relatively short link, there is over dB difference between the minimum and maxi-mum losses.HFBR- X ZTable 2. Example Loss CalculationAttenuation Loss - dB min.max.loss/meter 0. 9 0.4 total 0.9.Bulkhead Connection Loss - dB min. max.loss/bulkhead 0.7 .8total .4 .6System Loss - dB min. max.total . 7.7 = αmin=αmaxLink DesignThe fundamental requirement in the design of a fiber-optic link is to ensure that the receiver gets the proper amount of light. As mentioned earlier, this actually plac-es three requirements on the design:For a high output voltage,. input power must be LESS than the maximum P R(H).For a low output voltage,. input power must be GREATER than the minimum P R(L), . input power must be LESS than the maximum P R(L).The first requirement is usually easy to meet: just ensure that the LED drive current is below about 0 µA, or that the forward voltage drop of the LED is less than about .0 V.The second requirement defines the underdrive, or sen-sitivity, limit of the receiver. You must ensure that the receiver has enough input power. This requires that the minimum transmitter coupled power minus the maxi-mum system losses be GREATER than the minimum P R(L). In equation form:P Tmin – αmax > P R(L)min .You should start your design with the transmitter drive current at the maximum recommended current of 60 mA, and decrease it later on in the design if required. Re-member to use the maximum link length when calculat-ing the maximum system losses.Another way of looking at the same requirement is in terms of an optical power budget (OPB). The opti-cal power budget is how much optical power you can“spend” on losses in your system; it is defined as the dif-ference between the minimum transmitted power and the minimum P R(L):OPB = P Tmin – P R(L)minYour total system losses must then be less than the opti-cal power budget:αmax < OPB.You may want to include a safety or power margin (PM) in your design. This margin is included to account for any decreases in the received optical power over the lifetime of the link. The received power may decrease over time due to increases in attenuation of the fiber, due to optical contamination of the connectors or active components, or due to a drop in the output power of the transmitter. If you include a power margin in your calculations, your system losses plus the power margin must be less than the optical power budget:αmax + PM < OPB.A typical power margin is around dB; choose a larger margin for harsh environments and a smaller margin for more benign environments. For example, if your maxi-mum system losses are dB and you want a power mar-gin o f d B, t hen y ou m ust h ave a n o ptical p ower b udget o f greater than dB. As another example, if you have an op-tical power budget of 0 dB and you want a power margin of dB, then your maximum system losses must be less than 7 dB.To calculate the minimum allowable transmitter drive current, determine if there is any budget left over after subtracting system losses and the power margin. This is the amount that you can decrease the transmitter out-put power by decreasing the drive current:Remaining budget = OPB – (αmax + PM).As an example, let’s assume we have a 40 kBd m link with standard cable, bulkhead connections, and a power margin of dB. We have already calculated the maximum losses for this system:Maximum system losses: αmax = 7.7 dB.With a power margin of dB, the optical pow-er budget, OPB, must be greater than 7.7 dB + dB = 0.7 dB, or 0.7 dB < OPB.The 40 kBd transmitter can couple a minimum power of - .6 dBm over temperature at 60 mA, and the receiver has a minimum P R(L) of - 9 dBm. Therefore the optical power budget is given by:OPB = - .6 dBm - (- 9 dBm) = .4 dB.There is plenty of power budget to cover the system losses and power margin. To determine the minimum transmitter drive current, determine the remaining bud-get:Remaining budget = .4 dB - (7.7 dB + dB) = 4.6 dB.This is how much we can decrease the transmitter out-put power and still guarantee that we will not under-drive the receiver. According to Figure 8, decreasing the drive current to about 4 mA will drop the output power by about the right amount. You can see why we call the 40 kBd link a “low-current” link!So far, we’ve covered the first two requirements for de-signing a fiber-optic link. The third requirement defines the overdrive limit of the receiver; you must ensure that the receiver does not get too much power. In other words, the maximum possible received optical power, which equals the maximum transmitter power minus the minimum system losses, must be LESS than the max-imum P R(L). In equation form:P Tmax – αmin < P R(L)maxRemember to use the shortest link length for calculating the minimum system losses.If the received optical power is too high, then the trans-mitter coupled power must be decreased by decreasing the drive current. To calculate the maximum allowable transmitter drive current, first determine how far above P R(L)max the received power is, and then decrease the transmitter output power by that much:Amount of decrease = (P Tmax - αmin ) - P R(L)maxLet’s use our previous example to illustrate. We have al-ready calculated the minimum system losses:Minimum system losses: αmin = . dB.The 40 kBd transmitter can couple a maximum power of -4. dBm at 60 mA, and the receivcr has a maximum P R(L) of - .7 dBm. First determine the maximum possible re-ceived power:-4. dBm - . dB = -6.8 dBm.This is above the overdrive limit, P R(L)max , of - .7 dBm. Therefore, we must decrease the transmitter drive cur-rent to decrease the transmitter coupled power:Amount of decrease = -6.8 dBm - ( .7 dBm) = 6.8 dB.According to Figure 8, decreasing the transmitter drivecurrent to about 4 mA will ensure that the receiver is not overdriven. For the example link discussed above, the minimum transmitter drive current is about 4 mA, and the maximum current is about 4 mA. Choosing a current between the minimum and maximum currents will provide additional safety or power margin.After you have determined the minimum transmit-ter drive current from underdrive considerations and the maximum current from overdrive considerations, it might turn out that the maximum is less than the mini-mum (this did not happen, however, in the above exam-ples). This occurs when the maximum possible range, or variation, of received power is greater than the dynamic range of the receiver. If this does occur, you can reduce the possible range of received power by doing any or all of the following:. Use improved cable. Improved cable has a smaller range of attenuation than standard cable and will therefore reduce the possible range of loss in the link. . Reduce the maximum link length.. Restrict the allowable variation in the length of the link. A link that is designed to operate from 0 m to 0 m will have more possible variation in the received power than a link designed to operate from 8 m to 0 m (the above examples dealt with a fixed link length of m).4. Reduce the number of bulkhead connections. There is a possible connection loss variation of ( .8 dB - 0.7dB) = . dB per bulkhead connection.。

Web Authentication Application NoteWeb Authentication Application Note什么是Web认证?在Web认证开启的情况，内网用户通过网页浏览器的登入窗口输入认证信息，其界面如下：当用户输入有效认证信息之后，该主机即拥有访问Internet的权限。

如果用户不能通过认证，路由器会封锁该主机发往Internet的数据。

Web认证设置范例该范例演示了在Vigor 2910上设置Web认证的基本操作。

如果要了解有关Web认证的更多选项的功能，请参考Web认证选项功能介绍一节。

1. 按照如下方式连接设备:2. 各设备的IP地址配置如下:• Vigor 2910 LAN口: 192.168.1.1/24• Vigor 2910 WAN口: 172.17.1.128/24, Gateway: 172.17.1.1• 主机: 192.168.1.10/24, Gateway: 192.168.1.1• 也可以在主机上设置DHCP来从2910上自动获取一个IP地址。

提示: 上述IP地址仅作示例用。

请按照实际网络结构来配置IP地址。

3. 登录到Vigor 2910的Web管理界面，并进入Web Authentication页面:在Account s_etting中，选择Common Account并配置好用户名密码。

此处设置为draytek/draytek。

点击OK以保存设置。

4. 在内部主机上，打开网页浏览器:• 输入任意网址进行浏览，比如• 此时Vigor 2910不会显示该网页的内容，而是显示Web认证的欢迎页面。

默认的欢迎页面如下:• 点击Here进入认证界面。

• 如果使用IE浏览器，可能会遇到如下的安全提醒(跟浏览器的安全设置相关):• 当看到该提示时，点击Yes。

• 如果使用Firefox浏览器，会得到如下的安全提醒(跟浏览器的安全设置相关):• 当看到该提示时，点击Yes。

Page 1NTi Audio 信号发生器 MR-PRO 可以产生 1-10 Hz 的低频正弦信号，正弦信号的分辨率为1Hz。

这些测试信号一般会在研究低频振荡（如开动的振动源）或地震波中应用到。

本应用指南将详细描述怎么样利用 MR-PRO 来进行振动校准的应用。

信号发生器产生 1-10 Hz 范围内的低失真测试信号。

这些测试信号主要用来驱动振动振荡器和振动传感器的校准。

振荡器和振动传感器一般用在汽车、航空以及机械行业。

1.振动传感器的校准振动传感器一般工作在 1 Hz - 20 kHz 范围内。

为了校准振动加速度，振动传感器的灵敏度需要精确到 mV/g 或 pC/g。

另外，振幅-频率响应应该被记录下来并且产生平坦度公差，符合厂商的规格。

便携式信号发生器 MR-PRO 是理想的测试信号源，它可以提供在1 Hz-20 kHz 范围内精确的测试信号来进行震荡传感器的校准。

信号发生器驱动振荡器，一个宽带电压表读取振动传感器的输出信号的电平（或者利用 NTi Audio Acoustilyzer 来量测振动频率和电平）MR- PRO 振荡器测试配置:用 MR-PRO 与 AL1 校正振动传感器振动测试 震荡器与振动传感器的校准NTI AGIm alten Riet 102 9494 Schaan Liechtenstein, Europe Phone +423 239 60 60 Fax +423 239 60 89 ******************NTI Americas Inc.PO Box 231027Tigard, Oregon 97281USAPhone +1 503 684 7050Fax +1 503 684 7051**********************所有信息若更改不另行通知. AL1,MiniLINK,MR-PRO 为 NTI AG, 的注册商标.NTI Japan Ltd.Ryogokusakamoto Bldg. 1-8-4Ryogoku, 130-0026 Sumida-kuTokyo, JapanPhone +81 3 3634 6110Fax +81 3 3634 6160*******************NTI 中国恩缇艾音频设备技术(苏州)有限公司中国苏州市新区滨河路1388号X2创意街区6幢 3A 722室电话: +86 - 512 6802 0075传真: +86 - 512 6802 0097*******************如何测量传感器的灵敏度？•将 MR-PRO 的输出频率调到 159.2Hz(=1000rad/s, 典型校准频率)。

全球定位系统应用说明1简介1.1概述本文给出了sim7100 GPS功能的使用。

用户可以得到关于sim7100 GPS /A-GPS功能有用的信息通过这个文件迅速。

全球定位系统的功能是提供在命令格式，他们是专为客户设计他们的全球定位系统应用程序很容易。

用户可以访问这些命令通过USB接口，GPS在与sim7100模块通信。

SIM7100 GPS特征：●支持S-GPS和A-GPS功能。

●支持GLONASS功能。

●支持单机模式，MS基础模式和MS辅助模式●支持冷启动和热启动。

●支持NMEA-0183标准的一个子集。

●支持NMEA句子NMEA端口输出。

●GPS支持（用户平面）和CP（控制平面）的方法。

●MS辅助模式支持单一固定；MS为基础的模式支持连续固定。

●如果有必要的话，支持证书。

支持GPS模块上电时自动启动，它仅支持单机模式1.2全球定位系统模式介绍在辅助模式下，当一个定位的请求发出时，有效的网络信息被提供给位置服务器，并援助来自位置服务器的请求。

位置服务器向手机发送辅助信息。

手机/移动设备测量的GPS观测值给位置服务器提供GPS测量与有效网络数据（对于给定的空中接口技术）。

位置服务器然后计算定位信息，并把结果返回到请求的实体。

在以微软为基础的模式下，位置服务器所提供的辅助数据不仅包括协助手机测量卫星信号所需的信息，还包括计算手机位置所需的信息。

因此，并不是提供全球定位系统测量值和可用的网络数据回到位置服务器，而是移动计算手机上的位置，并将结果传递给请求的实体。

在独立模式下，手机直接从GPS和GLONASS卫星解调数据。

相比辅助模式，这种模式会有点降低冷启动灵敏度，和一个较长的第一次固定时间。

然而，它不需要服务器的交互和工程网络覆盖。

GPS优先于GLONASS，所以如果GPS 具有固定的位置，导航引擎将关闭全球导航卫星系统（GLONASS），以节省电力。

如果你想要GPS和GLONASS的混合，你可以先用AT指令改变模式表1 GPS操作模式1.3.4 gpsonextra辅助文件源和政策高通所产生的援助文件和高通合作伙伴托管。