ADC1204812-Bit Plus Sign 216kHz 8-Channel Sampling Analog-to-Digital ConverterGeneral DescriptionOperating from a single 5V power supply,the ADC12048is a 12bit +sign,parallel I/O,self-calibrating,sampling analog-to-digital converter (ADC)with an eight input fully dif-ferential analog multiplexer.The maximum sampling rate is 216kHz.On request,the ADC goes through a self-calibration process that adjusts linearity,zero and full-scale errors.The ADC12048’s 8-channel multiplexer is software program-mable to operate in a variety of combinations of single-ended,differential,or pseudo-differential modes.The fully differential MUX and the 12-bit +sign ADC allows for the difference between two signals to be digitized.The ADC12048can be configured to work with many popular microprocessors/microcontrollers and DSPs including Na-tional’s HPC family,Intel386and 8051,TMS320C25,Mo-torola MC68HC11/16,Hitachi 64180and Analog Devices ADSP21xx.For complementary voltage references see the LM4040,LM4041or LM9140.Featuresn 8-channel programmable Differential or Single-Ended multiplexern Programmable Acquisition Times and user-controllable Throughput Ratesn Programmable data bus width (8/13bits)n Built-in Sample-and-Holdn Programmable Auto-Calibration and Auto-Zero cycles n Low power standby mode nNo missing codesKey Specifications(f CLK =12MHz)n Resolution12-bits +sign n 13-bit conversion time 3.6µs,maxn 13-bit throughput rate216ksamples/s,minn Integral Linearity Error (ILE)±1LSB,max n Single Supply +5V ±10%n V IN RangeGND to V A +n Power consumption —Normal operation 34mW,max —Stand-by mode75µw,maxApplicationsn Medical instrumentation n Process control systems n Test equipment n Data logging nInertial guidanceBlock DiagramTRI-STATE ®is a registered trademark of National Semiconductor Corporation.DS012387-1April 2000ADC1204812-Bit Plus Sign 216kHz 8-Channel Sampling Analog-to-Digital Converter©2000National Semiconductor Corporation Connection DiagramsOrdering InformationIndustrial Temperature RangePackage−40˚C ≤T A ≤+85˚CADC12048CIV PLCC ADC12048CIVF PQFP ADC12048EVALEvaluation boardPin DescriptionPLCC Pkg.PQFP Pkg.Pin NameDescriptionPin Number Pin Number644CH0The eight analog inputs to the Multiplexer.Active channels are selected based on the contents of bits b3–b0of the Configuration register.Refer to section titled MUX for more details.71CH182CH293CH3159CH41610CH51711CH61812CH7148COM This pin is another analog input pin used as a pseudo ground when the multiplexer is configured in single-ended mode.137V REF +Positive reference input.The operating voltage range for this input is 1V ≤V REF +≤V A +(see Figure 3and 4).This pin should be bypassed to AGND at least with a parallel combination of a 10µF and a 0.1µF (ceramic)capacitors.The capacitors should be placed as close to the part as possible.PLCC PackageDS012387-2Order Number ADC12048CIV See NS Package Number V44APQFP PackageDS012387-3Order Number ADC12048CIVF See NS Package Number VGZ44AA D C 12048 2ADC12048 Pin Description(Continued)PLCC Pkg.PQFP Pkg.Pin Name DescriptionPin Number Pin Number126V REF−Negative reference input.The operating voltage range for this input is0V≤V REF−≤V REF+−1(see Figure3and4).This pin should bebypassed to AGND at least with a parallel combination of a10µF anda0.1µF(ceramic)capacitor.The capacitors should be placed as closeto the part as possible.1913MUX OUT−The inverting(negative)and non-inverting(positive)outputs of themultiplexer.The analog inputs to the MUX selected by bits b3–b0of2115MUX OUT+the Configuration register appear at these pins.2014ADCIN−ADC inputs.The inverting(negative)and non-inverting(positive)inputsinto the ADC.2216ADCIN+2418WMODE The logic state of this pin at power-up determines which edge of thewrite signal(WR)will latch in data from the data bus.If tied low,theADC12048will latch in data on the rising edge of the WR signal.If tiedto a logic high,data will he latched in on the falling edge of the WRsignal.The state of this pin should not be changed after power-up.2519SYNC The SYNC pin can be programmed as an input or an output.TheConfiguration register’s bit b8controls the function of this pin.Whenprogrammed as an input pin(b8=1),a rising edge on this pin causesthe ADC’s sample-and-hold to hold the analog input signal and beginconversion.When programmed as an output pin(b8=0),the SYNCpin goes high when a conversion begins and returns low whencompleted.26–3120–25D0–D513-bit Data bus of the ADC12048.D12is the most significant bit andD0is the least significant.The BW(bus width)bit of the Configurationregister(b12)selects between an8-bit or13-bit data bus width.Whenthe BW bit is cleared(BW=0),D7–D0are active and D12–D8are34–4029–34D6–D12always in TRI-STATE.When the BW bit is set(BW=1),D12–D0areactive.4337CLK The clock input pin used to drive the ADC12048.The operating rangeis0.05MHz to12MHz.4438WR WR is the active low WRITE control input pin.A logic low on this pinand the CS will enable the input buffers of the data pins D12–D0.Thesignal at this pin is used by the ADC12048to latch in data on D12–D0.The sense of the WMODE pin at power-up will determine which edgeof the WR signal the ADC12048will latch in data.See WMODE pindescription.139RD RD is the active low read control input pin.A logic low on this pin andCS will enable the active output buffers to drive the data bus.240CS CS is the active low Chip Select input ed in conjunction with theWR and RD signals to control the active data bus input/output buffersof the data bus.341RDY RDY is an active low output pin.The signal at this pin indicates when arequested function has begun or ended.Refer to section FunctionalDescription and the digital timing diagrams for more detail.442STDBY This is the standby active low output pin.This pin is low when theADC12048is in the standby mode and high when the ADC12048is outof the standby mode or has been requested to leave the standby mode.104V A+Analog supply input pin.The device operating supply voltage range is+5V±10%.Accuracy is guaranteed only if the V A+and V D+areconnected to the same potential.This pin should be bypassed to AGNDwith a parallel combination of a10µF and a0.1µF(ceramic)capacitor.The capacitors should be placed as close to the supply pins of the partas possible.3Pin Description(Continued)PLCC Pkg.PQFP Pkg.Pin Name DescriptionPin Number Pin Number115AGNDAnalog ground pin.This is the device’s analog supply groundconnection.It should be connected through a low resistance and low inductance ground return to the system power supply.32and 4126and 35V D +Digital supply input pins.The device operating supply voltage range is +5V ±10%.Accuracy is guaranteed only if the V A +and V D +are connected to the same potential.This pin should be bypassed to DGND with a parallel combination of a 10µF and a 0.1µF (ceramic)capacitor.The capacitors should be placed as close to the supply pins of the part as possible.33and 4227and 36DGNDDigital ground pin.This is the device’s digital supply ground connection.It should be connected through a low resistance and low inductance ground return to the system power supply.A D C 12048 4Absolute Maximum Ratings(Notes1,2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage(V A+and V D+) 6.0V Voltage at all Inputs−0.3V to V++0.3V |V A+−V D+|300mV |AGND−DGND|300mV Input Current at Any Pin(Note3)±30mA Package Input Current(Note3)±120mA Power Dissipation(Note4)at T A=25˚C875mW Storage Temperature−65˚C to+150˚C Lead TemperatureVF PackageVapor Phase(60sec.)210˚C Infared(15sec.)220˚C V Package,Infared(15sec.)300˚C ESD Susceptibility(Note5) 3.0kVOperating Ratings(Notes1,2,6,7,8,9)Temperature Range(T min≤T A≤T max)−40˚C≤T A≤85˚C Supply VoltageV A+,V D+ 4.5V to5.5V |V A+−V D+|≤100mV |AGND−DGND|≤100mV V IN Voltage Rangeat all Inputs GND≤V IN≤V A+ V REF+Input Voltage1V≤V REF+≤V A+ V REF−Input Voltage0≤V REF−≤V REF+−1V V REF+−V REF−1V≤V REF≤V A+ V REF Common Mode(Note16)0.1V A+≤V REFCM≤0.6V A+Converter DC CharacteristicsThe following specifications apply to the ADC12048for V A+=V D+=5V,V REF+=4.096V,V REF−=0.0V,12-bit+sign conver-sion mode,f CLK=12.0MHz,R S=25Ω,source impedance for V REF+and V REF−≤1Ω,fully differential input with fixed2.048V common-mode voltage(V INCM),and minimum acquisition time,unless otherwise specified.Boldface limits apply for T A=T J =T MIN to T MAX;all other limits T A=T J=25˚CSymbol Parameter Conditions Typical Limits Unit(Note10)(Note11)(Limit) Resolution with No MissingCodesAfter Auto-Cal13Bits(max)ILE Integral Linearity Error After Auto-Cal(Notes12,17)±0.6±1LSB(max)DNL Differential Non-Linearity After Auto-Cal±1LSB(max) Zero Error After Auto-Cal(Notes13,17)V INCM=5.0V±5.5LSB(max)V INCM=2.048V±2.5LSB(max)V INCM=0V±5.5LSB(max) Positive Full-Scale Error After Auto-Cal(Notes12,17)±1.0±2.5LSB(max)Negative Full-Scale Error After Auto-Cal(Notes12,17)±1.0±2.5LSB(max)DC Common Mode Error After Auto-Cal(Note14)±2±5.5LSB(max)TUE Total Unadjusted Error After Auto-Cal(Note18)±1LSB Power Supply CharacteristicsThe following specifications apply to the ADC12048for V A+=V D+=5V,V REF+=4.096V,V REF−=0.0V,12-bit+sign conver-sion mode,f CLK=12.0MHz,R S=25Ω,source impedance for V REF+and V REF−≤1Ω,fully differential input with fixed2.048V common-mode voltage,and minimum acquisition time,unless otherwise specified.Boldface limits apply for T A=T J=T MIN to T MAX;all other limits T A=T J=25˚CSymbol Parameter Conditions Typical Limits Unit(Note10)(Note11)(Limit)PSS Power Supply Sensitivity V D+=V A+=5.0V±10%(Note15)Zero Error V REF+=4.096V±0.1LSBFull-Scale Error V REF−=0V±0.5LSBLinearity Error±0.1LSBADC120485Power Supply Characteristics(Continued)The following specifications apply to the ADC12048for V A +=V D +=5V,V REF +=4.096V,V REF −=0.0V,12-bit +sign conver-sion mode,f CLK =12.0MHz,R S =25Ω,source impedance for V REF +and V REF −≤1Ω,fully differential input with fixed 2.048V common-mode voltage,and minimum acquisition time,unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C Symbol ParameterConditionsTypical Limits Unit (Note 10)(Note 11)(Limit)I D +V D +Digital Supply CurrentStart Command (Performing aconversion)with SYNC configured as an input and driven with a 214kHz signal.Bus width set to 13.f CLK =12.0MHz,Reset Mode 850µA f CLK =12.0MHz,Conversion2.452.8mA (max)I A +V A +Analog Supply CurrentStart Command (Performing aconversion)with SYNC configured as an input and driven with a 214kHz signal.Bus width set to 13.f CLK =12.0MHz,Reset Mode 2.3mA f CLK =12.0MHz,Conversion2.34.0mA (max)I STStandby Supply Current Standby Mode (I D ++I A +)f CLK =Stopped 515µA (max)f CLK =12.0MHz100120µA (max)Analog MUX Inputs CharacteristicsThe following specifications apply to the ADC12048for V A +=V D+=5V,V REF +=4.096V,V REF −=0.0V,12-Bit +sign conver-sion mode,f CLK =12.0MHz,R S =25Ω,source impedance for V REF +and V REF +≤1Ω,fully differential input with fixed 2.048V common-mode voltage,and minimum acquisition time,unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C Symbol ParameterConditionsTypical Limits Unit (Note 10)(Note 11)(Limit)I ON MUX ON Channel Leakage CurrentON Channel =5V,OFF Channel =0V 0.05 1.0µA (min)ON Channel =0V,OFF Channel =5V −0.05−1.0µA (max)I OFF MUX OFF Channel Leakage CurrentON Channel =5V,OFF Channel =0V 0.05 1.0µA (min)ON Channel =0V,OFF Channel =5V−0.05−1.0µA (max)I ADCIN ADCIN Input Leakage Current 0.05 2.0µA (max)R ONMUX On ResistanceV IN =2.5V 310500Ω(max)MUX Channel-to-Channel R ON MatchingV IN =2.5V±20%ΩC MUX MUX Channel and COM Input Capacitance10pF C ADCADCIN Input Capacitance70pF C MUXOUT MUX Output Capacitance20pFReference InputsThe following specifications apply to the ADC12048for V A +=V D +=5V,V REF +=4.096V,V REF −=0.0V,12-bit +sign con-version mode,f CLK =12.0MHz,R S =25Ω,source impedance for V REF +and V REF −≤1Ω,fully differential input with fixed 2.048V common-mode voltage,and minimum acquisition time,unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C Symbol ParameterConditionsTypical Limits Unit (Note 10)(Note 11)(Limit)I REFReference Input CurrentV REF +4.096V,V REF−=0V Analog Input Signal:1kHz 145µA (Note 20)80kHz136µA C REFReference Input Capacitance85pFA D C 12048 6Digital Logic Input/Output CharacteristicsThe following specifications apply to the ADC12048for V A+=V D+=5V,V REF+=4.096V,V REF−=0.0V,12-bit+sign con-version mode,f CLK=12.0MHz,R S=25Ω,source impedance for V REF+and V REF−≤1Ω,fully differential input with fixed2.048V common-mode voltage,and minimum acquisition time,unless otherwise specified.Boldface limits apply for T A=T J =T MIN to T MAX;all other limits T A=T J=25˚CSymbol Parameter Conditions Typical Limits Unit(Note10)(Note11)(Limit) V IH Logic High Input Voltage V A+=V D+=5.5V 2.0V(min) V IL Logic Low Input Voltage V A+=V D+=4.5V0.8V(max) I IH Logic High Input Current V IN=5V0.035 2.0µA(max) I IL Logic Low Input Current V IN=0V−0.035−2.0µA(max) V OH Logic High Output Voltage V A+=V D+=4.5V2.4V(min)I OUT=−1.6mAV OL Logic Low Output Voltage V A+=V D+=4.5V0.4V(max)I OUT=1.6mAI OFF TRI-STATE®OutputLeakage Current V OUT=0VV OUT=5V±2.0µA(max)C IN D12–D0InputCapacitance10pFConverter AC CharacteristicsThe following specifications apply to the ADC12048for V S+=V D+=5V,V REF+=4.096V,V REF−=0.0V,12-bit+sign con-version mode,f CLK=12.0MHz,R S=25Ω,source impedance for V REF+and V REF−≤1Ω,fully differential input with fixed 2.048V common-mode voltage,and minimum acquisition time,unless otherwise specified.Boldface limits apply for T A=T J=T MIN to T MAX;all other limits T A=T J=25˚CSymbol Parameter Conditions Typical Limits Unit(Note10)(Note11)(Limit) t Z Auto Zero Time7878clks+120ns clks(max) t CAL Full Calibration Time49464946clks+120ns clks(max) CLK Duty Cycle50%40%(min)60%(max) t CONV Conversion Time Sync-Out Mode4444clks(max)t AcqSYNCOUT Acquisition Time(Programmable)Minimum for13Bits99clks+120ns clks(max) Maximum for13Bits7979clks+120ns clks(max)Digital Timing CharacteristicsThe following specifications apply to the ADC12048,13-bit data bus width,V A+=V D+=5V,f CLK=12MHz,t f=3ns and C L=50pF on data I/O linesSymbol Parameter Conditions Typical Limits Units(Note10)(Note11)(Limit)t TPR Throughput Rate Sync-Out Mode(SYNC Bit=“0”)9Clock Cycles ofAcquisition Time222kHzt CSWR Falling Edge of CS to Falling Edge of WR0nst WRCS Active Edge of WR to Rising Edge of CS0nst WR WR Pulse Width2030ns(min)t WRSETFalling Write Setup Time WMODE=“1”20ns(min)t WRHOLDFalling Write Hold Time WMODE=“1”5ns(min)t WRSETRising Write Setup Time WMODE=“0”20ns(min)t WRHOLDRising Write Hold Time WMODE=“0”5ns(min)t CSRD Falling Edge of CS to Falling Edge of RD0nst RDCS Rising Edge of RD to Rising Edge of CS0nst RDDATA Falling Edge of RD to Valid Data8-Bit Mode(BW Bit=“0”)4058ns(max)ADC120487Digital Timing Characteristics(Continued)The following specifications apply to the ADC12048,13-bit data bus width,V A +=V D +=5V,f CLK =12MHz,t f =3ns and C L =50pF on data I/O linesSymbol ParameterConditionsTypical Limits Units (Note 10)(Note 11)(Limit)t RDDATA Falling Edge of RD to Valid Data 13-Bit Mode (BW Bit =“1”)2644ns (max)t RDHOLD Read Hold Time2332ns (max)t RDRDY Rising Edge of RD to Rising Edge of RDY2438ns (max)t WRRDY Active Edge of WR to Rising Edge of RDYWMODE =“1”4265ns (max)t STNDBYActive Edge of WR to Falling Edge of STDBYWMODE =“0”.Writing the Standby Command into the Configuration Register 200230ns (max)t STDONEActive Edge of WR to Rising Edge of STDBYWMODE =“0”.Writing the RESET Command into the Configuration Register 3045ns (max)t STDRDYActive Edge of WR to Falling Edge of RDYWMODE =“0”.Writing the RESET Command into the Configuration Register1.42.5ms (max)t SYNCMinimum SYNC Pulse Width510ns (min)Notes on SpecificationsNote 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is functional,but do not guarantee specific performance limits.For guaranteed specifications and test conditions,see the Electrical Characteristics.The guaranteed specifications apply only for the test conditions listed.Some performance characteristics may degrade when the device is not operated under the listed test condi-tions.Note 2:All voltages are measured with respect to GND,unless otherwise specified.Note 3:When the input voltage (V IN )at any pin exceeds the power supply rails (V IN <GND or V IN >(V A +or V D +)),the current at that pin should be limited to 30mA.The 120mA maximum package input current limits the number of pins that can safely exceed the power supplies with an input current of 30mA to four.Note 4:The maximum power dissipation must he derated at elevated temperatures and is dictated by T Jmax ,(maximum junction temperature),θJA (package junc-tion to ambient thermal resistance),and T A (ambient temperature).The maximum allowable power dissipation at any temperature is P Dmax =(T Jmax −T A )/θJA or the number given in the Absolute Maximum Ratings,whichever is lower.For this device,T Jmax =150˚C,and the typical thermal resistance (θJA )of the ADC12048in the V package,when board mounted,is 55˚C/W,and in the VF package,when board mounted,is 67.8˚C/W.Note 5:Human body model,100pF discharged through 1.5k Ωresistor.Note 6:Each input and output is protected by a nominal 6.5V breakdown voltage zener diode to GND;as shown below,input voltage magnitude up to 0.3V above V A +or 0.3V below GND will not damage the ADC12048.There are parasitic diodes that exist between the inputs and the power supply rails and errors in the A/D conversion can occur if these diodes are forward biased by more than 50mV.As an example,if V A +is 4.50V DC ,full-scale input voltage must be ≤4.55V DC to ensure accurate conversions.Note 7:V A +and V D +must be connected together to the same power supply voltage and bypassed with separate capacitors at each V +pin to assure conversion/comparison accuracy.Refer to the Power Supply Considerations section for a detailed discussion.Note 8:Accuracy is guaranteed when operating at f CLK =12MHz.Note 9:With the test condition for V REF (V REF +−V REF −)given as +4.096V,the 12-bit LSB is 1.000mV.Note 10:Typicals are at T A =25˚C and represent most likely parametric norm.Note 11:Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).Note 12:Positive integral linearity error is defined as the deviation of the analog value,expressed in LSBs,from the straight line that passes through positive full-scale and zero.For negative integral linearity error,the straight line passes through negative full-scale and zero.DS012387-4A D C 12048 8Notes on Specifications(Continued)Note 13:Zero error is a measure of the deviation from the mid-scale voltage (a code of zero),expressed in LSB.It is the average value of the code transitions be-tween −1to 0and 0to +1(see Figure 8).Note 14:The DC common-mode error is measured with both inputs shorted together and driven from 0V to 5V.The measured value is referred to the resulting out-put value when the inputs are driven with a 2.5V input.Note 15:Power Supply Sensitivity is measured after an Auto-Zero and Auto Calibration cycle has been completed with V A +and V D +at the specified extremes.Note 16:V REFCM (Reference Voltage Common Mode Range)is defined asNote 17:The ADC12048’s self-calibration technique ensures linearity and offset errors as specified,but noise inherent in the self-calibration process will result in a repeatability uncertainly of ±0.20LSB.Note 18:Total Unadjusted Error (TUE)includes offset,full scale linearity and MUX errors.Note 19:The ADC12048parts used to gather the information for these curves were auto-calibrated prior to taking the measurements at each test condition.The auto-calibration cycle cancels any first order drifts due to test conditions.However,each measurement has a repeatability uncertainty error of 0.2LSB.See (Note 17).Note 20:The reference input current is a DC average current drawn by the reference input with a full-scale sinewave input.The ADC12048is continuously con-verting with a throughput rate of 206kHz.Note 21:These typical curves were measured during continuous conversions with a positive half-scale DC input.A 240ns RD pulse was applied 25ns after the RDY signal went low.The data bus lines were loaded with 2HC family CMOS inputs (C L ∼20pF).Note 22:Any other values placed in the command field are meaningless.However,if a code of 101or 110is placed in the command field and the CS,RD and WR go low at the same time,the ADC12048will enter a test mode.These test modes are only to be used by the manufacturer of this device.A hardware power-off and power-on reset must be done to get out of these test modes.Electrical CharacteristicsDS012387-5FIGURE 1.Output Digital Code vs the Operating Input Voltage Range (General Case)ADC120489Electrical Characteristics(Continued)DS012387-6FIGURE 2.Output Digital Code vs the Operating Input Voltage Range for V REF =4.096VDS012387-7FIGURE 3.V REF Operating Range (General Case)A D C 1204810Electrical Characteristics(Continued)DS012387-8FIGURE4.V REF Operating Range for V A=5VDS012387-9FIGURE5.Transfer Characteristic ADC12048Electrical Characteristics(Continued)DS012387-10FIGURE 6.Simplified Error vs Output Code without Auto-Calibration or Auto-Zero CyclesDS012387-11FIGURE 7.Simplified Error vs Output Code after Auto-Calibration CycleDS012387-12FIGURE 8.Offset or Zero Error Voltage (Note 13)A D C 12048Timing DiagramsDS012387-13 FIGURE9.Sync-Out Write(WMODE=1,BW=1),Read and Convert CyclesDS012387-14 FIGURE10.Sync-In Write(WMODE=1,BW=1),Read and Convert Cycles ADC12048Timing Diagrams(Continued)DS012387-46FIGURE 11.Sync-Out Write (WMODE =0,BW =1),Read and Convert CyclesDS012387-47FIGURE 12.Sync-In Write (WMODE =0,BW =1),Read and Convert CyclesA D C 12048Timing Diagrams(Continued)DS012387-48 FIGURE13.Sync-Out Read and Convert Cycles.The MUX channelis the channel selected on the most recent write cycle.DS012387-49 FIGURE14.Sync-In Read and Convert Cycles.The MUX channelis the channel selected on the most recent write cycle.ADC12048Timing Diagrams(Continued)DS012387-50FIGURE 15.8-Bit Bus Read Cycle (Sync-Out)DS012387-51FIGURE 16.8-Bit Bus Read Cycle (Sync-In)A D C 12048Timing Diagrams(Continued)Typical Performance Characteristics(See(Note19),Electrical Characteristic Section)DS012387-15FIGURE17.Write Signal Negates RDY(Writing the Standby,Auto-Cal or Auto-Zero Command)DS012387-16 FIGURE18.Standby and Reset Timing(13-Bit Data Bus Width)Integral Linearity Error(INL) Change vs Clock FrequencyDS012387-17Full-Scale Error Change vsClock FrequencyDS012387-18Zero Error Change vsClock FrequencyDS012387-19ADC12048Typical Performance Characteristics(See (Note 19),Electrical Characteristic Section)(Continued)Integral Linearity Error (INL)Change vs TemperatureDS012387-20Full-Scale Error Change vs TemperatureDS012387-21Zero Error Change vs TemperatureDS012387-22Integral Linearity Error (INL)Change vs Reference VoltageDS012387-23Full-Scale Error Change vs Reference Voltage DS012387-24Zero Error Change vs Reference VoltageDS012387-25Integral Linearity Error (INL)Change vs Supply Voltage DS012387-39Full-Scale Error Change vs Supply Voltage DS012387-40Zero Error Change vs Supply VoltageDS012387-41A D C 12048Typical Performance Characteristics(See(Note21),Electrical Characteristic Section)Supply Currents vsClock FrequencyDS012387-42Reference Currents vsClock FrequencyDS012387-43Analog Supply Currentvs TemperatureDS012387-44Digital Supply Currentvs TemperatureDS012387-45ADC12048Typical Performance Characteristics(See (Note 21),Electrical Characteristic Section)(Continued)Full Scale Differential 1,099Hz Sine Wave InputDS012387-26Full Scale Differential 18,677Hz Sine Wave InputDS012387-27Full Scale Differential 38,452Hz Sine Wave Input DS012387-28Full Scale Differential 79,468Hz Sine Wave InputDS012387-29Half Scale Differential 1kHz Sine Wave Input,f S =153.6kHz DS012387-30Half Scale Differential 20kHz Sine Wave Input,f S =153.6kHzDS012387-31Half Scale Differential 40kHz Sine Wave Input,f S =153.6kHz DS012387-32Half Scale Differential 75kHz Sine Wave Input,f S =153.6kHzDS012387-33A D C 12048ADC12048 Typical Performance Characteristics(See(Note21),Electrical Characteristic Section)(Continued)Register Bit DescriptionCONFIGURATION REGISTER(Write Only)This is a13-bit write-only register that is used to program the functionality of the ADC12048.All data written to the ADC12048willalways go to this register only.The contents of this register cannot be read.MSB LSBb12b11b10b9b8b7b6b5b4b3b2b1b0BW COMMAND FIELD SYNC HB SE ACQ TIME MUX ADDRESSPower on State:0100Hexb3–b0:The MUX ADDRESS bits configure the analog input MUX.They select which input channels of the MUX will connect tothe MUXOUT+and MUXOUT−pins.(Refer to the MUX section for more details on the MUX.)Power-up value is0000.TABLE1.MUX Channel Assignmentb3b2b1b0MUXOUT+MUXOUT−0000CH0CH10001CH1CH00010CH2CH30011CH3CH20100CH4CH50101CH5CH40110CH6CH70111CH7CH61000CH0COM1001CH1COM1010CH2COM1011CH3COM1100CH4COM1101CH5COM1110CH6COM1111CH7COMb5–b4:The ACQ TIME bits select one of four possible acquistion times in SYNC-OUT mode.(Refer to Selectable AcquisitionTime section.)b5b4Clocks009011510471179b6:When the Single-Ended bit(SE bit)is set,conversion results will be limited to positive values only and any negative conver-sion results will appear as a code of zero in the Data register.The SE bit is cleared at power-up.b7:The High Byte bit(HB)is meaningful only in8-bit mode(BW bit b12=“0”)and is a don’t care condition in13-bit mode(BWbit b12=“1”).This bit is used to access the upper byte of the Configuration Register in8-bit mode.When this bit is set and bitb12=0,the next byte written to the ADC12048will program the upper byte of the Configuration register.The HB bit will automati-cally be cleared when data is written to the upper byte of the Configuration register,allowing the lower byte to be accessed withthe next write.The HB bit is cleared at power-up.b8:The SYNC bit.When the SYNC bit is set,the SYNC pin is programmed as an input and the converter is in synchronous mode.In this mode a rising edge on the SYNC pin causes the ADC to hold the input signal and begin a conversion.When b15cleared,the SYNC pin is programmed as an output and the converter is in an asynchronous mode.In this mode the signal at the SYNCpin indicates the status of the converter.The SYNC pin is high when a conversion is taking place.The SYNC bit is set atpower-up.b11–b9:The command field.These bits select the mode of operation of the ADC12048.Power-up value is000.(See(Note22))21。
