AT24c02中文资料

1Features•Low-voltage and Standard-voltage Operation, VCC = 2.7V–5.5V •Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),1024 x 8 (8K), or 2048 x 8 (16K)•Two-wire Serial Interface•Schmitt Trigger, Filtered Inputs for Noise Suppression •Bidirectional Data Transfer Protocol •400 kHz Compatibility•8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes •Partial Page Writes Allowed•Self-timed Write Cycle (5 ms max)•High Reliability–Endurance: One Million Write Cycles –Data Retention: 100 Years –ESD Protection: >3000VDescriptionThe AT24C01A/02SC/04SC/08SC/16SC provide 1024/2048/4096/8192/16384 bits of serial, electrically-erasable, and programmable read-only memory (EEPROM) orga-nized as 128/256/512/1024/2048 words of 8 bits each. The devices are optimized for use in smart card applications where low-power and low-voltage operation may be essential. The devices are available in several standard ISO 7816 smart card modules (see Ordering Information, pages 12–13). All devices are functionally equivalent to Atmel serial EEPROM products offered in standard IC packages (PDIP , SOIC, TSSOP ,MAP), with the exception of the slave address and write protect functions, which are not required for smart card applications.Figure 1. Card Module Contact2AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04Figure 2. Block DiagramPin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.Memory OrganizationAT24C01ASC, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each, the 1K requires a 7-bit data word address for random word addressing.AT24C02SC, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing.Absolute Maximum Ratings*NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings ” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.3AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04AT24C04SC, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing.AT24C08SC, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address random word addressing.AT24C16SC, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address random word addressing.Pin CapacitanceDC CharacteristicsAC CC 2.V IL min and V IH max are reference only and are not tested.AC CharacteristicsTable 2. Pin Capacitance (1)Applicable over recommended operating range from T = 25°C, f = 1.0 MHz, V = +2.7VTable 3. DC Characteristics (1)(1)4AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04A CC (unless otherwise noted)2.This parameter is characterized and is not 100% tested.Device OperationCLOCK AND DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL-low time periods (see Figure 3 on page 5). Data changes during SCL-high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command (see Figure 4 on page 6).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the Stop command will place the EEPROM in a standby power mode (see Figure 4 on page 6).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. Each word requires the receiver to acknowledge that it has received a valid command or data byte. During the transmission of commands from the host to the EEPROM, the EEPROM will send a zero to the host to acknowledge that it has received a valid command byte. This occurs on the ninth clock cycle of the com-mand byte. During read operations, the host will send a zero to the EEPROM to acknowledge that it has received a valid data byte and that it requests the next sequen-tial data byte to be transmitted during the subsequent eight clock cycles. This occurs on the ninth clock cycle of the data byte. If the host does not transmit this acknowledge bit,the EEPROM will disable the read operation and return to standby mode.STANDBY MODE: The AT24C01ASC/02SC/04SC/08SC/16SC feature a low-power standby mode that is enabled upon power-up and after the receipt of the stop bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss, or system reset, any two-wire part can be reset by following these steps:1.Clock up to 9 cycles.2.Look for SDA high in each cycle while SCL is high.3.Create a start condition as SDA is high.Table 4. AC Characteristics (1) (Continued)5AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04Timing DiagramsBus TimingFigure 1. Bus TimingNote:SCL: Serial Clock, SDA: Serial Data I/OWrite Cycle TimingFigure 2. Write Cycle TimingNotes:1.The write cycle time t WR is the time from a valid stop condition of a write sequence tothe end of the internal clear/write cycle.2.SCL: Serial Clock, SDA: Serial Data I/OData ValidityFigure 3.Data Validity6AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04Start and Stop DefinitionFigure 4. Start and Stop DefinitionOutput AcknowledgeFigure 5.Output Acknowledge7AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04Device AddressingThe 1K, 2K, 4K, 8K, and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 6on page 7).The device address word consists of a mandatory “1”, “0”, “1”, “0” sequence for the first four most significant bits as shown. This is common to all the serial EEPROM devices.The next three bits of the device address word are the most significant data word address bits for the AT24C16SC (16K), which requires a total of 11 address bits. The AT24C08SC (8K) requires only 10 total word address bits. The most significant two bits are included in the device address word. The unused bit of the device address word should be set to “0”. The AT24C04SC (4K) requires only nine total data word address bits. The most significant bit is included in the device address word. The two unused bits of the device address word should be set to “0”. The AT24C02SC (2K) and AT24C01ASC (1K) do not require any address bits in the device address word. The three unused bits of the device address word should be set to “0”.The eighth bit of the device address is the read/write operation select bit. A read opera-tion is initiated if this bit is high, and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a “0” (ACK). If a suc-cessful compare is not made, the chip will return to a standby state (NO ACK).Figure 6. Device AddressNote:P0, P1, P2 = Data word address bits8AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04Write OperationsBYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” (ACK) and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0” (ACK) and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condi-tion. At this time the EEPROM enters an internally-timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 7).Figure 7. Byte WritePAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K,and 16K devices are capable of 16-byte page writes.A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 7(1K/2K) or 15 (4K, 8K, 16K) more data words. The EEPROM will respond with a “0”(ACK) after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 8).Figure 8. Page WriteNote:* = DON ’T CARE bit for 1KThe data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address,internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (1K/2K) or 16 (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will “roll over ” and previous data will be overwritten.ACKNOWLEGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-ing a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed9AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04will the EEPROM respond with a “0” (ACK), allowing the read or write sequence to continue.Read OperationsRead operations are initiated the same way as write operations, with the exception that the read/write select bit in the device address word is set to “1”. There are three read operations: current address read, random address read, and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “rollover ” during read is from the last byte of the last memory page to the first byte of the first page. The address “rollover ” during write is from the last byte of the cur-rent page to the first byte of the same page.Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out.The microcontroller does not respond with an input “0” but does generate a following stop condition (refer to Figure 9)Figure 9. Current Address Read.RANDOM READ: A random read requires a “dummy ” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” (NO ACK) but does generate a following stop condition (refer to Figure 10).Figure 10. Random ReadNote:* = DON ’T CARE bit for 1K)10AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “rollover ” and the sequen-tial read will continue. The sequential read operation is terminated when the microcontroller does not respond with a “0” (NO ACK) but does generate a following stop condition (refer to Figure 11).Figure 11.Sequential Read11AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04AT24C01ASC Ordering InformationAT24C02SC Ordering InformationAT24C04SC Ordering InformationAT24C08SC Ordering InformationAT24C16SC Ordering Information12AT24C01ASC/02SC/04SC/08SC/16SC1610B–SEEPR–04/0413AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04Smart Card ModulesDisclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company ’s standard warranty which is detailed in Atmel ’s Terms and Conditions located on the Company ’s web site. The Company assumes no responsibil ity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wit h out notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel ’s products are not auth orized for use as critical components in life support devices or systems.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. 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Features•Low Voltage and Standard Voltage Operation5.0 (V CC = 4.5V to 5.5V)2.7 (V CC = 2.7V to 5.5V)2.5 (V CC = 2.5V to 5.5V)1.8 (V CC = 1.8V to 5.5V)•Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),1024 x 8 (8K) or 2048 x 8 (16K)•2-Wire Serial Interface•Bidirectional Data Transfer Protocol•100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility •Write Protect Pin for Hardware Data Protection•8-Byte Page (1K, 2K), 16-Byte Page (4K, 8K, 16K) Write Modes •Partial Page Writes Are Allowed •Self-Timed Write Cycle (10 ms max)•High ReliabilityEndurance: 1 Million Cycles Data Retention: 100 Years•Automotive Grade and Extended Temperature Devices Available •8-Pin and 14-Pin JEDEC SOIC and 8-Pin PDIP PackagesDescriptionThe AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial elec-trically erasable and programmable read only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C01A/02/04/08/16 is available in space saving 8-pin PDIP, 8-pin and 14-pin SOIC packages and is accessed via a 2-wire serial interface. In addition,the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to5.5V) and 1.8V (1.8V to 5.5V) versions.Pin Configurations8-Pin PDIP8-Pin SOIC14-Pin SOICAT24C01A/02/04/08/16Block Diagram*NOTICE: Stresses beyond those listed under “Absolute Maxi-mum Ratings” may cause permanent damage to the device.This is a stress rating only and functional operation of thedevice at these or any other conditions beyond those indi-cated in the operational sections of this specification is notimplied. Exposure to absolute maximum rating conditionsfor extended periods may affect device reliability. Absolute Maximum Ratings*Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positiveedge clock data into each E2PROM device and negativeedge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for se-rial data transfer. This pin is open-drain driven and may bewire-ORed with any number of other open-drain or opencollector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1and A0 pins are device address inputs that are hard wiredfor the AT24C01A and the AT24C02. As many as eight1K/2K devices may be addressed on a single bus system(device addressing is discussed in detail under the DeviceAddressing section).The AT24C04 uses the A2 and A1 inputs for hard wireaddressing and a total of four 4K devices may be ad-dressed on a single bus system. The A0 pin is a no con-nect.The AT24C08 only uses the A2 input for hardwire ad-dressing and a total of two 8K devices may be addressedon a single bus system. The A0 and A1 pins are no con-nects.The AT24C16 does not use the device address pins whichlimits the number of devices on a single bus to one. TheA0, A1 and A2 pins are no connects.(continued)Applicable over recommended operating range from: T AI = -40°C to +85°C, V CC = +1.8V to +5.5V, T AC = 0°C to +70°C,Note:1.V IL min and V IH max are reference only and are not tested.DC CharacteristicsWRITE PROTECT (WP): The AT24C01A/02/04/16 has a Write Protect pin that provides hardware data protection.The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protectpin is connected to V CC , the write protection feature is en-abled and operates as shown in the following table.Pin Description (Continued)Memory OrganizationAT24C01A, 1K SERIAL E 2PROM: Internally organized with 128 pages of 1-byte each, the 1K requires a 7 bit data word address for random word addressing.AT24C02, 2K SERIAL E 2PROM: Internally organized with 256 pages of 1-byte each, the 2K requires an 8 bit data word address for random word addressing.AT24C04, 4K SERIAL E 2PROM: The 4K is internally or-ganized with 256 pages of 2-bytes each. Random word addressing requires a 9 bit data word address.AT24C08, 8K SERIAL E 2PROM:The 8K is internally or-ganized with 4 blocks of 256 pages of 4-bytes each. Ran-dom word addressing requires a 10 bit data word address.AT24C16, 16K SERIAL E 2PROM: The 16K is internally organized with 8 blocks of 256 pages of 8-bytes each.Random word addressing requires an 11 bit data word ad-dress.Pin Capacitance (1)Note:1. This parameter is characterized and is not 100% tested.AT24C01A/02/04/08/16Note:1. This parameter is characterized and is not 100% tested.Applicable over recommended operating range from T A = -40°C to +85°C, V CC = +1.8V to +5.5V, CL = 1 TTL Gate and100 pF (unless otherwise noted).AC CharacteristicsDevice OperationCLOCK and DATA TRANSITIONS: The SDA pin is nor-mally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as de-fined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the E 2PROM in a standby power mode (refer to Start and Stop Definition timing diagram).ACKNOWLEDGE: All addresses and data words are se-rially transmitted to and from the E 2PROM in 8 bit words.The E 2PROM sends a zero to acknowledge that it has re-ceived each word. This happens during the ninth clock cy-cle.STANDBY MODE: The AT24C01A/02/04/08/16 features a low power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and thecompletion of any internal operations.Bus Timing SCL: Serial ClockSDA: Serial Data I/OWrite Cycle Timing SCL: Serial Clock SDA: Serial Data I/ONote: 1.The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.AT24C01A/02/04/08/16Data ValidityStart and Stop DefinitionOutput AcknowledgeDevice AddressingThe 1K, 2K, 4K, 8K and 16K E2PROM devices all require an 8 bit device address word following a start condition to enable the chip for a read or write operation (refer to Fig-ure 1).The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the E2PROM devices.The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K E2PROM. These 3 bits must compare to their corresponding hard-wired input pins.The 4K E2PROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corre-sponding hard-wired input pins. The A0 pin is no connect. The 8K E2PROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect.The 16K does not use any device address bits but instead the 3 bits are used for memory page addressing. These page addressing bits on the 4K, 8K, and 16K devices should be considered the most significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect.The eighth bit of the device address is the read/write op-eration select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the E2PROM will output a zero. If a compare is not made, the chip will return to a standby state.Write OperationsBYTE WRITE: A write operation requires an 8 bit data word address following the device address word and ac-knowledgement. Upon receipt of this address, the E2PROM will again respond with a zero and then clock in the first 8 bit data word. Following receipt of the 8 bit data word, the E2PROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the E2PROM enters an internally-timed write cycle to the nonvolatile memory. All inputs are disabled during this write cycle and the E2PROM will not respond until the write is complete (refer to Figure 2).PAGE WRITE: The 1K/2K E2PROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are ca-pable of 16-byte page writes.A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the E2PROM acknowledges receipt of the first data word, the microcon-troller can transmit up to seven (1K/2K) or fifteen (4K, 8K, 16K) more data words. The E2PROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop con-dition (refer to Figure 3).The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally incremented following the re-ceipt of each data word. The higher data word address bits are not incremented, retaining the memory page row loca-tion. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data words are transmitted to the E2PROM, the data word address will “roll over” and previous data will be overwrit-ten.ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the E2PROM inputs are dis-abled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the E2PROM respond with a zero allowing the read or write sequence to continue.Read OperationsRead operations are initiated the same way as write op-erations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word ad-dress counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page.Once the device address with the read/write select bit set to one is clocked in and acknowledged by the E2PROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 4).RANDOM READ: A random read requires a “dummy”byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the E2PROM, the micro-(continued) AT24C01A/02/04/08/16Figure 1.Device AddressFigure 2.Byte WriteFigure 3. Page Write(* = DON’T CARE bit for 1K)controller must generate another start condition. The mi-crocontroller now initiates a current address read by send-ing a device address with the read/write select bit high.The E 2PROM acknowledges the device address and seri-ally clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 5).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read.After the microcontroller receives a data word, it responds with an acknowledge. As long as the E 2PROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words.When the memory address limit is reached, the data word address will “roll over” and the sequential read will con-tinue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 6).Read Operations(Continued)Figure 5. Random Read(*= DON’T CARE bit for 1K)Figure 4.Current Address ReadFigure 6. Sequential ReadAT24C01A/02/04/08/16Ordering InformationOrdering InformationOrdering Information。

3.2.5 密码储存电路密码储存电路采用I2C总线at24c02存储芯片存放密码，可实现断电密码不消失，at24c02存储芯片可长期存储信息，可上百万次以上重新擦写。

图3-5 密码储存电路2.4.3 I2C总线密码存储芯片at24c02介绍图2-3 at24c02引脚图（1）引脚功能介绍及相关知识WP：写保护引脚，将该引脚接VCC，E2PROM就实现写保护（只读）。

引脚接地或悬空，可以对器件进行读写操作。

SCL：串行时钟引脚，串行输入输出时该引脚用于输入时钟。

SDA：串行数据输入输出引脚，用来输入输出数据，该引脚为射极开路输出，需接上拉电阻。

（2）I2C总线协议只有总线非忙时才被允许进行数据传送，在传送时，当时钟线为高电平，数据线必须为固定状态，不允许有跳变。

时钟线为高电平时数据线的任何电平变化将被当作总线的启动或停止条件。

（3）起始条件起始调教必须在所有操作命令之前发送。

时钟线保持高电平期间，数据线电平从高到低跳变作为I2C总线的启动信号。

CAT24Cxxx一直监视SDA和SCL电平信号，直到条件满足时才响应。

（4）停止条件时钟线保持高电平期间，数据线电平从低到高跳变作为I2C总线的停止信号。

（5）器件地址的约定主器件在发送启动命令后开始传送数据，主器件发送相应的从器件地址，8位从器件地址的高四位固定为1010，接下来的3位用来定义存储器的地址，对于CAT24C021/022，这三位无意义，对于CAT24C41/042，接下来的2位无意义，第三位是地址高位，CAT24C081/082中，第一位无意义，后两位表示地址高位。

最后一位为读写控制位，“1”表示对从器件进行读写操作，“0”表示写操作。

在主器件发送启动命令和一字节从器件地址后，如果与从器件地址吻合，CAT24C02将发送一个应答信号，然后再根据读/写控制为进行读或写操作。

（6）应答信号每次数据传送成功后，接收器件将发送一个应答信号。

当第九个时钟信号产生时，产生应答型号的器件将SDA下拉为低，通知已经接受到8位数据，接收到起始条件和从器件地址后，CAT24C02发送一个应答信号，如果为写操作，每接收到一个字节数据，CAT24C02发送一个应答信号。

一、EPROM与EEPROM：EPROM（Erasable Programmable Read Only Memory），中文含意为“可擦除可编程只读存储器”。

它是一种可重写的存储器芯片，并且其内容在掉电的时候也不会丢失；换句话说，它是非易失性的。

它通过EPROM编程器进行编程，EPROM编程器能够提供比正常工作电压更高的电压对EPROM编程。

一旦经过编程，EPROM只有在强紫外线的照射下才能够进行擦除。

为了进行擦除，EPROM的陶瓷封装上具有一个小的石英窗口，这个石英窗口一般情况下使用不透明的粘带覆盖，当擦除时将这个粘带揭掉，然后放置在强紫外线下大约20分钟。

主要IC有27XX系列和27CXX系列。

EEPROM（electrically erasable, programmable, read-only ）是一种电可擦除可编程只读存储器，并且其内容在掉电的时候也不会丢失。

在平常情况下，EEPROM与EPROM一样是只读的，需要写入时，在指定的引脚加上一个高电压即可写入或擦除，而且其擦除的速度极快！通常EEPROM芯片又分为串行EEPROM和并行EEPROM两种，串行EEPROM在读写时数据的输入／输出是通过2线、3线、4线或SPI 总线等接口方式进行的，而并行EEPROM的数据输入／输出则是通过并行总线进行的。

主要IC有28XX系列。

二、24c02芯片硬件介绍：1、引脚说明：A0，A1，A2——地址输入引脚，走位硬件寻址的依据，同种芯片可同时连接8片（2^3）；Vcc，Gnd——电源，接地引脚，1.8-5.5vWp——写保护，当Wp接地时，允许对器件的正常读写操作；当Wp接高电平时，写保护，只能进行读操作。

SDA——串行地址/数据输入/输出端口，双向传输，漏极开路，需外接上拉电阻到Vcc（典型阻值为10k）。

SCL——串行时钟输入，高低电平不同状态与SDA配合，执行不同的命令。

2、存储结构：24c02的容量是2k，256字节。

CA T24C 161/162(16K)，CAT24C081 /082(8K) CAT24C041/042(4K)，CAT24C021/022(2K)I2C串行CMOS E2PROM,精确的复位控制器和看门狗定时器控制电路特性•数据线上的看门狗定时器(仅对CA T24Cxxl)籲可编程复位门槛电平籲高数据传送速率为400KHz和I2C总线兼容• 2.7V至6V的工作电压•低功耗CMOS工艺籲16字节页写缓冲区籲片内防误擦除写保护籲高低电平复位信号输出——精确的电源电压监视器——可选择5V、3.3V和3V的复位门槛电平•100万次擦写周期•数据保存可长达100年•8脚DIP或SOIC封装•商业级、工业级和汽车温度范围概述CA T24Cxxx是集E2PROM存储器，复位微控制器和看门狗定时器三种流行功能与一体的芯片。

CAT24C161/162 (16K)，CAT24C081/082 (8K)，CA T24C041/042 (4K)和CAT24C021/022 (2K)以I2C是串行CMOS E2PROM器件。

釆用CMOS工艺大降低了器件的功耗。

CA T24Cxxx 另一特点是16字节的页写缓冲区，提供8脚DIP和SOIC 封装。

CA T24Cxxx的复位功能和看门狗定时器功能保证系统出现故障的时候能给CPU —个复位信号。

CA T24Cxxx 的2脚输出低电平复位信号，7脚输出高电平复位信号。

CAT24Cxxl看狗溢出信号从SDA脚输出。

CAT24Cxx2不具备看门狗功能。

绝对最大参数工作温度：-55°C〜125°C贮存温度：-65°C〜15°C各管脚承受对地电压：-2.0V〜Vcc+2.0V VCC对地电压范围：-2.0V〜7.0V 最大功耗： 1.0W管脚焊接温度(10S): 300 °C输出短路电流：100mA管脚配置]V C C ]RESET方框图表一直流操作特性表二上电时序管脚介绍WP：写保护将该管脚接Vcc，E2PRON就实现写保护（只读)。

AT24C02芯片使用介绍AT24C02简介AT24C02是一个2K 位串行CMOS E2PROM ，内部含有256个8位字节，有一个16字节页写缓冲器。

该器件通过IIC 总线接口进行操作，有专门的写保护功能。

应用于AT24C02制造过程的先进CMOS 技术实质上减少了器件的功耗。

AT24C02特性1、采用I 2C 总线传输数据。

2、工作电压范围：1.8V ～6.0V 。

3、采用低功耗CMOS 技术制造。

4、当WP 为高电平时，AT24C02进入写保护状态。

5、页写缓冲器。

6、自定时擦写周期。

7、1,000,000 编程/擦除周期。

8、寿命长，可保存数据100 年。

9、2种封装：8脚DIP SOIC 或TSSOP 封装。

10、温度范围：商业级、工业级和汽车级。

AT24C02管脚描述1、SCL 串行时钟管脚AT24C02串行时钟输入管脚用于产生该器件所有数据发送或接收的时钟，SCL 串行时钟管脚是一个输入管脚。

2、SDA 串行数据AT24C02的双向串行数据管脚SDA，用于该器件所有数据的发送或接收。

SDA 管脚是一个开漏输出管脚。

3、A0、A1、A2 器件地址输入端这3个输入管脚用于多个器件级联时设置器件地址，当这些管脚悬空时默认值为0。

AT24C02 最大可级联8个器件。

如果只有一个AT24C02被总线寻址，这三个地址输入脚（A0、A1、A2 ）可悬空或连接到Vss 或 GND。

4、WP 写保护如果WP管脚连接到Vcc，AT24C02中所有的内容都被写保护只能读。

当WP管脚连接到Vss 或 GND 或悬空时，允许AT24C02器件进行正常的读/写操作。

5、V管脚CC管脚接+1.8V～+6.0V 工作电压的正极。

AT24C02的VCC6、V SS 管脚AT24C02的V SS 管脚接+1.8V ～+6.0V 工作电压的负极（即GND ）。

AT24C02的器件寻址AT24C02的芯片地址为1010，其地址控制字格式为1010A2A1A0R/W 。

325密码储存电路密码储存电路采用l2C总线at24c02存储芯片存放密码，可实现断电密码不消失，at24c02存储芯片可长期存储信息，可上百万次以上重新擦写。

2.4.3 I 2C总线密码存储芯片at24c02介绍S-I&ad TSSOP图2-3 at24c02 引脚图（1）引脚功能介绍及相关知识WP写保护引脚，将该引脚接VCC U PROM就实现写保护（只读）。

引脚接地或悬空，可以对器件进行读写操作。

SCL串行时钟引脚，串行输入输出时该引脚用于输入时钟。

SDA串行数据输入输出引脚，用来输入输出数据，该引脚为射极开路输出，需接上拉电阻。

（2） |2C总线协议只有总线非忙时才被允许进行数据传送，在传送时，当时钟线为高电平，数据线必须为固定状态，不允许有跳变。

时钟线为高电平时数据线的任何电平变化将被当作总线的启动或停止条件。

（3）起始条件起始调教必须在所有操作命令之前发送。

时钟线保持高电平期间，数据线电平从高到低跳变作为I2C总线的启动信号。

CAT24Cxx＞一直监视SDA和SCL电平信号，直到条件满足时才响应。

(4) 停止条件时钟线保持高电平期间，数据线电平从低到高跳变作为l 2C 总线的停止信号。

(5) 器件地址的约定主器件在发送启动命令后开始传送数据，主器件发送相应的从器件地址， 8位从器件地址的高四位固定为1010,接下来的3位用来定义存储器的地址，对 于CAT24C021/022这三位无意义，对于 CAT24C41/042接下来的2位无意义， 第三位是地址高位，CAT24C081/082中，第一位无意义，后两位表示地址高位。

最后一位为读写控制位，“ 1”表示对从器件进行读写操作，“ 0 ”表示写操 作。

在主器件发送启动命令和一字节从器件地址后，如果与从器件地址吻合， CAT24C02各发送一个应答信号，然后再根据读/写控制为进行读或写操作。

(6) 应答信号每次数据传送成功后，接收器件将发送一个应答信号。

24c02读写—相关资料AT24C02是美国Atmel公司的低功耗CMOS型E2PROM，内含256×8位存储空间，具有工作电压宽(2.5～5.5 V)、擦写次数多(大于10 000次)、写入速度快(小于10 ms)、抗干扰能力强、数据不易丢失、体积小等特点。

而且他是采用了I2C总线式进行数据读写的串行器件，占用很少的资源和I／O线，并且支持在线编程，进行数据实时的存取十分方便。

1 AT24C02的引脚功能AT24C02引脚如图1所示。

他的的1、2、3脚是3根地址线，用于确定芯片的硬件地址。

第8脚和第4脚分别为正、负电源。

第5脚SDA为串行数据输入／输出，数据通过这根双向I2C总线串行传送。

第6脚SCL为串行时钟，SDA和SCL为漏极开路端，在实际的应用当中都需要和正电源间各接一个5.1 kΩ的电阻上拉。

第7脚为WP写保护端，接地时允许芯片执行一般的读写操作；接正电源时只允许对器件进行读操作。

2 AT24C02的内部结构图2为AT24C02的内部结构图。

启动、停止逻辑单元 接收数据引脚SDA上的电平信号，判断是否进行启动和停止操作串行控制逻辑单元 根据SCL，SDA电平信号以及“启动、停止逻辑”部件发出的各种信号进行区分，并排列出有关的“寻址”、“读数据”和“写数据”等逻辑，将他们传送到相应的操作单元。

例如：当操作命令为“寻址”时候，他将通知地址计数器加1，并启动“地址比较”器进行工作。

在“读数据”时，他控制“Dout／确认逻辑”单元；在“写数据”时候，他控制“高压泵／定时”电路，以便向E2PROM电路提供编程所需要的高电压。

地址／计数器单元 产生访问E2PROM所需要的存储单元的地址，并将其分别送到X译码器进行字选，送到Y译码器进行位选。

高压泵／定时单元 由于E2PROM数据写入时候需要向电路施加编程高电压，为了解决单一电源电压的供电问题，芯片生产厂家采用了电压的片内提升电路。

电压的提升范围一般可以达12～21.5 V。