DM9301资料

© 2000 Fairchild Semiconductor CorporationDS006407

August 1986Revised March 2000DM74LS194A 4-Bit Bidirectional Universal Shift RegisterDM74LS194A4-Bit Bidirectional Universal Shift RegisterGeneral DescriptionThis bidirectional shift register is designed to incorporatevirtually all of the features a system designer may want in ashift register; they feature parallel inputs, parallel outputs,right-shift and left-shift serial inputs, operating-mode-con-trol inputs, and a direct overriding clear line. The registerhas four distinct modes of operation, namely:Parallel (broadside) loadShift right (in the direction QA toward QD)Shift left (in the direction QD toward QA)Inhibit clock (do nothing)Synchronous parallel loading is accomplished by applyingthe four bits of data and taking both mode control inputs,S0 and S1, HIGH. The data is loaded into the associatedflip-flops and appear at the outputs after the positive transi-tion of the clock input. During loading, serial data flow isinhibited.Shift right is accomplished synchronously with the risingedge of the clock pulse when S0 is HIGH and S1 is LOW.Serial data for this mode is entered at the shift-right datainput. When S0 is LOW and S1 is HIGH, data shifts leftsynchronously and new data is entered at the shift-leftserial input.Clocking of the flip-flop is inhibited when both mode controlinputs are LOW.FeaturessParallel inputs and outputssFour operating modes:Synchronous parallel loadRight shiftLeft shiftDo nothingsPositive edge-triggered clockingsDirect overriding clear Ordering Code:Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.Connection DiagramOrder NumberPackage NumberPackage DescriptionDM74LS194AMM16A16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 NarrowDM74LS194ANN16E16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide元器件交易网2DM74LS194AFunction TableH = HIGH Level (steady state)L = LOW Level (steady state)X = Don’t Care (any input, including transitions)↑ = Transition from LOW-to-HIGH levela, b, c, d = The level of steady state input at inputs A, B, C or D, respectively.QA0, QB0, QC0, QD0 = The level of QA, QB, QC, or QD, respectively, before the indicated steady state input conditions were established.QAn, QBn, QCn, QDn = The level of QA, QB, QC, respectively, before the most-recent ↑ transition of the clock.Logic DiagramInputsOutputsClearModeClockSerialParallelQAQBQCQDS1S0LeftRightABCDLXXXXXXXXXLLLLHXXLXXXXXXQA0QB0QC0QD0HHH↑XXabcdabcdHLH↑XHXXXXHQAnQBnQCnHLH↑XLXXXXLQAnQBnQCnHHL↑HXXXXXQBnQCnQDnHHHL↑LXXXXXQBnQCnQDnLHLLXXXXXXXQA0QB0QC0QD0元器件交易网DM74LS194AAbsolute Maximum Ratings(Note 1)Note 1: The “Absolute Maximum Ratings” are those values beyond whichthe safety of the device cannot be guaranteed. The device should not beoperated at these limits. The parametric values defined in the ElectricalCharacteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions” table will define the conditionsfor actual device operation.Recommended Operating ConditionsNote 2: CL = 15 pF, TA = 25°C and VCC = 5V.Note 3: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.Note 4: TA = 25°C and VCC = 5V.Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted)Note 5: All typicals are at VCC = 5V, TA = 25°C.Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second.Note 7: With all outputs open, inputs A through D grounded, and 4.5V applied to S0, S1, CLEAR, and the serial inputs, ICC is tested with momentary ground,then 4.5V applied to CLOCK.Supply Voltage7VInput Voltage7VOperating Free Air Temperature Range0°C to +70°CStorage Temperature Range−65°C to +150°CSymbolParameterMinNomMaxUnitsVCCSupply Voltage4.7555.25VVIHHIGH Level Input Voltage2VVILLOW Level Input Voltage0.8VIOHHIGH Level Output Current−0.4mAIOLLOW Level Output Current8mAfCLKClock Frequency (Note 2)025MHzClock Frequency (Note 3)020tWPulse WidthClock20ns(Note 4)Clear20tSUSetup TimeMode30ns(Note 4)Data20tHHold Time (Note 4)0nstRELClear Release Time (Note 4)25nsTAFree Air Operating Temperature070°CSymbolParameterConditionsMinTypMaxUnits(Note 5)VIInput Clamp VoltageVCC = Min, II = −18 mA−1.5VVOHHIGH Level VCC = Min, IOH = Max2.73.4VOutput VoltageVIL = Max, VIH = MinVOLLOW Level VCC = Min, IOL = Max0.350.5Output VoltageVIL = Max, VIH = MinVIOL = 4 mA, VCC = Min0.4IIInput Current @ Max Input VoltageVCC = Max, VI = 7V0.1mAIIHHIGH Level Input CurrentVCC = Max, VI = 2.7V20µAIILLOW Level Input CurrentVCC = Max, VI = 0.4V−0.4mAIOSShort Circuit Output CurrentVCC = Max (Note 6)−20−100mAICCSupply CurrentVCC = Max (Note 7)1523mA元器件交易网

TMS320DM642中文资料

1.2 概述

TMS320C64x DSP芯片（包括TMS320DM642）是在TMS320C6000 DSP平台上的高性能定点DSP。TMS320DM642（DM642）是基于有TI开发的第二代高性能，先进VelociTI技术的VLIW结构（VelociTI1.2），从而使得这些DSP芯片成为数字多媒体的极好的选择。

DM642在主频720MHz下处理速度达到5760MIPS，并且给高性能DSP规划提供了廉价的解决方案。DM642操作灵活的高速处理器和用数字表达容量的阵列处理器。C64x DSP核具有64个32位字长的通用寄存器和8个独立的功能单元——两个结果为32位的乘法器和6个ALUs——是VelociTI1.2的升级版。VelociTI1.2升级版在8个功能单元里包括新的指令，可以在视频和图像应用方面提高性能，并能对VelociTI结构进行扩充。DM642每周期能够提供4个16位MACs，每秒可提供2880百万个MACs，或者8个8位MACs，每秒5760MMACs。DM642具有特殊应用的硬件结构，片上存储器和与其它的C6000系列DSP平台相似的额外的片上外围设备。

DM642使用两级缓存，有一个强大的多变的外围设置。一级程序缓存L1P是一个128Kbit的直接映射缓存，另一级数据缓存L1D是一个128Kbit双路结合设置缓存。L2存储器能被配置成映射存储器，高速缓存或者两者结合。外围设置包括：3个可配置的视频端口；1个10/100Mb/s的以太网控制器（EMAC）；1个管理数据输入输出（MDIO）；1个内插VCXO控制接口；1个McASP0；1个I2C总线；2个McBSPs；3个32位通用定时器；1个用户配置的16位或32位主机接口（HPI16/HPI32）；1个PCI；1个16引脚的通用输入输出口（GP0），具有可编程中断/事件产生模式；1个64位IMIFA，可以与同步和异步存储器和外围设备相连。

© 2000 Fairchild Semiconductor CorporationDS006427

August 1986Revised March 2000DM74LS365A Hex 3-STATE Buffer/Bus DriverDM74LS365A Hex 3-STATE Buffer/Bus DriverGeneral DescriptionThis device contains six independent gates each of whichperforms a non-inverting buffer function. The outputs havethe 3-STATE feature. When enabled, the outputs exhibitthe low impedance characteristics of a standard LS outputwith additional drive capability to permit the driving of buslines without external resistors. When disabled, both theoutput transistors are turned OFF presenting a high-imped-ance state to the bus line. Thus the output will act neitheras a significant load nor as a driver. To minimize the possi-bility that two outputs will attempt to take a common bus toopposite logic levels, the disable time is shorter than theenable time of the outputs. Ordering Code:Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.Connection DiagramFunction TableY = AH = HIGH Logic LevelL = LOW Logic LevelX = Either LOW or HIGH Logic LevelHi-Z = 3-STATE (Outputs are disabled)Order NumberPackage NumberPackage DescriptionDM74LS365AMM16A16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 NarrowDM74LS365ANN16E16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 WideInputOutputG1G2AYHXXHi-ZXHXHi-ZLLHHLLLL元器件交易网2DM74LS365AAbsolute Maximum Ratings(Note 1)Note 1: The “Absolute Maximum Ratings” are those values beyond whichthe safety of the device cannot be guaranteed. The device should not beoperated at these limits. The parametric values defined in the ElectricalCharacteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions” table will define the conditionsfor actual device operation.Recommended Operating ConditionsElectrical Characteristics over recommended operating free air temperature range (unless otherwise noted)Note 2: All typicals are at VCC = 5V, TA = 25°C.Note 3: Both G inputs are at 2V.Note 4: Both G inputs at 0.4V.Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.Note 6: ICC is measured with the DATA inputs grounded and the OUTPUT CONTROLS at 4.5V.Switching Characteristics at VCC = 5V and TA = 25°CNote 7: CL = 5 pF.Supply Voltage7VInput Voltage7VOperating Free Air Temperature Range0°C to +70°CStorage Temperature Range−65°C to +150°CSymbolParameterMinNomMaxUnitsVCCSupply Voltage4.7555.25VVIHHIGH Level Input Voltage2VVILLOW Level Input Voltage0.8VIOHHIGH Level Output Current−2.6mAIOLLOW Level Output Current24mATAFree Air Operating Temperature070°CSymbolParameterConditionsMinTypMaxUnits(Note 2)VIInput Clamp VoltageVCC = Min, II = −18 mA−1.5VVOHHIGH Level VCC = Min, IOH = Max2.43.4VOutput VoltageVIL = Max, VIH = MinVOLLOW Level VCC = Min, IOL = Max0.350.5Output VoltageVIL = Max, VIH = MinVIOL = 12 mA, VCC = Min0.250.4IIInput Current @ Max Input VoltageVCC = Max, VI = 7V0.1mAIIHHIGH Level Input CurrentVCC = Max, VI = 2.7V20µAIIL LOW Level VCC = Max, VI = 0.5V (Note 3)A Input−20µAInput CurrentVCC = Max, VI = 0.4V (Note 4)A Input−0.4mAVCC = Max, VI = 0.4VG Input−0.4IOZHOff-State Output Current withVCC = Max, VO = 2.4V20µAHIGH Level Output Voltage AppliedVIH = Min, VIL = MaxIOZLOff-State Output Current withVCC = Max, VO = 0.4V−20µALOW Level Output Voltage AppliedVIH = Min, VIL = MaxIOSShort Circuit Output CurrentVCC = Max (Note 5)−20−100mAICCSupply CurrentVCC = Max (Note 6)1424mARL = 667ΩSymbolParameterCL = 50 pFCL = 150 pFUnitsMinMaxMinMaxtPLHPropagation Delay Time LOW-to-HIGH Level Output1625nstPHLPropagation Delay Time HIGH-to-LOW Level Output1625nstPZHOutput Enable Time to HIGH Level Output3040nstPZLOutput Enable Time to LOW Level Output3040nstPHZOutput Disable Time from HIGH Level Output (Note 7)20nstPLZOutput Disable Time from LOW Level Output (Note 7)20ns元器件交易网DM74LS365APhysical Dimensions inches (millimeters) unless otherwise noted16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 NarrowPackage Number M16A元器件交易网4DM74LS365A Hex 3-STATE Buffer/Bus DriverPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 WidePackage Number N16EFairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.2.A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or 元器件交易网

DM5406󰁋DM7406

Hex

Inverting

Buffers

with

High

Voltage

Open-Collector

Outputs

June1989

DM5406󰁋DM7406HexInvertingBufferswith

HighVoltageOpen-CollectorOutputs

GeneralDescription

Thisdevicecontainssixindependentbufferseachofwhich

performsthelogicINVERTfunction󰀟Theopen-collectorout-

putsrequireexternalpull-upresistorsforproperlogicalop-

eration󰀟Pull-UpResistorEquations

RMAXeVO(Min)bVOHN1(IOH)aN2(IIH)

RMINeVO(Max)bVOLIOLbN3(IIL)

Where󰀌N1(IOH)etotalmaximumoutputhighcurrentforall

outputstiedtopull-upresistor

N2(IIH)etotalmaximuminputhighcurrentforall

inputstiedtopull-upresistor

N3(IIL)etotalmaximuminputlowcurrentforall

inputstiedtopull-upresistor

ConnectionDiagram

Dual-In-LinePackage

TL󰁋F󰁋6496–1OrderNumberDM5406J󰀷DM5406W󰀷DM7406MorDM7406N

SeeNSPackageNumberJ14A󰀷M14A󰀷N14AorW14B

FunctionTable

YeA

InputOutput

AY

LH

HL

HeHighLogicLevel

LeLowLogicLevel