MSP430F149中文资料.pdf

MSP430F149 定时器（1）利用定时器A的模式2（连续）实现的定时资料利用定时器A的模式2（连续）实现的定时资料在程序中对TACTL的控制，当TACTL为如下的赋值时TACTL = TASSEL_2 + MC_2 + TAIE; // SMCLK, contmode, interrupt可以改变TASSEL_X来实现不同的定时，当为TASSEL_1时选ACLK为定时时钟，可以实现最短2S的定时，其次为2S的倍数的定时。

当为TASSEL_2时选SMCLK为定时时钟，定时取决于SMCLK的时钟源，1、SMCLK选DCO = 800KHZ为时钟源，最短定时时间为0.08S 的定时，其次为其倍数。

2、SMCLK选XT2也即外部高频晶振，此时定时取决于晶振频率，及其对分频的设置上。

主要是设置BCSCTL1及BCSCTS2.BCSCTL1 &= ~XT2OFF;BCSCTL2 |= SELS + DIVS_3;通过对上面两句的不同设置，可实现不同的延时。

/****************************************************************************** // MSP-FET430P140 Demo - Timer_A, Toggle P3.4, Overflow ISR, DCO SMCLK//// Description: Toggle P3.4 using software and Timer_A overflow ISR.// In this example an ISR triggers when TA overflows. Inside the TA// overflow ISR P3.4 is toggled. Toggle rate is approximatlely 12Hz.// Proper use of the TAIV interrupt vector generator is demonstrated.// ACLK = n/a, MCLK = SMCLK = TACLK = default DCO ~800kHz//// MSP430F149// ---------------// /|| XIN|-// | | |// --|RST XOUT|-// | |// | P3.4|-->LED//// Dasheng// LiTian Electronic Inc.// Feb 2008// Built with IAR Embedded Workbench Version: 3.42A功能: 由定时器A，采用800KHz的DCO，来实现近一秒的定时中断；计算方法: T = 1/800,000 = 1.25uS so 根据连续计数模式，当计到0XFFFF时，发生溢出中断因此溢出一次的时间是: 65536*1.25 = 0.0819S,所以计时1秒需12次溢出。

MSP430是德州公司新开发的一类具有16位总线的带FLASH的单片机,由于其性价比和集成度高,受到广大技术开发人员的青睐.它采用16位的总线，外设和内存统一编址,寻址范围可达64K,还可以外扩展存储器。

具有统一的中断管理，具有丰富的片上外围模块，片内有精密硬件乘法器、两个16位定时器、一个14路的12位的模数转换器、一个看门狗、6路P口、两路USART通信端口、一个比较器、一个DCO内部振荡器和两个外部时钟，支持8M的时钟。

由于为FLASH型,则可以在线对单片机进行调试和下载,且JTAG口直接和FET(FLASH EMULATION TOOL)的相连,不须另外的仿真工具,方便实用,而且,可以在超低功耗模式下工作,对环境和人体的辐射小,测量结果为100mw左右的功耗(电流为14mA左右),可靠性能好,加强电干扰运行不受影响，适应工业级的运行环境,适合与做手柄之类的自动控制的设备.我们相信MSP430单片机将会在工程技术应用中得以广泛应用,而且,它是通向DSP系列的桥梁,随着自动控制的高速化和低功耗化，MSP430系列将会得到越来越多人的喜爱。

第三章MSP430F149 资源的应用介绍及开发第一节中断介绍及存储器段介绍中断在MSP430中得以广泛的应用，它可以快速进入中断程序，之后返回中断前的状态，其时序为：PC执行程序中断允许置位SR中的GIE置位 EINT（中断开）中断到，中断标志位（IFG）置位从中断向量表中读取中断程序的入口地址，进入中断程序执行中断程序中断允许位复位 RETI中断返回回到原来地址。

具体应用将会在应用程序中的到应用。

有关中断源和中断优先级及中断允许位、中断标志位在参考资料1上有详细介绍。

MSP430单片机的片上存储器共为64K，表示为图：第三节 P 口MSP430F149有6个8位的P口，其中P1、P2口占两个中断向量，共可以接16 个中断源，还可以直接利用 P口的输入输出寄存器，直接对外进行通信。

基于MSP430F149的GPS
(芯片篇)
1、系统功能框图
2芯片资料：
MSP430F149：
低电源电压范围：1.8~3.6V
超低功耗：待机模式：1.6uA 关闭模式(RAM保持)：0.1uA 活动模式：280uA at 1MHz，2.2V
5种省电模式
6us内从待机模式唤醒
16位RISC结构，125ns指令周期
带内部参考，采样保持和自动扫描特性的12位A/D转换器
有7个捕获/比较寄存器的16位定时器Timer_B 有3个捕获/比较寄存器的16位定时器Timer_A
片内集成比较器
串行在线编程，无需外部编程电压，安全熔丝可编程代码保护.
器件系列包括：–MSP430F133：8KB+256B闪速存储器，256B的RAM –MSP430F135：16KB+256B闪速存储器，512B的RAM –MSP430F147，MSP430F1471：32KB+256B闪速存储器，1KB的RAM –MSP430F148， MSP430F1481：48KB+256B闪速存储器，2KB的RAM –MSP430F149， MSP430F1491：60KB+256B闪速存储器，2KB的RAM
可用封装：64脚方形扁平封装(QFP).
功能框图。

MSP430单片机的开发及应用设计人：陈小忠西安邮电学院电子信息工程系电子0002班西安邮电学院63# 7100612003年7月目录第一章概述第二章MSP430 F149语言介绍第一节开发环境及程序下载第二节语言介绍第三章MSP430F149 资源的应用介绍及开发第一节中断介绍及存储器段介绍第二节硬件乘法器第三节P口第四节定时器及数模转换第五节时钟模块第六节USART通信模块第七节比较器第八节模数转换第四章MSP430F149开发板的介绍及测试第一节模数转换模块第二节传感器模块第三节外存和实时时钟模块第四节485和232模块第五节电源管理模块及晶振模块第六节PWM波形滤波第一章概述MSP430是德州公司新开发的一类具有16位总线的带FLASH 的单片机,由于其性价比和集成度高,受到广大技术开发人员的青睐.它采用16位的总线,外设和内存统一编址,寻址范围可达64K,还可以外扩展存储器.具有统一的中断管理,具有丰富的片上外围模块,片内有精密硬件乘法器、两个16位定时器、一个14路的12位的模数转换器、一个看门狗、6路P口、两路USART 通信端口、一个比较器、一个DCO内部振荡器和两个外部时钟,支持8M 的时钟.由于为FLASH 型,则可以在线对单片机进行调试和下载,且JTAG口直接和FET(FLASH EMULATION TOOL)的相连,不须另外的仿真工具,方便实用,而且,可以在超低功耗模式下工作,对环境和人体的辐射小,测量结果为100mw左右的功耗(电流为14mA左右),可靠性能好,加强电干扰运行不受影响，适应工业级的运行环境,适合与做手柄之类的自动控制的设备.我们相信MSP430单片机将会在工程技术应用中得以广泛应用,而且,它是通向DSP系列的桥梁,随着自动控制的高速化和低功耗化 ,MSP430系列将会得到越来越多人的喜爱.通过两过多月的毕业设计,我对MSP430有了初步了解,对内部的硬件资源和自身的汇编语法进行了实验,并开发了一个应用板,并进行了调试.鉴于时间和能力有限,没能对所有的应用一一实验.第二章 MSP430 F149语言介绍MSP430是德州公司的新产品,有独特的开发环境和自身语言,下面是我在毕业设计中对F149的开发环境熟悉中遇到的一些问题的处理和汇编语言的用法及程序中遇到的问题的体会.第一节开发环境及程序下载1.开发环境:在EW23环境下进行编程,汇编,连接,在C—SPY环境下进行调试,下载是在连接之后,调试之前,通过计算机的串口下载的.关于环境的操作,可以参考有关资料,其中可能遇到的问题及解决方法有:(1) .汇编是对源程序而言的,因此必须打开一个源文件才能汇编,而连接是对一个工程文件而言的,连接是对工程文件的所有源代码(包括多个源文件)和数据的定位,因此连接必须打开一个工程文件才能连接.(2) 连接中必须将库文件的路径改正确,且必须选定C—SPY的驱动方式,即在project中的options的xlink的include下修改(先选中)xcl的库路径为$TOOLKIT_DIR$\icc430\msp430F149A.xcl ,选择C—SPY 的驱动drive为simulator或FLASH EMULATION TOOL ,当没连接430片子时可以选simulator,当连接430片子时,选 FLASH EMULATION TOOL进行在线下载调试.(3) 由于430支持汇编语言和C语言两种语言,因此可以在一个工程文件中同时用两种语言,但建议用汇编语言,因为便于在调试时寻找逻辑和指令的联系及地址的定位正确与否.(4) 在在线的C—SPY 的调试中,单步需要将Control的Reatime前的勾取消才能进行单步测试.(5) 在线调试时,不能将58 管脚（复位/非屏蔽中断）外部变高,否则,会强制退出调试环境.2.程序下载原理及脱机工作原理:程序的在线调试是通过JATG口和F149片子的 RST、TCK、TDI、TDO、TMS引脚按一定的时序串行的传递程序代码和数据的,调试指令的命令传递都是通过这些数据线和控制线传递的,下载时序可参见资料1,其中的地址0FFFEH为复位向量的地址,它是程序遇到非屏蔽中断和程序启动的首要地址,地址中存放的是程序段开始的首地址,因此必须把程序段的首地址标号表示在中断向量中或程序伪指令的开头位置,否则,连接时将会出错,具体的表示方法在下一节中表示.程序的下载和在线调试的电源是通过计算机在JATG提供的,不须另外给加电源.脱机工作时,是将F149的电源线上电,此时的复位时序同下载后在线复位的时序一样,只是时钟是通过F149内部时钟DCO提供的,上电后,程序将复位向量0FFFE中的地址装入PC,PC开始从程序段的首地址开始执行.脱机工作启动不需要任何操作,只需上电即可,电压要大于1.8v,一般取3v左右,另外,在脱机工作时,可以给RST端口加一个低电平脉冲以复位从程序开始重新执行.第二节指令介绍MSP430有自身语言,汇编语言也不同于其他类型的单片机,伪指令也是变幻魔测,但又很重要,下面是我毕业设计的一些尝试、出问题的地方.也可参见资料。

#ifndef __msp430x14x#define __msp430x14x/************************************************************ * STANDARD BITS************************************************************/#define BIT0 0x0001#define BIT1 0x0002#define BIT2 0x0004#define BIT3 0x0008#define BIT4 0x0010#define BIT5 0x0020#define BIT6 0x0040#define BIT7 0x0080#define BIT8 0x0100#define BIT9 0x0200#define BITA 0x0400#define BITB 0x0800#define BITC 0x1000#define BITD 0x2000#define BITE 0x4000#define BITF 0x8000/************************************************************ * STATUS REGISTER BITS************************************************************/#define C 0x0001#define Z 0x0002#define N 0x0004#define V 0x0100#define GIE 0x0008#define CPUOFF 0x0010#define OSCOFF 0x0020#define SCG0 0x0040#define SCG1 0x0080/* Low Power Modes coded with Bits 4-7 in SR */#ifndef __IAR_SYSTEMS_ICC /* Begin #defines for assembler */#define LPM0 CPUOFF#define LPM1 SCG0+CPUOFF#define LPM2 SCG1+CPUOFF#define LPM3 SCG1+SCG0+CPUOFF#define LPM4 SCG1+SCG0+OSCOFF+CPUOFF/* End #defines for assembler */#else /* Begin #defines for C */#define LPM0_bits CPUOFF#define LPM1_bits SCG0+CPUOFF#define LPM2_bits SCG1+CPUOFF#define LPM3_bits SCG1+SCG0+CPUOFF#define LPM4_bits SCG1+SCG0+OSCOFF+CPUOFF#include <In430.h>#define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */#define LPM0_EXIT _BIC_SR(LPM0_bits) /* Exit Low Power Mode 0 */#define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */#define LPM1_EXIT _BIC_SR(LPM1_bits) /* Exit Low Power Mode 1 */#define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */#define LPM2_EXIT _BIC_SR(LPM2_bits) /* Exit Low Power Mode 2 */#define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */#define LPM3_EXIT _BIC_SR(LPM3_bits) /* Exit Low Power Mode 3 */#define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */#define LPM4_EXIT _BIC_SR(LPM4_bits) /* Exit Low Power Mode 4 */#endif /* End #defines for C *//************************************************************ * PERIPHERAL FILE MAP************************************************************//************************************************************ * 特殊功能寄存器地址和控制位************************************************************/ /*中断使能1*/#define IE1_ 0x0000sfrb IE1 = IE1_;#define WDTIE 0x01 /*看门狗中断使能*/#define OFIE 0x02 /*外部晶振故障中断使能*/#define NMIIE 0x10 /*非屏蔽中断使能*/#define ACCVIE 0x20 /*可屏蔽中断使能/flash写中断错误*/#define URXIE0 0x40 /*串口0接收中断使能*/#define UTXIE0 0x80 /*串口0发送中断使能*//*中断标志1*/#define IFG1_ 0x0002sfrb IFG1 = IFG1_;#define WDTIFG 0x01 /*看门狗中断标志*/#define OFIFG 0x02 /*外部晶振故障中断标志*/#define NMIIFG 0x10 /*非屏蔽中断标志*/#define URXIFG0 0x40 /*串口0接收中断标志*/#define UTXIFG0 0x80 /*串口0发送中断标志*//* 中断模式使能1 */#define ME1_ 0x0004sfrb ME1 = ME1_;#define URXE0 0x40 /* 串口0接收中断模式使能*/#define USPIE0 0x40 /* 同步中断模式使能*/#define UTXE0 0x80 /* 串口0发送中断模式使能*//* 中断使能2 */#define IE2_ 0x0001sfrb IE2 = IE2_;#define URXIE1 0x10 /* 串口1接收中断使能*/#define UTXIE1 0x20 /* 串口1发送中断使能*//* 中断标志2 */#define IFG2_ 0x0003sfrb IFG2 = IFG2_;#define URXIFG1 0x10 /* 串口1接收中断标志*/#define UTXIFG1 0x20 /* 串口1发送中断标志*//* 中断模式使能2 */#define ME2_ 0x0005sfrb ME2 = ME2_;#define URXE1 0x10 /* 串口1接收中断模式使能*/#define USPIE1 0x10 /* 同步中断模式使能*/#define UTXE1 0x20 /* 串口1发送中断模式使能*//************************************************************* 看门狗定时器的寄存器定义************************************************************/#define WDTCTL_ 0x0120sfrw WDTCTL = WDTCTL_;#define WDTIS0 0x0001 /*选择WDTCNT的四个输出端之一*/#define WDTIS1 0x0002 /*选择WDTCNT的四个输出端之一*/#define WDTSSEL 0x0004 /*选择WDTCNT的时钟源*/#define WDTCNTCL 0x0008 /*清除WDTCNT端: 为1时从0开始计数*/#define WDTTMSEL 0x0010 /*选择模式0: 看门狗模式; 1: 定时器模式*/#define WDTNMI 0x0020 /*选择NMI/RST 引脚功能0:为RST; 1:为NMI*/#define WDTNMIES 0x0040 /*WDTNMI=1时.选择触发延0:为上升延1:为下降延*/ #define WDTHOLD 0x0080 /*停止看门狗定时器工作0:启动;1:停止*/#define WDTPW 0x5A00 /* 写密码:高八位*//* SMCLK= 1MHz定时器模式*/#define WDT_MDLY_32 WDTPW+WDTTMSEL+WDTCNTCL /* TSMCLK*2POWER15=32ms 复位状态*/#define WDT_MDLY_8 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0 /* TSMCLK*2POWER13=8.192ms " */#define WDT_MDLY_0_5 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1 /* TSMCLK*2POWER9=0.512ms " */#define WDT_MDLY_0_064 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0 /* TSMCLK*2POWER6=0.512ms " *//* ACLK=32.768KHz 定时器模式*/#define WDT_ADLY_1000 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL /* TACLK*2POWER15=1000ms " */#define WDT_ADLY_250 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0 /* TACLK*2POWER13=250ms " */#define WDT_ADLY_16 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1 /* TACLK*2POWER9=16ms " */#define WDT_ADLY_1_9 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0 /* TACLK*2POWER6=1.9ms " *//* SMCLK=1MHz看门狗模式*/#define WDT_MRST_32 WDTPW+WDTCNTCL /* TSMCLK*2POWER15=32ms 复位状态*/#define WDT_MRST_8 WDTPW+WDTCNTCL+WDTIS0 /* TSMCLK*2POWER13=8.192ms " */#define WDT_MRST_0_5 WDTPW+WDTCNTCL+WDTIS1 /* TSMCLK*2POWER9=0.512ms " */#define WDT_MRST_0_064 WDTPW+WDTCNTCL+WDTIS1+WDTIS0 /* TSMCLK*2POWER6=0.512ms " *//* ACLK=32KHz看门狗模式*/#define WDT_ARST_1000 WDTPW+WDTCNTCL+WDTSSEL /* TACLK*2POWER15=1000ms " */#define WDT_ARST_250 WDTPW+WDTCNTCL+WDTSSEL+WDTIS0 /* TACLK*2POWER13=250ms " */#define WDT_ARST_16 WDTPW+WDTCNTCL+WDTSSEL+WDTIS1 /* TACLK*2POWER9=16ms " */ #define WDT_ARST_1_9 WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0 /* TACLK*2POWER6=1.9ms " *//************************************************************硬件乘法器的寄存器定义************************************************************/#define MPY_ 0x0130 /* 无符号乘法*/sfrw MPY = MPY_;#define MPYS_ 0x0132 /* 有符号乘法*/sfrw MPYS = MPYS_;#define MAC_ 0x0134 /* 无符号乘加*/sfrw MAC = MAC_;#define MACS_ 0x0136 /* 有符号乘加*/sfrw MACS = MACS_;#define OP2_ 0x0138 /* 第二乘数*/sfrw OP2 = OP2_;#define RESLO_ 0x013A /* 低6位结果寄存器*/sfrw RESLO = RESLO_;#define RESHI_ 0x013C /* 高6位结果寄存器*/sfrw RESHI = RESHI_;#define SUMEXT_ 0x013E /*结果扩展寄存器*/constsfrw SUMEXT = SUMEXT_;/************************************************************ * DIGITAL I/O Port1/2 寄存器定义有中断功能************************************************************/#define P1IN_ 0x0020 /* P1 输入寄存器*/constsfrb P1IN = P1IN_;#define P1OUT_ 0x0021 /* P1 输出寄存器*/sfrb P1OUT = P1OUT_;#define P1DIR_ 0x0022 /* P1 方向选择寄存器*/sfrb P1DIR = P1DIR_;#define P1IFG_ 0x0023 /* P1 中断标志寄存器*/sfrb P1IFG = P1IFG_;#define P1IES_ 0x0024 /* P1 中断边沿选择寄存器*/sfrb P1IES = P1IES_;#define P1IE_ 0x0025 /* P1 中断使能寄存器*/sfrb P1IE = P1IE_;#define P1SEL_ 0x0026 /* P1 功能选择寄存器*/sfrb P1SEL = P1SEL_;#define P2IN_ 0x0028 /* P2 输入寄存器*/constsfrb P2IN = P2IN_;#define P2OUT_ 0x0029 /* P2 输出寄存器*/sfrb P2OUT = P2OUT_;#define P2DIR_ 0x002A /* P2 方向选择寄存器*/sfrb P2DIR = P2DIR_;#define P2IFG_ 0x002B /* P2 中断标志寄存器*/sfrb P2IFG = P2IFG_;#define P2IES_ 0x002C /* P2 中断边沿选择寄存器*/sfrb P2IES = P2IES_;#define P2IE_ 0x002D /* P2 中断使能寄存器*/sfrb P2IE = P2IE_;#define P2SEL_ 0x002E /* P2 功能选择寄存器*/sfrb P2SEL = P2SEL_;/************************************************************ * DIGITAL I/O Port3/4寄存器定义无中断功能************************************************************/#define P3IN_ 0x0018 /* P3 输入寄存器*/constsfrb P3IN = P3IN_;#define P3OUT_ 0x0019 /* P3 输出寄存器*/sfrb P3OUT = P3OUT_;#define P3DIR_ 0x001A /* P3 方向选择寄存器*/sfrb P3DIR = P3DIR_;#define P3SEL_ 0x001B /* P3 功能选择寄存器*/sfrb P3SEL = P3SEL_;#define P4IN_ 0x001C /* P4 输入寄存器*/constsfrb P4IN = P4IN_;#define P4OUT_ 0x001D /* P4 输出寄存器*/sfrb P4OUT = P4OUT_;#define P4DIR_ 0x001E /* P4 方向选择寄存器*/sfrb P4DIR = P4DIR_;#define P4SEL_ 0x001F /* P4 功能选择寄存器*/sfrb P4SEL = P4SEL_;/************************************************************ * DIGITAL I/O Port5/6 I/O口寄存器定义PORT5和6 无中断功能************************************************************/#define P5IN_ 0x0030 /* P5 输入寄存器*/constsfrb P5IN = P5IN_;#define P5OUT_ 0x0031 /* P5 输出寄存器*/sfrb P5OUT = P5OUT_;#define P5DIR_ 0x0032 /* P5 方向选择寄存器*/sfrb P5DIR = P5DIR_;#define P5SEL_ 0x0033 /* P5 功能选择寄存器*/sfrb P5SEL = P5SEL_;#define P6IN_ 0x0034 /* P6 输入寄存器*/constsfrb P6IN = P6IN_;#define P6OUT_ 0x0035 /* P6 输出寄存器*/sfrb P6OUT = P6OUT_;#define P6DIR_ 0x0036 /* P6 方向选择寄存器*/sfrb P6DIR = P6DIR_;#define P6SEL_ 0x0037 /* P6 功能选择寄存器*/sfrb P6SEL = P6SEL_;/************************************************************* USART 串口寄存器"UCTL","UTCTL","URCTL"定义的各个位可串口1 串口2公用************************************************************//* UCTL 串口控制寄存器*/#define PENA 0x80 /*校验允许位*/#define PEV 0x40 /*偶校验为0时为奇校验*/#define SPB 0x20 /*停止位为2 为0时停止位为1*/#define CHAR 0x10 /*数据位为8位为0时数据位为7位*/#define LISTEN 0x08 /*自环模式(发数据同时在把发的数据接收回来)*/#define SYNC 0x04 /*同步模式为0异步模式*/#define MM 0x02 /*为1时地址位多机协议(异步) 主机模式(同步);为0时线路空闲多机协议(异步) 从机模式(同步)*/#define SWRST 0x01 /*控制位*//* UTCTL 串口发送控制寄存器*/#define CKPH 0x80 /*时钟相位控制位(只同步方式用)为1时时钟UCLK延时半个周期*/#define CKPL 0x40 /*时钟极性控制位为1时异步与UCLK相反;同步下降延有效*/#define SSEL1 0x20 /*时钟源选择位:与SSEL0组合为0,1,2,3四种方式*/#define SSEL0 0x10 /*"0"选择外部时钟,"1"选择辅助时钟,"2","3"选择系统子时钟*/#define URXSE 0x08 /*接收触发延控制位(只在异步方式下用)*/#define TXWAKE 0x04 /*多处理器通信传送控制位(只在异步方式下用)*/#define STC 0x02 /*外部引脚STE选择位为0时为4线模式为1时为3线模式*/#define TXEPT 0x01 /*发送器空标志*//* URCTL 串口接收控制寄存器同步模式下只用两位:FE和OE*/#define FE 0x80 /*帧错标志*/#define PE 0x40 /*校验错标志位*/#define OE 0x20 /*溢出标志位*/#define BRK 0x10 /*打断检测位*/#define URXEIE 0x08 /*接收出错中断允许位*/#define URXWIE 0x04 /*接收唤醒中断允许位*/#define RXWAKE 0x02 /*接收唤醒检测位*/#define RXERR 0x01 /*接收错误标志位*//************************************************************* USART 0 串口0寄存器定义************************************************************/#define U0CTL_ 0x0070 /* 串口0基本控制寄存器*/sfrb U0CTL = U0CTL_;#define U0TCTL_ 0x0071 /* 串口0发送控制寄存器*/ sfrb U0TCTL = U0TCTL_;#define U0RCTL_ 0x0072 /* 串口0接收控制寄存器*/ sfrb U0RCTL = U0RCTL_;#define U0MCTL_ 0x0073 /* 波特率调整寄存器*/sfrb U0MCTL = U0MCTL_;#define U0BR0_ 0x0074 /* 波特率选择寄存器0 */sfrb U0BR0 = U0BR0_;#define U0BR1_ 0x0075 /* 波特率选择寄存器1 */sfrb U0BR1 = U0BR1_;#define U0RXBUF_ 0x0076 /* 接收缓存寄存器*/ constsfrb U0RXBUF = U0RXBUF_;#define U0TXBUF_ 0x0077 /* 发送缓存寄存器*/sfrb U0TXBUF = U0TXBUF_;/* 改变的寄存器名定义*/#define UCTL0_ 0x0070 /* UART 0 Control */sfrb UCTL0 = UCTL0_;#define UTCTL0_ 0x0071 /* UART 0 Transmit Control */ sfrb UTCTL0 = UTCTL0_;#define URCTL0_ 0x0072 /* UART 0 Receive Control */sfrb URCTL0 = URCTL0_;#define UMCTL0_ 0x0073 /* UART 0 Modulation Control */ sfrb UMCTL0 = UMCTL0_;#define UBR00_ 0x0074 /* UART 0 Baud Rate 0 */sfrb UBR00 = UBR00_;#define UBR10_ 0x0075 /* UART 0 Baud Rate 1 */sfrb UBR10 = UBR10_;#define RXBUF0_ 0x0076 /* UART 0 Receive Buffer */ constsfrb RXBUF0 = RXBUF0_;#define TXBUF0_ 0x0077 /* UART 0 Transmit Buffer */sfrb TXBUF0 = TXBUF0_;#define UCTL_0_ 0x0070 /* UART 0 Control */sfrb UCTL_0 = UCTL_0_;#define UTCTL_0_ 0x0071 /* UART 0 Transmit Control */ sfrb UTCTL_0 = UTCTL_0_;#define URCTL_0_ 0x0072 /* UART 0 Receive Control */ sfrb URCTL_0 = URCTL_0_;#define UMCTL_0_ 0x0073 /* UART 0 Modulation Control */ sfrb UMCTL_0 = UMCTL_0_;#define UBR0_0_ 0x0074 /* UART 0 Baud Rate 0 */sfrb UBR0_0 = UBR0_0_;sfrb UBR1_0 = UBR1_0_;#define RXBUF_0_ 0x0076 /* UART 0 Receive Buffer */constsfrb RXBUF_0 = RXBUF_0_;#define TXBUF_0_ 0x0077 /* UART 0 Transmit Buffer */sfrb TXBUF_0 = TXBUF_0_;/************************************************************ * USART 1 串口1寄存器定义************************************************************/#define U1CTL_ 0x0078 /* 串口1基本控制寄存器*/sfrb U1CTL = U1CTL_;#define U1TCTL_ 0x0079 /* 串口1发送控制寄存器*/sfrb U1TCTL = U1TCTL_;#define U1RCTL_ 0x007A /* 串口1接收控制寄存器*/sfrb U1RCTL = U1RCTL_;#define U1MCTL_ 0x007B /* 波特率调整控制寄存器*/sfrb U1MCTL = U1MCTL_;#define U1BR0_ 0x007C /* 波特率选择寄存器0 */sfrb U1BR0 = U1BR0_;#define U1BR1_ 0x007D /* 波特率选择寄存器1 */sfrb U1BR1 = U1BR1_;#define U1RXBUF_ 0x007E /* 接收缓存*/constsfrb U1RXBUF = U1RXBUF_;#define U1TXBUF_ 0x007F /* 发送缓存*/sfrb U1TXBUF = U1TXBUF_;/* 改变的寄存器名定义*/#define UCTL1_ 0x0078 /* UART 1 Control */sfrb UCTL1 = UCTL1_;#define UTCTL1_ 0x0079 /* UART 1 Transmit Control */sfrb UTCTL1 = UTCTL1_;#define URCTL1_ 0x007A /* UART 1 Receive Control */sfrb URCTL1 = URCTL1_;#define UMCTL1_ 0x007B /* UART 1 Modulation Control */sfrb UMCTL1 = UMCTL1_;#define UBR01_ 0x007C /* UART 1 Baud Rate 0 */sfrb UBR01 = UBR01_;#define UBR11_ 0x007D /* UART 1 Baud Rate 1 */sfrb UBR11 = UBR11_;#define RXBUF1_ 0x007E /* UART 1 Receive Buffer */constsfrb RXBUF1 = RXBUF1_;sfrb TXBUF1 = TXBUF1_;#define UCTL_1_ 0x0078 /* UART 1 Control */sfrb UCTL_1 = UCTL_1_;#define UTCTL_1_ 0x0079 /* UART 1 Transmit Control */sfrb UTCTL_1 = UTCTL_1_;#define URCTL_1_ 0x007A /* UART 1 Receive Control */sfrb URCTL_1 = URCTL_1_;#define UMCTL_1_ 0x007B /* UART 1 Modulation Control */sfrb UMCTL_1 = UMCTL_1_;#define UBR0_1_ 0x007C /* UART 1 Baud Rate 0 */sfrb UBR0_1 = UBR0_1_;#define UBR1_1_ 0x007D /* UART 1 Baud Rate 1 */sfrb UBR1_1 = UBR1_1_;#define RXBUF_1_ 0x007E /* UART 1 Receive Buffer */constsfrb RXBUF_1 = RXBUF_1_;#define TXBUF_1_ 0x007F /* UART 1 Transmit Buffer */sfrb TXBUF_1 = TXBUF_1_;/************************************************************ * Timer A 定时器A寄存器定义************************************************************/#define TAIV_ 0x012E /* Timer A 中断向量寄存器*/sfrw TAIV = TAIV_;#define TACTL_ 0x0160 /* Timer A 控制寄存器*/sfrw TACTL = TACTL_;#define TACCTL0_ 0x0162 /* Timer A 捕获/比较控制寄存器0 */sfrw TACCTL0 = TACCTL0_;#define TACCTL1_ 0x0164 /* Timer A 捕获/比较控制寄存器1 */sfrw TACCTL1 = TACCTL1_;#define TACCTL2_ 0x0166 /* Timer A 捕获/比较控制寄存器2 */sfrw TACCTL2 = TACCTL2_;#define TAR_ 0x0170 /* Timer A 16位计数器内容*/sfrw TAR = TAR_;#define TACCR0_ 0x0172 /* Timer A 捕获/比较寄存器0 */sfrw TACCR0 = TACCR0_;#define TACCR1_ 0x0174 /* Timer A 捕获/比较寄存器1 */sfrw TACCR1 = TACCR1_;#define TACCR2_ 0x0176 /* Timer A 捕获/比较寄存器2 */sfrw TACCR2 = TACCR2_;/* 改变的寄存器名定义*/#define CCTL0_ 0x0162 /* Timer A Capture/Compare Control 0 */ sfrw CCTL0 = CCTL0_;#define CCTL1_ 0x0164 /* Timer A Capture/Compare Control 1 */ sfrw CCTL1 = CCTL1_;#define CCTL2_ 0x0166 /* Timer A Capture/Compare Control 2 */ sfrw CCTL2 = CCTL2_;#define CCR0_ 0x0172 /* Timer A Capture/Compare 0 */sfrw CCR0 = CCR0_;#define CCR1_ 0x0174 /* Timer A Capture/Compare 1 */sfrw CCR1 = CCR1_;#define CCR2_ 0x0176 /* Timer A Capture/Compare 2 */sfrw CCR2 = CCR2_;/*TACTL 控制寄存器16个位寄存器定义*/#define TASSEL2 0x0400 /* 未用*/#define TASSEL1 0x0200 /* 时钟输入源控制位1 */#define TASSEL0 0x0100 /* 时钟输入源控制位0 */#define ID1 0x0080 /* 分频系数选择位1 */#define ID0 0x0040 /* 分频系数选择位0 */#define MC1 0x0020 /* 计数模式控制位1 */#define MC0 0x0010 /* 计数模式控制位0 */#define TACLR 0x0004 /* 置1位清除定时器*/#define TAIE 0x0002 /* 定时器中断允许*/#define TAIFG 0x0001 /* 定时器中断标志*/#define MC_0 00*0x10 /* 停止模式*/#define MC_1 01*0x10 /* 增计数模式*/#define MC_2 02*0x10 /* 连续计数模式*/#define MC_3 03*0x10 /* 增/减计数模式*/#define ID_0 00*0x40 /* 直通*/#define ID_1 01*0x40 /* 2分频*/#define ID_2 02*0x40 /* 4分频*/#define ID_3 03*0x40 /* 8分频*/#define TASSEL_0 00*0x100 /* 时钟源为TACLK */#define TASSEL_1 01*0x100 /* 时钟源为ACLK */#define TASSEL_2 02*0x100 /* 时钟源为SMCLK */#define TASSEL_3 03*0x100 /* 时钟源为INCLK *//* Timer A ,Timer B 可公用捕获/比较控制寄存器X */#define CM1 0x8000 /* 捕获模式选择位1 */#define CM0 0x4000 /* 捕获模式选择位0 */#define CCIS1 0x2000 /* 捕获输入信号源选择位1 */#define CCIS0 0x1000 /* 捕获输入信号源选择位0 */#define SCS 0x0800 /* 信号同步位0:异步捕获;1:同步捕获*/#define SCCI 0x0400 /* 锁存输入信号*/#define CAP 0x0100 /* 模式选择: 0:比较模式;1:捕获模式*/#define OUTMOD2 0x0080 /* 输出模式选择位2 */#define OUTMOD1 0x0040 /* 输出模式选择位1 */#define OUTMOD0 0x0020 /* 输出模式选择位0 */#define CCIE 0x0010 /* 中断允许位*/#define CCI 0x0008 /* 读出输入信号源位ccis0\1 */#define OUT 0x0004 /* 输出信号(选择输出模式0) */#define COV 0x0002 /* 捕获溢出标志*/#define CCIFG 0x0001 /* 中断标志*/#define OUTMOD_0 0*0x20 /* 输出模式*/#define OUTMOD_1 1*0x20 /* 置位模式*/#define OUTMOD_2 2*0x20 /* 翻转/复位模式*/#define OUTMOD_3 3*0x20 /* 置位/复位模式*/#define OUTMOD_4 4*0x20 /* 翻转模式*/#define OUTMOD_5 5*0x20 /* 复位模式*/#define OUTMOD_6 6*0x20 /* 翻转/置位模式*/#define OUTMOD_7 7*0x20 /* 复位/置位模式*/#define CCIS_0 0*0x1000 /* 选择CCIXA为捕获事件的输入信号源*/#define CCIS_1 1*0x1000 /* 选择CCIXB为捕获事件的输入信号源*/#define CCIS_2 2*0x1000 /* 选择GND为捕获事件的输入信号源*/#define CCIS_3 3*0x1000 /* 选择VCC为捕获事件的输入信号源*/#define CM_0 0*0x4000 /* 禁止捕获模式*/#define CM_1 1*0x4000 /* 上升延捕获模式*/#define CM_2 2*0x4000 /* 下降沿捕获模式*/#define CM_3 3*0x4000 /* 上升沿和下降沿都捕获模式*//************************************************************ * Timer B 定时器B寄存器定义************************************************************/#define TBIV_ 0x011E /* 中断向量寄存器:BIT1-BIT3有效*/sfrw TBIV = TBIV_;#define TBCTL_ 0x0180 /* 定时器B控制寄存器:全部控制都集中在这*/ sfrw TBCTL = TBCTL_;#define TBCCTL0_ 0x0182 /* 定时器B捕获/比较控制寄存器0*/sfrw TBCCTL0 = TBCCTL0_;#define TBCCTL1_ 0x0184 /* 定时器B捕获/比较控制寄存器1 */sfrw TBCCTL1 = TBCCTL1_;#define TBCCTL2_ 0x0186 /* 定时器B捕获/比较控制寄存器2 */sfrw TBCCTL2 = TBCCTL2_;#define TBCCTL3_ 0x0188 /* 定时器B捕获/比较控制寄存器3 */sfrw TBCCTL3 = TBCCTL3_;#define TBCCTL4_ 0x018A /* 定时器B捕获/比较控制寄存器4 */sfrw TBCCTL4 = TBCCTL4_;#define TBCCTL5_ 0x018C /* 定时器B捕获/比较控制寄存器5 */sfrw TBCCTL5 = TBCCTL5_;#define TBCCTL6_ 0x018E /* 定时器B捕获/比较控制寄存器6 */sfrw TBCCTL6 = TBCCTL6_;#define TBR_ 0x0190 /* 计数器*/sfrw TBR = TBR_;#define TBCCR0_ 0x0192 /* 定时器B捕获/比较寄存器0 */sfrw TBCCR0 = TBCCR0_;#define TBCCR1_ 0x0194 /* 定时器B捕获/比较寄存器1 */sfrw TBCCR1 = TBCCR1_;#define TBCCR2_ 0x0196 /* 定时器B捕获/比较寄存器2 */sfrw TBCCR2 = TBCCR2_;#define TBCCR3_ 0x0198 /* 定时器B捕获/比较寄存器3 */sfrw TBCCR3 = TBCCR3_;#define TBCCR4_ 0x019A /* 定时器B捕获/比较寄存器4 */sfrw TBCCR4 = TBCCR4_;#define TBCCR5_ 0x019C /* 定时器B捕获/比较寄存器5 */sfrw TBCCR5 = TBCCR5_;#define TBCCR6_ 0x019E /* 定时器B捕获/比较寄存器6 */sfrw TBCCR6 = TBCCR6_;/* 定时器B控制寄存器:全部控制都集中在这*/#define SHR1 0x4000 /* 装载比较锁存器控制位1 :受TBCCTLx中的CCLDx位控制*/#define SHR0 0x2000 /* 装载比较锁存器控制位0 :受TBCCTLx中的CCLDx位控制*/#define TBCLGRP1 0x4000 /* 装载比较锁存器控制位1 :受TBCCTLx中的CCLDx位控制*/ #define TBCLGRP0 0x2000 /* 装载比较锁存器控制位0 :受TBCCTLx中的CCLDx位控制*/ #define CNTL1 0x1000 /* 定时器位数长度控制位1 */#define CNTL0 0x0800 /* 定时器位数长度控制位0 */#define TBSSEL2 0x0400 /* 未用*/#define TBSSEL1 0x0200 /* 时钟输入源控制位1 */#define TBSSEL0 0x0100 /* 时钟输入源控制位0 */#define TBCLR 0x0004 /* 置1清除定时器*/#define TBIE 0x0002 /* 中断允许*/#define TBIFG 0x0001 /* 中断标志*/#define TBSSEL_0 0*0x0100 /* 时钟源为:TBCLK */#define TBSSEL_1 1*0x0100 /* 时钟源为: ACLK */#define TBSSEL_2 2*0x0100 /* 时钟源为:SMCLK */#define TBSSEL_3 3*0x0100 /* 时钟源为:INCLK */#define CNTL_0 0*0x0800 /* 16 位计数模式*/#define CNTL_1 1*0x0800 /* 12 位计数模式*/#define CNTL_2 2*0x0800 /* 10 位计数模式*/#define CNTL_3 3*0x0800 /* 8 位计数模式*/#define SHR_0 0*0x2000 /* 单独装载(初始值) */#define SHR_1 1*0x2000 /* 分三组装载: 1 - 3 groups (1-2, 3-4, 5-6) */#define SHR_2 2*0x2000 /* 分二组装载: 2 - 2 groups (1-3, 4-6)*/#define SHR_3 3*0x2000 /* 不分组装载: 3 - 1 group (all) */#define TBCLGRP_0 0*0x2000 /* 单独装载(初始值) */#define TBCLGRP_1 1*0x2000 /* 分三组装载: 1 - 3 groups (1-2, 3-4, 5-6) */#define TBCLGRP_2 2*0x2000 /* 分二组装载: 2 - 2 groups (1-3, 4-6)*/#define TBCLGRP_3 3*0x2000 /* 不分组装载: 3 - 1 group (all) *//* Additional Timer B Control Register bits are defined in Timer A */#define SLSHR1 0x0400 /* Compare latch load source 1 */#define SLSHR0 0x0200 /* Compare latch load source 0 */#define CLLD1 0x0400 /* 定义比较锁存器TBCLx的装载方式控制位1 */#define CLLD0 0x0200 /* 定义比较锁存器TBCLx的装载方式控制位0 */#define SLSHR_0 0*0x0200 /* 立即装载*/#define SLSHR_1 1*0x0200 /* TBR 计数到0时装载*/#define SLSHR_2 2*0x0200 /* 在增减模式下,计数到TBCLx或0时装载; 在连续计数模式下,计数到0时装载*/#define SLSHR_3 3*0x0200 /* 当计数到TBCL0时装载*/#define CLLD_0 0*0x0200 /* 立即装载*/#define CLLD_1 1*0x0200 /* TBR 计数到0时装载*/#define CLLD_2 2*0x0200 /* 在增减模式下,计数到TBCLx或0时装载; 在连续计数模式下,计数到0时装载*/#define CLLD_3 3*0x0200 /* 当计数到TBCL0时装载*//************************************************************* Basic Clock Module************************************************************/#define DCOCTL_ 0x0056 /* DCO 时钟频率控制寄存器:复位后的值位060h*/sfrb DCOCTL = DCOCTL_;#define BCSCTL1_ 0x0057 /* 系统时钟控制寄存器1 :复位后的值位084h*/sfrb BCSCTL1 = BCSCTL1_;#define BCSCTL2_ 0x0058 /* 系统时钟控制寄存器2 :复位后的值位000h*/sfrb BCSCTL2 = BCSCTL2_;/* DCO 时钟频率控制寄存器*/#define MOD0 0x01 /* DCO插入周期控制位0 */#define MOD1 0x02 /* DCO插入周期控制位1 */#define MOD2 0x04 /* DCO插入周期控制位2 */#define MOD3 0x08 /* DCO插入周期控制位3 */#define MOD4 0x10 /* DCO插入周期控制位4 */#define DCO0 0x20 /* 8种频率控制位0 */#define DCO1 0x40 /* 8种频率控制位1 */#define DCO2 0x80 /* 8种频率控制位2 *//* 系统时钟控制寄存器1 :复位后的值位084h*/#define RSEL0 0x01 /* 选择内部电阻控制位0 */#define RSEL1 0x02 /* 选择内部电阻控制位1 */#define RSEL2 0x04 /* 选择内部电阻控制位2 */#define XT5V 0x08 /* 必须为0*/#define DIVA0 0x10 /* ACLK分频系数控制位0*/#define DIVA1 0x20 /* ACLK分频系数控制位1 */#define XTS 0x40 /* LFXT1工作模式控制位0:低频模式. / 1: 高频模式. */ #define XT2OFF 0x80 /* XT2CLK 使能控制位0:开启; 1:关闭*/#define DIVA_0 0x00 /* ACLK分频系数为: 1 */#define DIVA_1 0x10 /* ACLK分频系数为: 2 */#define DIVA_2 0x20 /* ACLK分频系数为: 4 */#define DIVA_3 0x30 /* ACLK分频系数为: 8 *//* 系统时钟控制寄存器2 :复位后的值位000h*/#define DCOR 0x01 /* 内外电阻选择控制位*/#define DIVS0 0x02 /* SMCLK分频控制位0*/#define DIVS1 0x04 /* SMCLK分频控制位1 */#define SELS 0x08 /* SMCLK 时钟源选择位t 0COCLK / 1:XT2CLK/LFXTCLK */ #define DIVM0 0x10 /* MCLK分频控制位0 */#define DIVM1 0x20 /* MCLK分频控制位1 */#define SELM0 0x40 /* MCLK 时钟输入源选择位0 */#define SELM1 0x80 /* MCLK 时钟输入源选择位1 */#define DIVS_0 0x00 /* SMCLK 分频系数为: 1 */#define DIVS_1 0x02 /* SMCLK 分频系数为: 2 */#define DIVS_2 0x04 /* SMCLK 分频系数为: 4 */#define DIVS_3 0x06 /* SMCLK 分频系数为: 8 */#define DIVM_0 0x00 /* MCLK 分频系数为: 1 */#define DIVM_1 0x10 /* MCLK 分频系数为: 2 */#define DIVM_2 0x20 /* MCLK 分频系数为: 4 */#define DIVM_3 0x30 /* MCLK 分频系数为: 8 */#define SELM_0 0x00 /* MCLK 时钟输入源: DCOCLK */#define SELM_1 0x40 /* MCLK 时钟输入源: DCOCLK */#define SELM_2 0x80 /* MCLK 时钟输入源: XT2CLK/LFXTCLK */#define SELM_3 0xC0 /* MCLK 时钟输入源: LFXTCLK *//************************************************************* * Flash Memory FLASH操作寄存器定义*************************************************************/#define FCTL1_ 0x0128 /* FLASH控制寄存器1:控制编程、擦除*/sfrw FCTL1 = FCTL1_;#define FCTL2_ 0x012A /* FLASH 控制寄存器2 ：控制时钟分频*/sfrw FCTL2 = FCTL2_;#define FCTL3_ 0x012C /* FLASH 控制寄存器3：状态标志*/sfrw FCTL3 = FCTL3_;#define FRKEY 0x9600 /* 读FLASH 密码*/#define FWKEY 0xA500 /* 写FLASH 密码*/#define FXKEY 0x3300 /* for use with XOR instruction *//* FLASH控制寄存器1:控制编程、擦除*/#define ERASE 0x0002 /* 擦除段使能*/#define MERAS 0x0004 /* 主存擦除使能*/#define WRT 0x0040 /* 编程使能*/#define BLKWRT 0x0080 /* 段编程使能*//* FLASH 控制寄存器2 ：控制时钟分频*/#define FN_0 0x0000 /*直通*/#define FN_1 0x0001 /*2分频*/#define FN_2 0x0002 /*3分频*/#define FN_3 0x0003 /*4分频*/#define FN_4 0x0004 /*5分频*/#define FN_5 0x0005 /*6分频*/#define FN_6 0x0006 /*7分频*/#define FN_7 0x0007 /*8分频*/#define FN_8 0x0008 /*9分频*/#define FN_9 0x0009 /*10分频*/#define FN_10 0x000A /*11分频*/#define FN_11 0x000B /*12分频*/#define FN_12 0x000C /*13分频*/#define FN_13 0x000D /*14分频*/#define FN_14 0x000E /*15分频*/#define FN_15 0x000F /*16分频*/#define FN_16 0x0010 /*17分频*/#define FN_17 0x0011 /*18分频*/#define FN_18 0x0012 /*19分频*/#define FN_19 0x0013 /*20分频*/#define FN_20 0x0014 /*21分频*/#define FN_21 0x0015 /*22分频*/#define FN_22 0x0016 /*23分频*/#define FN_23 0x0017 /*24分频*/#define FN_24 0x0018 /*25分频*/#define FN_25 0x0019 /*26分频*/#define FN_26 0x001A /*27分频*/#define FN_27 0x001B /*28分频*/#define FN_28 0x001C /*29分频*/#define FN_29 0x001D /*30分频*/#define FN_30 0x001E /*31分频*/#define FN_31 0x001F /*32分频*/#define FN_32 0x0020 /*33分频*/#define FN_33 0x0021 /*34分频*/#define FN_34 0x0022 /*35分频*/#define FN_35 0x0023 /*36分频*/#define FN_36 0x0024 /*37分频*/#define FN_37 0x0025 /*38分频*/#define FN_38 0x0026 /*39分频*/#define FN_39 0x0027 /*40分频*/#define FN_40 0x0028 /*41分频*/#define FN_41 0x0029 /*42分频*/#define FN_42 0x002A /*43分频*/#define FN_43 0x002B /*44分频*/#define FN_44 0x002C /*45分频*/#define FN_45 0x002D /*46分频*/#define FN_46 0x002E /*47分频*/#define FN_47 0x002F /*48分频*/#define FN_48 0x0030 /*49分频*/#define FN_49 0x0031 /*50分频*/#define FN_50 0x0032 /*51分频*/#define FN_51 0x0033 /*52分频*/#define FN_52 0x0034 /*53分频*/#define FN_53 0x0035 /*54分频*/#define FN_54 0x0036 /*55分频*/#define FN_55 0x0037 /*56分频*/#define FN_56 0x0038 /*57分频*/#define FN_57 0x0039 /*58分频*/#define FN_58 0x003A /*59分频*/#define FN_59 0x003B /*60分频*/#define FN_60 0x003C /*61分频*/#define FN_61 0x003D /*62分频*/#define FN_62 0x003E /*63分频*/#define FN_63 0x003F /*64分频*/#define FSSEL_0 0x0000 /* Flash时钟选择: ACLK */ #define FSSEL_1 0x0040 /* Flash时钟选择: MCLK */ #define FSSEL_2 0x0080 /* Flash时钟选择: SMCLK */ #define FSSEL_3 0x00C0 /* Flash时钟选择: SMCLK */ /* FLASH 控制寄存器3：状态标志*/#define BUSY 0x0001 /* Flash忙标志*/#define KEYV 0x0002 /* Flash安全键值出错标志*/#define ACCVIFG 0x0004 /* Flash非法访问中断标志*/#define WAIT 0x0008 /* 等待指示信号位*/#define LOCK 0x0010 /* 锁定位*/#define EMEX 0x0020 /* 紧急退出位*//************************************************************ * Comparator A 比较器A寄存器定义************************************************************/#define CACTL1_ 0x0059 /* 比较器A控制寄存器1 */sfrb CACTL1 = CACTL1_;#define CACTL2_ 0x005A /* 比较器A控制寄存器2 */sfrb CACTL2 = CACTL2_;#define CAPD_ 0x005B /*比较器A端口禁止寄存器*/sfrb CAPD = CAPD_;/* 比较器A控制寄存器1 */#define CAIFG 0x01 /*比较器A中断标志*/#define CAIE 0x02 /* 比较器A中断使能*/#define CAIES 0x04 /* 比较器A中断边沿触发选择0:上升延1:下降延*/ #define CAON 0x08 /* 比较器电源开关*/#define CAREF0 0x10 /* 选择参考源位0 */#define CAREF1 0x20 /* 选择参考源位1 */#define CARSEL 0x40 /* 选择内部参考源加到比较器的正端或负端*/#define CAEX 0x80 /* 交换比较器的输入端*/#define CAREF_0 0x00 /* 选择参考源0 : Off 使用外部参考源*/#define CAREF_1 0x10 /* 选择参考源1 : 0.25*Vcc为参考源*/#define CAREF_2 0x20 /* 选择参考源2 : 0.5*Vcc为参考源*/#define CAREF_3 0x30 /* 选择参考源3 : Vt*//* 比较器A控制寄存器2 */#define CAOUT 0x01 /* 比较器输出*/#define CAF 0x02 /* 选择比较器是否经过RC低通滤波器*/#define P2CA0 0x04 /* 外部引脚信号连接到比较器A的CA0 */#define P2CA1 0x08 /* 外部引脚信号连接到比较器A的CA1 */#define CACTL24 0x10#define CACTL25 0x20#define CACTL26 0x40#define CACTL27 0x80#define CAPD0 0x01 /* Comp. A Disable Input Buffer of Port Register .0 */#define CAPD1 0x02 /* Comp. A Disable Input Buffer of Port Register .1 */#define CAPD2 0x04 /* Comp. A Disable Input Buffer of Port Register .2 */#define CAPD3 0x08 /* Comp. A Disable Input Buffer of Port Register .3 */#define CAPD4 0x10 /* Comp. A Disable Input Buffer of Port Register .4 */#define CAPD5 0x20 /* Comp. A Disable Input Buffer of Port Register .5 */#define CAPD6 0x40 /* Comp. A Disable Input Buffer of Port Register .6 */#define CAPD7 0x80 /* Comp. A Disable Input Buffer of Port Register .7 *//************************************************************* ADC12 A/D采样寄存器定义************************************************************//*ADC12转换控制类寄存器*/#define ADC12CTL0_ 0x0;' /* ADC12 Control 0 */sfrw ADC12CTL0 = ADC12CTL0_;#define ADC12CTL1_ 0x01A2 /* ADC12 Control 1 */sfrw ADC12CTL1 = ADC12CTL1_;/*ADC12中断控制类寄存器*/#define ADC12IFG_ 0x01A4 /* ADC12 Interrupt Flag */sfrw ADC12IFG = ADC12IFG_;#define ADC12IE_ 0x01A6 /* ADC12 Interrupt Enable */sfrw ADC12IE = ADC12IE_;#define ADC12IV_ 0x01A8 /* ADC12 Interrupt Vector Word */sfrw ADC12IV = ADC12IV_;/*ADC12存贮器类寄存器*/#define ADC12MEM_ 0x0140 /* ADC12 Conversion Memory */#ifndef __IAR_SYSTEMS_ICC#define ADC12MEM ADC12MEM_ /* ADC12 Conversion Memory (for assembler) */ #else#define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */ #endif#define ADC12MEM0_ ADC12MEM_ /* ADC12 Conversion Memory 0 */sfrw ADC12MEM0 = ADC12MEM0_;#define ADC12MEM1_ 0x0142 /* ADC12 Conversion Memory 1 */sfrw ADC12MEM1 = ADC12MEM1_;#define ADC12MEM2_ 0x0144 /* ADC12 Conversion Memory 2 */sfrw ADC12MEM2 = ADC12MEM2_;#define ADC12MEM3_ 0x0146 /* ADC12 Conversion Memory 3 */sfrw ADC12MEM3 = ADC12MEM3_;#define ADC12MEM4_ 0x0148 /* ADC12 Conversion Memory 4 */sfrw ADC12MEM4 = ADC12MEM4_;#define ADC12MEM5_ 0x014A /* ADC12 Conversion Memory 5 */sfrw ADC12MEM5 = ADC12MEM5_;#define ADC12MEM6_ 0x014C /* ADC12 Conversion Memory 6 */sfrw ADC12MEM6 = ADC12MEM6_;#define ADC12MEM7_ 0x014E /* ADC12 Conversion Memory 7 */。

An IMPORTANT NOTICE at the end of this data sheet addresses availability,warranty,changes,use in safety-critical applications,intellectual property matters and other important disclaimers.PRODUCTION DATA.MSP430F149,MSP430F148,MSP430F147MSP430F1491,MSP430F1481,MSP430F1471MSP430F135,MSP430F133SLAS272H –JULY 2000–REVISED MAY 20181Device Overview1.1Features•Low Supply Voltage Range,1.8V to 3.6V •Ultra-Low Power Consumption:–Active Mode:280µA at 1MHz,2.2V –Standby Mode:1.6µA–Off Mode (RAM Retention):0.1µA •Five Power-Saving Modes•Wakeup From Standby Mode in Less Than 6µs •16-Bit RISC Architecture,125-ns Instruction Cycle Time•12-Bit Analog-to-Digital Converter (ADC)With Internal Reference,Sample-and-Hold,and Autoscan Feature•16-Bit Timer_B With Seven Capture/Compare-With-Shadow Registers•16-Bit Timer_A With Three Capture/Compare Registers•On-Chip Comparator•Serial Onboard Programming,No External Programming Voltage Needed,Programmable Code Protection by Security Fuse•Serial Communication Interface (USART),Functions as Asynchronous UART or Synchronous SPI Interface–Two USARTs (USART0,USART1)On MSP430F14x and MSP430F14x1Devices –One USART (USART0)On MSP430F13x Devices•Family Members (Also See Device Comparison )–MSP430F133–8KB +256Bytes of Flash Memory,256Bytes of RAM –MSP430F135–16KB +256Bytes of Flash Memory,512Bytes of RAM–MSP430F147,MSP430F1471–32KB +256Bytes of Flash Memory,1KB of RAM–MSP430F148,MSP430F1481–48KB +256Bytes of Flash Memory,2KB of RAM–MSP430F149,MSP430F1491–60KB +256Bytes of Flash Memory,2KB of RAM 1.2Applications•Sensor Systems •Industrial Controls•Hand-Held Meters1.3DescriptionThe Texas Instruments MSP430™family of ultra-low-power microcontrollers (MCUs)consist of several devices featuring different sets of peripherals targeted for various applications.The architecture,combined with five low-power modes is optimized to achieve extended battery life in portable measurement applications.The device features a powerful 16-bit RISC CPU,16-bit registers,and constant generators that attribute to maximum code efficiency.The digitally controlled oscillator (DCO)allows wake-up from low-power modes to active mode in less than 6µs.The MSP430F13x,MSP430F14x,and MSP430F14x1MCUs support two built-in 16-bit timers,a fast 12-bit ADC on the MSP430F13x and the MSP430F14x devices,one USART on the MSP430F13x devices or two USARTs on the MSP430F14x and MSP430F14x1devices,and 48I/O pins.The hardware multiplier enhances the performance and offers a broad code and hardware-compatible family solution.For complete module descriptions,see the MSP430x1xx Family User’s Guide .XT2IN XT2OUTTMS TCK TDI/TCLK TDO/TDIRST/NMIR 2MSP430F149,MSP430F148,MSP430F147MSP430F1491,MSP430F1481,MSP430F1471MSP430F135,MSP430F133SLAS272H –JULY 2000–REVISED MAY 2018Device Overview Copyright ©2000–2018,Texas Instruments Incorporated(1)For the most current device,package,and ordering information,see the Package Option Addendum in Section 8,or see the TI website at .(2)The sizes shown here are approximations.For the package dimensions with tolerances,see the Mechanical Data in Section 8.Device Information (1)PART NUMBERPACKAGE BODY SIZE (2)MSP430F149IPM LQFP (64)10mm ×10mm MSP430F149IPAG TQFP (64)10mm ×10mm MSP430F1491IRTD VQFN (64)9mm ×9mm1.4Functional Block DiagramsFigure 1-1shows the functional block diagram for the MSP430F13x MCUs.Figure 1-1.Functional Block Diagram,MSP430F13xXT2OUTTMS TCK TDI/TCLK TDO/TDIRST/NMIRR 3MSP430F149,MSP430F148,MSP430F147MSP430F1491,MSP430F1481,MSP430F1471MSP430F135,MSP430F133SLAS272H –JULY 2000–REVISED MAY 2018Device Overview Copyright ©2000–2018,Texas Instruments Incorporated Figure 1-2.Functional Block Diagram,MSP430F14xFigure 1-3shows the functional block diagram for the MSP430F14x1MCUs.Figure 1-3.Functional Block Diagram,MSP430F14x14MSP430F149,MSP430F148,MSP430F147MSP430F1491,MSP430F1481,MSP430F1471MSP430F135,MSP430F133SLAS272H –JULY 2000–REVISED MAY 2018Table of Contents Copyright ©2000–2018,Texas Instruments IncorporatedTable of Contents1Device Overview (1)1.1Features ..............................................11.2Applications ...........................................11.3Description ............................................11.4Functional Block Diagrams (2)2Revision History .........................................53Device Comparison . (6)3.1Related Products (6)4Terminal Configuration and Functions (7)4.1Pin Diagrams .........................................74.2Signal Descriptions (105)Specifications (16)5.1Absolute Maximum Ratings (16)5.2ESD Ratings........................................165.3Recommended Operating Conditions ...............165.4Supply Current Into AV CC and DV CC ExcludingExternal Current .....................................175.5Thermal Resistance Characteristics ................185.6Schmitt-Trigger Inputs –Ports P1,P2,P3,P4,P5,and P6...............................................185.7Standard Inputs –RST/NMI,JTAG (TCK,TMS,TDI/TCLK,TDO/TDI)...............................185.8Inputs –Px.y,TAx,TBx............................185.9Leakage Current ....................................195.10Outputs –Ports P1,P2,P3,P4,P5,and P6.......195.11Output Frequency ..................................195.12Typical Characteristics –Ports P1,P2,P3,P4,P5,and P6Outputs (20)5.13Wake-up Time From LPM3.........................215.14RAM .................................................215.15Comparator_A .......................................215.16Typical Characteristics –Comparator_A ............225.17PUC and POR ......................................235.18DCO Frequency .....................................245.19DCO When Using R OSC .............................255.20Crystal Oscillator,LFXT1...........................265.21Crystal Oscillator,XT2..............................265.22USART0,USART1..................................265.2312-Bit ADC,Power Supply and Input RangeConditions ...........................................275.2412-Bit ADC,External Reference ....................275.2512-Bit ADC,Built-In Reference . (28)5.2612-Bit ADC,Timing Parameters....................305.2712-Bit ADC,Linearity Parameters ...................305.2812-Bit ADC,Temperature Sensor and Built-In V MID315.29Flash Memory .......................................315.30JTAG Interface ......................................325.31JTAG Fuse.........................................326Detailed Description (33)6.1CPU .................................................336.2Instruction set .......................................346.3Operating Modes ....................................346.4Interrupt Vector Addresses ..........................356.5Bootloader (BSL)....................................356.6JTAG Fuse Check Mode ............................366.7Memory ..............................................366.8Peripherals ..........................................406.9Input/Output Diagrams (48)7Device and Documentation Support (59)7.1Getting Started and Next Steps .....................597.2Device Nomenclature ...............................597.3Tools and Software .................................617.4Documentation Support .............................627.5Related Links ........................................637.6Community Resources ..............................637.7Trademarks ..........................................637.8Electrostatic Discharge Caution .....................647.9Export Control Notice ...............................647.10Glossary .............................................648Mechanical,Packaging,and OrderableInformation (65)5MSP430F149,MSP430F148,MSP430F147MSP430F1491,MSP430F1481,MSP430F1471MSP430F135,MSP430F133SLAS272H –JULY 2000–REVISED MAY 2018Revision History Copyright ©2000–2018,Texas Instruments Incorporated 2Revision HistoryNOTE:Page numbers for previous revisions may differ from page numbers in the current version.Changes from February 12,2009to May 23,2018Page•Document format and organization changes throughout ........................................................................1•Added Section 1.2,Applications ....................................................................................................1•Added Section 3,Device Comparison ............................................................................................6•Added Section 5.2,ESD Ratings ..................................................................................................16•Removed note (2)with duplicate information from the f LFXT1parameter in Section 5.3,Recommended OperatingConditions ...........................................................................................................................16•Removed duplicate conditions "XTS =0,SELM =0or 1"from the second row of Test Conditions on the I (AM)parameter in Section 5.4,Supply Current Into AV CC and DV CC Excluding External Current ..............................17•Added Section 5.5,Thermal Resistance Characteristics ......................................................................18•Removed ADC12DIV from the equation in the TYP value of the t CONVERT parameter (because ADC12CLK isafter division)in Section 5.26,12-Bit ADC,Timing Parameters ..............................................................30•Changed all instances of bootstrap loader to bootloader throughout document ............................................35•Added Section 7,Device and Documentation Support (59)6MSP430F149,MSP430F148,MSP430F147MSP430F1491,MSP430F1481,MSP430F1471MSP430F135,MSP430F133SLAS272H –JULY 2000–REVISED MAY 2018Device Comparison Copyright ©2000–2018,Texas Instruments Incorporated(1)For the most current package and ordering information,see the Package Option Addendum in Section 8,or see the TI website at.(2)Package drawings,thermal data,and symbolization are available at .(3)Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available.For example,a number sequence of 3,5would represent two instantiations of Timer_A,the first instantiation having 3and the second instantiation having 5capture/compare registers and PWM output generators,respectively.(4)Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available.For example,a number sequence of 3,5would represent two instantiations of Timer_B,the first instantiation having 3and the second instantiation having 5capture/compare registers and PWM output generators,respectively.3Device ComparisonTable 3-1summarizes the features of the device variants in this data sheet.Table 3-1.Device Comparison (1)(2)Device Flash SRAM Timer_A (3)Timer_B (4)USART COMP_AADC12(Channels)I/Os Package MSP430F14960KB 2KB 372184864-pin PM 64-pin PAG 64-pin RTD MSP430F149160KB 2KB 372184864-pin PM 64-pin RTD MSP430F14848KB 2KB 372184864-pin PM 64-pin PAG 64-pin RTD MSP430F148148KB 2KB 372184864-pin PM 64-pin RTD MSP430F14732KB 1KB 372184864-pin PM 64-pin PAG 64-pin RTD MSP430F147132KB 1KB 372184864-pin PM 64-pin RTD MSP430F13516KB512bytes331184864-pin PM 64-pin PAG 64-pin RTD MSP430F1338KB 256bytes 331184864-pin PM 64-pin PAG 64-pin RTD3.1Related ProductsFor information about other devices in this family of products or related products,see the following links.TI 16-bit and 32-bit microcontrollers High-performance,low-power solutions to enable the autonomousfuture Products for MSP430ultra-low-power microcontrollersOne platform.One ecosystem.Endlesspossibilities.Products for other MSP430microcontrollers MCUs for metrology,monitoring,system control,andcommunications Companion Products for MSP430F149Review products that are frequently purchased or used with thisproduct.Reference Designs The TI Designs Reference Design Library is a robust reference design library thatspans analog,embedded processor,and connectivity.Created by TI experts to help you jump start your system design,all TI Designs include schematic or block diagrams,BOMs,and design files to speed your time to market.171819P5.4/MCLK P5.3P5.2P5.1P5.0P4.7/TBCLK P4.6P4.5P4.4P4.3P4.2/TB2P4.1/TB1P4.0/TB0P3.7P3.6P3.5/URXD0484746454443424140393837363534332012345678910111213141516DV CC P6.3/A3P6.4/A4P6.5/A5P6.6/A6P6.7/A7V REF+XIN XOUT Ve REF+V REF−/Ve REF−P1.0/TACLK P1.1/TA0P1.2/TA1P1.3/TA2P1.4/SMCLK21222324P 5.6/A C L K T D O /T D I 63626160596458A V P 6.2/A 2P 6.1/A 1P 6.0/A 0R S T /N M I T C K T M S P 2.6/A D C 12C L K P 2.7/T A 0P 3.0/S T E 0P 3.1/S I M O 0P 1.7/T A 2P 2.1/T A I N C L K P 2.2/C A O U T /T A 0P 2.3/C A 0/T A 1P 2.4/C A 1/T A 2P 2.5/R o s c 5655545725262728295352P 1.5/T A 0X T 2I N X T 2O U T 515049303132P 3.2/S O M I 0P 3.3/U C L K 0P 3.4/U T X D 0P 5.7/T B O U T HT D I /T C L K P 5.5/S M C L KA V D V P 1.6/T A 1P 2.0/A C L K C CS SS S7MSP430F149,MSP430F148,MSP430F147MSP430F1491,MSP430F1481,MSP430F1471MSP430F135,MSP430F133SLAS272H –JULY 2000–REVISED MAY 2018Terminal Configuration and Functions Copyright ©2000–2018,Texas Instruments Incorporated 4Terminal Configuration and Functions4.1Pin DiagramsFigure 4-1shows the pinout for the MSP430F133and MSP430F135MCUs in the 64-pin PM,PAG,and RTD packages.Figure 4-1.64-Pin PM,PAG,or RTD Package (Top View)for MSP430F133and MSP430F135171819P5.4/MCLK P5.3/UCLK1P5.2/SOMI1P5.1/SIMO1P5.0/STE1P4.7/TBCLK P4.6/TB6P4.5/TB5P4.4/TB4P4.3/TB3P4.2/TB2P4.1/TB1P4.0/TB0P3.7/URXD1P3.6/UTXD1P3.5/URXD0484746454443424140393837363534332012345678910111213141516DV CC P6.3/A3P6.4/A4P6.5/A5P6.6/A6P6.7/A7V REF+XIN XOUT Ve REF+V REF−/Ve REF−P1.0/TACLK P1.1/TA0P1.2/TA1P1.3/TA2P1.4/SMCLK21222324P 5.6/A C L K T D O /T D I 63626160596458A V P 6.2/A 2P 6.1/A 1P 6.0/A 0R S T /N M I T C K T M S P 2.6/A D C 12C L K P 2.7/T A 0P 3.0/S T E 0P 3.1/S I M O 0P 1.7/T A 2P 2.1/T A I N C L K P 2.2/C A O U T /T A 0P 2.3/C A 0/T A 1P 2.4/C A 1/T A 2P 2.5/R o s c 5655545725262728295352P 1.5/T A 0X T 2I N X T 2O U T 515049303132P 3.2/S O M I 0P 3.3/U C L K 0P 3.4/U T X D 0P 5.7/T B O U T HT D I /T C L K P 5.5/S M C L KA V D V P 1.6/T A 1P 2.0/A C L K C CS SS S8MSP430F149,MSP430F148,MSP430F147MSP430F1491,MSP430F1481,MSP430F1471MSP430F135,MSP430F133SLAS272H –JULY 2000–REVISED MAY 2018Terminal Configuration and FunctionsCopyright ©2000–2018,Texas Instruments IncorporatedFigure 4-2shows the pinout for the MSP430F147,MSP430F148,and MSP430F149MCUs in the 64-pin PM,PAG,and RTD packages.Figure 4-2.64-Pin PM,PAG,or RTD Package (Top View)for MSP430F147,MSP430F148,and MSP430F149171819P5.4/MCLK P5.3/UCLK1P5.2/SOMI1P5.1/SIMO1P5.0/STE1P4.7/TBCLK P4.6/TB6P4.5/TB5P4.4/TB4P4.3/TB3P4.2/TB2P4.1/TB1P4.0/TB0P3.7/URXD1P3.6/UTXD1P3.5/URXD0484746454443424140393837363534332012345678910111213141516DV CC P6.3P6.4P6.5P6.6P6.7ReservedXIN XOUT DV SS DV SSP1.0/TACLK P1.1/TA0P1.2/TA1P1.3/TA2P1.4/SMCLK21222324P 5.6/A C L K T D O /T D I 63626160596458A V P 6.2P 6.1P 6.0R S T /N M I T C K T M S P 2.6P 2.7/T A 0P 3.0/S T E 0P 3.1/S I M O 0P 1.7/T A 2P 2.1/T A I N C L K P 2.2/C A O U T /T A 0P 2.3/C A 0/T A 1P 2.4/C A 1/T A 2P 2.5/R o s c 5655545725262728295352P 1.5/T A 0X T 2I N X T 2O U T 515049303132P 3.2/S O M I 0P 3.3/U C L K 0P 3.4/U T X D 0P 5.7/T B O U T HT D I /T C L K P 5.5/S M C L KA V D V P 1.6/T A 1P 2.0/A C L K C CS SS S9MSP430F149,MSP430F148,MSP430F147MSP430F1491,MSP430F1481,MSP430F1471MSP430F135,MSP430F133SLAS272H –JULY 2000–REVISED MAY 2018Terminal Configuration and Functions Copyright ©2000–2018,Texas Instruments Incorporated Figure 4-3shows the pinout for the MSP430F1471,MSP430F1481,and MSP430F1491MCUs in the 64-pin PM and RTD packages.Figure 4-3.64-Pin PM or RTD Package (Top View)for MSP430F1471,MSP430F1481,and MSP430F149110MSP430F149,MSP430F148,MSP430F147MSP430F1491,MSP430F1481,MSP430F1471MSP430F135,MSP430F133SLAS272H –JULY 2000–REVISED MAY 2018Terminal Configuration and FunctionsCopyright ©2000–2018,Texas Instruments Incorporated4.2Signal DescriptionsTable 4-1describes the signals for the MSP430F13x and MSP430F14x MCUs.See Table 4-2for the MSP430F14x1signal descriptions.Table 4-1.Signal Descriptions for MSP430F13x and MSP430F14xSIGNAL NAME PIN NO.I/O DESCRIPTIONAV CC 64Analog supply voltage,positive terminal.Supplies the analog portion of the ADC.AV SS 62Analog supply voltage,negative terminal.Supplies the analog portion of the ADC.DV CC 1Digital supply voltage,positive terminal.Supplies all digital parts.DV SS63Digital supply voltage,negative terminal.Supplies all digital parts.P1.0/TACLK 12I/O General-purpose digital I/O pin Timer_A,clock signal TACLK inputP1.1/TA013I/OGeneral-purpose digital I/O pinTimer_A,capture:CCI0A input,compare:Out0output BSL transmitP1.2/TA114I/O General-purpose digital I/O pinTimer_A,capture:CCI0A input,compare:Out0output BSL transmitP1.3/TA215I/O General-purpose digital I/O pinTimer_A,capture:CCI2A input,compare:Out2output P1.4/SMCLK 16I/O General-purpose digital I/O pin SMCLK signal outputP1.5/TA017I/O General-purpose digital I/O pin Timer_A,compare:Out0output P1.6/TA118I/O General-purpose digital I/O pin Timer_A,compare:Out1output P1.7/TA219I/O General-purpose digital I/O pin Timer_A,compare:Out2output/P2.0/ACLK 20I/O General-purpose digital I/O pin ACLK outputP2.1/TAINCLK21I/OGeneral-purpose digital I/O pin Timer_A,clock signal at INCLK P2.2/CAOUT/TA022I/OGeneral-purpose digital I/O pin Comparator_A outputTimer_A,capture:CCI0B input BSL receiveP2.3/CA0/TA123I/OGeneral-purpose digital I/O pin Timer_A,compare:Out1output Comparator_A inputP2.4/CA1/TA224I/O General-purpose digital I/O pin Timer_A,compare:Out2output Comparator_A inputP2.5/R OSC 25I/O General-purpose digital I/O pininput for external resistor defining the DCO nominal frequency P2.6/ADC12CLK 26I/O General-purpose digital I/O pin Conversion clock for ADC P2.7/TA027I/O General-purpose digital I/O pin Timer_A,compare:Out0outputP3.0/STE028I/O General-purpose digital I/O pinSlave transmit enable for USART0in SPI mode P3.1/SIMO029I/O General-purpose digital I/O pinSlave in/master out of USART0in SPI mode P3.2/SOMI030I/O General-purpose digital I/O pinSlave out/master in of USART0in SPI modeP3.3/UCLK031I/O General-purpose digital I/OUSART0clock:external input in UART or SPI mode,output in SPI mode P3.4/UTXD032I/OGeneral-purpose digital I/O pinTransmit data out for USART0in UART mode11MSP430F149,MSP430F148,MSP430F147MSP430F1491,MSP430F1481,MSP430F1471MSP430F135,MSP430F133SLAS272H –JULY 2000–REVISED MAY 2018Terminal Configuration and Functions Copyright ©2000–2018,Texas Instruments IncorporatedTable 4-1.Signal Descriptions for MSP430F13x and MSP430F14x (continued)SIGNAL NAMEPIN NO.I/O DESCRIPTION (1)MSP430F14x devices onlyP3.5/URXD033I/O General-purpose digital I/O pin Receive data in for USART0in UART mode P3.6/UTXD1(1)34I/O General-purpose digital I/O pin Transmit data out for USART1in UART mode P3.7/URXD1(1)35I/O General-purpose digital I/O pin Receive data in for USART1in UART mode P4.0/TB0.36I/O General-purpose digital I/O pin Timer_B,capture:CCI0A or CCI0B input,compare:Out0output P4.1/TB137I/O General-purpose digital I/O pin Timer_B,capture:CCI1A or CCI1B input,compare:Out1output P4.2/TB238I/O General-purpose digital I/O pin Timer_B,capture:CCI2A or CCI2B input,compare:Out2output P4.3/TB3(1)39I/O General-purpose digital I/O pin Timer_B,capture:CCI3A or CCI3B input,compare:Out3output P4.4/TB4(1)40I/O General-purpose digital I/O pin Timer_B,capture:CCI4A or CCI4B input,compare:Out4output P4.5/TB5(1)41I/O General-purpose digital I/O pin Timer_B,capture:CCI5A or CCI5B input,compare:Out5output P4.6/TB6(1)42I/O General-purpose digital I/O pin Timer_B,capture:CCI6A or CCI6B input,compare:Out6output P4.7/TBCLK43I/O General-purpose digital I/O pin Timer_B,clock signal TBCLK input P5.0/STE1(1)44I/O General-purpose digital I/O pin Slave transmit enable for USART1in SPI mode P5.1/SIMO1(1)45I/O General-purpose digital I/O pin Slave in/master out of USART1in SPI mode P5.2/SOMI1(1)46I/O General-purpose digital I/O pin Slave out/master in of USART1in SPI mode P5.3/UCLK1(1)47I/O General-purpose digital I/O pin USART1clock:external input in UART or SPI mode,output in SPI mode P5.4/MCLK48I/O General-purpose digital I/O pin Main system clock MCLK output P5.5/SMCLK49I/O General-purpose digital I/O pin Submain system clock SMCLK output P5.6/ACLK50I/O General-purpose digital I/O pin Auxiliary clock ACLK output P5.7/TBOUTH51I/O General-purpose digital I/O pin Switch all PWM digital output ports to high impedance for Timer_B7(TB0to TB6)P6.0/A059I/O General-purpose digital I/O pin Analog input A0for ADC P6.1/A160I/O General-purpose digital I/O pin Analog input A1for ADC P6.2/A261I/O General-purpose digital I/O pin Analog input A2for ADC P6.3/A32I/O General-purpose digital I/O pin Analog input A3for ADC P6.4/A43I/O General-purpose digital I/O pin Analog input A4for ADC P6.5/A54I/O General-purpose digital I/O pin Analog input A5for ADC P6.6/A65I/O General-purpose digital I/O pin Analog input A6for ADC P6.7/A76I/O General-purpose digital I/O pinAnalog input A7for ADC12MSP430F149,MSP430F148,MSP430F147MSP430F1491,MSP430F1481,MSP430F1471MSP430F135,MSP430F133SLAS272H –JULY 2000–REVISED MAY 2018Terminal Configuration and Functions Copyright ©2000–2018,Texas Instruments IncorporatedTable 4-1.Signal Descriptions for MSP430F13x and MSP430F14x (continued)SIGNAL NAMEPIN NO.I/O DESCRIPTION RST/NMI58I Reset input Nonmaskable interrupt input port Bootloader start TCK57I Test clock,the clock input port for device programming test and bootloader start TDI/TCLK55I Test data input or test clock input.The device protection fuse is connected to TDI/TCLK.TDO/TDI54I/O Test data output or programming data input TMS56I Test mode select,used as an input port for device programming and test VeREF+10I Input for an external reference voltage to the ADC VREF+7O Output of positive terminal of the reference voltage in the ADC VREF −/VeREF −11I Negative terminal for the ADC reference voltage for both sources,the internal reference voltage or an external applied reference voltage XIN8I Input port for crystal oscillator XT1,standard or watch crystals can be connected XOUT9O Output terminal of crystal oscillator XT1XT2IN53I Input port for crystal oscillator XT2,only standard crystals can be connected XT2OUT52O Output terminal of crystal oscillator XT2QFN Pad NA NA QFN package pad,connect to DV SS13MSP430F149,MSP430F148,MSP430F147MSP430F1491,MSP430F1481,MSP430F1471MSP430F135,MSP430F133SLAS272H –JULY 2000–REVISED MAY 2018Terminal Configuration and Functions Copyright ©2000–2018,Texas Instruments Incorporated Table 4-2describes the signals for the MSP430F14x1MCUs.See Table 4-1for the MSP430F13x and MSP430F14x signal descriptions.Table 4-2.Signal Descriptions for MSP430F14x1SIGNAL NAMEPIN NO.I/O DESCRIPTION AV CC64Analog supply voltage positive terminal AV SS62Analog supply voltage negative terminal DV CC1Digital supply voltage,positive terminal.Supplies all digital parts.DV SS63Digital supply voltage,negative terminal.Supplies all digital parts.P1.0/TACLK12I/O General-purpose digital I/O pin Timer_A,clock signal TACLK input P1.1/TA013I/O General-purpose digital I/O pin Timer_A,capture:CCI0A input,compare:Out0output BSL transmit P1.2/TA114I/O General-purpose digital I/O pin Timer_A,capture:CCI1A input,compare:Out1output P1.3/TA215I/O General-purpose digital I/O pin Timer_A,capture:CCI2A input,compare:Out2output P1.4/SMCLK16I/O General-purpose digital I/O pin SMCLK signal output P1.5/TA017I/O General-purpose digital I/O pin Timer_A,compare:Out0output P1.6/TA118I/O General-purpose digital I/O pin Timer_A,compare:Out1output P1.7/TA219I/O General-purpose digital I/O pin Timer_A,compare:Out2output P2.0/ACLK20I/O General-purpose digital I/O pin ACLK output P2.1/TAINCLK 21I/O General-purpose digital I/O pinTimer_A,clock signal at INCLKP2.2/CAOUT/TA022I/O General-purpose digital I/O pinTimer_A,capture:CCI0B inputComparator_A outputBSL receiveP2.3/CA0/TA123I/O General-purpose digital I/O pinTimer_A,compare:Out1outputComparator_A inputP2.4/CA1/TA224I/O General-purpose digital I/O pinTimer_A,compare:Out2outputComparator_A inputP2.5/R OSC 25I/O General-purpose digital I/O pinInput for external resistor defining the DCO nominal frequencyP2.626I/O General-purpose digital I/O pinP2.7/TA027I/O General-purpose digital I/O pinTimer_A,compare:Out0outputP3.0/STE028I/O General-purpose digital I/O pinSlave transmit enable for USART0in SPI modeP3.1/SIMO029I/O General-purpose digital I/O pinSlave in/master out of USART0in SPI modeP3.2/SOMI030I/O General-purpose digital I/O pinSlave out/master in of USART0in SPI modeP3.3/UCLK031I/O General-purpose digital I/OUSART0clock:external input in UART or SPI mode,output in SPI modeP3.4/UTXD032I/O General-purpose digital I/O pinTransmit data out for USART0in UART modeP3.5/URXD033I/OGeneral-purpose digital I/O pinReceive data in for USART0in UART mode14MSP430F149,MSP430F148,MSP430F147MSP430F1491,MSP430F1481,MSP430F1471MSP430F135,MSP430F133SLAS272H –JULY 2000–REVISED MAY 2018Terminal Configuration and FunctionsCopyright ©2000–2018,Texas Instruments Incorporated Table 4-2.Signal Descriptions for MSP430F14x1(continued)SIGNAL NAMEPIN NO.I/O DESCRIPTION P3.6/UTXD134I/O General-purpose digital I/O pin Transmit data out for USART1in UART mode P3.7/URXD135I/O General-purpose digital I/O pin Receive data in for USART1in UART mode P4.0/TB0.36I/O General-purpose digital I/O pin Timer_B,capture:CCI0A or CCI0B input,compare:Out0output P4.1/TB137I/O General-purpose digital I/O pin Timer_B,capture:CCI1A or CCI1B input,compare:Out1output P4.2/TB238I/O General-purpose digital I/O pin Timer_B,capture:CCI2A or CCI2B input,compare:Out2output P4.3/TB339I/O General-purpose digital I/O pin Timer_B,capture:CCI3A or CCI3B input,compare:Out3output P4.4/TB440I/O General-purpose digital I/O pin Timer_B,capture:CCI4A or CCI4B input,compare:Out4output P4.5/TB541I/O General-purpose digital I/O pin Timer_B,capture:CCI5A or CCI5B input,compare:Out5output P4.6/TB642I/O General-purpose digital I/O pin Timer_B,capture:CCI6A or CCI6B input,compare:Out6output P4.7/TBCLK43I/O General-purpose digital I/O pin Timer_B,clock signal TBCLK input P5.0/STE144I/O General-purpose digital I/O pin Slave transmit enable for USART1in SPI mode P5.1/SIMO145I/O General-purpose digital I/O pin Slave in/master out of USART1in SPI mode P5.2/SOMI146I/O General-purpose digital I/O pin Slave out/master in of USART1in SPI mode P5.3/UCLK147I/O General-purpose digital I/O pin USART1clock:external input in UART or SPI mode,output in SPI mode P5.4/MCLK48I/O General-purpose digital I/O pin Main system clock MCLK output P5.5/SMCLK49I/O General-purpose digital I/O pin Submain system clock SMCLK output P5.6/ACLK50I/O General-purpose digital I/O pin Auxiliary clock ACLK output P5.7/TBOUTH51I/O General-purpose digital I/O pin Switch all PWM digital output ports to high impedance for Timer_B7(TB0to TB6)P6.059I/O General-purpose digital I/O pin P6.160I/O General-purpose digital I/O pin P6.261I/O General-purpose digital I/O pin P6.32I/O General-purpose digital I/O pin P6.43I/O General-purpose digital I/O pin P6.54I/O General-purpose digital I/O pin P6.65I/O General-purpose digital I/O pin P6.76I/O General-purpose digital I/O pin RST/NMI58I Reset input Nonmaskable interrupt input port Bootloader start TCK57I Test clock,the clock input port for device programming test and bootloader start TDI/TCLK55I Test data input or test clock input.The device protection fuse is connected to TDI/TCLK.TDO/TDI54I/O Test data output or programming data input TMS56I Test mode select,used as an input port for device programming and test DV SS10I Connect to DV SS Reserved7Reserved,do not connect externally。

指令集描述P(220—257)* DECX.A目的操作数减1* DECX.[W] 目的操作数减1* DECX.B 目的操作数减1语法DECV.A dstDECX dst 或DECX.W dstDECX.B dst操作dst – 1 →dst仿真SUBX.A#1,dstSUBX #1,dstSUBX.B #1,dst说明目的操作数减1 以前的内容丢失状态位N :结果为负时置位为正时复位Z : dst包含1时置位其他情况时复位C : dst包含0时置位其他情况时复位V : 产生算术溢出时置位其他情况时复位目的操作数的初始值为08000H时置位其他情况时复位方式位OscOff（晶振控制位），CPUOff（CPU控制位）和GIE（中断标志位）不受影响例子目的地址操作数减一DECX.A TONI ; TONI减一* DECDX.[W] 目的操作数减2* DECDX.B 目的操作数减2语法DECDX.A dstDECDX dst or DECDX.W dsDECDX.B dst操作dst - 2 -> dst仿真SUBX.A#2,dstSUBX #2,dstSUBX.B #2,dst说明目的操作数减2 以前的内容丢失状态位N : 结果为负时置位为正时复位Z : dst包含2时置位其他情况时复位C : dst包含0或1时置位其他情况时复位V : dst产生算术溢出时置位其他情况时复位目的操作数的初始值为08001H或08000H时置方式位OscOff, CPUOff 和GIE不受影响例子目的地址操作数减二DECDX.A TONI ; Decrement TONI* INCX.[W] 目的操作数加1* INCX.B 目的操作数加1语法INCX.A dstINCX dst or INCX.W dstINCX.B dst操作dst + 1 →dst仿真ADDX.A#1,dstADDX #1,dstADDX.B #1,dst说明目的操作数加1 以前的内容丢失状态位N : 结果为负时置位为正时复位Z : dst包含0FFFFFH时置位其他情况时复位dst包含0FFFFH时置位其他情况时复位dst包含0FFFH时置位其他情况时复位C: dst包含0FFFFFH时置位其他情况时复位dst包含0FFFFH时置位其他情况时复位dst包含0FFFH时置位其他情况时复位V : dst包含07FFFH时置位其他情况时复位dst包含07FFFH时置位其他情况时复位dst包含07FH时置位其他情况时复位方式位OscOff ,CPUOff 和GIE不受影响例子目的地址操作数加一INCX.A TONI ; Increment TONI (20-bits)* INCDX.A目的操作数加2* INCDX.[W] 目的操作数加2* INCDX.B 目的操作数加2语法INCDX.A dstINCDX dst or INCDX.W dstINCDX.B dst操作dst + 1 →dst仿真ADDX.A#2,dstADDX #2,dstADDX.B #2,dst说明目的操作数加2以前的内容丢失状态位N: 结果为负时置位为正时复位Z : dst包含0FFFFEH时置位其他情况时复位dst包含0FFFEH时置位其他情况时复位dst包含0FEH时置位其他情况时复位C: dst包含0FFFFEH或0FFFFFH时置位其他情况时复位dst包含0FFFEH或0FFFFH时置位其他情况时复位dst包含0FEH或0FFH时置位其他情况时复位V: dst包含07FFFEH或0FFFFH时置位其他情况时复位dst包含07FFEH或0FFFH时置位其他情况时复位dst包含07EH或0FH时置位其他情况时复位方式位OscOff ,CPUOff 和GIE不受影响例子目的地址操作数加二INCDX.B LEO ; Increment LEO by two* INVX.A目的操作数求反* INVX.[W] 目的操作数求反* INVX.B 目的操作数求反语法INVX.A dstINVX dst or INVX.W dstINVX.B dst操作.NOT.dst →dst仿真XORX.A#0FFFFFh,dstXORX #0FFFFh,dstXORX.B #0FFh,dst说明目的操作数取反以前的内容丢失状态位N : 结果为负时置位为正时复位Z :dst 包含0FFFFFH时置位其他情况时复位dst 包含0FFFFH时置位其他情况时复位dst 包含0FFH时置位其他情况时复位C :结果不为零时置位其他情况时复位( = .NOT.Zero )V 初始目的操作数为负时置位其他情况时复位方式位OscOff CPUOff 和GIE不受影响例子R5 求反INVX.A R5 ; R5求反MOVX.A源操作数移至目的操作数MOVX.[W] 源操作数移至目的操作数MOVX.B 源操作数移至目的操作数语法MOVX.A src,dstMOVX src,dst or MOVX.W src,dstMOVX.B src,dst操作src →dst说明源操作数被移至目的操作数源操作数不受影响目的操作数以前的内容丢失状态位N: 不影响状态位Z: 不影响状态位C: 不影响状态位V: 不影响状态位方式位OscOff ，CPUOff 和GIE不受影响例子移动18000H 到EDEMOVX. A#018000h, &EDE ; Move 18000h to EDE例子地起码表EDE(字数据)的内容被复制到表TOM 地址表的长度为030H MOV #EDE, R10 ;准备指针Loop MOV @R10+, TOM-EDE-2(R10) ;将R10 中的指针用于两表DEC R9 ;计数器减1JNZ Loop ;计数器<>0 继续........ ;完成例子地起码表EDE(字数据)的内容被复制到表TOM 地址表的长度为020H MOV #EDE, R10 ;准备指针MOV #020H, R9 ;计数器Loop MOV @R10+, TOM-EDE-2(R10) ;将R10 中的指针用于两表DEC R9 ;计数器减1JNZ Loop ;计数器<>0 继续........ ;完成28种MOVX寻址方式中的10种，一个指令可以使用MOVX，这样可以节省二个字节编码周期。

MSP430F149 开发板使用说明2009年09月第一章新手入门1.1 MSP430F149 学习板特点：选用16 位超低功耗单片机MSP430F149，采用子母双板分离设计，MCU 子板与集成外设母板通过插针座连接，使用灵活方便。

ØMCU 的全部IO都用插针引出，便于二次开发提供电源指示灯和上电自动复位、手动复位电路。

2、蜂鸣器实验（1）蜂鸣器1：单频音（步进变音调）（2）蜂鸣器2：奏乐（祝你平安）3、数码管实验（1）数码管1（显示0123）（2）数码管2（动态显示0~F）4、4×1 独立按键实验（1）键盘1：扫描数码管显示5、1602 液晶实验（1）1602 液晶1：动态字符显示（2）1602 液晶2：静态字符显示（3）1602 液晶3：内部时钟显示6、RS232 接口实验（1）RS232 接口1：MCU 发送数据PC 机显示（2）RS232 接口2：按键控制MCU 发送数据PC 机显示（3）RS232 接口3：PC 机发送数据MCU 液晶显示（4）RS232 接口4：MCU 回发接收到的PC 机数据7、RS485 接口实验（1）RS485 接口1：发送程序8、PS2 接口实验（1）PS2 接口1：PS2 控制1602 显示9、12-Bit 高精度温度传感器实验（1）温度传感器1：DS18B20 在液晶显示10、RTC 实时时钟实验（1）实时时钟1：DS1302 测试（2）实时时钟2：DS1302 电子钟11、2k Bit EEPROM 实验（1）EEPROM1：AT24C02 测试（2）EEPROM2：读出数据通过串口在PC 机显示12、12-Bit 模数转换器（ADC）接口实验（1）模数转换器2：ADC 在1602 液晶在显示（2）模数转换器3：ADC 通过串口在PC 机显示13、12864 液晶实验（与12864 液晶配套）（1）12864 液晶并口1：字符显示（2）12864 液晶并口2：汉字显示（3）12864 液晶并口3：图形显示（4）12864 液晶并口4：综合演示（5）12864 液晶串口5：字符显示（6）12864 液晶串口6：汉字显示（7）12864 液晶串口7：图形显示（8）12864 液晶串口8：综合演示14、HS0038红外接口实验（1）红外遥控解码实验，在数码管上显示三、开发板综合程序1、温度时间综合实验（1）DS18B20 + DS1302 + 16022、SSCOM综合实验（1）PC发送接收字符第三章板上资源详解本章详细介绍了MSP430F149 学习板上各个功能模块的硬件电路原理、使用方法和注意事项，使用前请仔细阅读。

MSP430单片机的开发及应用设计人：陈小忠西安邮电学院电子信息工程系电子0002班西安邮电学院63# 7100612003年7月目录第一章概述第二章MSP430 F149语言介绍第一节开发环境及程序下载第二节语言介绍第三章MSP430F149 资源的应用介绍及开发第一节中断介绍及存储器段介绍第二节硬件乘法器第三节P口第四节定时器及数模转换第五节时钟模块第六节USART通信模块第七节比较器第八节模数转换第四章MSP430F149开发板的介绍及测试第一节模数转换模块第二节传感器模块第三节外存和实时时钟模块第四节485和232模块第五节电源管理模块及晶振模块第六节PWM波形滤波第一章概述MSP430是德州公司新开发的一类具有16位总线的带FLASH 的单片机,由于其性价比和集成度高,受到广大技术开发人员的青睐.它采用16位的总线,外设和内存统一编址,寻址范围可达64K,还可以外扩展存储器.具有统一的中断管理,具有丰富的片上外围模块,片内有精密硬件乘法器、两个16位定时器、一个14路的12位的模数转换器、一个看门狗、6路P口、两路USART 通信端口、一个比较器、一个DCO内部振荡器和两个外部时钟,支持8M 的时钟.由于为FLASH 型,则可以在线对单片机进行调试和下载,且JTAG口直接和FET(FLASH EMULATION TOOL)的相连,不须另外的仿真工具,方便实用,而且,可以在超低功耗模式下工作,对环境和人体的辐射小,测量结果为100mw左右的功耗(电流为14mA左右),可靠性能好,加强电干扰运行不受影响，适应工业级的运行环境,适合与做手柄之类的自动控制的设备.我们相信MSP430单片机将会在工程技术应用中得以广泛应用,而且,它是通向DSP系列的桥梁,随着自动控制的高速化和低功耗化 ,MSP430系列将会得到越来越多人的喜爱.通过两过多月的毕业设计,我对MSP430有了初步了解,对内部的硬件资源和自身的汇编语法进行了实验,并开发了一个应用板,并进行了调试.鉴于时间和能力有限,没能对所有的应用一一实验.第二章 MSP430 F149语言介绍MSP430是德州公司的新产品,有独特的开发环境和自身语言,下面是我在毕业设计中对F149的开发环境熟悉中遇到的一些问题的处理和汇编语言的用法及程序中遇到的问题的体会.第一节开发环境及程序下载1.开发环境:在EW23环境下进行编程,汇编,连接,在C—SPY环境下进行调试,下载是在连接之后,调试之前,通过计算机的串口下载的.关于环境的操作,可以参考有关资料,其中可能遇到的问题及解决方法有:(1) .汇编是对源程序而言的,因此必须打开一个源文件才能汇编,而连接是对一个工程文件而言的,连接是对工程文件的所有源代码(包括多个源文件)和数据的定位,因此连接必须打开一个工程文件才能连接.(2) 连接中必须将库文件的路径改正确,且必须选定C—SPY的驱动方式,即在project中的options的xlink的include下修改(先选中)xcl的库路径为$TOOLKIT_DIR$\icc430\msp430F149A.xcl ,选择C—SPY 的驱动drive为simulator或FLASH EMULATION TOOL ,当没连接430片子时可以选simulator,当连接430片子时,选 FLASH EMULATION TOOL进行在线下载调试.(3) 由于430支持汇编语言和C语言两种语言,因此可以在一个工程文件中同时用两种语言,但建议用汇编语言,因为便于在调试时寻找逻辑和指令的联系及地址的定位正确与否.(4) 在在线的C—SPY 的调试中,单步需要将Control的Reatime前的勾取消才能进行单步测试.(5) 在线调试时,不能将58 管脚（复位/非屏蔽中断）外部变高,否则,会强制退出调试环境.2.程序下载原理及脱机工作原理:程序的在线调试是通过JATG口和F149片子的 RST、TCK、TDI、TDO、TMS引脚按一定的时序串行的传递程序代码和数据的,调试指令的命令传递都是通过这些数据线和控制线传递的,下载时序可参见资料1,其中的地址0FFFEH为复位向量的地址,它是程序遇到非屏蔽中断和程序启动的首要地址,地址中存放的是程序段开始的首地址,因此必须把程序段的首地址标号表示在中断向量中或程序伪指令的开头位置,否则,连接时将会出错,具体的表示方法在下一节中表示.程序的下载和在线调试的电源是通过计算机在JATG提供的,不须另外给加电源.脱机工作时,是将F149的电源线上电,此时的复位时序同下载后在线复位的时序一样,只是时钟是通过F149内部时钟DCO提供的,上电后,程序将复位向量0FFFE中的地址装入PC,PC开始从程序段的首地址开始执行.脱机工作启动不需要任何操作,只需上电即可,电压要大于1.8v,一般取3v左右,另外,在脱机工作时,可以给RST端口加一个低电平脉冲以复位从程序开始重新执行.第二节指令介绍MSP430有自身语言,汇编语言也不同于其他类型的单片机,伪指令也是变幻魔测,但又很重要,下面是我毕业设计的一些尝试、出问题的地方.也可参见资料。

开发板简介
实物图：
特点:
1、USB接口，支持USB供电、USB下载、USB通信（和PC机通信）外接供电，跑马灯；
2、可以通过USB接口和PC机做串口通信实验;
3、八个LED流水灯，方便程序的调试；
4、所有引脚由双排排针引出，并有引脚标注，2.54mm标准间距，扩展方便；
5、带有NRF905无线模块接口，可做无线数传实验；
6、板上留有标准14针JTAG仿真调试接口和复位按键；
7、板上预留三路3.3V和5V的取电接口，方便为外围设备供电；
8、板上可外接电源从电，也可以USB取电；
9、板上配有四个铜柱，增强电路板的耐用性和可靠性；
10、带有最小系统板，方便更换芯片；
11，1602液晶接口；
12，12864液晶接口；
13，DS18B20接口；
14，红外接收头，一体化接收头；
15，485模块，可做485通实实验；
16，RS232模块，可做RS232通信；
17，无线模块接口，可做CC1100，NRF24L01，NRF905无线通信；18，板载8M晶振，可以插拨，可以随意更换晶振；
19，板载AD模块，可做AD模数转换实验；
引脚图：。

基于MSP430F149的GPS
(芯片篇)
1、系统功能框图
2芯片资料：
MSP430F149：
低电源电压范围：1.8~3.6V
超低功耗：待机模式：1.6uA 关闭模式(RAM保持)：0.1uA 活动模式：280uA at 1MHz，2.2V
5种省电模式
6us内从待机模式唤醒
16位RISC结构，125ns指令周期
带内部参考，采样保持和自动扫描特性的12位A/D转换器
有7个捕获/比较寄存器的16位定时器Timer_B 有3个捕获/比较寄存器的16位定时器Timer_A
片内集成比较器
串行在线编程，无需外部编程电压，安全熔丝可编程代码保护.
器件系列包括：–MSP430F133：8KB+256B闪速存储器，256B的RAM –MSP430F135：16KB+256B闪速存储器，512B的RAM –MSP430F147，MSP430F1471：32KB+256B闪速存储器，1KB的RAM –MSP430F148， MSP430F1481：48KB+256B闪速存储器，2KB的RAM –MSP430F149， MSP430F1491：60KB+256B闪速存储器，2KB的RAM
可用封装：64脚方形扁平封装(QFP).
功能框图。