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TMX320LF2402AVFS中文资料

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External Memory Interface (LF2407A) − 192K Words x 16 Bits of Total Memory: 64K Program, 64K Data, 64K I/O Watchdog (WD) Timer Module 10-Bit Analog-to-Digital Converter (ADC) − 8 or 16 Multiplexed Input Channels − 500-ns MIN Conversion Time − Selectable Twin 8-State Sequencers Triggered by Two Event Managers Controller Area Network (CAN) 2.0B Module (LF2407A, 2406A, 2403A) Serial Communications Interface (SCI) 16-Bit Serial Peripheral Interface (SPI) (LF2407A, 2406A, LC2404A, 2403A) Phase-Locked-Loop (PLL)-Based Clock Generation Up to 40 Individually Programmable, Multiplexed General-Purpose Input / Output (GPIO) Pins Up to Five External Interrupts (Power Drive Protection, Reset, Two Maskable Interrupts) Power Management: − Three Power-Down Modes − Ability to Power Down Each Peripheral Independently Real-Time JTAG-Compliant Scan-Based Emulation, IEEE Standard 1149.1† (JTAG) Development Tools Include: − Texas Instruments (TI) ANSI C Compiler, Assembler/ Linker, and Code Composer Studio Debugger − Evaluation Modules − Scan-Based Self-Emulation (XDS510) − Broad Third-Party Digital Motor Control Support Package Options − 144-Pin LQFP PGE (LF2407A) − 100-Pin LQFP PZ (2406A, LC2404A) − 64-Pin TQFP PAG (LF2403A, LC2403A, LC2402A) − 64-Pin QFP PG (2402A) Extended Temperature Options (A and S) − A: − 40°C to 85°C − S: − 40°C to 125°C
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS
Table of Contents
元器件交易网
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 TMS320x240xA Device Summary . . . . . . . . . . . . . . . . . 5 Functional Block Diagram of the 2407A DSP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Peripheral Memory Map of the 2407A/2406A . . . . . . . 29 Device Reset and Interrupts . . . . . . . . . . . . . . . . . . . . . 30 DSP CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 TMS320x240xA Instruction Set . . . . . . . . . . . . . . . . . . . 34 Scan-Based Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Functional Block Diagram of the 2407A DSP CPU . . 35 Internal Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Event Manager Modules (EVA, EVB) . . . . . . . . . . . . 45 Enhanced Analog-to-Digital Converter (ADC) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Serial Communications Interface (SCI) Module . . . . 53
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Code Composer Studio and XDS510 are trademarks of Texas Instruments. Other trademarks are the property of their respective owners. † IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port; however, boundary scan is not supported in this device family.
SPRS145K − JULY 2000 − REVISΒιβλιοθήκη D AUGUST 2005D
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High-Performance Static CMOS Technology − 25-ns Instruction Cycle Time (40 MHz) − 40-MIPS Performance − Low-Power 3.3-V Design Based on TMS320C2xx DSP CPU Core − Code-Compatible With F243/F241/C242 − Instruction Set and Module Compatible With F240 Flash (LF) and ROM (LC) Device Options − LF240xA: LF2407A, LF2406A, LF2403A, LF2402A − LC240xA: LC2406A, LC2404A, LC2403A, LC2402A On-Chip Memory − Up to 32K Words x 16 Bits of Flash EEPROM (4 Sectors) or ROM − Programmable “Code-Security” Feature for the On-Chip Flash/ROM − Up to 2.5K Words x 16 Bits of Data/Program RAM − 544 Words of Dual-Access RAM − Up to 2K Words of Single-Access RAM Boot ROM (LF240xA Devices) − SCI/SPI Bootloader Up to Two Event-Manager (EV) Modules (EVA and EVB), Each Includes: − Two 16-Bit General-Purpose Timers − Eight 16-Bit Pulse-Width Modulation (PWM) Channels Which Enable: − Three-Phase Inverter Control − Center- or Edge-Alignment of PWM Channels − Emergency PWM Channel Shutdown With External PDPINTx Pin − Programmable Deadband (Deadtime) Prevents Shoot-Through Faults − Three Capture Units for Time-Stamping of External Events − Input Qualifier for Select Pins − On-Chip Position Encoder Interface Circuitry − Synchronized A-to-D Conversion − Designed for AC Induction, BLDC, Switched Reluctance, and Stepper Motor Control − Applicable for Multiple Motor and/or Converter Control

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SMJ320F240资料

SMJ320F240资料


Copyright © 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
元器件交易网
SMJ320F240 DSP CONTROLLER
SGUS029 – APRIL 1999
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Processed to MIL–PRF–38535 (QML) High-Performance Static CMOS Technology Includes the T320C2xLP Core CPU – Object Compatible With the TMS320C2xx Family – Source Code Compatible With SMJ320C25 – Upwardly Compatible With SMJ320C50 – 50-ns Instruction Cycle Time Memory – 544 Words × 16 Bits of On-Chip Data/Program Dual-Access RAM – 16K Words × 16 Bits of On-Chip Program Flash EEPROM – 224K Words × 16 Bits of Total Memory Address Reach (64K Data, 64K Program and 64K I/O, and 32K Global Memory Space) Event-Manager Module – 12 Compare / Pulse-Width Modulation (PWM) Channels – Three 16-Bit General-Purpose Timers With Six Modes, Including Continuous Up and Up / Down Counting – Three 16-Bit Full-Compare Units With Deadband – Three 16-Bit Simple-Compare Units – Four Capture Units (Two With Quadrature Encoder-Pulse Interface Capability)
MEMORY存储芯片TMS320F2811PBKA中文规格书

MEMORY存储芯片TMS320F2811PBKA中文规格书

11TMS320C6745,TMS320C6747SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014Submit Documentation FeedbackProduct Folder Links:TMS320C6745TMS320C6747Device Overview Copyright ©2008–2014,Texas Instruments Incorporated 3.3.1C674x DSP CPU DescriptionThe C674x Central Processing Unit (CPU)consists of eight functional units,two register files,and two data paths as shown in Figure 3-2.The two general-purpose register files (A and B)each contain 3232-bit registers for a total of 64registers.The general-purpose registers can be used for data or can be data address pointers.The data types supported include packed 8-bit data,packed 16-bit data,32-bit data,40-bit data,and 64-bit data.Values larger than 32bits,such as 40-bit-long or 64-bit-long values are stored in register pairs,with the 32LSBs of data placed in an even register and the remaining 8or 32MSBs in the next upper register (which is always an odd-numbered register).The eight functional units (.M1,.L1,.D1,.S1,.M2,.L2,.D2,and .S2)are each capable of executing one instruction every clock cycle.The .M functional units perform all multiply operations.The .S and .L units perform a general set of arithmetic,logical,and branch functions.The .D units primarily load data from memory to the register file and store results from the register file into memory.The C674x CPU combines the performance of the C64x+core with the floating-point capabilities of the C67x+core.Each C674x .M unit can perform one of the following each clock cycle:one 32x 32bit multiply,one 16x 32bit multiply,two 16x 16bit multiplies,two 16x 32bit multiplies,two 16x 16bit multiplies with add/subtract capabilities,four 8x 8bit multiplies,four 8x 8bit multiplies with add operations,and four 16x 16multiplies with add/subtract capabilities (including a complex multiply).There is also support for Galois field multiplication for 8-bit and 32-bit data.Many communications algorithms such as FFTs and modems require complex multiplication.The complex multiply (CMPY)instruction takes four 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output.There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values.The 32x 32bit multiply instructions provide the extended precision necessary for high-precision algorithms on a variety of signed and unsigned 32-bit data types.The .L Unit (or Arithmetic Logic Unit)now incorporates the ability to do parallel add/subtract operations on a pair of common inputs.Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel.There are also saturated forms of these instructions.The C674x core enhances the .S unit in several ways.On the previous cores,dual 16-bit MIN2and MAX2comparisons were only available on the .L units.On the C674x core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting.Finally,to increase data packing and unpacking throughput,the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions.Unpack instructions prepare 8-bit data for parallel 16-bit operations.Pack instructions return parallel results to output precision including saturation support.Other new features include:•SPLOOP -A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel.The SPLOOP buffer reduces the code size associated with software pipelining.Furthermore,loops in the SPLOOP buffer are fully interruptible.•Compact Instructions -The native instruction size for the C6000™devices is 32bits.Many common instructions such as MPY,AND,OR,ADD,and SUB can be expressed as 16bits if the C674x compiler can restrict the code to use certain registers in the register file.This compression is performed by the code generation tools.•Instruction Set Enhancement -As noted above,there are new instructions such as 32-bit multiplications,complex multiplications,packing,sorting,bit manipulation,and 32-bit Galois field multiplication.•Exceptions Handling -Intended to aid the programmer in isolating bugs.The C674x CPU is able to detect and respond to exceptions,both from internally detected sources (such as illegal op-codes)and from system events (such as a watchdog time expiration).•Privilege -Defines user and supervisor modes of operation,allowing the operating system to give a basic level of protection to sensitive resources.Local memory is divided into multiple pages,each with read,write,and execute permissions.19TMS320C6745,TMS320C6747SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014Submit Documentation FeedbackProduct Folder Links:TMS320C6745TMS320C6747Device Overview Copyright ©2008–2014,Texas Instruments IncorporatedTable 3-3.C674x L1/L2Memory Protection Registers (continued)BYTE ADDRESSACRONYM REGISTER DESCRIPTION (2)These addresses correspond to the L1D memory protection page attribute registers 0-15(L1DMPPA0-L1DMPPA15)of the C674xmegamaodule.These registers are not supported for this device.0x0184A670L1PMPPA28L1P memory protection page attribute register 28(controls memory address 0x00E06000-0x00E067FF)0x0184A674L1PMPPA29L1P memory protection page attribute register 29(controls memory address 0x00E06800-0x00E06FFF)0x0184A678L1PMPPA30L1P memory protection page attribute register 30(controls memory address 0x00E07000-0x00E077FF)0x0184A67CL1PMPPA31L1P memory protection page attribute register 31(controls memory address 0x00E07800-0x00E07FFF)0x0184A67F –0x0184ABFF-Reserved 0x0184AC00L1DMPFAR L1D memory protection fault address register 0x0184AC04L1DMPFSR L1D memory protection fault status register 0x0184AC08L1DMPFCR L1D memory protection fault command register 0x0184AC0C -0x0184ACFF-Reserved 0x0184AD00L1DMPLK0L1D memory protection lock key bits [31:0]0x0184AD04L1DMPLK1L1D memory protection lock key bits [63:32]0x0184AD08L1DMPLK2L1D memory protection lock key bits [95:64]0x0184AD0CL1DMPLK3L1D memory protection lock key bits [127:96]0x0184AD10L1DMPLKCMD L1D memory protection lock key command register 0x0184AD14L1DMPLKSTAT L1D memory protection lock key status register 0x0184AD18-0x0184ADFF-Reserved 0x0184AE00-0x0184AE3F-Reserved (2)0x0184AE40L1DMPPA16L1D memory protection page attribute register 16(controls memory address 0x00F00000-0x00F007FF)0x0184AE44L1DMPPA17L1D memory protection page attribute register 17(controls memory address 0x00F00800-0x00F00FFF)0x0184AE48L1DMPPA18L1D memory protection page attribute register 18(controls memory address 0x00F01000-0x00F017FF)0x0184AE4CL1DMPPA19L1D memory protection page attribute register 19(controls memory address 0x00F01800-0x00F01FFF)0x0184AE50L1DMPPA20L1D memory protection page attribute register 20(controls memory address 0x00F02000-0x00F027FF)0x0184AE54L1DMPPA21L1D memory protection page attribute register 21(controls memory address 0x00F02800-0x00F02FFF)0x0184AE58L1DMPPA22L1D memory protection page attribute register 22(controls memory address 0x00F03000-0x00F037FF)0x0184AE5CL1DMPPA23L1D memory protection page attribute register 23(controls memory address 0x00F03800-0x00F03FFF)0x0184AE60L1DMPPA24L1D memory protection page attribute register 24(controls memory address 0x00F04000-0x00F047FF)0x0184AE64L1DMPPA25L1D memory protection page attribute register 25(controls memory address 0x00F04800-0x00F04FFF)0x0184AE68L1DMPPA26L1D memory protection page attribute register 26(controls memory address 0x00F05000-0x00F057FF)0x0184AE6CL1DMPPA27L1D memory protection page attribute register 27(controls memory address 0x00F05800-0x00F05FFF)0x0184AE70L1DMPPA28L1D memory protection page attribute register 28(controls memory address 0x00F06000-0x00F067FF)0x0184AE74L1DMPPA29L1D memory protection page attribute register 29(controls memory address 0x00F06800-0x00F06FFF)0x0184AE78L1DMPPA30L1D memory protection page attribute register 30(controls memory address 0x00F07000-0x00F077FF)。

岭澳二期DCS简介

岭澳二期DCS简介


AS620自动化系统
FUM模块主要类型
功能模件 FUM210ESG FUM210-GB FUM230 FUM232 功能描述 驱动控制模件 性能 可以控制和监视8个单机驱动器，5个电机、电磁阀、开 关装置、执行机构，4个伺服驱动器，3个逆向驱动器。 采集28个二进制信号（28个单接点或14个换向接点） 采集和处理16个转换器输入信号，0~20mA或4~20mA， 2或4线制 可连接14个热电阻或28个热电偶信号
ES系统为过程控制提供全范围的设计和组态功 能，如AS自动系统的设计、OM系统设计、局域网 LAN设计、设计硬件、文件编制、控制参数的在线 显示及诊断等功能。ES与电厂总线(Plant Bus)及 终端总线（Terminal Bus）相连，这样能够与 AS620和OM690系统的数据进行在线交换。机组运 行时ES680可离线，因此ES680非冗余配臵.
总线通讯系统
特点： 100Mbps传输速率 传输介质采用较强抗电磁干扰能力的光纤. 功能强大的带星型耦合的交换机模块 内臵冗余管理器，持续监视网络功能，自动探测 数据传输链路，并在300MS内启动备用链路。 LED自诊断故障报警 工作状态及故障数据报告诊断工程师站
总线通讯系统
TXP工程设计组态
TXP主要性能指标（合同约定）
信号类别 模拟量输入信号 （标准电流） 准则 ≦+/-0.25% 验证方法 通道校验
模拟量输入信号 （温度）
≦+/-0.4%
通道校验
AP（CPU）负荷
≦50% （最坏情况） DS670记录CPU扫描周 期并计算
总线符合（Plant bus/Terminal ≦20% （最坏情况） 脚本测试 bus ）
TXS系统介绍
第2章 TMS320LF240X系列DSP概述1

第2章 TMS320LF240X系列DSP概述1

第2章 TMS320LF240X系列DSP概述该系列包括：闪存：TMS320LF2402、TMS320LF2406、TMS320LF2407ROM: TMS320LC2402、TMS320LC2404、TMS320LC2406最具革命性产品：LF2407/ LF2407A,是当今世界上集成度最高、性能最强的运动控制DSP芯片。

2.1 TMS320LF240x系列DSP控制器专为数字电机控制和其它控制系统而设计的。

是当前集成度最高、性能最强的运动控制芯片。

不但有高性能的C2XLP CPU内核，配置有高速数字信号处理的结构，且有控制电机的外设。

它将数字信号处理的高速运算功能，与面向电机的强大控制功能结合在一起，成为传统的多微处理器单元和多片系统的理想替代品。

主要用途：（1）电机（交流伺服、直流永磁、开关磁阻）的鲁棒控制器。

（2）无刷电机的全变速控制。

（3）使用先进的算法可降低传感器的数量。

（4）汽车电子制动系统。

（5）多电机系统的单处理器控制。

（6）与控制算法处理一起完成电源开关转换的控制。

处理速度：LF240x为30MIPS，LF240xA为40MIPS。

240X采用诸如自适应控制、卡尔曼滤波和控制等先进的控制算法，支持多项式的高速实时算法，因而可减少力矩纹波、降低攻耗、减少振动，从而延长被控设备的寿命，为各种电机提供了高速、高效和全变速的先进控制技术。

4级流水线结构，采用改进的哈佛结构。

指令系统: 信号处理指令、通用控制指令。

源代码和目标代码与24x同代产品兼容，源代码与C2x兼容，且与C5x向上兼容。

利用它的为反转变址寻址能力可进行基2的FFT运算。

片内外设及存储器等资源:同一代的器件有相同的CPU结构，但片内存储器和外设配置不同。

引脚功能介绍地址、数据、存储器控制信号A0-A15：D0-D15：DS：数据空间选通；PS：程序空间选通；IS：I/O空间选通；R/W：读写选通，指明与外围器件信号的传送方向;W/R/IOPC0：为R/W的反；WE：对外部3个空间写；RD：对外部3个空间读；ST RB：外部存储器选通；READY：插入等待状态；MP/MC：微处理器/微计算机（控制器）方式选择ENA_144：=1，使能外部信号；=0，无外部存储器。