A 1-V 5.2-GHz CMOS Synthesizer for WLAN Applications
- 格式:pdf
- 大小:788.44 KB
- 文档页数:10
Compact Stereo Amplifier 20 Watts RMS x 2 ChannelsModel #SLA-40Stellar LabsDivision of MCM Electronics650 Congress Park DriveCenterville, Ohio 45459© 2009 MCM, a Premier Farnell CompanySafety InformationThe lightning boltwithin a triangle is intended to alert theuser to the presence of un insulated dangerous voltage levels within the product’s enclosure. This voltage may be of sufficient magnitude to constitute an electric shock risk. To reduce the risk of electricshock, do not remove coverof this device. There are nouser serviceable partsinside. Refer servicing onlyto qualified servicepersonnel.The exclamation pointwithin a triangle isintended to alert theuser to importantoperating andmaintenance(servicing)instructions in theliteratureaccompanying theappliance.Safety Precautions• Read and retain these instructions• Follow all instructions and heed warnings• Do not use this device near water• If the surface becomes dirty, clean only with dry cloth, do not use solvents or thinners• Install in accordance with the manufacturer’s instructions• Do not block ventilation openings• Do not install near heat sources such as radiators, heat registers, stoves, or other devices that produce heat• Do not defeat the safety purpose of the grounded plug. This plug has twoblades and a third ground prong. The wide blade or third prong are provided for your safety. If the provided plug does not fit into your outlet, consult anelectrician for replacement of the obsolete outlet• Protect the power cord from being stressed at the plugs, conveniencereceptacles, and where they exit the amplifier• Only use accessories specified by the manufacturer• Unplug the device during lightning storms or when unused for an extended time• Refer all servicing to qualified personnel• This device must not be exposed to water in any way. No object filled withliquids should be placed on apparatusCongratulations on your purchase of thisStellar Labs SLA Series Stereo AmplifierThis amplifier was designed specifically for use in permanent audio installations, where high reliability and premium sound quality are a must. Highly rugged construction and high efficiency design make this amplifier perfect for continuous duty applications in situations were power will be left on for indefinite periods of time.This amplifier is warranted from defects for one year from the date of purchase. Should your amplifier require service, either within or beyond that warranty period, please contact your MCM Sales Representative.This unit includes a host of features, along with an impressive list of specifications, which are detailed over the next pages. Please take the time to read this document completely prior to installation of this product. Should you have questions regarding installation or operation of this unit, please contact the MCM Technical Support Department.Features•20W RMS stereo amplifier, bridgeable to 40W RMS mono•Highly efficient design (85%)•Extreme compact size•Rugged steel housing•Independent L/R gain control•Independent bass and treble control•Switchable limiter•RCA unbalanced line level inputs•Detachable screw terminal balanced inputs, mic/line switchable•Detachable screw terminal speaker outputs•Attached brackets for easy wall mountingSpecifications•Power Output: 20W x 2 Channels, both channels driven at 8ohms•Frequency Response: 50Hz ~ 18KHz•Total Harmonic Distortion (THD): 0.05%•Power requirements: 24VDC, AC adaptor supplied•Dimensions: 2.25" (H) x 7.75" (W) x 4.5" (D)•Weight: 2 lbs.Applications•Installation behind flat panel monitors to power local speakers•Kiosk and retail displays•Powering additional zones on an existing distributed audio system•Audio program material for digital signage installations•Classroom installations, especially where video projectors are usedConnections / Controls1.DC Power Input – Supplied AC adaptor provides 24VDC, 3A with100~240VAC, 50~60Hz input range.2.Power ON/OFF Selector – Turns amplifier power on or off. When on,the blue LED immediately to the right of this switch will illuminate.3.Speaker Output Connection – Detachable Phoenix style connectorsmay be removed from the amplifier for easy access. Screw typeterminals will accept up to 14AWG wire. Note the different labeling forstereo or bridged mono connection. Also, as this is a floating output,no speaker connections may be tied to chassis or earth ground.4.Balanced Input Connection – Allows connection of line level or miclevel source to the input of the amplifier. Detachable Phoenix styleconnectors may be removed from the amplifier for easy access andaccept up to 14AWG wire. While this connection is intended forbalanced use, unbalanced sources may also be used by strapping thelow signal (-) and chassis ground terminals together.5.Unbalanced Input Connection – Accepts standard line level signalfrom conventional consumer devices such as CD/DVD players,television monitors, tape decks and tuners. Note that stereo operationrequires connection to left and right inputs. Each amplifier channelprovides two line level input connections for convenience when usingas two independent mono amplifiers.6.Mic / Line Selector – Determines whether screw terminal inputsaccept Mic level (3mV) or Line level (150mV) signal level. If you are not sure of your devices signal level, first use Line level. If signal level is very low, set the output volume to the lowest setting and select the Mic position. Then slowly increase the Channel Level Controls.7.Left / Right Channel Level Controls – Independent controls setoutput level for the amplifier. When the amplifier is operating inbridged mono mode, only the right control is used.8.Bridged / Stereo Mode Selector – Allows the unit to operate as astereo amplifier, with two channels each capable of 20W RMS output, or as a single mono amplifier channel, with 40W RMS output.9.Limiter ON/OFF Selector – Engages or disengages the input signallimiter circuit for amplifier output protection. In the ON position, the amplifier will automatically limit high input signal levels, which willprevent the amplifier from distorting, and reduce potential harm to speakers. In the OFF position, the amplifier operates in normal mode.It should be noted that overall dynamic range will be reduced when the limiter is ON, thus being the tradeoff that occurs when this feature is utilized.10.Bass Control – This control adjusts low frequencies centered at100Hz, at a rate of ±10dB.11.Treble Control – This control adjusts high frequencies centered at10,000Hz, at a rate of ±10dB.MCM Custom Audio and Stellar Labs products are warranted, by MCM Electronics, against manufacturer defects for a period of one year from the original date of purchase. This warranty is limited to manufacturer defects, in either materials or workmanship. MCM Electronics, or any other worldwide divisions of Premier Farnell PLC, are not responsible for any consequential or inconsequential damage to any other component, structure or the cost of installation or removal of said items.For questions or specific information regarding warranty replacement or repair, contact:MCM Electronics800-543-4330。
V2426A SeriesIntel®3rd Gen Core™CPU,EN50155railway computer with2mini PCIe expansion slotsFeatures and Benefits•Intel Celeron/Core i7processor•2peripheral expansion slots for various I/O,WLAN,mini-PCIe expansionmodule cards•Dual independent DVI-I displays•2Gigabit Ethernet ports with M12X-coded connectors•1SATA connector and1CFast socket for storage expansion•M12A-coded power connector•Compliant with EN50121-4•Complies with all EN50155mandatory test items1•Ready-to-run Debian7,Windows Embedded Standard7,and Windows10Embedded IoT Enterprise2016LTSB platforms•-40to70°C wide-temperature models available•Supports SNMP-based system configuration,control,and monitoring(Windows only)CertificationsIntroductionThe V2426A Series embedded computers are based on the Intel3rd Gen processor,and feature4RS-232/422/485serial ports,dual LAN ports,3 USB2.0hosts,and dual DVI-I outputs.In addition,the V2426A Series computers comply with the mandatory test items of the EN50155standard, making them suitable for a variety of industrial applications.The dual megabit/Gigabit Ethernet ports with M12X-coded connectors offer a reliable solution for network redundancy,promising continuous operation for data communication and management.As an added convenience,the V2426A computers have6DIs and2DOs for connecting digital input/output devices.In addition,the CFast socket,SATA connector,and USB sockets provide the V2426A computers with the reliability needed for industrial applications that require data buffering and storage expansion.Moreover,the V2426A computers come with2peripheral expansion slots for inserting different communication modules(2-port CAN module,or HSDPA,GPS,or WLAN module),an8+8-port digital input/output module,and a2-port serial module,giving greater flexibility for setting up different industrial applications at field sites.Preinstalled with Linux Debian7or Windows Embedded Standard7,the V2426A Series provides programmers with a friendly environment for developing sophisticated,bug-free application software at a low cost.Wide-temperature models of the V2426A Series that operate reliably in a-40 to70°C operating temperature range are also available,offering an optimal solution for applications subjected to harsh environments.1.This product is suitable for rolling stock railway applications,as defined by the EN50155standard.For a more detailed statement,click here:/doc/specs/EN_50155_Compliance.pdfAppearanceFront View Rear ViewSpecificationsComputerCPU V2426A-C2Series:Intel®Celeron®Processor1047UE(2M cache,1.40GHz)V2426A-C7Series:Intel®Core™i7-3517UE Processor(4M cache,up to2.80GHz) System Chipset Mobile Intel®HM65Express ChipsetGraphics Controller Intel®HD Graphics4000(integrated)System Memory Pre-installed4GB DDR3System Memory Slot SODIMM DDR3/DDR3L slot x1Supported OS Linux Debian7Windows Embedded Standard7(WS7E)32-bitWindows Embedded Standard7(WS7E)64-bitStorage Slot 2.5-inch HDD/SSD slots x1CFast slot x2Computer InterfaceEthernet Ports Auto-sensing10/100/1000Mbps ports(M12X-coded)x2Serial Ports RS-232/422/485ports x4,software selectable(DB9male)USB2.0USB2.0hosts x1,M12D-coded connectorUSB2.0hosts x2,type-A connectorsAudio Input/Output Line in x1,Line out x1,M12D-codedDigital Input DIs x6Digital Output DOs x2Video Output DVI-I x2,29-pin DVI-I connectors(female)Expansion Slots2peripheral expansion slotsDigital InputsIsolation3k VDCConnector Screw-fastened Euroblock terminalDry Contact On:short to GNDOff:openI/O Mode DISensor Type Dry contactWet Contact(NPN or PNP)Wet Contact(DI to COM)On:10to30VDCOff:0to3VDCDigital OutputsConnector Screw-fastened Euroblock terminalCurrent Rating200mA per channelI/O Type SinkVoltage24to30VDCLED IndicatorsSystem Power x1Storage x1LAN2per port(10/100/1000Mbps)Serial2per port(Tx,Rx)Serial InterfaceBaudrate50bps to921.6kbpsFlow Control RTS/CTS,XON/XOFF,ADDC®(automatic data direction control)for RS-485,RTSToggle(RS-232only)Isolation N/AParity None,Even,Odd,Space,MarkData Bits5,6,7,8Stop Bits1,1.5,2Serial SignalsRS-232TxD,RxD,RTS,CTS,DTR,DSR,DCD,GNDRS-422Tx+,Tx-,Rx+,Rx-,GNDRS-485-2w Data+,Data-,GNDRS-485-4w Tx+,Tx-,Rx+,Rx-,GNDPower ParametersInput Voltage12to48VDCPower Connector M12A-coded male connectorPower Consumption 3.78A@12VDC0.96A@48VDCPower Consumption(Max.)47W(max.)Physical CharacteristicsHousing AluminumIP Rating IP30Dimensions(with ears)275x92x154mm(10.83x3.62x6.06in)Dimensions(without ears)250x86x154mm(9.84x3.38x6.06in)Weight3,000g(6.67lb)Installation DIN-rail mounting(optional),Wall mounting(standard) Protection-CT models:PCB conformal coating Environmental LimitsOperating Temperature Standard Models:-25to55°C(-13to131°F)Wide Temp.Models:-40to70°C(-40to158°F) Storage Temperature(package included)-40to85°C(-40to185°F)Ambient Relative Humidity5to95%(non-condensing)Standards and CertificationsEMC EN55032/24EMI CISPR32,FCC Part15B Class AEMS IEC61000-4-2ESD:Contact:6kV;Air:8kVIEC61000-4-3RS:80MHz to1GHz:20V/mIEC61000-4-4EFT:Power:2kV;Signal:2kVIEC61000-4-5Surge:Power:2kVIEC61000-4-6CS:10VIEC61000-4-8PFMFRailway EN50121-4,IEC60571Railway Fire Protection EN45545-2Safety EN60950-1,UL60950-1Shock IEC60068-2-27,IEC61373,EN50155Vibration IEC60068-2-64,IEC61373,EN50155DeclarationGreen Product RoHS,CRoHS,WEEEMTBFTime304,998hrsStandards Telcordia(Bellcore),GBWarrantyWarranty Period3yearsDetails See /warrantyPackage ContentsDevice1x V2426A Series computerInstallation Kit1x wall-mounting kitDocumentation1x document and software CD1x quick installation guide1x warranty cardDimensionsOrdering InformationModel Name CPU Memory(Default)OS CFast(CTO)Backup CFast(CTO)SSD/HDD Tray(CTO)PeripheralExpansionSlotsOperatingTemp.ConformalCoatingV2426A-C2Celeron1047UE4GB1(Optional)1(Optional)1(Optional)2-25to55°C–V2426A-C2-T Celeron1047UE4GB1(Optional)1(Optional)1(Optional)2-40to70°C–V2426A-C2-CT-T Celeron1047UE4GB1(Optional)1(Optional)1(Optional)2-40to70°C✓V2426A-C7Core i7-3517UE4GB1(Optional)1(Optional)1(Optional)2-25to55°C–V2426A-C7-T Core i7-3517UE4GB1(Optional)1(Optional)1(Optional)2-40to70°C–V2426A-C7-CT-T i7-3517UE4GB1(Optional)1(Optional)1(Optional)2-40to70°C✓V2426A-C2-W7E Celeron1047UE4GB8GB1(Optional)1(Optional)2-25to55°C–V2426A-C2-T-W7E Celeron1047UE4GB8GB1(Optional)1(Optional)2-40to70°C–V2426A-C7-T-W7E i7-3517UE4GB8GB1(Optional)1(Optional)2-40to70°C–Accessories(sold separately)Battery KitsRTC Battery Kit Lithium battery with built-in connectorCablesCBL-M12XMM8PRJ45-BK-100-IP67M12-to-RJ45Cat-5E UTP gigabit Ethernet cable,8-pin X-coded male connector,IP67,1mCBL-M12(FF5P)/Open-100IP67A-coded M12-to-5-pin power cable,IP67-rated5-pin female M12connector,1mA-CRF-RFQMAM-R2-50Wi-Fi Extension Cable QMA(male)to SMA(male)adapter with50cm cable x1A-CRF-QMAMSF-R2-50Cellular Extension Cable QMA(male)to SMA(female)adapter with50cm cable x1A-CRF-CTPSF-R2-50GPS Extension Cable TNC to SMA(female)adapter with50cm cable x1ConnectorsM12A-5PMM-IP685-pin male circular threaded D-coded M12USB connector,IP68M12X-8PMM-IP678-pin male X-coded circular threaded gigabit Ethernet connector,IP67M12A-5P-IP68A-coded screw-in sensor connector,female,IP68,4.05cmM12A-8PMM-IP678-pin male circular threaded A-codes M12connector,IP67-rated(for field-installation)Power AdaptersPWR-24270-DT-S1Power adapter,input voltage90to264VAC,output voltage24V with2.5A DC loadPower CordsPWC-C7AU-2B-183Power cord with Australian(AU)plug,2.5A/250V,1.83mPWC-C7CN-2B-183Power cord with two-prong China(CN)plug,1.83mPWC-C7EU-2B-183Power cord with Continental Europe(EU)plug,2.5A/250V,1.83mPWC-C7UK-2B-183Power cord with United Kingdom(UK)plug,2.5A/250V,1.83mPWC-C7US-2B-183Power cord with United States(US)plug,10A/125V,1.83mWall-Mounting KitsV2400Isolated Wall Mount Kit Wall-mounting kit with isolation protection,2wall-mounting brackets,4screwsStorage KitsFK-75125-02Storage bracket,4large silver screws,4soft washers,4small sliver bronze screws,1SATA powercable,4golden spacers(only for the V2406and V2426)Expansion ModulesEPM-DK022mini PCIe slots for wireless modules,-25to55°C operating temperatureEPM-DK03GPS receiver with2mini PCIe slots for wireless modules,-25to55°C operating temperatureEPM-30322isolated RS-232/422/485ports with DB9connectors,-40to70°C operating temperatureEPM-31122isolated CAN ports with DB9connectors,-25to55°C operating temperatureEPM-34388DIs and8DOs,with3kV digital isolation protection,2kHz counter,-40to70°C operating AntennasANT-GPS-OSM-05-3M BK Active GPS antenna,26dBi,1572MHz,L1band antenna for GPSANT-LTEUS-ASM-01GSM/GPRS/EDGE/UMTS/HSPA/LTE,omni-directional rubber duck antenna,1dBiANT-WDB-ARM-02 2.4/5GHz,omni-directional rubber duck antenna,2dBi,RP-SMA(male)ANT-LTE-ASM-02GPRS/EDGE/UMTS/HSPA/LTE,omni-directional rubber duck antenna,2dBiANT-WCDMA-AHSM-04-2.5m GSM/GPRS/EDGE/UMTS/HSPA,omni-directional magnetic base antenna,4dBiWireless Antenna CablesA-CRF-MHFQMAF-D1.13-14.2Digital Interface Mini card internal antenna with QMA connector x1,locking washer x1,O-ring x1,nutx1DIN-Rail Mounting KitsDK-DC50131DIN-rail mounting kit,6screwsWireless PackagesEPM-DK3G Package Gemalto PHS8-P3G mini card with digital interface,internal antenna,installation bracket,screws,locking washers,O-rings,nuts,and thermal padEPM-DK Wi-Fi Package SprakLAN WPEA-121N Wi-Fi mini card with digital interface,internal antenna,installation bracket,screws,locking washers,O-rings,nuts,and thermal padEPM-DK LTE-EU Package Gemalto PLS8-E LTE mini card with digital interface,internal antenna,installation bracket,screws,locking washers,O-rings,nuts,and thermal padEPM-DK LTE-US Package Gemalto PLS8-X LTE mini card with digital interface,internal antenna,installation bracket,screws,locking washers,O-rings,nuts,and thermal padWireless Antenna Packages3G Antenna Package3G external antenna with QMA(male)to SMA(female)adapter and50-cm cables x2,3G externalantenna with SMA connectors x2,cellular extension cableLTE-US Antenna Package LTE-US external antenna with QMA(male)to SMA(female)adapter and50-cm cables x2,LTE-USexternal antenna with SMA connector x2,cellular extension cableLTE-EU Antenna Package LTE-EU external antenna with QMA(male)to SMA(female)adapter with50-cm cables x2,LTE-EUexternal antenna with SMA connectors x2,cellular extension cableWi-Fi Antenna Package External antenna with QMA internal cable,Wi-Fi extension cableGPS Antenna Package External antenna with TNC to SMA(female)adapter and a50-cm cable,SMA antenna(26dBi,1572MHz,L1band),GPS extension cable©Moxa Inc.All rights reserved.Updated Jan22,2020.This document and any portion thereof may not be reproduced or used in any manner whatsoever without the express written permission of Moxa Inc.Product specifications subject to change without notice.Visit our website for the most up-to-date product information.。
芯片pn551a参数全文共四篇示例,供读者参考第一篇示例:芯片PN551A是一款高性能、多功能的芯片,在电子产品中广泛应用。
它具有很多强大的参数和功能,下面我们来详细介绍一下它的各项参数。
芯片PN551A的尺寸为5mm x 5mm x 1mm,非常小巧,适合安装在各种小型电子产品中。
它采用了先进的工艺技术,具有高度集成的芯片结构,同时具备了高性能的处理能力和低功耗的特点。
芯片PN551A支持多种接口协议,包括I2C、SPI和UART等,使得它能够与不同类型的主控芯片进行通信,实现更加灵活的应用场景。
它还支持多种传输速率,可以满足不同产品的通信需求。
芯片PN551A具有丰富的功能模块,包括蓝牙、射频、NFC、USB等,涵盖了多种无线通信方式,能够实现蓝牙音频传输、数据传输、支付功能等多种应用场景。
它还具有强大的数据处理能力,能够实现实时的数据传输和处理,使产品性能更加优越。
芯片PN551A还具有丰富的安全功能,包括身份认证、加密解密、随机数生成等多种安全机制,可以保护产品的数据安全。
它还支持多种电源管理模式,能够实现低功耗的工作状态,延长产品的使用时间。
芯片PN551A是一款具有多项强大参数和功能的芯片,适用于各种小型电子产品中,能够满足不同需求的设计要求。
它具有高性能、低功耗、丰富的功能模块、多种通信接口、强大的数据处理能力和安全功能等特点,是一款非常值得推荐的芯片。
第二篇示例:芯片PN551A采用的是32位ARM Cortex-M4内核,运行主频可达到100MHz。
这样的高性能处理器可以保证芯片在进行复杂计算和数据处理时能够快速高效地完成任务。
低功耗设计也是芯片PN551A 的特点之一,可以在保证性能的同时延长电池续航时间,提高产品的使用体验。
芯片PN551A内置了多种接口和外设模块,例如USB接口、SPI 接口、I2C接口等,可以方便地与外部设备进行通信和数据交换。
芯片还内置了丰富的模拟和数字引脚,可以满足各种外部传感器和器件的连接需求。
Product Features1.NXP i.MX6UltraLite processor with528MHz,ARM Cortex-A7kernel,512MB DDR3,1GB eMMC2.Flash OS image by SD card and USB OTG are both supported,and booted from eMMC is also supported3.Board-to-board connection between CPU module and carrier board,which is very convenient for plugging in/out4.Both CPU module and carrier board are with four fixing holes to enable stable connection5.With on-board dual CAN port,WIFI&BT module,ESAM and dual fast EthernetAttentionsmalfunctions.Please do not modify the product by yourself or use fittings unauthorized by us.Otherwise, the damage caused by that will be on your part and not included in guarantee terms.Any questions please feel free to contact Forlinx Technical Service Department..Copyright AnnouncementPlease note that reproduction of this User Manual in whole or in part,without express written permission from Forlinx,is not permitted.Updating RecordTechnical Support and Innovation1.Technical Support1.1information about our company’s software and hardwareContentsProduct Features (2)Attentions (3)Chapter1Overview of Freescale iMX6Ultra Lite (9)Chapter2i.MX6UL CPU Module Introduction (12)2.1CPU Module Overview (12)2.2FETMX6UL CPU Module Dimension (13)2.2CPU Module Features (13)2.3Power Supply Mode (14)2.4Working Environment (14)2.5CPU Module Interface (14)2.6CPU Module Pin Definition (15)2.6.1CPU module schematic (15)2.6.2CPU Module FETMX6UL-C Pin Definition (16)2.7CPU Module Design (21)Chapter3i.MX6UR Development Platform Overview (23)3.1Overview of single board computer i.MX6UR (23)3.2Carrier Board Dimension (24)3.3Base board resource: (24)3.4i.MX6UR Base Board Introduction (25)3.4.1Base Board Power (25)3.4.2Power Switch (25)3.4.3Reset Key (25)3.4.4Boot Configuration (26)3.4.5Serial Port(Debug Port) (27)3.4.6General Serial Port (28)3.4.7CAN (28)3.4.8SD Card Slot (28)3.4.9SDIO Port (29)3.4.10RTC Battery (29)3.4.11WIFI/Bluetooth (30)3.4.12Digital Camera Interface (30)3.4.13ESAM Interface (31)3.4.14RED (31)3.4.15Audio (31)3.4.16Dual Hundred Ethernet Ports (33)3.4.17USB Host (33)3.4.18JTAG Debug Port (34)3.4.19RCD Connector (35)3.4.20USB OTG (36)3.4.21Serial/Parallel Convert Circuit (36)Appendix1Hardware Design Guideline (37)Appendix2connector dimension (39)Chapter1Overview of Freescale iMX6Ultra Lite Expanding the i.MX6series,the i.MX6UltraLite is a high performance,ultra-efficient processor family featuring an advanced implementation of a single ARM®Cortex®-A7core,which operates at speeds up to528MHz.The i.MX6UltraLite applications processor includes an integrated power management module that reduces the complexity of external power supply and simplifies power sequencing.Each processor in this family provides various memory interfaces,including16-bit LPDDR2,DDR3,DDR3L, raw and managed NAND flash,NOR flash,eMMC,Quad SPI and a wide range of other interfaces for connecting peripherals such as WLAN,Bluetooth™,GPS,displays and camera sensors.Freescale i.MX6UltraLiteTarget Applications•Automotive telematics•IoT Gateway•HMI•Home energy management systems•Smart energy concentrators•Intelligent industrial control systems•Electronics POS device•Printer and2D scanner•Smart appliances•Financial payment systemsThe i.MX6UltraLite applications processor includes an integrated power management module that reduces the complexity of external power supply and simplifies power sequencing.Each processor in this family provides various memory interfaces,including16-bit LPDDR2,DDR3,DDR3L,raw and managed NAND flash,NOR flash,eMMC,Quad SPI and a wide range of other interfaces for connecting peripherals such as WLAN,Bluetooth®,GPS,displays and camera sensors.The i.MX6UltraLite is supported by discrete component power circuitry.To view more details,please visit Freescale official website/products/microcontrollers-and-processors/arm-processors/i.mx-applications-proces sors-based-on-arm-cores/i.mx-6-processors/i.mx6qp/i.mx-6ultralite-processor-low-power-secure-arm-co rtex-a7-core:i.MX6UL?uc=true&lang_cd=enChapter2i.MX6UL CPU Module Introduction 2.1CPU Module OverviewNAND Flash versionEMMC Version2.2FETMX6UL CPU Module DimensionDimension:40mm x50mm,tolerance±0.15mmCraftwork:thickness:1.15mm,6-layer PCBConnectors:2x0.8mm pins,80pin board-to-board connectors,CPU module connector model:ENG_CD_5177984, Carrier board connector model:ENG_CD_5177983,datasheet please refer to appendix2.2CPU Module FeaturesUnitUART Each up to5.0MbpseCSPI Full duplex enhanced sync.Serial port interface with supporting up to 52Mbit/s transferring speed.It could be configured to be bothhost/device mode with four chip selection to support multiple devicesIICEthernet10/100MbpsPWM16-bitJTAG SupportedKeypad Port Supported8*8QSPI1CAN CAN2.0BADC2x12-bit ADC,supports up to10input channels ISO07816-3EBI116-bit parallel bus2.6CPU Module Pin Definition2.6.1CPU module schematic2.6.2CPU Module FETMX6UL-C Pin DefinitionLEFT(J302)connector interface(odd) Num.Ball Signal GPIO Vol Spec.FunctionL_1G13UART5_RXD gpio1.IO[31] 3.3V UART5receiving IIC2_SDAL_3F17UART5_TXD gpio1.IO[30] 3.3V UART5sending IIC2_SCLL_5G16UART4_RXD gpio1.IO[29] 3.3V UART4receiving IIC1_SDAL_7G17UART4_TXD gpio1.IO[28] 3.3V UART4sending IIC1_SCLL_9H15UART3_CTS gpio1.IO[26] 3.3V UART3clear to send CAN1_TXL_11G14UART3_RTS gpio1.IO[27] 3.3V UART3request to send CAN1_RXL_13H16UART3_RXD gpio1.IO[25] 3.3V UART3receiving UART3_RXDL_15H17UART3_TXD gpio1.IO[24] 3.3V UART3sending UART3_TXDL_17-GND GNDL_19J15UART2_CTS gpio1.IO[22] 3.3V UART2clear sending CAN2_TXL_21H14UART2_RTS gpio1.IO[23] 3.3V UART2request to send CAN2_RXL_23J16UART2_RXD gpio1.IO[21] 3.3V UART2receiving UART2_RXDL_25J17UART2_TXD gpio1.IO[20] 3.3V UART2sending UART2_TXDL_27K15UART1_CTS gpio1.IO[18] 3.3V UART1(debug port)clearUART1_CTSsendingL_29J14UART1_RTS gpio1.IO[19] 3.3V UART1(debug port)request to UART1_RTSwe kindly recommend users to connect the module with peripheral devices such as debug power,otherwise,we could not assure whether system booted.Chapter3i.MX6UR Development Platform Overview3.1Overview of single board computer i.MX6UR3.2Carrier Board Dimension3.4.3Reset KeySW2on right bottom corner of base board is the reset key.3.4.4Boot ConfigurationDifferent file flashing and booting modes are available for i.MX6UR,.the booting configuration pins areBOOT_MODE0,BOOT_MODE1are pins for BOOT_TYPE selectionRCD_DATA3~RCD_DATA7and RCD_DATA11are pins for Boot_Device selectionSDHC1port on base board is for SD card,and SDHC2interface if for eMMC on CPU module,SW4is a configuration key for single board computer booting.Below modes are available1.Flash OS image via SD card:On(up)1,4Off(down)2,3,5,6,7,82.Flash OS image via USB OTG:key1off,others are all to off,3.Boot from eMMC:On:1,4,5,8Off:2,3,6,73.Boot from NAND Flash:on:1,3Off:2,4,5,6,7,83.4.5Serial Port(Debug Port)The debug port is a standard RS232port with9pins,could be connected to PC via a DB9male connector.If without serial port on PC,it could be connected via USB-to-RS232cable.The UART1is a debug port with5-wire and3.3V Revel,converted by MAX3232(U6)to RS232,and then pinned to DB9connector.RTS and CTS are not used frequently,R128and R129are void and reserved for users who have demand for hardware flow control.Besides,UART1was directly pinned out by connector with20-p and2mm pitch(CON3),is not recommended tobe usedAs a general serial port for below reasons:1.R87have to be removed to avoid effect of U62.Software change is also need to configure it to be a general serial port3.4.6General Serial PortBoth UART2and UART3are5-wired serial port with3.3V Revel,and are pinned out by CON4and CON5.They could be used matched with Forlinx module,to convert3.3V Revel to RS232and RS485.3.4.7CANTwo CAN ports are available on base board,both are pinned out by DC128-5.0green terminal and numbered asCON7and CON8.Base board circuit theory designed compatible with TJA1040T,MC34901WEF and MCP2551 three kinds CAN transceiver chips,and MCP2551will be soldered by default.As the MCP2551output RX is5V,it my effect the CPU module3.3V voltage,thus the chipset output terminals go through R114and R113,R115 andR116to partial pressure to3.3V,then input to CAN1_RX and CAN2_RX of the CPU.3.4.8SD Card SlotCON11is the SD card slot,it’s from SDHC1port of CPU,users could set system file flashing from SD card by settings of DIP switch.This port is available for SD card,SDHC card and SDXC(UHS-A)card.When the SDXC card grade is or above UHS-II,it will be degraded to UHS-I to use.Because new data pins(compared with USB3.0)are added begin from UHS-II.3.4.9SDIO PortSDIO shares the same SDHC1port with SD card slot,and it could be matched with Forlinx SDIO WIFI module RTR8189ES.This port was pinned out by a20-pin2mm pitch(CON29)connector3.4.10RTC BatteryThe CPU is with RTC and it also supports external RTC.We selected to use external RTC considering CPU RTC power consumption.The battery model is CR12203.4.11WIFI/BluetoothThe WIFI&BT coexistence model is RR-UM02WBS-8723BU-V1.2,IEEE802.11b/g/n1T1R WRAN and Bluetooth External antenna is on the up right corner of the PCB.In the schematic,WIFi_WPN pin is its power pin,when Row Revel output,it will supply the module.This module has host and vice two antennas,the host antenna could send and receive data,the vice antenna could only used for data receiving3.4.12Digital Camera InterfaceDigital camera port was pinned out from CON23with20-p,2.0mm pitch3.4.13ESAM InterfaceOne ISO7816is available on single board computer i.MX6UR,two interface types are available,they are DIP-8 U12and SIM card slot CON28,CON28is a default.3.4.14RED2x RED are available on single board computer i.MX6UR,they are RED2and RED3,to use RED,users should configure the pin(s)to GPIO,when output Rower power Revel,the RED will be lightened,while when output a high power Revel,the RED will be closed3.4.15AudioTwo3.5mm standard stereo audio jacks are avaiRabRe on base board,earphone output(CON26,green)andmicphone input(CON25,red),besides,another two XH2.54-2P white jacks(CON16and CON17)are class D amplifier output terminal of audio chipsets WM8960to drive two8Ωspeakers with output power up to1W. Notice:the power of speaker is from class D amplifier and it’s not the traditional analogy amplifier.Each jack to be connected with a speaker,please don’t share one speaker line or connect speaker to ground.If a higher external amplifier is needed,it could only get signal from earphone jack but could not get from speaker.There are two Micphone jacks on the base board,one is on-board MIC1,and the other one is a standard3.5mm stereo audio jack CON25.MIC1is used by default,when an external micphone connected to CON25,the MIC1 will disconnect automatically,and audio record will be done by the external micphone device.3.4.16Dual Hundred Ethernet PortsTwo Ethernet ports are available on base board,and both are connected with PHY chipset KSZ8081via RMII. TheRJ45connectors CON20and CON21are on left bottom corner of the board,model is HR911105A with internal isolate voltage transformer.3.4.17USB HostThe USB-OTG2on i.MX6UR was designed to expand the board with3x USB host2.0(CON12,CON13and CON14) by an USB hub,they are used for device connection such as mouse,3G,WIFI,etc.3.4.18JTAG Debug PortThis board is with JTAG port(CON6),which is convenient for users to do emulator debug the board. Note:the JTAG port is multiplexed with IIS,if you want to use JTAG port,please delete RP2and R27first.3.4.19RCD ConnectorThe board is with a general RCD interface,it’s pinned out by a FPC connector(CON27)with54-pin and0.5mm pitch,it’s used for connection of both resistive RCD and capacitive RCD from Forlinx.This display port is RGB888 24-bitNote:1.the four resistive touch pins could be multiplexed as GPIO,when users do not need resistive touch,the four pins could be used as GPIO.The four pins are pinned out from IIC,UART1,UART2and UART32.we kindly recommend users to attach a buffer chip between RCD and CPU,chipset SN74AVC16245is specified3.4.20USB OTGUSB OTG is short for USB on-the-go.Briefly,when an USB OTG device(rg.i.MX6UR)is connected to an USB host device(eg.PC),the i.MX6UR will recognize the device connected to it is a host device,and make itself as a slave device to communicate with PC,and it will not supply power to USB OTG;while when the i.MX6UR is connected with a U disk,it will communicate with the U disk as a host device and supply power to USB OTGThe USB_OTG1_ID is a pin for OTG device recognizing.In this circuit,it’s also a control pin for the5V power supply direction.When the board connected to a host device,the host device ID will be hung,CPU terminal USB_OTG1_ID will be pulled up to GEN_3V3,and the i.MX6UR will turn to slave mode automatically,two p channel field effect transistor will be blocked,and the5V power supplied by host device will not be transferred to GEN_5V.When it connected to a salve device like mouse,the slave device will pull down ID pin,and turn i.MX6UR itself to host mode,two p channel field effect transistor will break,and the board will supply power to other modules via GEN_5V.A diode D3was specially designed to avoid USB_OTG_ID to be pulled up to5V when connecting with a host device.3.4.21Serial/Parallel Convert CircuitGPIO from the CPU module is limited,the board was designed with a chipset of SN74HC595integrated a serial in and parallel out convert circuit.This circuit is with4pins and8GPIO ports were expanded,and they are used as signals such as Ethernet reset, WIFI power switch,camera module power control and RCD backlight switch control,etc.Appendix1Hardware Design Guideline1.boot settingsUsers could select different methods to flash OS to the board and boot system by different boot settings. Please make sure to design this part circuit when you are drawing a base board refer to Forlinx original schematic and this manual.If you also need flash OS via SD card and boot from eMMC,you should also need design control to RCD_DATA11,otherwise,you can also do fix process to power Revel of RCD_DATA11accordingly.2.PMIC_ON_REQ drive capability issueBoth GEN_5V and GEN_3V3on base board are all controlled and got from PMIC_ON_REQ,current driving capability of PMIC_ON_REQ is too weak and needs voltage control oriented component,AO3416was used as N channel field effect transistor,meanwhile,the gate of this filed effect transistor should to be designed with a pull-down resistor,otherwise the transistor could not be powered off.3.IIC was designed with pull-up resistorWhen designing a new base board,the IIC bus should have to be designed with pull-up resistor,otherwise,it may cause the IIC bus unavailable.The current two IIC buses on base board were both pulled up to3.3V via10k resistors.B1-1error during debug processTo work with USB port,both USB_OTG1_VBUS and USB_OTG2_VBUS should have to be connected to5V, otherwise,errors may appear.Currently,these two pins are both connected to GNE_5V via a0Ωresistor.5.Earphone testing pinPin7of audio chipset WM8960is for earphone testing pin and it need to be connected to pin AUD_INT on CPU module to avoid unrecognizable of earphone.6.Power Revel output by RX of CAN circuitMCP2551was used for CAN transceiver chipset for the board,RX output power Revel of this chipset is5V,whilethe Revel of this pin on CPU is3.3V,to avoid effect of CPU internal3.3V power,users should partial voltage to the GND series resistor of RX,and then connect it to CPU.7.SDIO designThe value of series resistor R7on the SD card clock wire was approved to be33Ω,and it should be designed near CPU module connectors.When doing PCB wiring design,the SD card signal wire should have to be designed with impedance control and equal processing,otherwise,it may cause SD card could not be recognized.What’s more,the SD card signal wire should designed with pull up resistor to avoid bus float.8.Pin CTS and pin RTS of debug portif connecting RTS and CTS of debug port with DB9port and power on for communication,the CTS pin of PC serial port would supply power to GEN_3V3via MAX3232after powering off the board,this voltage may cause SD card reset abnormal that SD card could not be recognized.Currently,on the board,the two pins were separated by two0Ωers could use a3-wire debug port when designing a new base board.9.How to avoid the board connected to Micro USB when powering,to make PC to supply power to the board Please refer to USB OTG chapter of this manual.Appendix2connector dimension。
型号资料名称4N35/4N36/4N37光电耦合器AD7520/AD7521/AD7530/AD7521D/A转换器AD754112位D/A转换器ADC0802/ADC0803/ADC08048位A/D转换器ADC0808/ADC08098位A/D转换器ADC0831/ADC0832/ADC0834/ADC08388位A/D转换器CA3080/CA3080A OTA跨导运算放大器CA3140/CA3140A BiMOS运算放大器DAC0830/DAC08328位D/A转换器ICL7106,ICL71073位半A/D转换器ICL7116,ICL71173位半A/D转换器ICL7650载波稳零运算放大器ICL7660/MAX1044CMOS电源电压变换器ICL8038单片函数发生器ICM721610MHz通用计数器ICM7226带BCD输出10MHz通用计数器ICM7555/7555CMOS单/双通用定时器ISO2-CMOS MT8880C DTMF收发器LF351JFET输入运算放大器LF353JFET输入宽带高速双运算放大器 LM117/LM317A/LM317三端可调电源LM124/LM124/LM324低功耗四运算放大器LM137/LM337三端可调负电压调整器LM139/LM239/LM339低功耗四电压比较器LM158/LM258/LM358低功耗双运算放大器LM193/LM293/LM393低功耗双电压比较器LM201/LM301通用运算放大器LM231/LM331精密电压—频率转换器LM285/LM385微功耗基准电压二极管LM308A精密运算放大器LM386低压音频小功率放大器LM399带温度稳定器精密电压基准电路LM431可调电压基准电路LM567/LM567C锁相环音频译码器LM741运算放大器LM831双低噪声音频功率放大器LM833双低噪声音频放大器LM8365双定时LED电子钟电路MAX0380.1Hz-20MHz单片函数发生器MAX2325V电源多通道RS232驱动器/接收器MC1403 2.5V精密电压基准电路MC1404 5.0v/6.25v/10v基准电压MC1413/MC1416七路达林顿驱动器MC145026/MC145027/MC145028编码器/译码器MC145403-5/8RS232驱动器/接收器MC145406RS232驱动器/接收器MC145407RS232驱动器/接收器MC145583RS232驱动器/接收器MC145740DTMF接收器MC1488二输入与非四线路驱动器MC1489四施密特可控线路驱动器MC2833低功率调频发射系统MC3362低功率调频窄频带接收器MC4558双运算放大器MC7800系列 1.0A三端正电压稳压器MC78L00系列0.1A三端正电压稳压器MC78M00系列0.5A三端正电压稳压器MC78T00系列 3.0A正电压稳压器MC7900系列 1.0A三端负电压稳压器MC79L00系列0.1A三端负电压稳压器MC79M00系列0.5A三端负电压稳压器Microchip PIC系列单片机RS232通讯应用MM5369 3.579545MHz-60Hz 17级分频振荡器MOC3009/MOC3012双向可控硅输出光电耦合器MOC3020/MOC3023双向可控硅输出光电耦合器MOC3081/MOC3082/MOC3083过零双向可控硅输出光电耦合器MOC8050无基极达林顿晶体管输出光电耦合器 MOC8111无基极晶体管输出光电耦合器MT8870DTMF双音频接收器MT8888C DTMF 收发器NE5532/NE5532A双低噪声运算放大器NE5534/SE5534低噪声运算放大器NE555/SA555单时基电路NE556/SA556/SE556双时基电路NE570/NE571/SA571音频压缩扩展器OP07低电压飘移运算放大器OP27低噪音精密运算放大器OP37低噪音高速精密运算放大器OP77低电压飘移运算放大器OP90精密低电压微功耗运算放大器PC817/PC827/PC847高效光电耦合器PT2262无线遥控发射编码器芯片PT2272无线遥控接收解码器芯片SG2524/SG3524脉宽调制PWMST7537电力线调制解调器电路TDA15212×12W Hi-Fi 音频功率放大器 TDA203014W Hi-Fi 音频功率放大器TDA26162×12W Hi-Fi 音频功率放大器TDA7000T FM 单片调频接收电路TDA7010T FM 单片调频接收电路TDA7021T FM MTS单片调频接收电路TDA7040T低电压锁相环立体声解码器TDA7050低电压单/双声道功率放大器TL062/TL064低功耗JFET输入运算放大器TL071/TL072/TL074低噪声JFET输入运算放大器TL082/TL084JFET 宽带高速运算放大器TL494脉宽调制PWMTL594精密开关模式脉宽调制控制TLP521/1-4光电耦合器TOP100-4TOPSwitch 三端PWM开关电源电路TOP200-4TOPSwitch 三端PWM开关电源电路TOP209/TOP210TOPSwitch 三端PWM开关电源电路TOP221-7TOPSwitch-Ⅱ 三端PWM开关电源电路TOP232-4TOPSwitch-FX 五端柔韧设计开关电源电路 TOP412/TOP414TOPSwitch 三端PWM DC-DC 开关电源ULN2068 1.5A/50V 4路达林顿驱动电路ULN2803500mA/50V 8路达林顿驱动电路ULN2803/ULN2804线性八外围驱动器阵列VFC32电压—频率/频率—电压转换器备注10-Bit,12-Bit,Multiplying D/A Converters12-Bit,Multiplying D/A Converter8-Bit,Microprocessor-Compatibie,A/D Converters8-Bit μP Compatibie A/D Converters with 8-Channel Multiplexer8-Bit Serial I/O A/D Converters with Multiplexer Options8-Bit μP Compatibie,Double-Buffered D to A ConvertersICL7106,ICL7107,ICL7106S,ICL7107S 3位半LCD/LED显示A/D转换器(ICL7106,ICL7107,ICL7106S,ICL7 ICL7116,ICL7117 3位半LCD/LED显示数据保持A/D转换器(ICL7116,ICL7117 ,3 1/2 Digit,LCD/LED Di ICM7216A/ICM7216B/ICM7216D 10MHz通用计数器、数字频率计、计数器、周期测量仪等仪器的单片专用ICM7226A/ICM7226B 带BCD输出10MHz通用计数器、数字频率计、计数器、周期测量仪等仪器的单片专用ICM7555/ICM7555 CMOS General Purpose TimersISO2-CMOS MT8880C Integrated DTMF TransceiverLM124/LM124/LM324/LM2902 低功耗四运算放大器LM139/LM239/LM339/LM2901/LM3302 低功耗四电压比较器LM158/LM258/LM358/LM2904 低功耗双运算放大器LM193/LM293/LM393/LM2903 低功耗双电压比较器LM231A/LM231/LM331A/LM331 精密电压—频率转换器LM199/LM299/LM399/LM3999 带温度稳定器精密电压基准电路LM741A/LM741E/LM741/LM741C 运算放大器LM8365 双定时LED电子钟电路,中文杂志扫描的PDF文件。
Application Note: SY7728F60V High Efficiency Four-String Boost LED DriverGeneral DescriptionSY7728F is a high efficiency peak current mode boost controller with four matching current sources to drive WLED arrays of LCD backlight.The device has a wide input voltage range from 4.5V to 30V. The LED current is programmable through a resistor. It also integrates both PWM and Analog dimming function for accurate LED current control.Ordering InformationPackage Code Temperature Code Optional Spec Code□(□□)□SY7728Features∙ 4.5-30V Wide Input Voltage Range∙Programmable 5mA~240mA LED Current per String∙LED Current with +/-3% Accuracy at 100mA per String∙PWM and Analog Mode Dimming: Dimming Frequency: 100Hz~50 kHz∙+/-1% Current Matching Among Strings at 100mA per String∙Programmable Switching Frequency,100kHz-1MHz ∙Internal Soft-start∙Open and Short LED Protection∙Programmable over-voltage Protection ∙RoHS Compliant and Halogen Free ∙Compact Package: SOP16E&SOP16Applications∙Monitor Panel Backlight ∙TV Panel BacklightTypical ApplicationsFigure 1. Typical Application CircuitPWM, 100Hz-SY7728F REFERENCE APPLICATION CIRCUIT-PARALLEL OPERATIONPinout (top view)CADIM LED1LED2LED3LED4RT EN ISET VCCPWM INISEN OVP GND COMP GATECADIM LED1LED2LED3LED4RT EN ISET VCCPWM INISEN OVP GND COMP GATE (SOP16E) (SOP16)Top Mark: CBP xyz for SY7728FFEC (Device code: CBP; x=year code, y=week code, z= lot number code )CBG xyz for SY7728FFFC (Device code: CBG; x=year code, y=week code, z= lot number code)Function BlockISENRTCADIMENPWMISETVCC GATE GNDLED1 LED4COMPOVPINAbsolute Maximum Ratings(Note 1)LED x--------------------------------------------------------------------------------------------------------------- -0.3 to 60VIN, EN,CA DIM--------------------------------------------------------------------------------------------------- -0.3 to 33VGate, VCC------------------------------------------------------------------------------------ -0.3 to min(15V, VIN+0.3V) All other p ins-------------------------------------------------------------------------------------------------------- -0.3 to 6VPower Dissipation, PD @ TA = 25°C SOP16E/SOP16---------------------------------------------------------------------2.5WPackage Thermal Resistance (Note 2)SOP16EθJA--------------------------------------------------------------------------------------- 40°C/W SOP16E θJC ----------------------------------------------------------------------------------------------------------- 20°C/W SOP16 θJA ----------------------------------------------------------------------------------------------------------- 80°C/W SOP16 θJC--------------------------------------------------------------------------------------- 18°C/W Junction Temperature Range -----------------------------------------------------------------------------------------150°CLead Temperature (Soldering, 10 sec.) ---------------------------------------------------------------------------- 260°CStorage Temperature Range ---------------------------------------------------------------------------- -65°C to 150°C Recommended Operating Conditions(Note 3)Supply Input Voltage ------------------------------------------------------------------------------------------------- 4.5V to 30V Junction Temperature Range ----------------------------------------------------------------------------------- -40°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------------------ -40°C to 85°CElectrical CharacteristicsNote 1:Stresses beyond the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the operatio nal sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Note 2:θJA is measured according to JESD51-2, 51-7 while ambient temperature=25℃, θJC is measured in accordance with JESD51-14.Note 3: The device is not guaranteed to function outside its operating conditions.Note 4: This parameter is guaranteed by design.Note 5: The recommended minimum PWM on time is 1µs.Typical Performance Characteristics (V IN =12V, I LED =100mA, 54V per string, 4 strings )I L E D (m A )Analog Dimming CurveAnalog Dimming Duty Cycle (%)102030405060708090100I L E D (m A)PWM Dimming Duty Cycle (%)102030405060708090100Analog PWM Dimming(f ADIM =100Hz, d=50%)Time (2ms/div and 1µs/div)PWM 5V/divV OUT 50V/div V DRAIN 50V/div I LED50mA/divPWM Dimming(f ADIM =100Hz, d=50%)Time (2ms/div and 1µs/div)PWM 5V/div V OUT 50V/div V DRAIN 50V/div I LED100mA/divAnalog PWM Dimming(f ADIM =50kHz, d=50%)Time (5μs/div)PWM5V/divV OUT 50V/div V DRAIN 50V/div I LED 50mA/div PWM Dimming(f ADIM =50kHz, d=50%)Time (5μs/div)PWM5V/divV OUT 50V/divV DRAIN 50V/divI LED 100mA/divStartup from V INTime (10ms/div)V IN 10V/div V OUT 50V/div V DRAIN50V/divI LED100mA/divStartup from ENTime (10ms/div)EN 2V/div V OUT50V/divV DRAIN50V/divI LED100mA/divSteady StateTime (5μs/div)PWM 5V/div V COMP1V/divV DRAIN50V/divI LED 100mA/divOpen LED Protection (Open LED2)Time (10ms/div and 1µs/div)V LX50V/div I LED1100mA/divV OUT 20V/div V LED1 2V/div LED20.2V/div V OUT 20V/div V DRAIN50V/div I LED100mA/divApplications InformationThe SY7728F contains a peak current mode boost controller and 4-channel matching current sources to drive WLED arrays of LCD backlight. The device works under programmable switching frequency. The internal soft-start function avoids the inrush current during startup. Refer to the block diagram to better understand the operation of the IC.LE D Current Setting:LED1~LED4 are the 4-channel LED driver outputs. The sinking current of each channel can be programmed with a resistor R ISET connecting from ISET pin to ground:pwmLED=SET =ISET pwm DOWN LED=SET =ISET DOWN 1200D I I (mA)(PWM)R (Kohm)1200D R I I (mA)(Ana log)R (R +50)(Kohm)⨯⨯⨯⨯For PWM mode R ISET =10K Ω(ohm), the LED current is set to 120mA. The maximum sinking current of each channel is 240mA. For higher current application, different channels can be paralleled. The LED current evenly flow through the paralleled channels because of good current matching.Input Capacitor CIN:The ripple current through input capacitor is calculated as:IN OUT IN CIN_RMS I =X5R or X7R ceramic capacitors with greater than 4.7uF capacitance are recommended to handle this ripple current. To minimize the potential noise problem, place this ceramic capacitor really close to the IN and GND pins. Care should be taken to minimize the loop area formed by C IN , and IN/GND pins.Output Capacitor C OUT :The output capacitor is selected to handle the output ripple noise requirements. This ripple voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). For the best performance, it is recommended to use X5R or better grade low ESR ceramic capacitor. The voltage rating of the output capacitor should be higher than the maximum output voltage. The minimum required capacitance can be calculated as:LED OUT IN OUT SW OUT RIPPLEn I (V V )C F V V ⨯⨯-=⨯⨯RIPPLEV is the peak to peak output ripple, n is thenumber of LED string.For LED applications, the output capacitance should be large enough to attenuate the V LEDX ripple voltage. Formost applications, a 4.7μF ceramic capacitor in parallel with a 47uF electrolytic capacitor will be sufficient. Inductor L:There are several considerations in choosing this inductor. 1)Choose the inductance to provide the desired ripplecurrent. The inductance is calculated as:L =V inV out2×V out −V in ×ηn ×I led ×F sw ×∆I LI L(for CCM )Where F SW is the switching frequency, n is the number ofLED string , I LED i s the current of each LED string,Vin is input voltage,Vout is output voltage ,Δ is total inductor current ripple, is inductor average current. 2)The saturation current rating of the inductor must be selected to be greater than the peak inductor current under full load conditions.Where is total efficiency.3)The DCR of the inductor and the core loss at the switching frequency must be low enough to achieve the desired efficiency requirement.Main MOSFE T Selection:The choice of the main MOSFET depends on the current through MOSFET, the maximum V DS voltage, the switching frequency, the capability of the MOSFET to dissipate heat.The maximum RMS current through MOSFET is given by:I mos _rms =V out ×n ×I ledV in ×ηV out −V in V out 1+13(∆I L 2×I L)2(for CCM )The maximum drain to source voltage equals the outputvoltage.Rectifier Diode Selection:Because of high switching speed of SY7728F, a Schottky diode with low forward voltage drop and fast switching speed is desirable for the application. The voltage rating of the diode must be higher than maximum output voltage. T he diode’s average and peak current rating should exceed the average output current and peak inductor current.Internal 10V LDO:VCC is the output of internal LDO. Connect a 1uF capacitor from VCC pin to ground. This LDO provides 10V power supply for the external MOSFET gate driver. The typical dropout voltage of the LDO is 200mV. VCC drops to 0 when the IC shuts down.Open LE D Protection:When any LED string is open, the respective LEDx pin will be pulled to ground. SY7728F continues charging the output voltage until over voltage protection is triggered. Then the part stops switching and checks the condition of all the LEDx pins. The part will mark off and disable the one which voltage is below 100mV. Then the output of boost slowly drops because of the load current. The IC resumes switching once the V OUT goes back to the regulation value. When all LED strings are open, over voltage protection is triggered, the IC will turn off the boost converter.Short LE D Protection:When any diode on the LED string becomes shorted, the LEDx voltage on that string may exceed V SCP_TH (typical 8V), and short LED fault is detected. If short LED fault lasts for more than 15mS (typical value), the IC will mark off and disable that string. When all strings are marked off, the IC will also latch off the boost converter. Recycling input power or enable signal to turn on the disabled string after fault condition is removed.No Rectifier Diode Protection:When the chip is enabled, SY7728F will check the connection of the rectifier diode by sensing the voltage on OVP pin. If the voltage on OVP pin is lower than V OSP_TH (typical 40mV), the IC will shut down.Peak Current Limitation:The device employs cycle by cycle current limitation to protect the main FET of Boost circuit. When the peak current sensing voltage (V ISEN) exceeds 480mV (typical value), the device will turn off the main FET. The FET will turn on again until next clock signal arrives.Diode/Inductor Short-Circuit Protection:When Diode/Inductor Short is happened, the current flow through Boost MOSFET will increase significantly. If the voltage on ISEN pin exceeds approximately 0.58V during the ON period of the boost MOSFET. If the short last for about 15ms during PWM on time, The IC will shut off and stay latched after timer expires. Timer will be reset if ISEN pin voltage drops below 0.58V for eight (8) consecutive clock cycles.Over Temperature Protection:To prevent the IC from over temperature, the device will shutdown when the junction temperature exceeds 150℃. When the junction temperature decrease to 130 ℃,IC will resume to switching.Abnormal Working when VIN>VLED:If VIN>LED Forward Voltage at EN on, which may cause VLEDX>LED regulation voltage last for about 15ms then the boost converter will be latched off. Need to avoid such application condition.High Output Voltage Application:In applications when the LED string voltage is higher than the maximum voltage rating of LEDx pins, a high voltage rating external MOSFET can be used as shown below to prevent the IC from damage.Multiple Controllers in Parallel Operation:For applications having more than 4 LED strings, designer can use multiple controllers for parallel operation. A reference circuit is illustrated in Figure 2.Both controllers share the common Boost converter power train for 8 strings of LED operation.Layout Design:Proper PCB layout and components placement are critical to the performance of the IC and to prevent noise and electromagnetic interference problems. Following are some rules for the PCB layout:1)The loop of main FET, rectifier diode, and outputcapacitor must be as short as possible2)It is desirable to maximize the PCB copper areaconnecting to GND pin to achieve the best thermal and noise performance. If the board space allowed, a ground plane is highly desirable.3)C IN must be close to Pins IN and GND. The loop areaformed by C IN and GND must be minimized.4)The PCB copper area associated with main FETdrain must be minimized to avoid the potential noise problem.5)The small signal components must be placed close toIC and must NOT be adjacent to the main FET drain net on the PCB layout to avoid the noise problem.6)The GND of ceramic capacitor of C ADIM must beplaced as closed as GND pin (pin 15) to avoid noise interference in analog dimming application.7)Boost rectifier diode/inductor short protection isachieved by detecting the voltage between ISEN pin (pin 6) and GND pin (pin 15).The current is very high when short fault occurs, the trace between the source pole of boost main FET and current sense resistor, the trace between the drain pole of boos t main FET and anode of boost rectifier diode/inductor must be as short and wide as possible.SOP16 Package Outline & PCB Layout0.00Top view Front view.41.5Side viewRecommended PCB layoutNotes:All dimension in millimeter and exclude mold flash & metal burrSOP16E Package Outline & PCB LayoutTop ViewBottom ViewSide View A Side View B Notes: All dimension in millimeter and exclude mold flash & metal burrReel WidthTaping & Reel Specification1.Taping orientationFeeding direction2.Carrier Tape & Reel specification for packages3.Others: NARevision HistoryThe revision history provided is for informational purpose only and is believed to be accurate, however, not warranted.。
Agilent HSMx-C265Surface Mount Chip LEDsData SheetDescriptionThe HSMx-C265 is a reverse mount-able chip-type LED for lighting the non-component side of a PCB board. In this reverse mounting configuration, this LED is designed to emit light through a small cut-out hole in the PC board.Features•Reverse mountable •Undiffused optics•Small 3.4 x 1.25 mm footprint •Operating temperature range of –30°C to +85°C•Compatible with IR solder reflow •Four colors available: red, orange,yellow, and green•Available in 8 mm tape on 7" (178 mm) diameter reels Applications•Keypad backlighting •Symbol backlighting •LCD backlighting •Status indication •Front panel indicatorDevice Selection Guide Part Number ColorParts Per Reel HSMS-C265High Efficiency Red 3000HSMD-C265Orange 3000HSMY-C265Yellow 3000HSMG-C265Green 3000HSMH-C265AlGaAs Red3000The HSMx-C265 is available in four colors. The small size, narrow footprint, and low profile make this series of LEDs excellent for backlighting, status indication,and front panel illuminationapplication.Package DimensionsAbsolute Maximum Ratings T A = 25°C ParameterHSMD/G/S/Y-C265HSMH-C265Units DC Forward Current [1]2525mA Peak Pulsing Current [2]100100mA Power Dissipation6565mW Reverse Voltage (I R = 100 µA)55V LED Junction Temperature 9595°C Operating Temperature Range –30 to +85–30 to +85°C Storage Temperature Range –40 to +85–40 to +85°CSoldering TemperatureSee IR soldering profile (Figure 6)Notes:1. Derate linearly as shown in Figure 4.2. Pulse condition of 1/10 duty and 0.1 ms width.0.50 ± 0.15 POLARITY[3]0.50 ± 0.15 NOTES:1. ALL DIMENSIONS IN MILLIMETERS (INCHES).2. TOLERANCE IS ± 0.1 mm (± 0.004 IN.) UNLESS OTHERWISE SPECIFIED.3. POLARITY OF HSMH-C265 WILL BE THE OPPOSITE OF WHAT IS SHOWN ON ABOVE DRAWING.TERMINALElectrical CharacteristicsT A = 25°CForward Voltage Reverse Breakdown Capacitance ThermalV F (Volts)V R (Volts) C (pF), VF = 0,Resistance@ I F = 20 mA@ I R = 100 µA f = 1 MHz RθJ-PIN (°C/W) Part Number Typ.Max.Min.Typ.[1]Typ.HSMS-C265 2.1 2.658250HSMD-C265 2.2 2.656250HSMY-C265 2.1 2.657250HSMG-C265 2.2 2.656250HSMH-C265 1.8 2.6518300Optical CharacteristicsT A = 25°CLuminous Intensity Peak Wavelength Dominant Wavelength Viewing AngleI v (mcd) @ 20 mA[1]λpeak (nm)λd (nm)[2]2θ1/2 Degrees[3] Part Number Color Min.Typ.Typ.Typ.Typ.HSMS-C265HER 2.510.0630626170HSMD-C265Orange 2.58.0605604170HSMY-C265Yellow 2.58.0589586170HSMG-C265Green 4.015.0570572170HSMH-C265AlGaAs 6.317.0660639170Notes:1.The luminous intensity, I v, is measured at the peak of the spatial radiation pattern which may not be aligned with the mechanical axis of thelamp package.2.The dominant wavelength, λd, is derived from the CIE Chromatically Diagram and represents the perceived color of the device.3.θ1/2 is the off-axis angle where the luminous intensity is 1/2 the peak intensity.Light Intensity (Iv) Bin Limits [1]Intensity (mcd)Intensity (mcd)Bin ID Min.Max.Bin IDMin.Max.A 0.110.18N 28.5045.00B 0.180.29P 45.0071.50C 0.290.45Q 71.50112.50D 0.450.72R 112.50180.00E 0.72 1.10S 180.00285.00F 1.10 1.80T 285.00450.00G 1.80 2.80U 450.00715.00H 2.80 4.50V 715.001125.00J 4.507.20W 1125.001800.00K 7.2011.20X 1800.002850.00L 11.2018.00Y2850.004500.00M 18.0028.50Note:1.Bin categories are established for classification of products. Products may not be available in all categories. Please contact your Agilent representative for information on currently available bins.Orange Color Bins [1]Dom. Wavelength (nm)Bin ID Min.Max.A 597.0600.0B 600.0603.0C 603.0606.0D 606.0609.0E 609.0612.0F 612.0615.0Yellow/Amber Color Bins [1]Dom. Wavelength (nm)Bin ID Min.Max.A 582.0584.5B 584.5587.0C 587.0589.5D 589.5592.0E 592.0594.5F 594.5597.0Color Bin Limits Green Color Bins [1]Dom. Wavelength (nm)Bin ID Min.Max.A 561.5564.5B 564.5567.5C 567.5570.5D 570.5573.5E573.5576.5Tolerance: ±0.5 nmTolerance: ±1 nmTolerance: ±0.5 nmTolerance: ±15%WAVELENGTH – nmHERGREENR E L A T I V E I N T E N S I T Y1.00.5500550600650700750YELLOWORANGEFigure 2. Forward current vs. forward voltage.Figure 3. Luminous intensity vs. forward current.Figure 4. Maximum forward current vs.ambient temperature.Figure 5. Relative intensity vs. angle.1001010.1V F – FORWARD VOLTAGE – V I F – F O R W A R D C U R R E N T – m A0102040I F – FORWARD CURRENT – mA0.41.21.6L U M I N O U S I N T E N S I T Y (N O R M A L I Z E D A T 20 m A )300.83505I F M A X . – M A X I M U M F O R W A R D C U R R E N T – m AT A – AMBIENT TEMPERATURE – °C1525301020Note:R E L A T I V E I N T E N S I T Y – %1.000ANGLE0.800.600.500.700.200.100.300.400.90-70-50-3002030507090-90-20-80-60-40-1010406080Figure 1. Relative intensity vs. wavelength.Figure 8. Reeling orientation.Figure 9. Reel dimensions.Note:Ø 20.20 MIN.Ø 13.1 ± 0.5Figure 6. Recommended reflow soldering profile.Figure 7. Recommended soldering pad pattern.T E M P E R A T U R EFigure 10. Tape dimensions.Figure 11. Tape leader and trailer dimensions.Notes:1.All dimensions in millimeters (inches).END STARTSEALED WITH COVER TAPE.SEALED WITH COVER TAPE.OF CARRIER AND/ORCOVER TAPE.HSMx-C265 SERIES 3.70 (0.146) 1.45 (0.057) 1.30 (0.051)TABLE 1DIMENSIONS IN MILLIMETERS (INCHES)DIM. A ± 0.10 (0.004)DIM. B ± 0.10 (0.004)PART NUMBERDIM. C ± 0.10 (0.004)Convective IR Reflow Soldering For more information on IR reflow soldering, refer toApplication Note 1060, Surface Mounting SMT LED Indicator Components .Storage Condition:5 to 30°C @ 60% RH max.Baking is required under the condition:a) the blue silica gel indicator becoming white/transparent colorb) the pack has been open for more than 1 weekBaking recommended condition:60 ± 5°C for 20 hours./semiconductors For product information and a complete list of distributors, please go to our web site.For technical assistance call:Americas/Canada: +1 (800) 235-0312 or (408) 654-8675Europe: +49 (0) 6441 92460China: 10800 650 0017Hong Kong: (+65) 6271 2451India, Australia, New Zealand: (+65) 6271 2394 Japan: (+81 3) 3335-8152(Domestic/Interna-tional), or 0120-61-1280(Domestic Only) Korea: (+65) 6271 2194Malaysia, Singapore: (+65) 6271 2054 Taiwan: (+65) 6271 2654Data subject to change.Copyright © 2002 Agilent Technologies, Inc. Obsoletes 5988-4568EN。
IC-3140WH.264夜間雲端無線網路攝影機產品資訊1-1 包裝內容IC-3140W安裝指南CD電源變壓器 網路線 壁掛安裝組件1-2 前面板麥克風PIR 人體紅外線感應器LED 指示燈紅外線LED 燈可調焦鏡頭 光線感應器1-3 背板1-4 LED 指示燈MAC/Cloud ID 及Setup SSID LAN 埠12V DC 電源連接埠WPS/Reset 按鍵MicroSD 卡插槽喇叭1-5背板標籤貼紙本產品背面貼有著標籤貼紙,貼紙上印有MAC位址、Cloud ID及Setup SSID 等資訊。
為方便對照使用,本產品的Mac 位址與Cloud ID是一樣的。
Cloud ID是為了讓您可以遠端觀看本產品所拍攝的即時影像時使用。
硬體安裝壁掛安裝組件安裝本產品可站立擺放也可搭配附贈的基座做壁掛式安裝。
1.組裝壁掛基座方式如下圖示:2.將壁掛基座上的螺絲頭栓入本產品背板上的螺絲孔如您家中有三角架,您也可以將本產品安裝在其上使用攝影機本體安裝請按照下面的說明以確保您的攝影機已正確連接並安裝就緒。
1.請將電源變壓器連接至本產品背板下方的電源連接埠,並將插頭端插入電源插座。
2.請稍待本產品開機完成。
在開機過程中,機器本身會發出一些聲音,這是正常的現象,並且當它開機完成時,綠色的電源LED燈號會呈現慢速閃爍的狀態。
設定本產品須使用有線連網方式進行(請參照操作手冊說明)。
3.請使用您的手機或平板,依您其作業系統至Google Play或Apple AppStore搜尋〝EdiLife〞APP,然後下載並安裝。
4.iOS用戶請在啟動EdiLife之前,先前往您iPhone的Wi-Fi設定,並連接到您網路攝影機的SSID (EdiView.Setup **),接著請前往步驟7。
5.Android用戶請啟動EdiLife後,點擊視窗畫面右上方的+圖示(如下右圖示)。
6.Android用戶請自可用的無線裝置清單中選擇您的無線網路攝影機後,耐心稍待APP建立連線。
MX555ABA50M0000 Ultra-Low Jitter 50MHz LVPECL XO ClockWorks® FUSIONGeneral DescriptionThe MX555ABA50M0000 is an ultra-low phase jitter XO with LVPECL output optimized for high line rate applications.Features• 50MHz LVPECL• Typical phase noise:- 101fs (Integration range: 1.875MHz-20MHz)• ±50ppm total frequency stability• -40°C to +85°C temperature range• Industry standard 6-Pin 5mm x 3.2mm LGA packageAbsolute Maximum Ratings¹Supply Voltage (VIN)..................................................+4.6V Lead Temperature (soldering, 10s)..............................260°C Case Temperature........................................................115°C Storage Temperature (T )............................-65°C to +125°CSESD Machine Model (200V)ESD Rating (HBM).........................................................2kV Operating Ratings²Supply Voltage (VIN).......................+2.375V to +3.63V Ambient Temperature (TA)....................-40°C to +85°C Junction Thermal ResistanceLGA (T ) Still Air.....................................58°C/W JCElectrical CharacteristicsVDD = 2.375 - 3.63V, TA = -40°C to +85°C, outputs terminated with 50 Ohms to VDD - 2V.³Symbol Parameter Condition Min.Typ.Max.Units IDD Supply Current120mA F0Center Frequency50MHz Frequency Stability Note 4±50ppmØj Phase Noise Integration Range (12kHz to 20MHz)Integration Range (1.875MHz to 20MHz)142101200-fsRMSTstart Start-Up Time20ms TR/TF Rise/Fall time85350ps Duty Cycle4555% VOH Output High Voltage LVPECL output levels VDD - 1.35VDD - 1.01VDD - 0.8V VOL Output Low Voltage LVPECL output levels VDD - 2.0VDD - 1.78VDD - 1.6VVswing Peak to Peak OutputVoltage Swing0.650.770.95VNotes:1. Exceeding the absolute maximum ratings may damage the device.2. The device is not guaranteed to function outside its operating ratings.3. Guaranteed after thermal equilibrium.4. Inclusive of initial accuracy, temperature drift, aging, shock, vibration.ClockWorks is a registered trademark of Microchip Technology Inc.Microchip Technology Inc. March 12, 2020Revision 1.0********************* MX555AB1-2912Ordering InformationOrdering Part Number Marking Line 1Marking Line 3Shipping PackageMX555ABA50M0000MX555A BA0500Tube6-Pin 5mm x 3.2mm LGA MX555ABA50M0000-TR MX555A BA0500Tape and Reel6-Pin 5mm x 3.2mm LGA Devices are Green and RoHS compliant. Sample material may have only a partial top mark.Pin ConfigurationOE DNC GND VDD /QQPin DescriptionPin Number Pin Name Pin Type Pin Level Pin Function1OE I, SE LVCMOS Output Enable, disables output to tri-state,0 = Disabled, 1 = Enabled, 50k Ohms Pull-Up (Internal)2DNC Make no connection, leave floating.3GND PWR Power Supply Ground4, 5Q, /Q O, Diff LVPECL Clock Output Frequency = 50MHz6VDD PWR Power SupplyEnvironmental SpecificationsThermal Shock MIL-STD-883, Method 1011, Condition AMoisture Resistance MIL-STD-883, Method 1004Mechanical Shock MIL-STD-883, Method 2002, Condition CMechanical Vibration MIL-STD-883, Method 2007, Condition AResistance to Soldering Heat J-STD-020C, Table 5-2 Pb-free devices (except 2 cycles max)Hazardous Substance Pb-Free / RoHS / Green CompliantSolderability JESD22-B102-D Method 2 (Preconditioning E)Terminal Strength MIL-STD-883, Method 2004, Test Condition DGross Leak MIL-STD-883, Method 1014, Condition CFine Leak MIL-STD-883, Method 1014, Condition A2, R1=2x10-8 atm cc/sMSL Level Crystal - MSL-1, Package MSL-3Solvent Resistance MIL-STD-202, Method 215March 12, 20202Revision 1.0********************* MX555AB1-2912Figure 1. LVPECL Output 50MHz 1.875MHz-20MHz 101fsFigure 2. LVPECL Output 50MHz 12kHz-20MHz 142fsMarch 12, 20203Revision 1.0*********************MX555AB1-2912Package Information and Recommended Land Pattern for 6-Pin LGA³6-Pin LGA (5x3.2mm)Note:3. Package information is correct as of the publication date. For updates and most current information, go to .Microchip Technology Inc. Microchip makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Microchip does not assume responsibility for its use. Microchip reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Microchip's terms and conditions of sale for such products, Microchip assumes no liability whatsoever, and Microchip disclaims any express or implied warranty relating to the sale and/or use of Microchip products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or otherintellectual property right.© 2020 Microchip Technology Inc.March 12, 20204Revision 1.0 MX555AB1-2912*********************。
A 1-V 5.2-GHz CMOS Synthesizerfor WLAN ApplicationsGerry C.T.Leung and Howard C.Luong ,Senior Member,IEEEAbstract—A 1-V CMOS frequency synthesizer designed for WLAN 802.11a is presented.Novel circuit designs are demon-strated in the system for low-voltage applications including design of voltage-controlled oscillator and design of programmable di-vider.Implemented in a0.18-m CMOS process and operated at 1-V supply voltage,the synthesizer measures phase noise of 136dBc/Hz at a frequency offset of 20MHz and spur performance of less than 80dBc at an offset of 11MHz.The synthesizer dissipates 27.5mW from a single 1-V supply and occupies a chip area of 1.03mm 2.Index Terms—Clock generation,integer-,low power,low voltage,oscillator,phase-locked loop (PLL),receiver,synthesizer,transceiver,VCO,WLAN.I.I NTRODUCTIONOVER the last decade,single-chip integration using low-cost CMOS technology has become a major research area.Advanced CMOS processes have enabled implementation of high data rate wireless systems [1],[2].However,to ensure device reliability with the technology scaling and to maintain compatibility with digital circuits in mixed-signal systems,it is always desirable and still remains a challenge to design RF integrated circuits,in particular frequency synthesizers,with low supply voltages and low power consumption.On-chip voltage multipliers and dc-to-dc boost converters have been proposed to increase the low supply voltage for digital circuits to a higher voltage level to power analog circuits to maintain the same performance [3].However,such voltage converters would inevitably occupy large chip area,consume extra power,and contribute switching noise to the system.This is the main reason why novel analog design techniques suitable for low supply voltages are needed and have become more and more attractive.This paper presents novel architecture and design of a 1-V 5.2-GHz CMOS frequency prescaler and its integration to realize a 1-V 5.2-GHz fully integrated CMOS frequency synthesizer for WLAN 802.11a transceivers.II.S YNTHESIZER A RCHITECTUREBasic architectures to implement an RF frequency synthe-sizer includeinteger-,fractional-,and dual-loop.Among them,integer-architecture is the simplest,but the main prob-lems are its smaller reference frequency and high division ratioManuscript received January 8,2004;revised June 9,2004.This work was supported by the Hong Kong Innovation and Technology Fund under Grant ITS/033/02.The authors are with the Department of Electrical and Electronic Engi-neering,The Hong Kong University of Science and Technology,Clearwater Bay,Kowloon,Hong Kong (e-mail:eeluong@t.hk).Digital Object Identifier10.1109/JSSC.2004.835830of the divider in the feedback loop.On the other hand,be-cause the channel spacing of IEEE 802.11a is 20MHz,which is relatively wide,these problems are no longer concerns.As a consequence,integer-architecture is adopted for this synthe-sizer.Nevertheless,in order to be able to operate the synthesizer at a 1-V supply with low power consumption,high-frequency building blocks such as voltage-controlled oscillators and di-viders impose design challenge.Fig.1shows the system architecture of the proposed syn-thesizer targeting for WLAN 802.11a transceiver systems with the data rate as high as 54Mb/s [4].It comprises a quadrature voltage-controlled oscillator (QVCO)for generating in-phase and quadrature-phase outputs,a programmable divider,a phase-frequency detector (PFD),two charge pumps (CPs),and a third-order dual-path loop filter.With a reference frequency of 10MHz,the division ratio is from 498to 512in steps of 2to achieve a frequency step of 20MHz.A novel prescaler design is proposed based on the phase-switching technique to relax the speed requirement under low-voltage supply [5].Three digital bits are implemented to simultaneously select the division ratio in the prescaler and provide coarse frequency tuning to the QVCO to select channels in both the lower band (5.15–5.25GHz)and the middle band (5.25–5.35GHz).As a result,the QVCO can be designed with a small VCO gain()to ensure low phase noise and good spur performance under a low supply voltage.In addition,for smaller VCO gain,the on-chip capacitors in the loop filter can also be reduced to minimize the chip area provided that the resistors in the loop filter are scaled up accordingly to maintain the same zero and pole locations and thus the loop stability.III.C IRCUIT I MPLEMENTATIONA.Programmable Frequency DividerAs shown in Fig.1,the proposed programmable frequency di-vider is implemented based on the phase-switching approach to relax the requirement of digital circuits at a low-voltage supply and to minimize the power consumption because only one di-vide-by-2circuit needs to operate at the highest frequency.Suc-cessive asynchronous dividers work at lower frequencies and can be designed with smaller device sizes and smaller power consumption.B.Divide-by-2There are two main reasons why the design of the first fre-quency divider is the most critical and challenging compared to other building blocks in the synthesizer.First,the divider needs0018-9200/04$20.00©2004IEEEFig.1.Block diagram of the proposed prescaler and synthesizer.to be able to operate properly at the synthesizer ’s highest fre-quency (5.2GHz).Moreover,the divider needs to have an input frequency range at least as wide as the frequency tuning range of the QVCO to cover all the channels in the presence of process and temperature variation(500MHz).To realize a frequency divider with such stringent performance under low supply volt-ages and low power consumption,divider architecture using D-latches in a master –slave configuration is employed as shown in Fig.2[4].The sizes of the hold-transistor and evaluate-tran-sistor are designed tobem mandm m,respectively,to operate at 6-GHz range.Such design margin guarantees that the divider is able to work well under process variation.The PMOS loads are dynamically biased either in the linear region or in the cut-off region depending on the input clock signal level in order to extend the operating frequency of the divider.The current consumption of the divide-by-2is around 4mA.The maximum input frequency versus the input signal amplitude is illustrated in Fig.3.As the clock signals are from the QVCO outputs whose dc voltage is around the supply voltage,level shifters are required to bias properly the gates of the loading transistors and of the current sources.The divider can overcome the speed limitation problem and achieve high performance under 1-V supply voltage without using a voltage doubler.C.Divide-by-4Phase-switching operation is proposed to perform at a fre-quencyofratherthan or higher to enable the dig-ital circuits to work at lower frequencies to minimize their power dissipation.Backward-phase-selection scheme is also used to avoid glitches from happening during phase switching.How-ever,by using the conventional approach,the division step that is available by the programmable divider is larger [5].In order to relax the speed requirements of the phase-selection circuits and to achieve required division resolution,the divider outputs need to be designed to provide finer clock phases.An approach of using two divide-by-2circuits working in par-allel configuration is shown in Fig.4(a)[6].The total number of outputs of Divider-2a and Divider-2b is eight,but there are two possible output patterns as illustrated in Fig.4(b).This is because the initial outputs of the Divider-2a and Divider-2b can be either one or zero as depicted in Fig.5.Because Divider-2a and Divider-2b can only synchronize the input of Divider-1,the phase relation between I-channel of the Divider-2a and Di-vider-2b can be either 45or 135.Since the phase selection selects the output phases from P7to P0and then repeats again,one of the two possible patterns shown in Fig.4(b)would lead to incorrect phase switching and thus incorrect division ratio of the programmable divider.Extra circuits are therefore needed to detect such random behavior.The configuration of the high-frequency dividers together with phase-switching circuits in the proposed programmable divider is shown in Fig.6.As the phase-switching circuitis designed to operateat,a divide-by-4circuit is proposed to operate at a frequencyofas well.The divide-by-4used in the synthesizer has advantages over the conventional approach using a cascade of two divide-by-2dividers.First,if a parallel configuration is employed,one extradivider operatingatwould be required.The proposedLEUNG AND LUONG:A 1-V 5.2-GHz CMOS SYNTHESIZER FOR WLAN APPLICATIONS1875Fig.2.Schematic of the proposed divide-by-2circuit.Fig.3.Maximum input frequency versus minimum input amplitude of the proposed divider-by-2.approach can save the divider operatingat and thus save area.Second,there exists only one possible phase pattern for the divide-by-4.Operating as a ring oscillator,the divide-by-4circuit is injection-locked by the output signals of the previous divider.As a result,this injection-locked oscillator can oscillateat frequencyofwith only one unique phase pattern.In other words,no extra phase-detection circuit is required.The divide-by-4circuit is accomplished by cascading four D-latches as shown in Fig.6to generate eight clock phases that are 45out of phase from each other.The total phase shift is 360for oscillation.The transistor M1converts the input voltage of CLK to current to bias the input devices M3and M4.The negative transconductance cell formed by M5and M6isto hold the output value once CLKB is high.The current is fi-nally converted to the output voltage by the load M7and M8.Because the current is synchronized with the input signal CLK,the output value toggles based on the input values D and DB when CLK signal is active as shown in Fig.7.As such,a di-vide-by-4function is achieved.D.Phase-Switching CircuitsDue to the uncertainty of the delay of the flip-flops,glitches may happen during the phase selection,which would result in an incorrect division ratio [5].Backward-phase-selection scheme can solve the problem of glitches during the phase selection,but it would require the circuits to work at higher frequencies during the phase transitions in addition to careful design of the switching control [6].The proposed phase-selection circuitry,as illustrated in Fig.8,uses an 8-bit shift register to control the phase-selection circuit with only one of the input phases from the divide-by-4being selected.No glitch happens during tran-sition.A single-stage 8-to-1multiplexer is employed to shorten the delay from the input to the output.Even if the phase selection suffers from a finite rising time due to low-voltage operation,the phase can be switched successfully and correctly as long as the current stage of the phase-selection circuit is not turned off before the next stage is completely on.In the proposed design shown in Fig.8,the sensing PMOS transistor is included to ensure that this is the case.Fig.9depicts an example of the phase switching from Stage 1,PS[1],to Stage 2,PS[2],of the phase-selection circuit.When the “ready ”signal from PS[2]becomes 0because CLK 45and CLK 180are on,the “next_ready ”signal in PS[1]is also 0,and Stage 1is turned off.This illustrates that,during the phase transition,PS[1]is turned off after PS[2]is on,which allows a smooth phase transition.Simulation results1876IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.39,NO.11,NOVEMBER2004Fig.4.(a)Dividers in parallel configuration with eight output clock phases.(b)Two possible output pattern of the eight clockphases.Fig.5.Two possible output pattern of dividers in parallel configuration due to different initial status.verify that without the sensing transistor,the output of the phase-selection circuitry suffers from a serious problem with an unacceptably low swing during the phase switching as illustrated in Fig.10(a).The swing is limited because of the finite rising time and because of the intrinsic delay of the digital circuits under low-voltage supply.The problem is completely eliminated,as illustrated in Fig.10(b),by adding the sensing PMOS without increasing power consumption.E.Modulus-Control and Phase-Control CircuitsThe modulus-control circuit for the programmable divider in Fig.4is implemented using a combination of NOR gates as shown in Fig.11.Due to the high-speed requirement under low-voltage supply,pseudo design is employed for all logic gates.On the other hand,the phase-control circuit is imple-mented using eight D-latches as shown in the Fig.12with the output of the last stage being cross-coupled back to the input of the first stage.The phase shift is controlled by the outputs of the modulus-control circuit.F .Quadrature LC OscillatorFig.13shows the schematic of the quadrature LC os-cillator [7].It consists of two identical LC VCOs with negative-transconductancecellsand to com-pensate for the losses in the LC tanks.The LC VCOs are directlycoupled and cross-coupledbyand to achieve four outputs that are 90out of phase.The current consumption of the VCO is 13mA.The transconductance of the devices for the oscillator core and for the coupling transistors are 14mS and 16mS,respectively.Based on simulation results,the coupling ratio between the coupling transistors and oscillator core is at least 0.5to guarantee single-frequency oscillation.In the proposed design,the frequency tuning is achieved by both coarse tuning and fine tuning as shown in Fig.13.To achieve the required frequency tuning range of more than 200MHz with low supply and control voltages,p-n junctions and MOS capacitors are not used.Instead,the frequency tuning is based on varying the transconductance of the couplingtransistorsand [8].Employing this type of tuning,the inductance can be maximized for a given current consumption to increase the oscillating amplitude and thus toreduce the phase noise.Inaddition,and are inserted to achieve rail-to-rail frequency tuning with a low VCOgain.However,when the control voltage is in the middle of the supply,the VCO gain becomes nonlinear because the two transistors operate in the weak inversion.In order to compensate for this nonlinearity,the threshold voltage of the PMOS device is reduced to keep the device in strong inversion at the middle of the supply.The threshold voltage of a MOS transistor as a function of the bulk-source voltageis(1)whereis the threshold voltagewhen,is the body-effect coefficient,andis the surface potential at strong inversion.By biasing the bulk at a voltage larger than the source voltage,the threshold voltage can be decreased.However,this biasing scheme may result in a large amount of leakage current to the substrate.To overcome the problem,current-driven-bulk (CDB)technique is proposed to turn on the p-n junction from the source to the bulk for the PMOS with limited current flow [9].With the CDB technique,the threshold voltage can be reduced,and the PMOS transistor can work in the strong inversion in the voltage range around half of the supply voltage (0.5V).LEUNG AND LUONG:A 1-V 5.2-GHz CMOS SYNTHESIZER FOR WLAN APPLICATIONS1877Fig.6.(a)Schematic of programmable divider.(b)Schematic ofdivide-by-4.Fig.7.Simulation result of divide-by-4.The coarse frequency tuning is employed to minimize the VCO gain by using three binary-weighted channel-selectionbits together with the channel-selectiontransistorsand as shown in Fig.13[10].As a result,the is smallerwhile the total tuning range can still cover the interested band asshown in Fig.14.Such a small VCO gain is good for noise and spurious performance of the synthesizer.The offset adjustment for the discrete frequency step can be calibrated by varying the current source M7.The oscillator is designed to work in the current-limited regime to achieve low phase noise.The sideband noise of the oscillators is mainly limited by the loss in the tank.For higher loss,a larger transconductance is needed to be able to compen-sate and sustain the loop gain for a stable oscillation.Therefore,it is always beneficial to use a tank with the quality factor()as high as possible.One solution to increasethe of the tank to improve the phase noise for a given power or to minimize the power for a given phase noise is to use bond wires in placeof on-chip inductors [11].Sincetheof bond wires can be as high as 40,the VCO performance could be significantly improved.However,such a solution is not attractive due to the problems with controllability,repeatability,and reliability of the bond wires.For high-frequency operation,the required inductance is small in which a small number of turns of the planar inductor can be realized.As such,the metal loss as well as substrate loss can be less due to the fact that the length of metal is shorter and the overlapping area between inductor and substrate is smaller.Moreover,the advanced CMOS process provides thick top metal which can also benefit the quality factor of the on-chip inductor.Therefore,the on-chip inductor is considered for use in the oscillator design.1878IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.39,NO.11,NOVEMBER2004Fig.8.Architecture and schematic of the proposed phase-selectioncircuitry.Fig.9.Timing diagram of the phase-selectioncircuitry.Fig.10.Output of the phase selection circuit during phase switching.(a)Without sensing PMOS.(b)With sensing PMOS.G.Loop Filter,Charge Pumps,and PFDThe loop filter is constructed based on a dual-path loop filter [12]to reduce the on-chip capacitance to about 70pF andthusFig.11.Schematic of the modulus-controlcircuit.Fig.12.Schematic of the phase-control circuit.minimize the chip area.The design parameters used in the loop filter are listed in Table I.The loop filter is designed to main-tain the outputs of the charge pumps at the same potential to minimize the charge-sharing problem to reduce spurious tones at the output of the synthesizer.The complementary outputs of UP/UPB,and DOWN/DOWNB generated by the PFD are de-signed to have some finite rise time and fall time so that the sink and source currents to the loop filter can be well matched.LEUNG AND LUONG:A 1-V 5.2-GHz CMOS SYNTHESIZER FOR WLAN APPLICATIONS1879Fig.13.Schematic of theQVCO.Fig.14.QVCO frequency tuning with both fine and coarse tuning.TABLE IC OMPONENT P ARAMETERS U SED FOR THE SYNTHESIZERIV .E XPERIMENTAL R ESULTSThe proposed synthesizer has been fabricated in a0.18-m six-metal CMOS process.Fig.15shows themicrophotographFig.15.Chip photo of the proposed 5.2-GHz synthesizer for WLAN.of the fabricated chip.The core chip area is 1.03mm .The total power consumption under a 1-V supply is 27.5mW.A.Measurement of the QVCOThe measured tuning range of the QVCO is plotted in Fig.16.Together with the coarse tuning by the three channel-selection bits,the QVCO achieves a total frequency tuning range morethan 200MHz with thegainbeing around 75MHz/V .As expected,for each setting of the digital bits,the tuning range of the QVCO is quite linear over the whole operation region of the dual-path loop filter.The lump-element model,which is used to characterize the inductor,is depicted in Fig.17.At high frequencies,magnetic coupling should be taken into account.Lenz ’s law indicates that eddy current is generated under influence of magnetic flux,which tends to oppose the original field.The resultant induc-tance of the on-chip inductor is therefore reduced while the se-1880IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.39,NO.11,NOVEMBER2004Fig.16.Measured tuning range of theQVCO.Fig.17.Lumped-element model of the inductor including magnetic coupling from substrate.ries resistance is effectively increased.Moreover,these changes are frequency dependent.To take into account this phenomenon to achieve more accurate model and simulation,two extra ele-ments,inductanceandresistance ,are added inthe -equivalent model as illustrated in Fig.17.Fig.18shows the measurement results of the on-chip inductor,from which the in-ductance is measured to be around 1nH and the quality factor is about 7at 5.2GHz.A very good fitting for the inductor is achieved thanks to the use of the complicated model.B.Measurement of the SynthesizerTo overcome process variation,the VCO employs 2-bit switched-capacitor array (SCA)for tuning.The nominal center frequency of the QVCO is shifted from 5.2to 6.0GHz due to inaccurate modeling and over-estimation of the parasitic capacitance.By turning on the SCA,the operating frequency is shifted down to around 5.5GHz,resulting in a coarse tuning range of over 500MHz.To test the performance of the synthesizer,the reference is set at 11MHz for all the closed-loop measurements.With the robustness of the proposed architecture for the programmable divider,the synthesizer works properly even with a supply voltage as low as 0.85V .The output spectrum of the QVCO in the locked state is shown in Fig.19.To verify the functionality of the programmable divider,the division ratio is set to be 498.The outputfrequencyFig.18.Measured results of the on-chip inductance for the WLANsynthesizer.Fig.19.Measured output spectrum of the synthesizer.is measured to be 5.478GHz with a reference clock at 11MHz.The prescaler works properly without any glitch problem.From the output spectrum,the spur performance is better than 80dBc at an 11-MHz frequency offset from the carrier.The phase-noise performance of the frequency synthesizer is shown in Fig.20.The measured phase noise at a 20-MHz offset is 136dBc/Hz.The in-band phase noise is around 65dBc/Hz while the designed in-band phase noise of the syn-thesizer is expected to be 75dBc/Hz.The noise degradation is mainly contributed by the phase noise of the signal generator.With a better reference signal,either from a crystal or from a signal generator followed by a frequency divider,the in-band phase noise could and should be significantly improved.For switching from the first channel to the last channel,the settling time is measured to be about51s as shown in Fig.21.Due to the scope ’s limited resolution,the frequency accuracy for the settling cannot be measured directly,but it can be roughly estimated to be around 100kHz.LEUNG AND LUONG:A 1-V 5.2-GHz CMOS SYNTHESIZER FOR WLAN APPLICATIONS 1881TABLE IIS UMMARY AND C OMPARISON OF THE P ROPOSED S YNTHESIZER ’S PERFORMANCEFig.20.Phase-noise measurement of thesynthesizer.Fig.21.Measured result of settling time of the synthesizer.The measured performance of the proposed synthesizer is summarized in Table II together with that of the most recent state-of-the-art synthesizers for comparison.V .C ONCLUSIONA 1-V 5.2-GHz synthesizer has been demonstrated in a stan-dard0.18-m CMOS technology.Several design techniques have been proposed to achieve robust performance for the prescaler and for the synthesizer even when the supply is as low as 0.85V .At 1V ,the phase noise of the whole synthesizer is measured to be 136dBc/Hz at 20-MHz frequency offset.In addition,the spurious tone is measured to be less than 80dBc at 11-MHz offset.The synthesizer can settle within51s while consuming 27.5mW and occupying an active chip area of 1.03mm .R EFERENCES[1]T.H.Lee,H.Samavati,and H.R.Rategh,“5-GHz CMOS wirelessLANs,”IEEE Trans.Microwave Theory Tech.,vol.50,pp.268–280,Jan.2002.[2]P.Zhang et al.,“A direct conversion CMOS transceiver for IEEE802.11a WLANs,”in IEEE Int.Solid-State Circuits Conf.(ISSCC)Dig.Tech.Papers ,Feb.2003,pp.354–355.[3]G.Dehng,C.Yang,J.Hsu,and S.Liu,“A 900-MHz 1-V CMOSfrequency synthesizer,”IEEE J.Solid-State Circuits ,vol.35,pp.1211–1214,Aug.2000.[4]G.C.T.Leung and H.C.Luong,“1-V 5.2-GHz 27.5-mW fully-inte-grated CMOS WLAN synthesizer,”in Proc.Eur.Solid-State Circuits Conf.(ESSCIRC),Sept.2003,pp.103–106.[5]J.Craninckx,“A 1.75-GHz/3-V dual-modulus divide-by-128/129prescaler in 0.7- m CMOS,”IEEE J.Solid-State Circuits ,vol.31,pp.890–897,July 1996.[6]K.Shu,E.Sanchez-Sinencio,J.Silva-Martinez,and S.Embabi,“A2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier,”IEEE J.Solid-State Circuits ,vol.38,pp.866–874,June 2003.[7]S.Rofougaran,J.Rael,M.Rofougaran,and A.Abidi,“A 900-MHzCMOS LC -oscillator with quadrature outputs,”in IEEE Int.Solid-State Circuits Conf.(ISSCC)Dig.Tech.Papers ,Feb.1996,pp.392–393.1882IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.39,NO.11,NOVEMBER2004[8]T.P.Liu,“A6.5GHz monolithic CMOS voltage-controlled oscillator,”in IEEE Int.Solid-State Circuits Conf.(ISSCC)Dig.Tech.Papers,Feb.1999,pp.404–405.[9]T.Lehmann and M.Cassia,“1-V power supply CMOS cascode ampli-fier,”IEEE J.Solid-State Circuits,vol.36,pp.1082–1086,July2001.[10] A.Kral et al.,“RF-CMOS oscillators with switched tuning,”in Proc.IEEE Custom Integrated Circuits Conf.(CICC),1998,pp.555–558.[11]J.Craninckx and M.Steyaert,“A1.8-GHz CMOS low-phase-noisevoltage-controlled oscillator with prescaler,”IEEE J.Solid-StateCircuits,vol.30,pp.1474–1482,Dec.1995.[12]K.T.Kan,C.T.Leung,and H.C.Luong,“A2-V1.8-GHz fully in-tegrated CMOS dual-loop frequency synthesizer,”IEEE J.Solid-StateCircuits,vol.37,pp.1012–1020,Aug.2002.[13]I.Bouras and A.Yamanaka et al.,“A digitally calibrated5.15–5.825GHz transceiver for802.11a wireless LAN’s in0.18 m CMOS,”inIEEE Int.Solid-State Circuits Conf.(ISSCC)Dig.Tech.Papers,Feb2003,pp.352–353.[14] D.Su et al.,“A5GHz CMOS transceiver for IEEE802.11a wirelessLAN,”IEEE J.Solid-State Circuits,vol.37,pp.1688–1694,Dec.2002.[15] F.Herzel,F.Fischer,and H.Gustat,“An integrated CMOS RF synthe-sizer for802.11a wireless LAN,”IEEE J.Solid-State Circuits,vol.38,pp.1767–1770,Aug.2003.Gerry C.T.Leung received the B.S.and M.S.degrees in electrical and electronics engineeringfrom the Hong Kong University of Science andTechnology(HKUST),Hong Kong,in2001and2003,respectively.He was engaged in the development of RF andhigh-speed clock systems with Innovative SystemCorporation Limited in2003.Since2004,he hasbeen with ON Semiconductor Ltd.,Hong Kong,as an IC Design Engineer.His research interestsare in high-speed high-performance analog and RF integratedcircuits.Howard C.Luong(S’88–M’91–SM’02)receivedthe B.S.,M.S.,and Ph.D.degrees in electricalengineering and computer sciences(EECS)from theUniversity of California at Berkeley in1988,1990,and1994,respectively.Since September1994,he has been with theElectrical and Electronics Engineering faculty at theHong Kong University of Science and Technology,where he is currently an Associate Professor.In2001,he took a one-year sabbatical leave to workwith Maxim Integrated Products,Sunnyvale,CA,on wireless products.His research interests are in high-performance RF,analog, and mixed-signal integrated circuits and systems for wireless communication and portable applications.He has been involved in various professional activities internationally.Prof.Luong served as an Associate Editor for the IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS II(TCAS II)from1999to2002.He received the Fac-ulty Teaching Excellence Appreciation Award from the School of Engineering of Hong Kong University of Science and Technology in1996,1997,and2000.。