BFR92W中文资料

BF257BF258-BF259October 1988HIGH VOLTAGE VIDEO AMPLIFIERSDESCRIPTIONThe BF257,BF258and BF259are silicon planar epitaxial NPN transistors in Jedec TO-39metal case.They are particularly designed for videooutput stages in CTV and MTV sets,class A audio output stages and drivers for horizontal deflection circuits.ABSOLUTE MAXIMUM RATINGSValueSymbol ParameterBF 257BF258BF259Unit V CBO Collector-base Voltage (I E =0)160250300V V CEO Collector-emitter Voltage (I B =0)160250300V V E BO Emitter-base Voltage (I C =0)5V I C Collector Current 100mA I CM Collector Peak Current200mA P t o t Total Power Dissipation at T amb ≤50°C 5W T s t g Storage Temperature –55to 200°C T jJunction Temperature200°C INTERNAL SCHEMATIC DIAGRAMTO-391/5ELECTRICAL CHARACTERISTICS (T amb =25°C unless otherwise specified)Symbol ParameterTest Conditions Min.Typ.Max.Unit I CB OCollector Cutoff Current (I E =0)for BF257for BF258for BF259V CB =100V V CB =200V V CB =250V 505050nA nA nA V (BR)CB OCollector-baseBreakdown Voltage (I E =0)I C =100µAfor BF257for BF258for BF259160250300V V V V (BR)CEO *Collector-emitter Breakdown Voltage (I B =0)I C =10mAfor BF257for BF258for BF259160250300V V V V (BR)EB OEmittter-baseBreakdown Voltage (I C =0)I E =100µA 5V V CE (s at )*Collector-emitter Saturation Voltage I C =30mA I B =6mA 1Vh FE *DC Current Gain I C =30mA V CE =10V 25f T Transition Frequency I C =15mA V CE =10V 90MHz C r eReverse CapacitanceI C =0f =1MHzV CE =30V3pF*Pulsed :pulse duration =300µs,duty cycle =1%.DC Current Gain.THERMAL DATAR t h j-cas e R t h j-ambThermal Resistance Junction-case Thermal Resistance Junction-ambientMax Max30175°C/W °C/WBF257-BF258-BF2592/5BF257-BF258-BF259 Collector Cutoff Current.Collector-base Capacitance.Transition Frequency.Power Rating Chart.Safe Operating Area.3/5DIM.mminch MIN.TYP.MAX.MIN.TYP.MAX.A 12.70.500B 0.490.019D 6.60.260E 8.50.334F 9.40.370G 5.080.200H 1.20.047I 0.90.035L45o (typ.)LGI DAFE BHTO39MECHANICAL DATAP008BBF257-BF258-BF2594/5BF257-BF258-BF259 Information furnished is believed to be accurate and reliable.However,SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use.No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.Specificationsmentioned in this publication are subject to change without notice.This publication supersedes and replaces all information previously supplied.SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics.©1994SGS-THOMSON Microelectronics-All Rights ReservedSGS-THOMSON Microelectronics GROUP OF COMPANIESAustralia-Brazil-France-Germany-Hong Kong-Italy-Japan-Korea-Malaysia-Malta-Morocco-The Netherlands-Singapore-Spain-Sweden-Switzerland-Taiwan-Thailand-United Kingdom-U.S.A5/5。

Preliminary W89C926 PENTIC+PCMCIA ETHERNET NETWORKTWISTED PAIR INTERFACE CONTROLLERPublication Release Date: January 1996GENERAL DESCRIPTIONThe W89C926 PENTIC+ is a CMOS device designed for easy implementation of PCMCIA R2.1compatible CSMA/CD local area networks. The W89C926 combines a W89C902 Serial LAN Coprocessor for Twisted-pair (SLCT) with a PCMCIA Bus Interface (PBI), thus integrating into a single chip all the registers and logic necessary to connect the SLCT to buffer SRAMs, flash memories (or an EEPROM), and the PCMCIA system bus.The PCMCIA Bus Interface (PBI) is designed to provide a switchless setting architecture that allows the card setting to be configured by software. It implements a full set of PCMCIA registers for PCMCIA R2.1 compatibility and a set of configuration registers for switchless card setting. The card can be configured quickly and easily by modifying the contents of the configuration registers. The PENTIC+ can run with shared memory mode and NE2000TM I/O mode drivers on a 16-bit bus interface. No extra effort is needed to ensure software compatibility.The PENTIC+ provides a flexible flash memory (up to 128 KB)/EEPROM (up to 512 bytes)architecture for PCMCIA nonvolatile storage and an ID/Configuration auto-load architecture for power-on initialization. Vendors can store the Ethernet ® ID, configuration, and CIS in the flash memory or EEPROM. The PENTIC+ will auto-load necessary information when power is switched on.FEATURES• Runs with NE2000TMor shared memory drivers• Supports up to 128 KB flash memory (8K/112K for attribute/common memory) or 512 bytesEEPROM (for attribute memory only) for nonvolatile memory• Uses one 16 KB SRAM or one 32 KB SRAM (if EEPROM is used) for 16 KB Ethernet ring buffer • Auto-load algorithm provided for power-on initialization • Supports necessary PCMCIA registers• Configuration registers allow switchless card setting • UTP/BNC auto media-switching function provided •Drives necessary LEDs for network status display• Single 5V power supply with low power consumption • 100-pin thin package (TQFP) fits into PCMCIA Type II profileEthernet ® is a registered trademark of the Xerox Corporation.NE2000TM is a trademark of Novell, Inc.PIN CONFIGURATIONPublication Release Date: January 1996PIN DESCRIPTIONPublication Release Date: January 1996Pin Description, continuedPin Description, continuedPublication Release Date: January 1996Pin Description, continuedNote: I: input pin; O: output pin; IO: bidirectional input/output pin; TTL: TTL level buffer stage; ODH: open drain buffer stage;MOS: MOS level buffer stage; 3SH: Tri-state buffer stage; DIF: differential buffer stage, XTAL: crystal.BLOCK DIAGRAMPublication Release Date: January 1996FUNCTIONAL DESCRIPTIONADDRESS MAPPINGEEPROM MAPPINGEEPROM ADDRESSHIGH BYTELOW BYTE 00H -Word Count01H CFB CFA 02H ID-1ID-003H ID-3ID-204H ID-5ID-405H Check SumBoard Type (05H)06H-08H --09H 57H 57H 0AH-nH CIS CIS (n+1) H-FFH--Notes:1. The fifth (05H) word is used for shared memory mode and the ninth (09H) word is used for NE2000 mode.2. Word Count = nH (n should be set as a non zero value, a zero value will cause an unpredicted error).ATTRIBUTE MEMORY MAPPINGTYPE CONTENTS ATTRIBUTE MEMORYOFFSET (HA0-16)00000HFlash CIS 00F9EH00FA0H Flash ID-000FA2H Flash ID-100FA4H Flash ID-200FA6H Flash ID-300FA8H Flash ID-400FAAH Flash ID-500FACH Flash Board Type (05H)00FAEH Flash Check Sum00FB0H Flash-00FB2H Flash-00FB4H Flash-00FB6H Flash-00FB8H Flash-00FBAH Flash-00FBCH Flash57H00FBEH Flash57H00FC0H Flash CFA00FC2H Flash CFB---00FD0H Register COR00FD2H Register CCSR00FD4H Register-00FD6H Register SCR-Register Reserved (see note) 00FF0H Register CFA00FF2H Register CFB00FF4H Register SRRegister Reserved 00FF6H00FFEHFlash CIS 01000H03FFEHPublication Release Date: January 1996EECS/FCS Pull Low (EEPROM)ATTRIBUTE MEMORY OFFSET (HA0-16)TYPE CONTENTS00000H 003D6HMemory (SRAM)CIS-Unsued -00FD0H Register COR 00FD2H Register CCSR 00FD4H Register -00FD6HRegister SCR-Register Reserved (see note)00FF0H Register CFA 00FF2H Register CFB 00FF4H Register SR 00FF6H 00FFEH Register Reserved01000H 03FFEHUnused-Notes:1.The reserved register space in the attribute space is left for future extension. Users should not place their application in this area.2. When EECS/FCS is pulled high, address 00FA0H to 00FFEH is used for Ethernet ID, configuration, and registers. Vendors should not put CIS in this region.3. When EECS/FCS is pulled low, Address 00000H to 003D6H is read-only. The PENTIC+ will ignore write accesses to this area.NE2000 Mode MappingI/O MappingSYSTEM I/O OFFSET (HA0-4)NAME OPERATION 00H 0FH LCE Core Registers Register Read/Write 10H 17H Remote DMA PortRemote DMA Read/Write 18H 1FHReset PortSoftware ResetNotes:1. The PENTIC+ decodes only HA0-4 for I/O access, so the IOBase address is left for the host adapter and the socket service to determine.2. To issue a S/W reset, simply issue an I/O read to the Reset Port. The PENTIC+ will assert a 600 nS internal reset pulse to reset the core state machine. If the host tries to access the PENTIC+, WAIT will be asserted low until the reset is completed.Buffer Memory MappingNIC COREMEMORY MAPNE2000 COMPATIBLE0000H001FHID Registers0020H00FFHAliased0100H3FFFHID Registers4000H 7FFFH Buffer SRAM (16K × 8)8000H BFFFHAliased ID RegistersC000HFFFFHAliased Buffer SRAMNonvolatile Memory MappingF/EE = 1 (flash memory used)SYSTEMOFFSET (HA0-16)MEMORY TYPE NAME00000H 03FFFH Attribute/FlashCIS/ID/PCMCIA Register(8K × 8)04000H 1FFFFH Common/Flash(112K × 8)F/EE = 0 (EEPROM used)SYSTEMOFFSET (HA0-16)MEMORY TYPE NAME00000H 003D6H Attribute/(Note)CIS(492 × 8)Notes:1. This attribute memory is an image from EEPROM. It is actually resident in upper half of the SRAM after power-on auto-loading.2. Refer to "Attribute Memory Mapping" for detailed locations.3. The PENTIC+ decodes HA0-16 for memory access. The (common or attribute) MEMBase addresses are left for the host adapter and the socket service to determine.Publication Release Date: January 1996Shared Memory Mode MappingI/O MappingSYSTEM I/O OFFSET (HA0-4)NAME OPERATION 00H MMA I/O Write 01H Word/-Byte I/O Read 05H MMB I/O Write 08H 0FH ID Registers I/O Read 10H 1FHLCE Core RegistersRegister Read/WriteNotes:1. The PENTIC+ decodes only HA0-4 for I/O access, so the IOBase address is left for the host adapter and the socket service to determine.2. MMA and MMB are used for shared memory mapping control. Since the PENTIC+ decodes only MSA = 0000H to 03FFFH for shared memory that is, the shared memory base address for the PENTIC+ is 00000H, MMB and bit 0 to 5 of MMA should be set to 0.3. Since the PENTIC+ supports 16-bit mode only, the Word/-Byte will be read as 01H.Buffer Memory MappingSYSTEMOFFSET (HA0-16)MEMORY TYPE SHARED MEMORY MODE 00000H 03FFFH Common/SRAM Buffer SRAM (16K × 8)04000H 07FFFHCommon/(Note)UnusedNotes:1. This region is occupied by flash memory.2. The PENTIC+ decodes HA0-16 for memory access. The (common or attribute) MEMBase addresses are left for the host adapter and the socket service to determine.Nonvolatile Memory Mapping F/EE = 1 (flash memory used)SYSTEM OFFSET (HA0-16)MEMORY TYPENAME00000H 03FFFH Attribute/Flash CIS/ID/PCMCIA Register(8K × 8)04000H 1FFFFHCommon/Flash(112K × 8)F/EE = 0 (EEPROM used)SYSTEM OFFSET (HA0-16)MEMORY TYPENAME 00000H 003D6HAttribute/(Note)CIS (492x 8)Notes:1. This attribute memory is an image from EEPROM. It is physically resident in upper half of the SRAM after power-on auto-loading.2. Refer to "Attribute Memory Mapping" for detailed locations.3. The PENTIC+ decodes HA0-16 for memory access. The (common or attribute) MEMBase addresses are left for the host adapter and the socket service to determine.REGISTER FILEThe W89C926 PENTIC+ has four register sets: the core register set, the PCMCIA configuration register set, the LAN configuration register set, and the special control register set. The core register set is the same as that in the W89C90 and will not be discussed here. The other three register sets are described below.PCMCIA Configuration Register SetThe PENTIC+ provides three PCMCIA configuration registers needed to ensure compatibility with various operating systems.COR (Configuration Option Register)Access Address: AMBase + 00FD0H Access Type: Attribute Memory Read/Write BIT SYMBOL DESCRIPTION0-5IDX0-5Configuration IndexThese six bits are used to indicate entry of the card configuration table located in the CIS (Card Information Structure; refer to PCMCIA R2.1).These bits are 0 at power-on.6-Reserved, must be 1 (level mode interrupt) when read.7SRESETS/W ResetA software reset is issued when a 1 is written to this bit. This is the same as a H/W reset except that this bit and the necessary information (CFA,CFB, CIS, and Ethernet ID) are not cleared, and the auto-load procedure is not performed. Returning a 0 to this bit will leave the PENTIC+ in a post-reset state the same as that following a hardware reset. The value of this bit at power-on is 0.Publication Release Date: January 1996CCSR (Card Configuration and Status Register)Access Address: AMBase + 00FD2H Access Type: Attribute Memory Read/Write BIT SYMBOLDESCRIPTION0-Reserved, must be 0.1IntrInterrupt StatusThis bit indicates the internal status of an interrupt request. It remains high until the condition that caused the interrupt request has been serviced.This bit is 0 at power-on.2-7-Reserved, must be 0s.SCR (Socket and Copy Register)The SCR is used to enable the PENTIC+ to distinguish between similar cards installed in the same system.Access Address: AMBase + 00FD6H Access Type: Attribute Memory Read/Write BIT SYMBOL DESCRIPTION0-3SocNumSocket NumberSet these bits to indicate to the PENTIC+ that it is located in the n'thsocket. The first socket is numbered 0. This permits any cards designed to do so to share a common set of IO ports while remaining uniquely identifiable. These bits are 0 at power-on.4-6CopNumCopy NumberSet these bits to indicate to the PENTIC+ that it is the n'th copy of another card installed in the system that is configured identically. The first identical card should be assigned a value of 0 as its copy number. This permits any cards designed to do so to share a common set of I/O ports whileremaining uniquely identifiable and consecutively ordered. These bits are 0s at power-on.7-Reserved, must be 0.LAN Configuration Register SetThese two registers are used for LAN configuration control.CFA (Configuration Register A)This register is used to select the PENTIC+'s operating mode and LED control.Access Address: AMBase + 00FF0H Access Type: Attribute Memory Read/WriteCFB (Configuration Register B)Access Address: AMBase + 00FF2HPublication Release Date: January 1996Special Control Register SetThese registers are used for special checking or EEPROM access control.Signature Register (SR)A signature register is used for identification so that the software driver can easily distinguish between different chips. The content can be read out in toggled order as follows:Access Address: AMBase + 00FF4H Access Type: Attribute Memory ReadMSB LSB(2N)th time:10001000where N = 1, 2, ... (after H/W reset)(2N-1)th time:00000000EEPROM Access Register (EEAR)This register is located on page 3 and is used for EEPROM read/write access control. It is inhibited when EECS/FCS is pulled high.Access Address: IOBase + 02H Access Type: I/O Read/WriteEEPROM Address/Data Register (ADR)This register is located on page 3 and is used for EEPROM address or data transfer during EEPROM access.Access Address: IOBase + 04HAccess Type: I/O Read/WritePOWER-ON INITIALIZATION AND AUTO-LOADING PROCESSWhen powered on, the system should reset the card first, as required by the PCMCIA specifications. The reset signal will trigger a number of internal operations: First, the PENTIC+ monitors the EECS/FCS pin to determined where the configurations are stored. If this pin is pulled high, the configurations are stored in the flash memory; if it is pulled low, they are stored in an EEPROM. Then, within 10ms after the reset pulse is negated, the PENTIC+ will automatically load the configurations, ID, and CIS data into the LAN configuration registers and the upper half of SRAM (if an EEPROM is used). During this auto-load procedure the PENTIC+ will assert IREQ low for Rdy/Bsy signaling, since the socket is configured at the memory-only interface during initialization. Note that this auto-load operation occurs only after a hardware reset pulse. A software reset (including setting COR.SRESET = 1) will not invoke this operation.EECS/FCS Pulled HighIf EECS/FCS is pulled high, this indicates that the configurations are stored in a flash memory. Accordingly, after a power-on reset the PENTIC+ will automatically load the LAN configuration registers from flash memory. The Ethernet IDs stored in the flash memory will be mapped into ID registers automatically when they are read.Publication Release Date: January 1996EECS/FCS Pulled LowIf EECS/FCS is pulled low, this indicates that the configurations, Ethernet ID, and CIS are stored inan EEPROM. In this case, after a power-on reset the PENTIC+ will load the configurations into the LAN configuration registers and the Ethernet IDs and CIS into the higher half of SRAM memory (with auto-mapping to ID registers and attribute memory space, respectively). Since the EEPROM used is a 93C66, a serial EEPROM storage device, the access time is quite long and the system has to wait for the loading sequence (refer to PCMCIA R2.1). Loading a word of EEPROM typically takes 34 µS.The exact time for EEPROM loading depends on the length of CIS but must not exceed 10 mS.EEPROM Contents Load BackWhen an EEPROM is used to store CIS, the PENTIC+ allows the contents of the EEPROM to bemodified by means of the following sequence:write (EEAR, EOS = 1 EW/ER = 1)write (ADR, address);write (ADR, word_data);wait ( );repeat (read(EEAR, EOS); ) until (EOS = 0);/* The entire sequence should be consecutive or the process will be aborted. */Publication Release Date: January 1996The ADR register located at page3 04H of the core controller is used as a temporary register for EEPROM read/write. When the EEPROM load-back sequence specified above is performed, the content of the specified address will be overwritten by the new data. Note that since the EEPROM is word-aligned, each time the sequence is performed one word of data is modified. The address range available is from 00H to ffH. To make sure that the EEPROM is written correctly, the programmer can use the following read-check process to read a word from a specified address in the EEPROM.write (EEAR, EOS = 1 EW/ER = 0);write (ADR, address);wait ( );repeat (read(EEAR, EOS); ) until (EOS = 0);read(ADR);/* read word data *//* The entire sequence should be consecutive or the process will be aborted. */Note that data will be kept in the ADR until they are updated. That is, the data can be read out any time afterwards unless new data have been written.SRAM Physical MapWhen an EEPROM is used for attribute memory storage, the 32K byte SRAM has two roles in the PENTIC+ design: the first 16K bytes of SRAM serve as an Ethernet buffer ring, while the remainder is used for temporary storage of Ethernet IDs and CIS storage (if EECS/FCS is pulled low). The detailed physical mapping of the SRAM memory is shown in the table below. When a flash memory is used, only a 16K byte SRAM is needed to serve as the Ethernet ring buffer.Note that if EECS/FCS is pulled low, the CIS is stored in the SRAM starting at address 4010H. The length of the CIS depends on the word count specified in the first byte of EEPROM. During a power-on reset, the PENTIC+ will load the exact word count specified in the EEPROM rather than read in all bytes in the EEPROM.The PENTIC+ will automatically translate the address from the host if the host tries to read CIS. It will translate the attribute memory address by assuming that the first CIS byte is stored at 00H of attribute memory, the second CIS byte is stored at 02H, and so forth. Users should assign CIS accordingly, or else the CIS may be lost.Also note that for auto-load information write protection, the PENTIC+ will ignore any write operation above 4000H of SRAM. If it is necessary to change the settings, users should do so by writing the flash memory or EEPROM.Minimal System DesignA low-cost, dedicated LAN card can be designed using the PENTIC+ chip, a 32K x 8 SRAM, a serial EEPROM (93C66/93CS66), and a pig tail for the network interface MAU, along with certain other peripheral components. The following is a sample CIS table that can be used with this minimal system design:01 03 dc 03 ff17 03 5b 09 ff1a 05 01 01 e0 1f 0f1b 13 c1 c1 7d 19 55 15 26 00 33 43 16 45 70 ff ff 48 40 00 0014 00f0 09 'WinICard' ff21 02 06 0320 04 u00 u01 u02 u0315 14 04 01 u04 u05 u06 u07 u08 u09 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 00 ffff ffFLASH MEMORY ACCESSThe flash access and the buffer SRAM share the same memory support bus. The address pins of the flash memory are directly connected to MSA bus and data are accessed through the MSD bus. EECS/FCS is active low if it is pulled high and the attribute memory is accessed in the range 00000H to 03FFFH or the common memory is accessed in the range 04000H to 1FFFFH. Note that CFB.FWE should be set to 1 before a flash write command is issued.I/O MODE OPERATIONThe I/O mode provides two DMA channels for system access. The remote DMA moves data between system memory space and local memory space. The local DMA moves data between the FIFO of the SLCT and local memory space. However, since the SLCT can handle local DMA operations without system intervention (refer to the data sheet for the SLCT), the system has to perform only re-mote DMA reads/writes.In a transmit operation, the data should first be moved from the system to local buffer memory. This is simply an "OUT" command on the PC. Then the system orders the SLCT to start transmission, and the local DMA starts to move data from buffer memory to the transmit FIFO for transmission.In a receive operation, the local DMA moves received data from the receive FIFO to the buffer and asserts IREQ to the system when the buffer ring needs to be serviced. The system must move dataPublication Release Date: January 1996out before the buffer ring overflows. This is done through a remote DMA read operation, which is simply a "IN" command on the PC.SHARED MEMORY MODE OPERATIONIn this mode, the local memory is mapped as part of the system memory. When it requires data transmission, the host fills the transmit buffer SRAM by a memory move operation and then issues a transmit command to the PENTIC+. When it receives data, the PENTIC+ will generate an interrupt to the host by asserting IREQ when one or more packets have been received. The PENTIC+ will then place the packets into the shared memory. The host should check the shared memory and remove the data before the buffer ring overflows.Bus arbitration is performed between the host and LCE core for shared memory usage. When memory accesses are issued, the arbiter will grant the bus master an acknowledge signal, which is a BACK to the LCE or a WAIT signal to the host. There is no predefined priority in the PENTIC+; bus arbitration is performed on a first-come, first-served basis.To implement the shared memory mode, the PENTIC+ uses memory mapping register A (MMA) and memory mapping register B (MMB) for memory mapping control. Since the PENTIC+ will operate in 16-bit shared memory operation at shared memory base address 00000H only, 0s should be written to MMB and bit 0 to 5 of MMA. The contents of the MMA are described below. MMA (Memory Mapping Register A)MMA is used for memory enable and software reset. It is located in I/O space, 00H, and can be ac-cessed only in shared memory mode. Access Address: IOBASE + 00H Access Type: write-onlyBIT SYMBOLDESCRIPTION0-5-Reserved. Should be set to 0.6MEN If this bit is high, the buffer memory may be accessed by the system; if it is low, the buffer memory access is disabled. This bit is 0 at power-on.7SRESETA shared memory mode software reset is issued when a 1 is written to this bit. Writing a 0 to this bit will clear the software reset. This bit is 0 at power-on.AUTO MEDIA-SWITCHING FUNCTIONThe PENTIC+ also provides a user-friendly auto media-switching function. If the PENTIC+ is configured at the TPI, link checking is enabled, and the UTP link is broken, the PENTIC+ will detect the link status and switch to the BNC port immediately. After the UTP link is repaired, the PENTIC+will detect the good link and switch back to the TPI again.If, however, the PENTIC+ is not configured at the TPI or link checking is disabled, the auto media-switching function will be disabled.BUS ARBITRATION AND STATE DIAGRAMThe PENTIC+ handles bus arbitration automatically. It can operate in four modes: idle state, slave read/write mode, DMA mode, and shared memory mode. The PENTIC+ controls the on-board devices by decoding these modes.At power-on, the PENTIC+ is in idle mode. If a register read/write command is issued, the PENTIC+enters the slave read/write mode. If a local DMA or remote DMA (I/O mode only) is initiated by the PENTIC+ core coprocessor, the PENTIC+ enters DMA mode. A memory command will place the PENTIC+ in memory mode. At any given time, the PENTIC+ can be in only one state. The PENTIC+handles state changes automatically. However, two events, such as a DMA command and a memory command, may be requested at the same time; in this case, the PENTIC+ allocates the bus on a first-come, first-served basis. No predefined priority is set within the PENTIC+.In cases where the system has no authority on the requested bus, the PENTIC+ will drive the WAIT pin low so that the system can insert wait states. After the PENTIC+ has released the bus authority,WAIT is deasserted to instruct the system to stop inserting wait states.SLCT CORE FUNCTIONThe SLCT core coprocessor has five major logic blocks that control Ethernet operations: the register files, transmit logic, receive logic, FIFO logic, and DMA logic. The relationship between these blocks is depicted in the following block diagram.Publication Release Date: January 1996Core Register FilesThe register files of the SLCT can be accessed by means of IO commands. The PENTIC+ should be in slave mode when the system accesses the register files. The command register (CR) determines the page number of the register file, while the system address HA<0:4> selects one register address from 01H to 0FH (I/O mode) or from 10H to 1FH (shared memory mode). The PCMCIA IORD and IOWR are the read/write commands used to activate the I/O operations. Refer to the W89C90 data sheet for more detailed information on the registers. DMA Interface LogicIn I/O mapping mode, the SLCT provides two types of DMA operations, local DMA and remote DMA.In shared memory mode, only local DMA is available.Local DMAThe local DMA transfers data from/to the on-board buffers. To perform data reception or transmission from/to remote nodes in the network, data must be moved from/to the FIFO. To enhance the effi-ciency of the transmission, the local DMA transfers data in batches: data are first collected and then moved in a batch. Up to 12 bytes of data can be moved in each transfer. This scheme reduces time wasted in requesting the bus.A local DMA begins by requesting the local bus. If the local bus is available to the SLCT core, the bus arbiter inside the PENTIC+ responds at once by asserting the bus acknowledge (BACK, refer to LCE); if, on the other hand, the bus is currently authorized to another device, the arbiter will not assert the bus acknowledge and the SLCT must wait. Note that this sequence will not affect the host system or system bus signals. After each batch of data is transferred, the SLCT checks the FIFO threshold levels to determine if another batch transfer should be requested. Remote DMAA remote DMA can be performed only in I/O mode. The remote DMA moves data between the host and the local buffers. Unlike a local DMA, the remote DMA is word-wide: the remote DMA operation transfers one word each time.Since a remote DMA is simply a system I/O operation, it sometimes affects the system bus. If the remote DMA is interleaved with other devices, WAIT is asserted to force the system to insert wait states. The PENTIC+ will automatically handle any arbitration necessary.FIFO LogicThe SLCT has a 16-byte FIFO, which acts as an internal buffer to compensate for differences in the transmission/reception speed of different DMAs. The FIFO has FIFO threshold pointers to determine the level at which it should initiate a local DMA. The threshold levels, Which are different for reception and transmission, are defined in the DCR register.The FIFO logic also provides FIFO overrun and underrun signals for network management purposes. If received packets are flooding into the FIFO but the SLCT still does not have bus authority, the FIFO may be overrun. On the other hand, if a transmission begins before data are fed into the FIFO, it may be underrun. Either case results in a network error. FIFO overruns and underruns can be prevented by changing the values of the FIFO thresholds.Normally, the data in the FIFO cannot be read; reading FIFO data during normal operation may cause WAIT to be asserted and the system to hang. In loopback mode, however, the SLCT allows FIFO data to be read by byte in order to check the correctness of the loopback operation.Receive LogicThe receive logic is responsible for receiving the serial network data and packing the data in byte/word sequence. The receive logic thus has serial-to-parallel logic in addition to network detection capability.The PENTIC+ accepts both physical addresses and group addresses (multicast and broadcast ad-dresses). The SLCT extracts the address field from the serial input data. It then determines if the address is acceptable according to the configurations defined in the Receive Configuration Register (RCR). If the address is not acceptable, the packet reception is aborted. If the address is acceptable, the data packet is sent to the serial-to-parallel logic before being fed into the FIFO.After receiving a data packet, the SLCT automatically adds four bytes of data receive status, next packet pointer, and two bytes of receive byte count into the FIFO for network management purposes. The receive status contains the status of the incoming packet, so that the system can determine if the packet is desired. The next packet pointer points to the starting address of the next packet in the local receive ring. The receive byte count is the length of the packet received by the SLCT. Note that the receive byte count may be different from the "length" field specified in the Ethernet packet format. These four bytes of data will be transferred to the local buffer with the last batch of the local DMA. However, these four bytes are stored at the first four addresses of the packet.Transmit LogicThe SLCT must be filled before transmission may begin. That is, the local DMA read must begin before the SLCT starts transmission. The SLCT first transmits 62 bits of preamble, then two bits of SFD, and then the data packet. The parallel-to-serial logic serializes the data from the FIFO into a data packet. After the data packet, the SLCT optionally adds four bytes of cyclic redundancy code (CRC) to the tail of the packet.A protocol PLA determines the network operations of the PENTIC+. Collision detection, random back-off, and auto retransmit are implemented in the transmit logic. The protocol PLA ensures that the PENTIC+ follows the IEEE 802.3 protocol.SNA ModuleThe PENTIC+ also contains a serial network adaptor (SNA), which adapts the non-return-to-zero (NRZ) used in the core processor and host system to Manchester coded network symbols. Two kinds of interfacing signals are provided in the PENTIC+: an AUI interface for Ethernet and a coaxial。

Products Solutions Services EA01085D/06/EN/02.1571303752Installation InstructionsInstalling sensor partsProsonic Flow 92F, Prowirl 72, 73, Prowirl 200Instruction is valid for the following spare part sets:Order number Original Spare part set OrdernumberOriginal Spare part set50093513Kit gasket Prowirl 77, 72, 73, 2001 × gasket 25.0/20 × 0.76 mm, (1.0/0.79 × 0.03 inch) Kalrez 50103480Kit DSC-sensor Prowirl 72 standard 3.1Basic version, 316L, –40 to +260 °C, (–40 to +500 °F)1 × Sensor Prowirl 72 complete 3.1,4 × screw M5 × 121 × gasket 25.0/20 × 1.0 mm (1.0/0.79 × 0.04 inch)Sigraflex HD1 × gasket 25.0/20 × 1.0 mm (1.0/0.79 × 0.04 inch)Viton1 × gasket 25.0/20 × 0.8 mm (1.0/0.79 × 0.03 inch)Gylon50093514Kit 10 gaskets Prowirl 77, 72, 73, 20010 × gasket 25.0/20 × 1.0 mm (1.0/0.79 × 0.04 inch) Viton 50103481Kit DSC-sensor Prowirl 72 high-/low temperature 3.1High/low temp., 316L, –200 to +400 °C(–330 to +750 °F)1 × sensor Prowirl 72 complete HT 3.14 × screw M5 × 121 × gasket 25.0/20 × 1.0 mm (1.0/0.79 × 0.04 inch)Sigraflex HD1 × gasket 25.0/20 × 1.0 mm (1.0/0.79 × 0.04 inch)Viton1 × gasket 25.0/20 × 0.8 mm (1.0/0.79 × 0.03 inch)Gylon50093627Kit 10 gasket Prowirl 70, 72, 20010 × gasket flat 17.0/9.5 × 1.0 mm (0.67/0.37 × 0.04 inch)Grafoil50103482Kit DSC-sensor Prowirl 72, 77 Alloy C-22, 3.1,–200 to +400 °C (–330 to +750 °F)1 × sensor Prowirl 72 complete HT C-22 3.1,4 × screw M5 × 121 × gasket 25.0/20 × 1.0 mm (1.0/0.79 × 0.04 inch)Sigraflex Z1 × gasket 25.0/20 × 1.0 mm (1.0/0.79 × 0.04 inch)Viton1 × gasket 25.0/20 × 0.8 mm (1.0/0.79 × 0.03 inch)Gylon50095114Kit 10 gasket Prowirl 77, 72, 73, 20010 × gasket 25.0/20 × 0.8 mm (1.0/0.79 × 0.03 inch) Gylon50103474Kit preamplifier Prowirl 72, 731 × preamplifier V05 Prowirl50103483Kit DSC-sensor Prowirl 72 high pressure 3.1Inconel 718,–200 to +400 ¢XC (–330 to +750 °F)1 × sensor Prowirl 72 complete high pressure 3.14 × screw M8 × 201 × gasket 25.0/20 × 1.0 mm (1.0/0.79 × 0.04 inch) Sigraflex HD1 × gasket 25.0/20 × 0.1 mm (1,0/0,79 × 0.04 inch) Viton1 × gasket 25.0/20 × 0.8 mm (1,0/0,79 × 0.04 inch) Gylon50103479Kit DSC-sensor Prowirl 72 standardBasic version, 316L, –40 to +260 °C, (–40 to +500 °F)1 × sensor Prowirl 72 complete, 4 × screw M5 × 121 × gasket 25.0/20 × 1.0 mm (1.0/0.79 × 0.04 inch) Sigraflex HD1 × gasket 25.0/20 × 1.0 mm (1.0/0.79 × 0.04 inch) Viton1 × gaslet 25.0/20 × 0.8 mm (1.0/0.79 × 0.03 inch) Gylon50103484Kit connection board Prowirl 72, 73 FS electronic Ex1 × connection board L48 FS transmitter VDM Ex‣The order number of the spare part set (on the packaging label) can differ from the product number (on the label directly on the spare part)!‣The order number of the relevant spare part set can be established by entering the material number of the spare part in the spare parts finder.‣We recommend that the Installation Instructions be kept with the packaging at all times.Pressure test after sensor removalAfter sensor removal a pressure test principally is recommended.The pressure test is required for devices which had been delivered with Option PED or a pressure test certificate.Order numberOriginal Spare part kitOrder numberOriginal Spare part kit50103485Kit connection board Prowirl 72, 73 FS sensor Ex 1 × connection board L47 FS sensor VDM Ex71026988Kit gaskets housing 92F FS3 × O-Ring 113.90 × 3.53 (4.48 × 0.14 inch)1 × O-Ring 73.00 × 3.00 (2.87× 0.12 inch)1 × O-Ring 47.00 × 5.34 (1.85× 0.21 inch)1 × O-Ring 52.39 × 3.53 (2.06× 0.14 inch)50103892Kit gaskets housing Prowirl 72, 73 compact1 × O-Ring 113.90 × 3.53 (4.48 × 0.14 inch) NBR1 × O-Ring 49.21 × 3.53 (1.93 × 0.14 inch) NBR 1 × O-Ring 73.00 × 3.00 (2.87 × 0.12 inch) NBR 71026990Kit gaskets housing 92F compact1 × O-Ring 113.90 × 3.53 (4.48 × 0.14 inch)1 × O-Ring 73.00 × 3.00 (2.87 × 0.12 inch)1 × O-Ring 47.00 × 5.34 (1.85 × 0.21 inch)1 × O-Ring 52.39 × 3.53 (2.06 × 0.14 inch)50103893Kit gaskets housing Prowirl 72, 73 FS2 × O-Ring 113.90 × 3.53 (4.48 × 0.14 inch)2 × O-Ring 49.21 × 3.53 (1.93 × 0.14 inch)1 × O-Ring 47.00 × 5.34 (1.85 × 0.21 inch)2 × O-Ring 73.00 × 3.00 (2.87 × 0.12 inch)71026991Kit connection board 92F FS electronic Ex1 × connection board L55 FS1 × cable tree complete 92F Prosonic F FS50106028Kit DSC-sensor PW73 high/low temperature316L + Temp. Sensor, –200 to +400 °C (–330 to +750 °F)1 × sensor Prowirl 73 complete thermal sensor4 × screw M5 × 121 × gasket 25.0/20 × 1.0 mm (1.0/0.79 × 0.04 inch) Sigraflex HD 1 × gasket 25.0/20 × 1.0 mm (1.0/0.79 × 0.04 inch) Viton 1 × gaslet 25.0/20 × 0.8 mm (1.0/0.79 × 0.03 inch) Gylon 71026992Kit connection board 92F FS sensor Ex1 × connection board L55 FS50106029Kit DSC-sensor PW73 high/low temperature 3.1316L + Temp. Sensor, –200 to +400 °C (–330 to +750 °F)1 × sensor Prowirl 73 complete thermal sensor 3.1 B4 × screw M5 × 121 × gasket 25.0/20 × 1.0 mm (1.0/0.79 × 0.04 inch) Sigraflex HD 1 × gasket 25.0/20 × 1.0 mm (1.0/0.79 × 0.04 inch) Viton 1 × gaslet 25.0/20 × 0.8 mm (1.0/0.79 × 0.03 inch) Gylon 71034586Kit gaskets 77, 72, 73, 200 HD5 × Dichtungsscheibe 25.0/20 × 1.0 mm(1.0/0.79 × 0.04 inch) Sigraflex HD71034588Kit 20 gaskets Prowirl 77, 72, 73, 20020 × gasket 25/20 × 1 mm (1.0/0.79 × 0.04 inch)Sigraflex HD 71023367Kit DSC-sensor Prowirl 72 max pressure 3.1Titanium,–50 to +400 °C (–60 to +750 °F)1 × sensor Prowirl W72 complete max pressure 3.1 Exd4 × screw M10 × 351 × gasket 17.5/10 × 0.8 mm (0.68/0.4 × 0.04 inch) Grafoil71117952Kit DSC-sensor PW 73 high pressure 3.11 × sensor PW73 complete HP, 4 × screw M8 × 20, 3.11 × gasket 25.0/20 × 1.0 mm (1.0/0.79 × 0.04 inch)Sigraflex HD1 × gasket 25.0/20 × 1.0 mm (1.0/0.79 × 0.04 inch) Viton 1 × gasket 25.0/20 × 0.8 mm (1.0/0.79 × 0.03 inch) GylonAppropriate UseThe spare parts set and Installation Instructions are used to replace a faulty unit with a functioning unit of the same type.Use genuine parts from Endress+Hauser only.Only original spare parts supplied by Endress+Hauser shall be used with the measuring device.The verification has to be done via W@M Device Viewer, this procedure is explained below.For some devices there is an overview of the correct spare parts inside the connection compartment cover.If the spare part is listed there, the verification is no longer required.=Authorized personnelNOTICEThe person who carries out the repair is responsible for safety during the work, the quality of work completed and safety of the device after repair.Approval of the measuring device Group of persons authorized to carry out repairswithout approval 2, 3with approval (for Ex. IECEx, ATEX, FM, CSA, TIIS, NEPSI) 2, 31 = Trained customer technician2 = Service technician authorized by Endress+Hauser3 = Endress+Hauser (send measuring device back to manufacturer)Safety instructions• Check whether the spare part matches the identification label on the measuring device, as explained on the previous page.• The spare parts set and Installation Instructions are used to replace a faulty unit with a functioning unit of the same type. Use genuine parts from Endress+Hauser only.• In the case of Ex-certified measuring devices: Only open ina de-energized state (once a delay of 10 minutes has elapsed after switching off the power supply) or in environments which do not have a potentially explosive atmosphere.• The measuring device is energized. Danger: Risk of electric shock! Open the measuring device in a de-energized state only. • Before removing the device: set the process in a safe condition and purge the pipe of dangerous materials.• Hot surfaces! Risk of injury!Before commencing work, allow the system and measuring device to cool down to a touchable temperature.• In the case of measuring devices in custody transfer, the custody transfer status no longer applies once the lead seal has been removed.• Comply with national regulations governing mounting, electri-cal installation, commissioning, maintenance and repair proce-dures.• Requirements with regard to specialized technical staff for the mounting, electrical installation, commissioning, maintenance and repair of the measuring devices:trained in instrument safetyfamiliar with the individual operation conditions of the devices for Ex-certified measuring devices: also trained in explosion protection• Follow the Operating Instructions for the device.• Risk of damaging electronic components!Ensure you have a working environment protected from electro-static discharge.• After removing the electronics cover, there is a risk of electric shock as shock protection is removed! Switch off the measuring device before removing internal covers.• Modifications to the measuring device are not permitted.• In the case of measuring devices in safety-related applications in accordance with IEC 61508 or IEC 61511:After repair recommission in accordance with Operating Instructions. Document the repair procedure.• Only open housing for a brief period. Avoid the penetration of foreign bodies, moisture or contaminants.• Caution! When replacing amplifier boards, I/O boards or submo-dules, ensure compatibility with existing software. The process for reading out the software revision number is described in the Operating Instructions (device functions).If the software of the board is not compatible, it should be upda-ted using an operating software package (e.g. Field Care). In the event of functional changes, notify the plant owner/operator.• Replace defective seal/gaskets with genuine parts from Endress+Hauser only.• If threads are damaged or defective, the measuring device must be repaired.• Threads (e.g. of the cover for the electronics and connection compartments) must be lubricated. Use an acid-free, non-harde-ning grease if an abrasion resistant dry lubricant is non-existent.• If spacing is reduced or the dielectric strength of the measuring device cannot be guaranteed during repair work, perform a test on completion of the work (e.g. high-voltage test in accordance with the manufacturer's instructions).• Service connector:– do not connect in potentially explosive atmospheres.– only connect to Endress+Hauser service devices.• Observe the instructions for transporting and returning the device outlined in the Operating Instructions.• If you have any questions, contact your Endess+Hauser service organization.Tool list for Prosonic Flow 92 F, Prowirl 72, 73acid-free,non-hardeninggreaseTool list for Prowirl 200Safety symbolsA0011189-ENDANGER!This symbol alerts you to a dangerous situation. Failure to avoid this situation will result in serious or fatal injury.A0011190-ENWARNING!This symbol alerts you to a dangerous situation. Failure to avoid this situation can result in serious or fatal injury.A0011191-ENCAUTION!This symbol alerts you to a dangerous situation. Failure to avoid this situation can result in minor or medium injury.A0011192-ENNOTICE!This symbol contains information on procedures and other facts which do not result in personal injury.DANGERWARNINGCAUTIONNOTICEImportant advice to the replacement of the sensor compact and remote version!1.The sealing surface must not get scratched.2.Remove sealing disk using a suitable tool, without scratching the sealing surface.3.Clean the sealing surface on the meter body using a suitable solvent and lint-free cloth.4.The bore in which it sits must be completely clean.5.Place the new sensor seal on the sealing surface with the inscription (if present) facing upwards.6.Apply grease to the thread and head contacts of the sensor screws.7.Apply one drop of grease to both the thread and the connec-ting surfaces of the screws. The grease used must be suited to the application temperature range. The high-temperature paste HTP (50048898) is recommeded.8.For orientation DSC-Sensor see the graphic below:DANGER!•To replace the sensor, the piping must be completely depressu-rized. The residual pressure on the piping may cause the sensor eject rapidly as soon as the mounting screws are released!•In the case of toxic, explosive or combustible media, the piping in which the measuring device is installed must bedecontaminated prior to replacing the sensor!•Let the the pipe cool down to a safe temperatures before starting the work.Overview de-assembly/assembly Prosonic Flow 92F, Prowirl 72, 73Overview de-assembly/assembly Prowirl 200Removing the components of the device:page Mounting the components of the device:page Removing transmitter compact- and remote version Prowirl 72, 73, Prosonic Flow 92 F7 Re-assembly Prowirl 72, 72, Prosonic Flow 9210Replacing gasket, O-ring cover, connection board Prowirl 72, 73, Prosonic Flow 92 F wall mounting 8Recommended torques for Prowirl 72, 7310Replacing O-Ring cover, connection board Prowirl 72, 73 remote version8Replacing gasket, O-ring cover, connection board Prowirl 72, 73, Prosonic Flow 92 F wall mounting 9Replacing DSC-sensor Prowirl 72, 739Removing the components of the device:page Mounting the components of the device:page Removing the Transmitter Prowirl 200 compact version 11 Assembly DSC-sensor Prowirl 20013Removing connection housing Prowirl 200 remote version from the housing post12Mounting the transmitter Prowirl 200 compact version, replacing the S-DAT14Re-assembly DSC-sensor Prowirl 20012Mounting the connection housing Prowirl 200 remote version 15Important procedure following sensor replacement 15Recomended torques Prowirl 20015Prowirl 72, 73, Prosonic Flow 92 F1. Removing transmitter compact- and remote version Prowirl 72, 73, Prosonic Flow 92 FCAUTION!Before starting work on the device switch off its power supply!3. Replacing O-Ring cover, connection board Prowirl 72, 73 remote versionCAUTION!Before starting work on the device switch off its power supply!CAUTION!Before starting work on the device switch off its power supply!Replacing DSC-sensor Prowirl 72, 735. Replacing DSC-sensor Standard Prowirl 72, 73, gasket6. Replacing DSC-sensor high-/low temperature Prowirl 72, 73, gasket7. Replacing DSC-sensor high pressure Prowirl 72, 73, gasket8. Replacing DSC-sensor max. pressure Prowirl 72, 73, gasket9. Re-assembly Prowirl 72, 72, Prosonic Flow 92When assembling, note temperature specifications and torques in the table in →Chap.11!Re-assembly is carried out in reverse order, unless otherwise instructed. The following must be noted:10. Important procedure following sensor replacementNOTICEAfter sensor replacement the service technician should carry out the following procedure:Service Transducer Block → Sensor-Serial Number DSC-Sensor. Note: Serial number is engraved directly on the DSC-Sensor!→ For further information see SH00012DEN , page 24, chapter 2.3.28.11. Recommended torques for Prowirl 72, 73position H = screws housing support position S = screws sensor7****-**0*********7****-**1********* 7****-**3********* 7****-**4*********7****-**2*********7****-**6*********see page 9→Chap.5see page 9→Chap. 5see page 9→Chap.6see page 9→Chap.6see page 10→Chap.7see page 10→Chap.7see page 10→Chap.8see page 10→Chap.8Pos. HPos. SPos. HPos. SPos. H Pos. S Pos. H Pos. SSteps; tighten in a diagonally opposite sequenceSteps and bolting sequence1.1.1.1.2.1.1.A, B, A, B, D, C2.B, A,C, D3.A, B, C, DTorques [Nm (lbft)7,0 (5,2)7,0 (5,2)7,0 (5,2)10,0 (7,4)15,0 (11,0)14,0 (10,3)10,0 (7,4)20,0 (14,8)26,0 (19,2)Apply one drop of grease to each screw. The grease used must be suited to the application temperature range.The high-temperature paste HTP (50048898) is recommended.Prowirl 2001. Removing the Transmitter Prowirl 200 compact versionCAUTION!Before starting work on the device switch off its power supply!Store S-DAT (see graphic 8 + 9) in a save place and replace in spare transmitter ( →Chap.11, graphic 5 + 6 )!1. 2. 3.2. Removing connection housing Prowirl 200 remote version from the housing postCAUTION!Before starting work on the device switch off its power supply!Re-assembly DSC-sensor Prowirl 2003. Removing DSC-sensor in Prowil D, F, R (Volume flow basic)4. Removing DSC-sensor in Prowirl D, F, R (Volume flow High -/low temp. or Mass flow (integrated Temperature measurement))5. Removing DSC-sensorinProwirl O, C (Volume flow Alloy 718 or Mass flow Alloy 718)6. Removing DSC-sensor in Prowirl O (Volume flow Titanium)Assembly DSC-sensor Prowirl 200DANGER!To tighten the screws of the housing support (H) and the sensor (S) see the table on page 15!7. Assembly DSC-sensor in Prowil D, F, R(Volume flow basic)8. Assembly DSC-sensor in Prowirl D, F, R(Volume flow High -/low temp. or Mass flow (integrated Temperature measurement))9. Assembly DSC-sensor in Prowirl O, C (Volume flow Alloy 718 or Mass flow Alloy 718)10. Assembly DSC-sensor in Prowirl O (Volume flow Titanium)11. Mounting the transmitter Prowirl 200 compact version, replacing the S-DAT12. Mounting the connection housing Prowirl 200 remote version13. Important procedure following sensor replacementNOTICEAfter sensor replacement the service technician should carry out the following procedure:Expert → Sensor → Sensor adjustm. → Sensor adjustm. (7734)Start DSC sensor adjustment for saving the reference measrurement data.→ For further information see SH01019DEN , page 30, chapter "Sensor adjustment".14. Recommended torques for Prowirl 200position H = screws housing support position S = screws sensorDSC-sensor D, R, F (volume flow basic)and housing postDSC-sensor D, R, F (high/low temperature) andhousing postDSC-sensor O, C (volume flow, Alloy 718)and housing post DSC-sensor O (titanium)and housing postsee page 13→Chap. 7see page 13→Chap. 7see page 13→Chap. 8see page 13→Chap. 8see page 13→Chap. 9see page 13→Chap. 9see page 13→Chap. 10see page 13→Chap. 10Pos. HPos. SPos. HPos. SPos. HPos. SPos. HPos. SSteps; tighten in a diagonally opposite sequenceSteps and bolting sequence1.1.1.1.2.1.1.A, B, A, B, D, C2.B, A,C, D3.A, B, C, DTorques [Nm (lbft)7.0 (5.2)7.0 (5.2)7.0 (5.2)10.0 (7.4)15.0 (11.0)14.0 (10.3)10.0 (7.4)20.0 (14.8)26.0 (19.2)Apply one drop of grease to each screw. The grease used must be suited to the application temperature range.The high-temperature paste HTP (50048898) is recommended.。

INTEGRATED MULTIPLE REPEATER IIPublication Release Date: November 1996GENERAL DESCRIPTION.................................................................................................................2FEATURES........................................................................................................................................2ORDERING INFORMATION..............................................................................................................2SYSTEM DIAGRAM ..........................................................................................................................3PIN CONFIGURATION......................................................................................................................3PIN DESCRIPTION ...........................................................................................................................4BLOCK DIAGRAM.............................................................................................................................8FUNCTIONAL DESCRIPTION...........................................................................................................8AUI Interface and Twisted Pair Line Transceiver..........................................................................................8Link Test Function.........................................................................................................................................8Automatic Polarity Reversal Function...........................................................................................................9Port Partition/Reconnection Logic.................................................................................................................9Port Status Direct Report Function...............................................................................................................9Initial State After Reset...............................................................................................................................11Management Logic and Management Interface.........................................................................................11IMPR II Programmable Options..................................................................................................................15The IMPR II Kernel Logic............................................................................................................................15Inter-IMPR II Interface.................................................................................................................................16ABSOLUTE MAXIMUM RATINGS...................................................................................................17DC CHARACTERISTICS.................................................................................................................17AC CHARACTERISTICS.................................................................................................................19System Clock Timing..................................................................................................................................19Reset Timing...............................................................................................................................................19Management Bus Clock Timing..................................................................................................................20Management Bus Carrier Sense Timing.....................................................................................................20Inter-IMPR II Interface Input Timing............................................................................................................21Inter-IMPR II Interface Output Timing.........................................................................................................22Inter-IMPR II Interface Collision Timing.......................................................................................................23Inter-IMPR II Interface to AUI/TP Port Timing.............................................................................................23Output Driver Timing...................................................................................................................................24Repetition Timing (part 1)...........................................................................................................................24Repetition Timing (part 2)...........................................................................................................................25Link Test Timing..........................................................................................................................................26PACKAGE DIMENSIONS. (28)GENERAL DESCRIPTIONThe Integrated Multiple Port Repeater II (IMPR II) implements the repeater functions specified by section 9 of the IEEE 802.3 standard and twisted pair line transceiver functions conforming to the 10BASE-T standard. The IMPR II provides eight Twisted Pair (TP) Line Transceiver Ports and an Attachment Unit Interface (AUI) port. Each Twisted Pair (TP) Line Transceiver Port can connect to an Ethernet segment through a twisted pair line. The AUI port can connect to a thick Ethernet segment by means of a 50-meter AUI cable. The IMPR II provides an AUI/TP port status direct report function, which uses the ten port status pins and two select pins to indicate collisions, port link/activity, partition, polarity, and network utilization. The inter-IMPR II interface includes signals for connecting more than one IMPR II to increase the total number of hub ports. The manageable functions of the repeater and twisted pair line transceiver in the IMPR II can be accessed through a serial interface. FEATURES•Functions conform to IEEE 802.3 section 9 specifications•Single 5V power supply•CMOS process for lower power dissipation•Twisted-Pair (TP) line media interface compatible with 10 BASE-T specifications•Differential interface compatible with AUI specifications• Port status direct report function•Asynchronous Inter-IMPR II interface for large hub applications•Serial management interface allows for network management and makes port status information accessible•AUI and TP port carrier sense signals observable through a port activity monitor port•Internal main state machine performs fragment extension, packet repetition, and collision handling functions•Internal jabber lockup protection state machine monitors the length of each input packet to prevent transmission of excessively large packets•Separate partition state machine for each TP port and AUI port can isolate ports when an excessive number of collisions occur and reconnect them using certain algorithms•On-chip PLL, Manchester encoder/decoder, and FIFOORDERING INFORMATIONTYPE NO.PACKAGEW89C982AF100-pin QFPPublication Release Date: November 1996SYSTEM DIAGRAMPIN DESCRIPTIONPublication Release Date: November 1996ContinuedMANAGEMENT BUS PINSNAME NO.I/O DESCRIPTIONMSI27I Management Data in:The management command is serially clocked into IMPR II byMCLK.MSO29O Management Data Out:The network status or the internal management status of the IMPRII is serially read out from MSO whenever the IMPR II receives astatus read command.TEST37I IMPR II Test Mode:This pin should be tied high during test mode and tied low duringnormal operations.PCRS32O Network Port Carrier Sense:The carrier sense signals for the IMPR II's internal logic from theAUI port and eight TP ports are serially sampled and outputthrough PCRS. The output bits are stream synchronized to X1clock.STR31O Network Port Carrier Sense Strobe:The serial bit stream on PCRS can be latched by an external latchusing the STR signal. The STR goes high for two X1 clock cyclesafter the nine carrier sense bits are output through PCRS.X134I System Clock Input:An external 20 MHz system clock source is connected to this pin toprovide the operating clock. For crystal applications, a 20 MHzcrystal may be connected across pins X1 and X2.X235O Crystal Clock Feedback:Pin X2 should be left floating when an external clock source isused.PORT STATUS DIRECT REPORT INTERFACE PINSM1 M02526I Port Status Direct Report Select Pins:These two pins control the output status of the port status pins.Four output states can be selected by M1, M0:TP Link/Activity Partition Polarity error UtilizationAUI COL/Activity Partition Loopback error UtilizationM1 0 0 1 1M0 0 1 0 1XCOL-RPT 47O Collision Status Direct Report Output: Whenever a collision event occurs, this pin is active high. This pin drives a TTL data buffer,which directly drives an LED.Publication Release Date: November 1996ContinuedPORT STATUS DIRECT REPORT INTERFACE PINSNAME NO.I/O DESCRIPTIONAUI -RPT 48OAUI Port Status Direct Report Output: This pin outputs the AUI port status selected by M0/M1. This pin drives a TTL data buffer, which directly drives an LED.TP0 -RPT TP7 -RPT 49−51,54−58OTP Port Status Direct Report Output: These pins output the TP port status selected by M0/M1.These pins drive a TTL data buffer, which directly drives an LED.POWER GROUND PINSV DD 10, 19, 52,64, 73IPower Supply for TP Transmit/Port Status Pins: +5V DC power supply.V SS 7, 22, 53,61, 76I Ground for TP Transmit/Port Status Pins.AV DD87ITP Receive Power Supply: +5V DC power supply.This pin should be decoupled with a 22 µF capacitor and kept separate from other power and ground planes.AV SS 94I TP Receive Ground: Grounding pins.PLL -V DD 1IPLL Power Supply: +5V DC power supply.This pin should be decoupled with a 22 µF capacitor and kept separate from other power and ground planes.PLL -V SS 2I PLL Ground: Grounding pins.DV DD 33, 41I Digital Power Supply: +5V DC power supply.DV SS30, 36, 43IDigital Ground: Grounding pins.BLOCK DIAGRAMFUNCTIONAL DESCRIPTIONThe Integrated Multiple Port Repeater II implements the functions stipulated in the IEEE repeater specifications, the functions specified by 10BASE-T standards, and functions for network management. It provides an Inter-IMPR II interface to allow implementation of a repeater set with more network ports. The block functions of the IMPR II are described below.AUI Interface and Twisted Pair Line TransceiverThe AUI provides an interface for an external Medium Attached Unit (MAU) connected to the IMPR II.The IMPR II can be used to connect a 10BASE2 or 10BASE5 Ethernet to a 10BASE-T Ethernet via a coaxial transceiver. The Twisted Pair Line Transceiver provides the interface used to connect IEEE 802.3 LAN stations (Data Terminal Equipment, or DTEs) into Ethernet networks constructed from twisted pair media. The Twisted Pair Line Transceiver also contains a link test function and autopolarity reversal function for wiring detection.Link Test FunctionThe link test function of the TP port is used to check whether the TP port is linked to an active TP port. The TP port will enter link fail state if it does not receive any packets or link test pulses for more than 60 mS, until it receives either six consecutive link pulses or a packet. When the TP port is in linkPublication Release Date: November 1996fail state, the IMPR II will not transmit any signal (packets or link pulses) on the TP port and the first input packet will not be retransmitted. The IMPR II will transmit link test pulses to any TP port after the transmitter of the TP port has been inactive for more than 16 mS after the TP port enters link good state. The link test function of the TP port is user-programmable using the management functions of the IMPR II. The TP port is forced into link good status if the link test function is disabled.The link test function is enabled by default each time the IMPR II is reset.Automatic Polarity Reversal FunctionThe automatic polarity reversal function checks the polarity of the input data packets or link pulses.The polarity of the TP port will be set to negative when the polarity of the first input packet or the first three consecutive link pulses following reset or following entry of the TP port into link fail state are detected to be negative. Once the polarity of the TP port is set to negative, all consequent input packets will be retransmitted with data that are inverted with respect to the input packet after the TP port enters link good state. If the polarity of the TP port is not set to negative, all input packets will be retransmitted without any modification of the data polarity. Once the polarity of the TP port is determined, the polarity of this port will not be updated until the IMPR II is either reset or re-enters link fail state, regardless of whether the automatic polarity reversal function is disabled or enabled. The automatic polarity reversal function is user-programmable using the management functions of the IMPR II and is enabled by default each time the IMPR II is reset. The default status of polarity is "correct" when the IMPR II is in reset state.Port Partition/Reconnection LogicThe port partition/reconnection logic implements the segment partitioning algorithm and the segment reconnection algorithm. These algorithms are defined by IEEE specifications and are used to protect the network from malfunctioning segments. There are nine partition/reconnection machines in an IMPR II. Each port partition reconnection machine controls an individual network port.A network port will be partitioned by the IMPR II when either of the following conditions is detected:(1) A collision condition exists continuously for a period of up to 1024 bit times.(2) Thirty-two consecutive collisions occur.A collision condition is defined as more than two network ports attempting to transmit simultaneously or as a receive collision from the AUI.The IMPR II can reconnect a partitioned network port using algorithms selected by programming the management logic. The following are the two reconnection algorithms:(1) Standard reconnection algorithm:A partitioned network port will be reconnected if a data packet longer than 512 bit times is retransmitted to or received from that port without collision.(2) Alternative reconnection algorithm:A partitioned network port will be reconnected if a data packet longer than 512 bit times is retransmitted to that port without collision.The reconnection algorithms for all the TP ports and the AUI port are programmed individually;however, all the TP ports use the same algorithm. The standard algorithm is selected by default each time the IMPR II is reset.Port Status Direct Report FunctionThe IMPR II provides one pin (XCOLRPT) for collision status report, two pins (M0/M1) for port status report mode selection, and nine pins for port status report (AUIRPT, TP0-7RPT). XCOLRPT is active when a collision occurs. Each of the nine port status report pins can directly report four aspects of the port status. Which aspect of the network status is reported by these pins is determined by the two mode selection pins, M1 and M0, as shown in the table below.TP LINK/ACTIVITY AUI COL/ACTIVITYPARTITIONTP POLARITYAUI LOOPBACK ERRORUTILIZATION UTILIZATIONM10011M011When M0 and M1 are set to "0," the pins report TP link/activity and AUI COL/activity. In this mode, a low output on AUIRPT and TP0-7RPT means all the TP ports are in the link fail state, a high means all the TP ports are in link good state, and the AUI is in collision state, and a 10 Hz signal means incoming packets are being received by the AUI/TP ports. (Note that the 10 Hz signal is still reported if the ports are partitioned or disabled.) If M0 is set to "1" and M1 to "0," the port partition status will be reported. In this mode, a "0" output means that all the ports are connected correctly, and a "1" means that the AUI/TP ports are in a partition state. When M0 is set to "0" and M1 to "1," AUI loopbackerrors and TP polarity status will be reported. In this mode, a "0" output means that the AUI loopback and TP polarity are correct, and a "1" means that an AUI loopback error has been detected and the TP port polarity is reversed. If M0 and M1 are both set to "1," the network utilization will be reported.In this mode, each LED stands for 10% of utilization. The percentage of network utilization is shown the following table.% OF UTILIZATIONAUI LEDTP0LEDTP1LEDTP2LEDTP3LEDTP4LEDTP5LEDTP6LEDTP7LED10%v 30%v v v 50%v v v v v 90%vvvvvvvvvUsing pins M1 and M0 and external transistors, the IMPR II can drive LEDs to indicate the status of the AUI/TP ports sequentially; the application circuit for the LEDs is shown below. If a simple decoder is connected to pins M1 and M0 and a switch circuit is connected to TP0RPT to TP7RPT, the TP port link/activity, partition, polarity, and network utilization can be displayed simultaneously.Publication Release Date: November 1996Initial State After ResetWhen RST is driven low, the IMPR II is reset. The minimum time the reset signal must be held low to trigger a reset is 100 µS. During reset, the IMPR II places all outputs in the inactive state (except for the auto polarity reversal function). Active low outputs stay high, active high outputs stay low, link test is enabled, and the TP link is in a fail state. The AUI/TP auto partition/reconnection uses the standard algorithm, AUI/TP transmitters are idle, AUI/TP receivers are enabled, IDAT and IJAM are in high-impedance state, STR is low, and the auto polarity reversal function is enabled.Management Logic and Management InterfaceThe major functions of the management logic are enabling/disabling networks, partitioning/recon-necting network ports, enabling/disabling the link test and autopolarity reversal functions of the twisted pair line transceiver, and accessing the link status and polarity status of the twisted pair line transceiver. The management interface is a signal bus that contains input/output signals to/from the management logic and the internal carrier sense signals for the nine network ports of the IMPR II.The management logic can accept and execute management commands when the IMPR II is in normal mode, i.e., the TEST pin of the IMPR II is tied low. All management commands are byte-oriented and are clocked into the IMPR II serially by an external clock. Some of the commands require an output from the IMPR II in response and some do not. At least 20 clocks are required to send a command that requires an output response from the IMPR II; 14 clocks are needed to send a command that requires no response. The serial command data stream and any associated output response data stream are structured in a manner compatible with the RS232 serial data format, i.e.,one start bit followed by eight data bits, with the LSB sent first and the MSB last.The following table summarizes the management commands. The LSBs of both the MSI data and the MSO data are shown on the right and the MSBs are shown on the left. Each command is described in more detail below.MSI INPUT DATA MSO READ DATA FUNCTIONS11010000P7 . . . P0Read link test status of TP ports11100000P7 . . . P0Read polarity status of TP ports10000000P7 . . . P0Read partition status of TP ports10001111P7 . . . P0Read bit rate error status of TP ports11110000M0000000Read MJLP status10001111PBSL0000Read AUI port status (B, S, L cleared)10001011PBSL0000Read AUI port status (S, L cleared)10001101PBSL0000Read AUI port status (B cleared)10001001PBSL0000Read AUI port status (None cleared)00111111None Enable AUI port00101111None Disable AUI port00110bbb None Enable TP ports00100bbb None Disable TP ports01010bbb None Enable TP port link test function01000bbb None Disable TP port link test function01110bbb None Enable TP ports auto polarity reversal function01100bbb None Disable TP ports auto polarity reversal function00011111None Set AUI port alternate reconnection algorithm00010000None Set TP port alternate reconnection algorithm00001CSA None Set IMPR II programmable optionRead Link Test Status of TP PortsThe link test status of all eight TP ports can be read using this command. Bits 0 through 7 correspond to the link test status of TP ports 0 through 7. A "1" on the MSO bit indicates "Link Good" status and a "0" indicates "Link Fail" status.Read Polarity Status of TP PortsThe polarity status of all eight TP ports can be read using this command. Bits 0 through 7 correspond to the polarity status of TP ports 0 through 7. A "1" on the MSO bit indicates reversed polarity and a "0" indicates positive polarity.Read Partition Status of TP PortsThe partition status of all eight TP ports can be read using this command. Bits 0 through 7 correspond to the polarity status of TP ports 0 through 7. A "1" on the MSO bit indicates a connected status and a "0" indicates a partitioned status.Publication Release Date: November 1996Read Bit Rate Error Status of TP PortsThe bit rate error status of the TP ports can be read using this command. Bits 0 through 7 correspond to the polarity status of TP ports 0 through 7. A "1" on the MSO bit indicates that a bit rate error has occurred and a "0" indicates no bit rate error has occurred.Read MJLP StatusThe MAU jabber lock-up protection status can be accessed using this command. A "1" on the MSB indicates the transmit function of the IMPR II has been inhibited. The status can also be cleared using this command.Read AUI Port StatusThe AUI port status, including partition, bit rate error, SQE test, and loopback error, can be accessed using different variations of this command. Four different specific commands can be used, as shown in the following table.MSI DATA MSO DATA CLEAR BITS10001111PBSL0000B, S, L read cleared. P not cleared.10001011PBSL0000S, L read cleared. P, B not cleared.10001101PBSL0000 B read cleared. P, S, L not cleared.10001001PBSL0000P, B, S, L not cleared.Enable AUI PortWhen disabled, the AUI port can be re-enabled using this command. The AUI port will then carry out normal transmitting and receiving operations. To reconnect a partitioned AUI port, the port must first be disabled and then re-enabled using this command.Disable AUI PortThis command is used to disable the AUI port. When the AUI port is disabled, all inputs (the carrier sense and the SQE) to the AUI port will be ignored by the IMPR II and the IMPR II will not transmit any signal on the AUI port. In addition, the partition machine for the AUI port will be forced into idle status.Enable TP PortsThis command is used to enable a disabled TP port, allowing it to perform normal transmitting and receiving operations. To reconnect a partitioned TP port or force a TP port into link fail state, the port must first be disabled and then re-enabled using this command.Disable TP PortsEach TP port can be disabled individually. Bits 0, 1, and 2 are used to indicate the TP port that is to be disabled, as follows:B2B1B0TP PORT DISABLED000TP0001TP1010TP2011TP3100TP4101TP5110TP6111TP7When a TP port is disabled, all inputs (the carrier sense) to that port will be ignored by the IMPR II and the IMPR II will not transmit any signal on the port. The partition machine for the port will be forced into the idle state and the link test will indicate that the port is in the "Link Fail" state.Enable TP Port Link Test FunctionThis command is used to re-enable a link-test disabled TP port. Using this command on a TP port that is already enabled will have no effect on the port.Disable TP Port Link Test FunctionThe TP port link test function can be enabled or disabled port-by-port. Bits 0, 1, and 2 are used to select which TP port is to be disabled in the manner described under the "Disable TP ports" command above. Once the link test function is disabled, the TP port will not enter the link fail state.Enable TP Port Auto Polarity Reversal FunctionThe auto polarity reversal function of the TP ports can be enabled or disabled port-by-port. Bits 0, 1, and 2 are used to indicate which TP port is to be enabled, in the manner described under the "Disable TP ports" command above. When the auto polarity reversal function is enabled, the TP port will check the polarity of input packets once it enters the link fail state. This function is enabled by default each time the IMPR II is reset.Disable TP Port Auto Polarity Reversal FunctionThis command is used to disable the auto polarity reversal function of a TP port so that the port will no longer check the polarity of input packets. If an input packet with reversed data is received, the IMPR II will not correct the polarity and retransmit the packet to all the network ports. In this case, failure to reverse the polarity may cause a network error.Set AUI Port Alternative Reconnection AlgorithmThe partition/reconnection scheme can be programmed for the alternative (transmit only) reconnection algorithm using this command. To return the partition/reconnection logic of the AUI port back to the standard reconnection (transmit or receive) algorithm, the IMPR II must be reset.Set TP Port Alternative Reconnection AlgorithmThe partition/reconnection scheme can be programmed for the alternative (transmit only) reconnection algorithm using this command. To return the partition/reconnection logic of a TP port back to the standard reconnection (transmit or receive) algorithm, the IMPR II must be reset.Publication Release Date: November 1996The other main function of the management logic is the port activity monitoring function. The internal carrier sense signal of all network ports is sampled out serially. The accuracy of the carrier sense signals is 10 bit times. The first bit samples the internal carrier sense signal of the AUI port, the second bit samples TP0, the third bit samples TP1, and so forth. The tenth bit time is idle, and a strobe signal will be active during the tenth bit time. With the help of the strobe signal, the serial sampled carrier sense signal can be latched to a serial-to-parallel shifter.IMPR II Programmable OptionsThree IMPR II programmable options can set by this command via the appropriate bit in MSI data.The three programmable options are CI reporting, AUI SQE test mask, and alternative port activity monitor function, which correspond to bits C, S, and A, respectively.CI ReportingSetting bit C = 1 will alter the function of the STR pin. STR will become an input pin for repeater management devices and PCRS will insert the CI bit immediately before the AUI bit.AUI SQE Test MaskSetting S = 1 will disable the AUI SQE test when the SQE signal is within the SQE test window and no jam pattern will be asserted after transmitted packets. The SQE test window is from 6 bit times to 34 bit times. When the SQE signal is larger than the SQE test window, a collision condition has occurred.Alternative Port Activity MonitorSetting A = 1 will enable the alternative PAM function, so that repeater management devices can monitor the status of each port using the unmodified PCRS signal.The IMPR II Kernel LogicThe kernel logic of the IMPR II includes a main state machine and glue logic, timers and counters,jabber lockup and fragment extension logic, a PLL decoder, encoder and transmitter, a 64-bit FIFO with FIFO control logic, and a preamble/jam generator. These blocks perform most of the operations needed to fulfill the requirements of the IEEE repeater specification. When a packet is received by a connected port, it is sent via the receive multiplexer to the PLL decoder. Data and collision status are sent to the main state machine via the port partition/reconnection logic. This enables the main state machine to determine the source of data to be repeated and the type of data to be transmitted. The transmit data may be either the received packet's data field or a preamble/jam pattern consisting of a 1010... bit pattern.Associated with the main state machine are a series of timers and counters which ensure that various IEEE specification times (referred to as the TW1 to TW6 times) are fulfilled. The PLL decoder decodes the received data from Manchester code format into NRZ format and recovers the jitter accumulated over the receiving segment.The preamble/jam generator and the FIFO compensate for the preamble bit loss caused by receptions by the twisted pair line transceiver. The FIFO is used to store the bits of the data field temporarily while the preamble/jam generator is sending the preamble of the transmitting packet. A 1010... jam pattern is generated under network collision conditions.The jabber lockup and fragment extension logic monitors the retransmitted packet. A jam pattern will be appended to short packets (less than 96 bits in length) to extend them to a full 96 bits. The jabber。

APPLICATION: Tractors: 250C (9/92-10/92); 345D, 445D (9/92); Tractors: 3230 (9/92-9/93); 3430 (9/92-5/94); (1)Oversize OD Liners Also Available (+.030 - 161177) or (+.100 - 161178) FO-192-Q (2)Not in Gasket Sets4/1/2004QTY ITEM # DESCRIPTION LETTERED ITEMSINCLUDED IN KIT1 964181 In-Frame Kit I1 965181 Out-of-Frame Kit O3 161133 STD Piston Kit (Includes Pin & Rings) O I3 161134 .020 Piston Kit (Includes Pin & Rings)3 161135 .030 Piston Kit (Includes Pin & Rings)3 161136 .040 Piston Kit (Includes Pin & Rings)3 161174 Liner (Flanged / Semi-Finished Bore) (1)3 161175 Liner, Diesel (Flanged / Finished 4.401" Bore)3 161128 STD Ring Set3 161129 .020 Ring Set3 161131 .030 Ring Set3 161132 .040 Ring Set3 261162 STD Rod Bearing O I3 261163 .002 Rod Bearing3 261164 .010 Rod Bearing3 261165 .020 Rod Bearing3 261166 .030 Rod Bearing3 261167 .040 Rod Bearing1 261175 STD Main Bearing Set O I1 261176 .002 Main Bearing Set1 261177 .010 Main Bearing Set1 261178 .020 Main Bearing Set1 261179 .030 Main Bearing Set1 261181 .040 Main Bearing Set1 361143 Head Gasket Set O I1 361116 Head Gasket 1 361126 Valve Cover Gasket (Steel Edge Molded Rubber)1 361142 Lower Gasket Set w/Seals O1 361141 Rear Seal Retainer Gasket 1 361127 Pan Gasket Set, Steel Pan (Use 361146 For Cast Pan) I1 361128 Front Crank Seal1 361144 Crank Spacer (2)1 361131 Rear Crank Seal1 301131 Rear Crank Wear Sleeve (2)3 261159 Pin Bushing: 250C, 345D, 445D (Straight)3 261161 Pin Bushing: 3230, 3430 (Tapered)1 261131 Cam Bearing Set6 761117 Rod Bolt, Early6 761118 Rod Nut, Early6 761127 Rod Capscrew, Late1 761122 Head Bolt Kit (9/16" Bolts)Tractors: 3230 (9/92-9/93); 3430 (9/92-5/94);(3)Use 561125 For Bushing OnlyFO-192-Q4/1/2004QTY ITEM # DESCRIPTION LETTERED ITEMSINCLUDED IN KIT1 969511 Camshaft Kit C1 969124 Valve Train Kit V1 561112 CamshaftC6 561111 Tappet C3 461119 STD Exhaust Valve V3 461121 .003 Exhaust Valve3 461122 .015 Exhaust Valve3 461123 .030 Exhaust Valve3 461124 STD Intake Valve V3 461125 .003 Intake Valve3 461126 .015 Intake Valve3 461127 .030 Intake Valve6 6 3 12 401141 461147 461146 461131 Service Repair Valve Guide (Use When Wear Exceeds .030) Valve Spring (2.39" Free Length) Spring/Retainer Kit (Incls Springs, Retainers, Seals) Valve Keeper (Half)VV3 461136 STD Exhaust Valve Seat3 461137 .020 Exhaust Valve Seat3 461138 STD Intake Valve Seat3 461139 .020 Intake Valve Seat3 461141 Exhaust Rocker Arm3 461142 Intake Rocker Arm1 461144 Rocker Arm Shaft3 461145 Rocker Arm Locating Spring1 561117 Cam Gear1 561126 Crank Gear1 561121 Idler Gear (3)1 561122 Hydraulic Pump Drive Gear (Rear of Cam)6 561115 Push Rod1 661112 Oil Pump1 661113 Intermediate Oil Pump Shaft 1 661114 Oil Pump Drive Gear & Shaft1 761228 Crankshaft (Pin Type Timing Gear)1 761123 Plug, Rear Cam / Hyd Pump Drive Gear Cover2 761125 Plug, Oil Galley (.824" OD)1 861127 Thermostat (168 Degree)1 861128 Thermostat (172 Degree)1 861129 Thermostat (180 Degree)1 861131 Thermostat (188 Degree)1 861133 Block Heater (1.500" Dia.Core Hole)。