同步复位和异步复位的区别

同步和异步的区别集锦

通俗版:

举个例子：普通B/S模式（同步）AJAX技术（异步）

同步：提交请求->等待服务器处理->处理完毕返回 这个期间客户端浏览器不能干任何事

异步: 请求通过事件触发->服务器处理（这是浏览器仍然可以作其他事情）->处理完毕

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同步就是你叫我去吃饭，我听到了就和你去吃饭；如果没有听到，你就不停的叫，直到我告诉你听到了，才一起去吃饭。

异步就是你叫我，然后自己去吃饭，我得到消息后可能立即走，也可能等到下班才去吃饭。

所以，要我请你吃饭就用同步的方法，要请我吃饭就用异步的方法，这样你可以省钱。

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举个例子 打电话时同步 发消息是异步

综述版:

异步通信”是一种很常用的通信方式。异步通信在发送字符时，所发送的字符之间的时间间隔可以是任意的。当然，接收端必须时刻做好接收的准备（如果接收端主机的电源都没有加上，那么发送端发送字符就没有意义，因为接收端根本无法接收）。发送端可以在任意时刻开始发送字符，因此必须在每一个字符的开始和结束的地方加上标志，即加上开始位和停止位，以便使接收端能够正确地将每一个字符接收下来。异步通信的好处是通信设备简单、便宜，但传输效率较低（因为开始位和停止位的开销所占比例较大）。

异步通信也可以是以帧作为发送的单位。接收端必须随时做好接收帧的准备。这是，帧的首部必须设有一些特殊的比特组合，使得接收端能够找出一帧的开始。这也称为帧定界。帧定界还包含确定帧的结束位置。这有两种方法。一种是在帧的尾部设有某种特殊的比特组合来标志帧的结束。或者在帧首部中设有帧长度的字段。需要注意的是，在异步发送帧时，并不是说发送端对帧中的每一个字符都必须加上开始位和停止位后再发送出去，而是说，发送端可以在任意时间发送一个帧，而帧与帧之间的时间间隔也可以是任意的。在一帧中的所有比特是连续发送的。发送端不需要在发送一帧之前和接收端进行协调（不需要先进行比特同步）。 每个字符开始发送的时间可以是任意的t0 0 1 1 0 1 1 0起始位结束位t每个帧开始发送的时间可以是任意的以字符为单位发送以帧为单位发送帧开始帧结束

Asynchronous & Synchronous ResetDesign Techniques - Part DeuxClifford E. CummingsDon MillsSteve GolsonSunburst Design, Inc.LCDM EngineeringTrilobyte Systemscliffc@mills@sgolson@ABSTRACTThis paper will investigate the pros and cons of synchronous and asynchronous resets. It willthen look at usage of each type of reset followed by recommendations for proper usage of eachtype.SNUG Boston 2003Asynchronous & Synchronous ResetRev 1.3Design Techniques - Part Deux21.0 IntroductionThe topic of reset design is surprisingly complex and poorly emphasized. Engineering schoolsgenerally do an inadequate job of detailing the pitfalls of improper reset design. Based on ourindustry and consulting experience, we have compiled our current understanding of issuesrelated to reset-design and for this paper have added the expertise of our colleague Steve Golson,who has done some very innovative reset design work. We continually solicit and welcome anyfeedback from colleagues related to this important design issue.We presented our first paper on reset issues and techniques at the March 2002 SNUGconference[4] and have subsequently received numerous email responses and questions relatedto reset design issues.We obviously did not adequately explain all of the issues related to the asynchronous resetsynchronizer circuit because many of the emails we have received have asked if there aremetastability problems related to the described circuit. The answer to this question is, no, thereare no metastability issues related to this circuit and the technical analysis and explanation arenow detailed in section 7.1 of this paper.Whether to use synchronous or asynchronous resets in a design has almost become a religiousissue with strong proponents claiming that their reset design technique is the only way toproperly approach the subject.In our first paper, Don and Cliff favored and recommended the use of asynchronous resets indesigns and outlined our reasons for choosing this technique. With the help of our colleague,Steve Golson, we have done additional analysis on the subject and are now more neutral on theproper choice of reset implementation.Clearly, there are distinct advantages and disadvantages to using either synchronous orasynchronous resets, and either method can be effectively used in actual designs. When choosinga reset style, it is very important to consider the issues related to the chosen style in order tomake an informed design decision.This paper presents updated techniques and considerations related to both synchronous andasynchronous reset design. This version of the paper includes updated Verilog-2001 ANSI-styleports in all of the Verilog examples.The first version of this paper included an interesting technique for synchronizing the resetting ofmultiple ASICs of a high speed design application. That material has been deleted from thispaper and readers are encouraged to read the first version of the paper if this subject is ofinterest.SNUG Boston 2003Asynchronous & Synchronous ResetRev 1.3Design Techniques - Part Deux32.0 Resets PurposeWhy be concerned with these annoying little resets anyway? Why devote a whole paper to sucha trivial subject? Anyone who has used a PC with a certain OS loaded knows that the hardwarereset comes in quite handy. It will put the computer back to a known working state (at leasttemporarily) by applying a system reset to each of the chips in the system that have or require areset.For individual ASICs, the primary purpose of a reset is to force the ASIC design (eitherbehavioral, RTL, or structural) into a known state for simulation. Once the ASIC is built, theneed for the ASIC to have reset applied is determined by the system, the application of the ASIC,and the design of the ASIC. For instance, many data path communication ASICs are designed tosynchronize to an input data stream, process the data, and then output it. If sync is ever lost, theASIC goes through a routine to re-acquire sync. If this type of ASIC is designed correctly, suchthat all unused states point to the “start acquiring sync” state, it can function properly in a systemwithout ever being reset. A system reset would be required on power up for such an ASIC if thestate machines in the ASIC took advantage of “don’t care” logic reduction during the synthesisphase.We believe that, in general, every flip-flop in an ASIC should be resetable whether or not it isrequired by the system. In some cases, when pipelined flip-flops (shift register flip-flops) areused in high speed applications, reset might be eliminated from some flip-flops to achieve higherperformance designs. This type of environment requires a predetermined number of clocksduring the reset active period to put the ASIC into a known state.Many design issues must be considered before choosing a reset strategy for an ASIC design,such as whether to use synchronous or asynchronous resets, will every flip-flop receive a reset,how will the reset tree be laid out and buffered, how to verify timing of the reset tree, how tofunctionally test the reset with test scan vectors, and how to apply the reset across multipleclocked logic partitions.3.0 General flip-flop coding style notes3.1 Synchronous reset flip-flops with non reset follower flip-flopsEach Verilog procedural block or VHDL process should model only one type of flip-flop. Inother words, a designer should not mix resetable flip-flops with follower flip-flops (flops with noresets) in the same procedural block or process[14]. Follower flip-flops are flip-flops that aresimple data shift registers.In the Verilog code of Example 1a and the VHDL code of Example 1b, a flip-flop is used tocapture data and then its output is passed through a follower flip-flop. The first stage of thisdesign is reset with a synchronous reset. The second stage is a follower flip-flop and is not reset,but because the two flip-flops were inferred in the same procedural block/process, the resetsignal rst_n will be used as a data enable for the second flop. This coding style will generateextraneous logic as shown in Figure 1.

异步电动机？和同步电动机有何区别，它们各自适用于哪些场合

同步电机就是靠励磁电流运行的，如果没有励磁，电机就是异步的。励磁是加在转子上的直流系统，它的旋转速度和极性与定子是一致的，如果励磁出现问题，电动机就会失步，调整不过来，触发保护“励磁故障”电动机跳闸

说的白一点，励磁电流就是同步电机转子中流过的电流（有了这个电流，使转子相当于一个电磁铁，有N极和S极），在正常运行时，这个电流是由外部加在转子上的直流电压产生的。以前这个直流电压是由直流电动机供给，现在大多是由可控硅整流后供给。我们通常把可控硅整流系统称为励磁装置。

异步机就是电机的转子转动的速度与定子所产生的旋转磁场的旋转速度不一致，有一个差值（不同步）。我们叫转差。这个转差与定子所产生的旋转磁场的转速的比率叫转差率。

同步机与异步机的区别在于：从供电方面说，异步机只是在定子侧加上电压（也有转子上加电压的），而同步机要在定子和转子上都加上电压。也就是说异步机是单边励磁，同步机是双边励磁。 从转速方面说，异步机的转速只与负荷大小有关（当然有一定的范围），而同步机的转速只与电网的频率有关。 从结构上说，同步电机与异步机转子的构造也不一样。异步机的转子是有夕钢片和铝条（或夕钢片和线圈组成），而同步机一般由数块磁钢和线圈组成（也有隐极式的不太一样）。 当然还有许多差别，如工艺要求、设计问题等等

首先说明一点的是，异步电机只用于电动机，极少用作发电机，都是同步电机用来发电。

异步电动机的原理主要是在定子中通入3相交流电，使其产生旋转磁场，转速为n0，即同步转速。不同的磁极对数p，在相同频率f=50Hz的交流电作用下，会产生不同的n0，n0=60f/p。

工作原理如下：

对称3相绕组通入对称3相电流，产生旋转磁场，磁场线切割转子绕组，根据电磁感应原理，转子绕组中产生e和i，转子绕组在磁场中受到电磁力的作用，即产生电磁转矩，使转子旋转起来，转子输出机械能量，带动机械负载旋转起来。

同步和异步的区别

答案一：

同步和异步是两种交互或者通信方式。放在计算机网络里有数据包的传输方式，放在总线级上又有外设和内存之间数据的传输方式。放在操作系统里，进程之间的交互也有同步和异步两种交互方式。但是其精髓是一样的。

计算机网络领域：

1.异步传输

通常，异步传输是以字符为传输单位，每个字符都要附加 1 位起始位和 1 位停止位，以标记一个字符的开始和结束，并以此实现数据传输同步。所谓异步传输是指字符与字符(一个字符结束到下一个字符开始)之间的时间间隔是可变的，并不需要严格地限制它们的时间关系。起始位对应于二进制值 0，以低电平表示，占用 1 位宽度。停止位对应于二进制值 1，以高电平表示，占用 1~2 位宽度。一个字符占用

5~8位，具体取决于数据所采用的字符集。例如，电报码字符为 5 位、ASCII码字符为 7 位、汉字码则为8 位。此外，还要附加 1 位奇偶校验位，可以选择奇校验或偶校验方式对该字符实施简单的差错控制。发送端与接收端除了采用相同的数据格式(字符的位数、停止位的位数、有无校验位及校验方式等)外，还应当采用相同的传输速率。典型的速率有：9 600 b/s、19.2kb/s、56kb/s等。

异步传输又称为起止式异步通信方式，其优点是简单、可靠，适用于面向字符的、低速的异步通信场合。例如，计算机与Modem之间的通信就是采用这种方式。它的缺点是通信开销大，每传输一个字符都要额外附加2～3位，通信效率比较低。例如，在使用Modem上网时，普遍感觉速度很慢，除了传输速率低之外，与通信开销大、通信效率低也密切相关。

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2. 同步传输

通常，同步传输是以数据块为传输单位。每个数据块的头部和尾部都要附加一个特殊的字符或比特序列，标记一个数据块的开始和结束，一般还要附加一个校验序列(如16位或32位CRC校验码)，以便对数据块进行差错控制。所谓同步传输是指数据块与数据块之间的时间间隔是固定的，必须严格地规定它们的时间关系。