RT2N62M中文资料

T62M0002ADigital Sound Processor EmbeddedSRAMFeatures! Operating voltage: 4.5V ~ 5.5V! ADM algorithm! Low noise ( -88dB typical)! Low distortion rate (0.5% typical)! Embedded SRAM! Automatic reset function! Package type: 16-pin DIP/SOP DescriptionThe T62M0002A is an echo/surround effect processor. It is designed for various audio systems including karaoke, television, sound equipment, etc. The chip consists of a built-in pre-amplifier, VCO or V oltage control OSC, Embedded SRAM, A/D and D/A converters as well as delay time control logic. Itsbuilt-In reply to SRAM can generate delay time effect and can control the delay time value through the external VCO resistor. The VCO circuit can reduce external components and make it easy to adjust the delay time.Part Number ExamplesPart NO. Pkg DescriptionT62M0002A-j 16-SOP 300mil-16-SOPT62M0002A-K 16-DIP 300mil-16-DIPTM Technology Inc. reserves the right P. 1 Publication Date: JUL. 2002TM Technology Inc. reserves the right P. 2 Publication Date: JUL. 2002 Block DiagramLP F1 INLP F1O UTLP F2O UTLP F2INO P 2O UTO P 2IN O P 1INO P 1O UTC C 0C C 1V C C R EF A GN DD GN D O S C _O V C OPIN ConfigurationT62M0002ATM Technology Inc. reserves the right P. 3 Publication Date: JUL. 2002 PIN DescriptionPin NO. Pin Name I/O Description 1 VCC - Analog and positive power supply 2 REF I Analog reference voltage 3 AGEND - Analog ground 4 DGEND - Digital ground 5 OSC_O I System oscillator output 6 VCO I System oscillator input,system frequency adjustable pin 7 CC1 - Currentcontrol18 CC2- Currentcontrol2 9 OP1_OUT O OP1output 10 OP1_IN I OP1 input 11 OP2_IN I OP2 input 12 OP2_OUT O OP2 output 13 LPF2_IN I Low pass filter2 input 14 LPF2_OUT O Low pass filter2 output 15 LPF1_OUT O Low pass filter1 output 16 LPF1_IN I Low pass filter1 inputFunction DescriptionThe T62M0002A is an echo/surround effect generator with built-in SRAM. It enaures low distortion as well as low noise for processing audio signal delay. The chip provides two playing modes(echo and surround) and the playing function block diagrams are shown as follows.- Surround Modeout -Echo ModeElectrical CharacteristicsTa=25ºC Symbol ParameterMin. Typ. Max. UnitTest ConditionsVDD ConditionsV oltage - - 4.5 5.0 5.5 V V CC OperatingCurrent 5V - - 15 30 mAI CC OperatingGain 5V RG V V oltage=47KΩ- 0.5 2.5 dBLV OMAX Maximum Output V oltage 5V THD=10% 1.0 1.6 - Vrms THD Total Harmonic Distortion 5V 30KHz L.P.F. - 0.5 1.5 %No Output Noise V oltage 5V DIN Audio - -88 -80 dbV Absolute Maximum RatingsSupply V oltage …………………………………………………. -0.3V to 6VInput V oltage …………………………………………………… Vss-0.3V to VDD+0.3VStorage Temperature ……………………………………………. -50ºC to 125ºCOperating Temperature ……………………………… -20ºC to 70ºCNote: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.TM Technology Inc. reserves the right P. 4 Publication Date: JUL. 2002Application CircuitsNote:”Radj” Value con set delay time. R/delay time Reference on Resistance / Delay Time Table.TM Technology Inc. reserves the right P. 5 Publication Date: JUL. 2002TM Technology Inc. reserves the right P. 6 Publication Date: JUL. 2002 Resistance / Delay Time Table .FCK 2.0M 2.5M 3.0M 3.5M 4.0M 4.5M 5.0M 5.5M Radj 53.40k 41.97k 33.41k 28.18k 24.00k 20.90k 18.20k 16.00k TD 264ms 226ms 174ms 150ms 130ms 117ms 106ms 95.2ms THD+N% 1.29% 0.95% 0.73% 0.57% 0.48% 0.41% 0.37% 0.33%FCK 6.0M 6.5M 7.0M 7.5M 8.0M 8.5M 9.0M 10M Radj 14.50k 12.90k 11.60k 10.70k 9.72k 9.07k 8.07k 6.98k TD 89ms 80.8ms 74.8ms 70.4ms 65.2ms 62.4ms 57.6ms 52.4ms THD+N% 0.29% 0.28% 0.25% 0.24% 0.22% 0.22% 0.21% 0.18%FCK 11M 12M 13M 14M 15M 16M 17M 18M Radj 5.99k 5.30k 4.52k 4.02k 3.48k 3.08k 2.64k 2.30k TD 47.6ms 44.2ms 40.2ms 37.6ms 35.0ms 33.0ms 30.8ms 29.0ms THD+N% 0.17% 0.15% 0.14% 0.14% 0.14% 0.14% 0.14%0.14%FCK 19M 20M 21M 22M Radj 2.16k 1.89k 1.69k 1.49k TD 27.8ms 26.2ms 25.0ms 24.0ms THD+N%0.14% 0.14% 0.14% 0.14%Note :This Table is for Surround Mode.R= Extend Resister for adjust FCK & TD.FCK= Oscillate output Frequency for Pin 5 .(Unit : MHZ) TD=Delay Time for output.THD=Total Harmonic Distortion. (TDH+N Ratio %)Pulse Clock Waveform for input PinTM Technology Inc. reserves the rightP. 7 Publication Date: JUL. 2002 IC PackageT62M0002A 16-SOPUnit:mmT62M0002A 16-DIPUnit:mm。

AI0197416A0-A15W DQ0-DQ14V CCM29F100T M29F100BE V SS15G RPDQ15A–1BYTE RBFigure 1.Logic DiagramM29F100T M29F100B1Mbit (128Kb x8or 64Kb x16,Boot Block)Single Supply Flash Memory5V ±10%SUPPLY VOLTAGE for PROGRAM,ERASE and READ OPERATIONS FAST ACCESS TIME:70ns FAST PROGRAMMING TIME–10µs by Byte /16µs by Word typicalPROGRAM/ERASE CONTROLLER (P/E.C.)–Program Byte-by-Byte or Word-by-Word –Status Register bits and Ready/Busy Output MEMORY BLOCKS–Boot Block (Top or Bottom location)–Parameter and Main blocksBLOCK,MULTI-BLOCK and CHIP ERASE MULTI-BLOCK PROTECTION/TEMPORARY UNPROTECTION MODESERASE SUSPEND and RESUME MODES –Read and Program another Block during Erase SuspendLOW POWER CONSUMPTION –Stand-by and Automatic Stand-by100,000PROGRAM/ERASE CYCLES per BLOCK20YEARS DATARETENTION –Defectivity below 1ppm/year ELECTRONIC SIGNATURE –Manufacturer Code:0020h–Device Code,M29F100T:00D0h –Device Code,M29F100B:00D1hDESCRIPTIONThe M29F100is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by-Byteor Word-by-Word basis using only a single 5V V CC supply.For Program and Erase operations the necessary high voltages are generated internally.The device can also be programmed in standard program-mers.The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks.Blocks can be protected against pro-graming and erase on programming equipment,and temporarily unprotected to make changes in the application.Each block can be programmed and erased over 100,000cycles.July 19981/30441SO44(M)TSOP48(N)12x 20mmDQ3DQ9DQ2A6DQ0W A3RB DQ6A8A9DQ13NC A10DQ14A2DQ12DQ10DQ15A–1V CC DQ4DQ5A7DQ7NC NC AI01975M29F100T M29F100B (Normal)121132425363748DQ8NC NC A1NC A4A5DQ1DQ11G A12A13NC A11BYTE A15A14V SSE A0RP V SS Figure 2A.TSOP Pin ConnectionsG DQ0DQ8A3A0E V SS A2A1A13V SSA14A15DQ7A12NC BYTE DQ15A–1DQ5DQ2DQ3V CCDQ11DQ4DQ14A9W RB A4NC RPA7AI01977M29F100T M29F100B 8234567910111213141516323130292827262524232220191817DQ1DQ9A6A5DQ6DQ134439383736353433A11A10DQ1021DQ12404314241NC A8Figure 2C.SO Pin Connections DQ3DQ9DQ2DQ0DQ6DQ13DQ14DQ12DQ10DQ15A–1V CC DQ4DQ5DQ7AI01976M29F100T M29F100B (Reverse)121132425363748DQ8DQ1DQ11NC BYTE V SS A0V SS A6A3A8A9NC A10A2A7NC NC NC NC A1NC A4A5A12A13A11A15A14RP W RB G EFigure 2B.TSOP Reverse Pin ConnectionsA0-A15Address InputsDQ0-DQ7Data Input/Outputs,Command Inputs DQ8-DQ14Data Input/OutputsDQ15A–1Data Input/Output or Address Input E Chip Enable G Output Enable W Write EnableRP Reset /Block Temporary Unprotect RB Ready/Busy Output BYTE Byte/Word Organisation V CC Supply Voltage V SSGroundTable 1.Signal NamesWarning:NC =Not Connected.Warning:NC =Not Connected.Warning:NC =Not Connected.2/30M29F100T ,M29F100BSymbol Parameter Value Unit T A Ambient Operating Temperature(3)–40to125°CT BIAS Temperature Under Bias–50to125°CT STG Storage Temperature–65to150°CV IO(2)Input or Output Voltages–0.6to7VV CC Supply Voltage–0.6to7V V(A9,E,G,RP)(2)A9,E,G,RP Voltage–0.6to13.5V Notes:1.Except for the rating”Operating Temperatur e Range”,stresses above those listed in the Table”Absolute Maximum Ratings”may cause permanent damage to the device.These are stress ratings only and operation of the device at these or any otherconditions above those indicated in the Operating sections of this specification is not implied.Exposure to Absolute MaximumRating conditions for extended periods may affect device reliability.Refer also to the STMicroelectronics SURE Program and other relevant quality documents.2.Minimum Voltage may undershoot to–2V during transition and for less than20ns.3.Depends on range.Table2.Absolute Maximum Ratings(1)Instructions for Read/Reset,Auto Select for read-ing the Electronic Signature or Block Protection status,Programming,Blockand ChipErase,Erase Suspend and Resume are written to the device in cyclesof commandsto a CommandInterfaceusing standard microprocessor write timings.The device is offered in TSOP48(12x20mm)and SO44packages.Both normal and reverse pinouts are available for the TSOP48package. OrganisationThe M29F100is organised as128Kb x8or64Kb x16bits selectable by the BYTE signal.When BYTE is Low the Byte-wide x8organisation is selected and the address lines are DQ15A–1and A0-A15.The Data Input/Output signal DQ15A–1 acts as address line A–1which selects the lower or upper Byte of the memory word for output on DQ0-DQ7,DQ8-DQ14remain at High impedance. When BYTE is High the memory uses the address inputs A0-A15and the Data Input/Outputs DQ0-DQ15.Memory control is provided by Chip Enable E,Output Enable G and Write Enable W inputs. AReset/Block TemporaryUnprotection RPtri-level input provides a hardware reset when pulled Low, andwhen heldHigh(atV ID)temporarily unprotects blocks previously protected allowing them to be programedand erased.Erase and Program opera-tions are controlled by an internal Program/Erase Controller(P/E.C.).Status Register data output on DQ7provides a Data Polling signal,and DQ6and DQ2provide Toggle signals to indicate the state of the P/E.C operations.A Ready/Busy RB output indicates the completion of the internal algorithms. Memory BlocksThe devices feature asymmetrically blocked archi-tectureproviding system memory integration.Both M29F100T and M29F100B devices have an array of5blocks,one Boot Block of16KBytes or8 KWords,two Parameter Blocks of8KBytes or4 KWords,one Main Block of32KBytes or16 KWords and one Main Blocks of64KBytes or32 KWords.The M29F100T has the Boot Block at the top of the memory address space and the M29F100B locates the Boot Block starting at the bottom.The memory maps are showed in Figure 3.Each block can be erased separately,any com-bination of blocks can be specified for multi-block erase or the entire chip may be erased.The Erase operations are managed automatically by the P/E.C.The block erase operation can be sus-pended in order to read from or program to any block not being ersased,and then resumed. Block protection provides additional data security. Each block can be separately protected or unpro-tected against Program or Erase on programming equipment.All previously protected blocks can be temporarily unprotected in the application.Bus OperationsThe following operations can be performed using the appropriatebus cycles:Read(Array,Electronic Signature,Block Protection Status),Write com-mand,Output Disable,Standby,Reset,Block Pro-tectio n,Unp ro te ctio n,Pro te cti on Verify, Unprotection Verify and Block Temporary Unpro-tection.See Tables4and5.DESCRIPTION(Cont’d)3/30M29F100T,M29F100B16K BOOT BLOCKAI019781FFFFh1C000h 1BFFFh1A000h 19FFFh 8K PARAMETER BLOCK8K PARAMETER BLOCK32K MAIN BLOCK 64K MAIN BLOCKM29F100T18000h 17FFFh 10000h 0FFFFh 00000hM29F100B 16K BOOT BLOCK8K PARAMETER BLOCK 8K PARAMETER BLOCK 32K MAIN BLOCK 64K MAIN BLOCK 1FFFFh10000h 0FFFFh 08000h 07FFFh 04000h 03FFFh 00000h 06000h 05FFFh Figure 3.Memory Map and Block Address Table (x8)Address Range (x8)Address Range (x16)A15A14A13A1200000h-03FFFh 0000h-1FFFh 000X 04000h-05FFFh 2000h-2FFFh 001006000h-07FFFh 3000h-3FFFh 001108000h-0FFFFh 4000h-7FFFh 01X X 10000h-1FFFFh8000h-FFFFh1XXXTable 3B.M29F100B Block Address TableAddress Range (x8)Address Range (x16)A15A14A13A1200000h-0FFFFh 0000h-7FFFh 0X X X 10000h-17FFFh 8000h-BFFFh 10X X 18000h-19FFFh C000h-CFFFh 11001A000h-1BFFFh D000h-DFFFh 11011C000h-1FFFFhE000h-FFFFh111XTable 3A.M29F100T Block Address Table4/30M29F100T ,M29F100BCommand InterfaceInstructions,made up of commands written in cy-cles,can be given to the Program/Erase Controller through a Command Interface(C.I.).For added data protection,program or erase execution starts after4or6cycles.The first,second,fourth and fifth cycles are used to input Coded cycles to the C.I. This Coded sequence is the same for all Pro-gram/Erase Controller instructions.The’Com-mand’itself and its confirmation,when applicable, are given on the third,fourth or sixth cycles.Any incorrect command or any improper command se-quence will reset the device to Read Array mode. InstructionsSeven instructions are defined to perform Read Array,Auto Select(to read the ElectronicSignature or Block ProtectionStatus),Program,Block Erase, Chip Erase,Erase Suspend and Erase Resume. The internal P/E.C.automatically handles all tim-ing and verification of the Program and Erase operations.The Status Register Data Polling,Tog-gle,Error bits and the RB output may be read at any time,during programming or erase,to monitor the progress of the operation.Instructions are composed of up to six cycles.The first two cycles input a Coded sequence to the Command Interfacewhich iscommon to all instruc-tions(see Table8).The third cycle inputs the instruction set-up command.Subsequent cycles output the addressed data,Electronic Signature or Block Protection Status for Read operations.In order to give additional data protection,the instruc-tions for Program and Block or Chip Erase require furthercommandinputs.For a Programinstruction, the fourth command cycle inputs the address and data to be programmed.For an Erase instruction (Block or Chip),the fourth and fifth cycles input a further Coded sequence before the Erase confirm command on the sixth cycle.Erasure of a memory block may be suspended,in orderto readdata from another block or to program data in another block, and then resumed.When power is first applied or if V CC falls below V LKO,the command interface is reset to Read Array.SIGNAL DESCRIPTIONSSee Figure1and Table1.Address Inputs(A0-A15).The address inputs for the memory array are latched during a write opera-tion on the falling edge of Chip Enable E or Write Enable W.In Word-wide organisation the address lines are A0-A15,in Byte-wide organisation DQ15A–1acts as an additional LSB address line.When A9is raised to V ID,either a Read Electronic Signature Manufacturer or Device Code,Block Protection Status or a Write Block Protection or Block Unprotection is enabled depending on the combination of levelson A0,A1,A6,A12and A15. Data Input/Outputs(DQ0-DQ7).Th e se In-puts/Outputsare used in the Byte-wide and Word-wide organisations.The input is data to be programmed in the memory array or a command to be written to the C.I.Both are latched on the rising edge of Chip Enable E or Write Enable W. The output is data from the Memory Array,the Electronic Signature Manufacturer or Device codes,the Block Protection Status or the Status register Data Polling bit DQ7,the Toggle Bits DQ6 and DQ2,the Error bit DQ5or the Erase Timer bit DQ3.Outputs are valid when Chip Enable E and Output Enable G are active.The output is high impedance when the chip is deselected or the outputsare disabled and when RP is at a Low level. Data Input/Outputs(DQ8-DQ14and DQ15A–1). These Inputs/Outputsare additionally used in the Word-wide organisation.When BYTEis High DQ8-DQ14and DQ15A–1act as the MSB of the Data Input or Output,functioning as described for DQ0-DQ7above,and DQ8-DQ15are’don’t care’for command inputs or status outputs.When BYTE is Low,DQ8-DQ14are high impedance,DQ15A–1is the Address A–1input.Chip Enable(E).The Chip Enable input activates the memory control logic,input buffers,decoders andsenseamplifiers.E Highdeselectsthe memory andreducesthe power consumptionto the standby level.E can also be used to control writing to the command register and to the memory array,while W remainsat a low level.The Chip Enable must be forced to V ID during the Block Unprotection opera-tion.Output Enable(G).The Output Enable gates the outputs through the data buffers during a read operation.When G is High the outputs are High impedance.G must be forced to V ID level during Block Protection and Unprotection operations. Write Enable(W).This input controls writing to the Command Registerand Addressand Datalatches. Byte/Word Organization Select(BYTE).The BYTE input selects the output configuration for the device:Byte-wide(x8)mode or Word-wide(x16) mode.When BYTE is Low,the Byte-wide mode is selected and the data is read and programmed on DQ0-DQ7.In this mode,DQ8-DQ14are at high impedance and DQ15A–1is the LSB address. When BYTE is High,the Word-wide mode is se-lected and the data is read and programmed on DQ0-DQ15.5/30M29F100T,M29F100BReady/Busy Output(RB).Ready/Busy is an open-drainoutput and gives the internalstateof the P/E.C.of the device.When RB is Low,the device is Busy with a Program or Erase operation and it will not accept any additional program or erase instructions except the Erase Suspend instruction. WhenRB is High,the deviceis readyfor any Read, Program or Erase operation.The RB will also be High when the memory is put in Erase Suspend or Standby modes.Reset/Block Temporary Unprotect Input(RP). The RP Input provides hardware reset and pro-tected block(s)temporary unprotection functions. Reset of the memory is acheived by pulling RP to V IL for at least500ns.When the reset pulse is given,if the memory is in Read or Standby modes, it will be available for new operations in50ns after the rising edge of RP.If the memory is in Erase, Erase Suspend or Program modes the reset will take10µs during which the RB signal will be held at V IL.The endof thememoryreset will beindicated by the rising edge of RB.A hardware reset during an Eraseor Programoperation will corrupt the data being programmed or the sector(s)being erased. Temporary block unprotection is made by holding RP at V ID.In this condition previously protected blocks can be programmed or erased.The transi-tion of RP from V IH to V ID must slower than500ns. When RP is returned from V ID to V IH all blocks temporarily unprotected will be again protected. V CC Supply Voltage.The power supply for all operations(Read,Program and Erase).V SS Ground.V SS is the reference for all voltage measurements.DEVICE OPERATIONSSee Tables4,5and6.Read.Read operations are used to output the contents of the Memory Array,the Electronic Sig-nature,the Status Register or the Block Protection Status.Both Chip Enable E and Output Enable G must be low in order to read the output of the memory.Write.Write operationsare used to give Instruction Commands to the memory or to latch input data to be programmed.Awrite operationis initiated when Chip Enable E is Low and Write Enable W is Low with Output Enable G High.Addresses are latched on the falling edge of W or E whicheveroccurs last. Commands andInput Data are latchedon the rising edge of W or E whichever occurs first.Output Disable.The data outputs are high imped-ance when the Output Enable G is High with Write Enable W High.Standby.The memory is in standby when Chip Enable E is High and the P/E.C.is idle.The power consumption is reduced to the standby level and the outputs are high impedance,independent of the Output Enable G or Write Enable W inputs. Automatic Standby.After150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumptionis reduced to the CMOS standby value,while outputs still drive the bus. Electronic Signature.Two codes identifying the manufacturer and the device can be read from the memory.The manufacturer’s code for STMi-croelectronics is20h,the devicecode is D0h for the M29F100T(T op Boot)and D1h for the M29F100B (Bottom Boot).These codes allow programming equipment or applications to automatically match their interface to the characteristics of the M29F100.The Electronic Signature is output by a Read operation when the voltage applied to A9is at V ID and address input A1is Low.The manufac-turer code is output when the Address input A0is Low and the device code when this input is High. Other Address inputs are ignored.The codes are output on DQ0-DQ7.The Electronic Signature can also be read,without raising A9to V ID,by giving the memory the Instruc-tion AS.If the Byte-wide configuration is selected the codes are output on DQ0-DQ7with DQ8-DQ14 at High impedance;if the Word-wide configuration is selected the codes are output on DQ0-DQ7with DQ8-DQ15at00h.Block Protection.Each block can be separately protected against Program or Erase on program-ming equipment.Block protection provides addi-tional data security,as it disables all program or eraseoperations.This modeis activatedwhen both A9and G are raised to V ID and an address in the block is applied on A12-A15.The Block Protection algorithm is shown in Figure14.Block protection is initiated on the edge of W falling to V IL.Then after a delay of100µs,the edge of W rising to V IH ends the protection operations.Block protection verify is achievedby bringing G,E,A0and A6to V IL andA1 to V IH,while W is at V IH and A9at V ID.Underthese conditions,reading the data output will yield01h if the block defined by the inputs on A12-A15is protected.Any attempt to program or erase a pro-tected block will be ignored by the device.6/30M29F100T,M29F100BOperation E G W RP BYTE A0A1A6A9A12A15DQ15A–1DQ8-DQ14DQ0-DQ7Read Word V IL V IL V IH V IH V IH A0A1A6A9A12A15Data Output Data Output Data Output Read Byte V IL V IL V IH V IH V IL A0A1A6A9A12A15Address InputHi-ZData Output Write Word V IL V IH V IL V IH V IH A0A1A6A9A12A15Data Input Data Input Data Input Write Byte V IL V IH V IL V IH V IL A0A1A6A9A12A15Address Input Hi-Z Data Input Output Disable V IL V IH V IH V IH X X X X X X X Hi-Z Hi-Z Hi-Z Standby V IH X X V IH X X X X X X X Hi-Z Hi-Z Hi-Z Reset X X X V IL X X X X X X X Hi-Z Hi-Z Hi-Z BlockProtection (2,4)V IL V ID V IL Pulse V IH X X X X V ID X X X X X BlocksUnprotection (4)V ID V ID V IL Pulse V IH X X X X V ID V IH V IH X X X BlockProtectionVerify (2,4)V ILV ILV IHV IHXV ILV IHV ILV IDA12A15XXBlock ProtectStatus (3)BlockUnprotection Verify (2,4)V IL V IL V IH V IH X V IL V IH V IH V ID A12A15X XBlock Protect Status (3)BlockTemporary Unprotection X X X V ID X X X X X X X X XXNotes:1.X =V IL or V IH2.Block Address must be given on A12-A15bits.3.See Table 6.4.Operation performed on programming equipment.Table er Bus Operations (1)CodeE G W A0A1A12-A15Other Addresses DQ0-DQ7Protected Block V IL V IL V IH V IL V IH Block Address Don’t Care 01h Unprotected BlockV ILV ILV IHV ILV IHBlock AddressDon’t Care00hTable 6.Read Block Protection with AS InstructionOrg.CodeDeviceE G W BYTE A0A1Other Addresses DQ15A–1DQ8-DQ14DQ0-DQ7Word-wideManufact.Code V ILV IL V IH V IH V IL V IL Don’t Care 000h 20h Device CodeM29F100T V IL V IL V IH V IH V IH V IL Don’t Care 000h D0h M29F100BV IL V IL V IH V IH V IH V IL Don’t Care 000h D1h Byte-wideManufact.CodeV ILV IL V IH V IL V IL V IL Don’t Care Don’t Care Hi-Z 20h Device CodeM29F100T V IL V IL V IH V IL V IH V IL Don’t Care Don’t Care Hi-Z D0h M29F100BV ILV ILV IHV ILV IHV ILDon’t CareDon’t CareHi-ZD1hTable 5.Read Electronic Signature (following AS instruction or with A9=V ID )7/30M29F100T,M29F100BBlock Temporary Unprotection.Any previously protected block can be temporarily unprotected in order to change stored data.The temporaryunpro-tection mode is activated by bringing RP to V ID. During the temporary unprotection mode the pre-viously protected blocks are unprotected.A block can be selected and data can be modified by executingthe Erase or Program instruction with the RP signal held at V ID.When RP is returned to V IH, all the previously protected blocks are again pro-tected.Block Unprotection.All protected blocks can be unprotected on programming equipment to allow updating of bit contents.All blocks must first be protected before the unprotection operation.Block unprotectionis activated when A9,G and E are at V ID and A12,A15at V IH.The Block Unprotection algorithm is shown in Figure15.Unprotection is initiatedby theedge of W falling to V IL.Aftera delay of10ms,the unprotection operation will end.Un-protectionverify is achieved by bringing G and E to V IL while A0is at V IL,A6and A1are at V IH and A9 remains at V ID.In these conditions,reading the output data will yield00h if the block defined by the inputs A12-A15has been succesfully unprotected. Each block must be separatelyverified by giving its address in order to ensure that it has been unpro-tected.INSTRUCTIONS AND COMMANDSThe Command Interface latches commands writ-ten to the memory.Instructions are made up from one or more commands to perform Read Memory Array,Read Electronic Signature,Read Block Pro-tection,Program,Block Erase,Chip Erase,Erase Suspend and Erase mands are made of address and data sequences.The in-structions require from1to6cycles,the first or first three of which are always write operationsused to initiate the instruction.They are followed by either further write cycles to confirm the first command or execute the command mand se-quencing must be followed exactly.Any invalid combination of commands will reset the device to Read Array.The increased number of cycles has been chosen to assure maximum data security. Instructions are initialised by two initial Coded cy-cles which unlock the Command Interface.In addi-tion,for Erase,instruction confirmation is again preceded by the two Coded cycles.Status Register BitsP/E.C.status is indicated during execution by Data Polling on DQ7,detection of Toggle on DQ6and DQ2,or Error on DQ5and Erase Timer DQ3bits.Any read attempt during Program or Erase com-mand executionwill automaticallyoutput these five Status Register bits.The P/E.C.automatically sets bits DQ2,DQ3,DQ5,DQ6and DQ7.Other bits (DQ0,DQ1and DQ4)are reserved for future use and should be masked.See Tables9and10. Data Polling Bit(DQ7).When Programming op-erations are in progress,this bit outputs the com-plement of the bit being programmed on DQ7. During Erase operation,it outputs a’0’.After com-pletion of the operation,DQ7will output the bit last programmed or a’1’after erasing.Data Polling is valid and only effective during P/E.C.operation, that is after the fourth W pulse for programming or after the sixth W pulse for erase.It must be per-formed at the address being programmed or at an address within the block being erased.If all the blocks selected for erasure are protected,DQ7will be set to’0’for about100µs,and then return to the previous addressed memory data value.See Fig-ure11for the Data Polling flowchart and Figure10 for the Data Polling waveforms.DQ7will also flag the Erase Suspend mode by switching from’0’to ’1’at the start of the Erase Suspend.In order to monitor DQ7in the Erase Suspend mode an ad-dress within a block being erased must be pro-vided.For a Read Operation in Erase Suspend mode,DQ7will output’1’if the read is attempted on a blockbeing erasedandthe data valueon other blocks.During Program operation in Erase Sus-pend Mode,DQ7will have the same behaviour as in the normal program execution outside of the suspend mode.Hex Code Command00h Invalid/Reserved10h Chip Erase Confirm20h Reserved30h Block Erase Resume/Confirm80h Set-up Erase90hRead Electronic Signature/Block Protection StatusA0h ProgramB0h Erase SuspendF0h Read Array/Resetmands8/30M29F100T,M29F100BMne.Instr.Cyc.1st Cyc.2nd Cyc.3rd Cyc.4th Cyc.5th Cyc.6th Cyc.7th Cyc.RD(2,4)Read/ResetMemory Array1+Addr.(3,7)XRead Memory Array until a new write cycle is initiated.Data F0h3+Addr.(3,7)Byte AAAAh5555h AAAAhRead Memory Array until a new write cycleis initiated.Word5555h2AAAh5555hData AAh55h F0hAS(4)Auto Select3+Addr.(3,7)Byte AAAAh5555h AAAAh Read Electronic Signature or BlockProtection Status until a new write cycle isinitiated.See Note5and6.Word5555h2AAAh5555hData AAh55h90hPG Program4Addr.(3,7)Byte AAAAh5555h AAAAh ProgramAddress Read Data Polling or Toggle Bituntil Program completes.Word5555h2AAAh5555hData AAh55h A0hProgramDataBE Block Erase6Addr.(3,7)Byte AAAAh5555h AAAAh AAAAh5555h BlockAddressAdditionalBlock(8) Word5555h2AAAh5555h5555h2AAAhData AAh55h80h AAh55h30h30hCE Chip Erase6Addr.(3,7)Byte AAAAh5555h AAAAh AAAAh5555h AAAAhNote9 Word5555h2AAAh5555h5555h2AAAh5555hData AAh55h80h AAh55h10hES(10)EraseSuspend1Addr.(3,7)X Read until Toggle stops,then read all the data needed from anyBlock(s)not being erased then Resume Erase.Data B0hER EraseResume1Addr.(3,7)X Read Data Polling or Toggle Bits until Erase completes or Erase issuspended another timeData30hNotes:mands not interpreted in this table will default to read array mode.2.A wait of t PLYH is necessary after a Read/Reset command if the memory was in an Erase or Program modebefore starting any new operation(see Table14and Figure9).3.X=Don’t Care.4.The first cycles of the RD or AS instructions are followed by read operations.Any number of read cycles can occur afterthe command cycles.5.Signature Address bits A0,A1at V IL will output Manufacturer code(20h).Address bits A0at V IH and A1at V IL will outputDevice code.6.Block Protection Address:A0at V IL,A1at V IH and A12-A15within the Block will output the Block Protection status.7.For Coded cycles address inputs A15is don’t care.8.Optional,additional Blocks addresses must be entered within the erase timeout delay after last write entry,timeout status can be verified through DQ3value(see Erase Timer Bit DQ3description).When full command is entered,read Data Polling or Toggle bit until Erase is completed or suspended.9.Read Data Polling,Toggle bits or RB until Erase completes.10.During Erase Suspend,Read and Data Program functions are allowed in blocks not being erased.Table8.Instructions(1)9/30M29F100T,M29F100BDQ Name Logic Level Definition Note7DataPolling’1’Erase Complete or eraseblock in Erase SuspendIndicates the P/E.C.status,check duringProgram or Erase,and on completionbefore checking bits DQ5for Program orErase Success.’0’Erase On-goingDQProgram Complete or dataof non erase block duringErase SuspendDQ Program On-going6Toggle Bit ’-1-0-1-0-1-0-1-’Erase or Program On-going Successive reads output complementarydata on DQ6while Programming or Eraseoperations are on-going.DQ6remains atconstant level when P/E.C.operations arecompleted or Erase Suspend isacknowledged.DQ Program Complete’-1-1-1-1-1-1-1-’Erase Complete or EraseSuspend on currentlyaddressed block5Error Bit ’1’Program or Erase Error This bit is set to’1’in the case ofProgramming or Erase failure.’0’Program or Erase On-going4Reserved3EraseTime Bit’1’Erase Timeout Period ExpiredP/E.C.Erase operation has started.Onlypossible command entry is Erase Suspend(ES).’0’Erase Timeout PeriodOn-goingAn additional block to be erased in parallelcan be entered to the P/E.C.2Toggle Bit ’-1-0-1-0-1-0-1-’Chip Erase,Erase or EraseSuspend on the currentlyaddressed block.Erase Error due to thecurrently addressed block(when DQ5=’1’).Indicates the erase status and allows toidentify the erased block 1Program on-going,Eraseon-going on another block orErase CompleteDQErase Suspend read onnon Erase Suspend block1Reserved0ReservedNotes:Logic level’1’is High,’0’is Low.-0-1-0-0-0-1-1-1-0-represent bit value in successive Read operations. Table9.Status Register BitsToggle Bit(DQ6).When Programming or Erasing operations are in progress,successive attempts to read DQ6will output complementarydata.DQ6will toggle following toggling of either G,or E when G is low.The operation is completed when two suc-cessive reads yield the same output data.The next readwill outputthe bitlastprogrammed or a’1’after erasing.The toggle bit DQ6is valid only during P/E.C.operations,that is after the fourth W pulse for programming or after the sixth W pulse for Erase.If the blocks selected for erasure are pro-tected,DQ6will toggle for about100µs and then return back to Read.DQ6will be set to’1’if a Read operationis attemptedon an Erase Suspendblock. When erase is suspended DQ6will toggle during programming operations in a block different to the block in Erase Suspend.Either E or G toggling will cause DQ6to toggle.See Figure12for Toggle Bit flowchart and Figure13for Toggle Bit waveforms.10/30M29F100T,M29F100B。

6MBI225U-1201200V / 225A 6 in one-packageFeatures· High speed switching· Voltage drive· Low inductance module structureApplications · Inverter for Motor drive· AC and DC Servo drive amplifierMaximum ratings and characteristicsThermal resistance characteristicsThermal resistanceContact Thermal resistance––0.12––0.20–0.0167 –IGBTFWDWith thermal compound°C/W°C/W°C/W*2 : Two thermistor terminals should be connected together, each other terminals should be connected together and shortedto base plate when isolation test will be done.*3 :Recommendable value : 2.5 to 3.5 N·m(M5) *4 :Recommendable value : 3.5 to 4.5 N·m(M6)Rth(j-c)Rth(j-c)Rth(c-f)*5IGBT Module U-Series*5 : This is the value which is defined mounting on the additional cooling fin with thermal compound.4Items Symbols Conditions Characteristics UnitMin.Typ. Max.· Uninterruptible power supply· Industrial machines, such as Welding machinesCharacteristics (Representative)VGE=0V, f= 1MHz, Tj= 25°CVcc=600V, I=225A, Tj= 25°CCollector current vs. Collector-Emitter voltage (typ.)Tj= 125°C / chipCapacitance vs. Collector-Emitter voltage (typ.)Dynamic Gate charge (typ.)Collector current vs. Collector-Emitter voltage (typ.)Tj= 25°C / chipCollector current vs. Collector-Emitter voltage (typ.)VGE=15V / chipTj=25°C / chipCollector-Emitter voltage vs. Gate-Emitter voltage (typ.)010020030040050060012345C o l l e c t o r c u r r e n t : I c [A ]VGE=20V15V12V10V8V010020030040050060012345C o l l e c t o r c u r r e n t : I c [A ]VGE=20V 15V12V10V8V010020030040050060001234C o l l e c t o r c u r r e n t : I c [A ]Tj=125°CTj=25°C246810510152025C o l l e c t o r - E m i t t e r v o l t a g e : V C E [ V ]Ic=450A Ic=225A Ic= 112.5A0.11.010.0100.0102030C a p a c i t a n c e : C i e s , C o e s , C r e s [ n F ]200400600800100012001400C o l l e c t o r -E m i t t e r v o l t a g e : V C E [ 200V /d i v ]G a t e - E m i t t e r v o l t a g e : V G E [ 5V /d i v]Vcc=600V, Ic=225A, VGE=±15V, Tj= 25°CStray inductance <= 100nHSwitching loss vs. Collector current (typ.)Vcc=600V, VGE=±15V, Rg=3ΩVcc=600V, Ic=225A, VGE=±15V, Tj= 125°C+VGE=15V,-VGE <= 15V, RG >= 3Ω ,Tj <= 125°CSwitching time vs. Collector current (typ.)Vcc=600V, VGE=±15V, Rg=3Ω, Tj=125°CSwitching time vs. Gate resistance (typ.)Switching time vs. Collector current (typ.)Vcc=600V, VGE=±15V, Rg=3Ω, Tj= 25°CReverse bias safe operating area (max.)Switching loss vs. Gate resistance (typ.)10100100010000100200300400S w i t c h i n g t i m e : t o n , t r , t o f f , t f [ n s e c ]Collector current : Ic [ A ]10100100010000100200300400S w i t c h i n g t i m e : t o n , t r , t o f f , t f [ n s e c ]Collector current : Ic [ A ]10100100010000110100S w i t c h i n g t i m e : t o n , t r , t o f f , t f [ n s e c ]Gate resistance : Rg [ Ω ]trtftoffton 01020304050100200300400500S w i t c h i n g l o s s : E o n , E o f f , E r r [ m J /p u l s e ]Collector current : Ic [ A ]Eon(125°C)Eon(25°C)Eoff(125°C)Err(125°C)Err(25°C)Eoff(25°C)0255075100125150110100S w i t c h i n g l o s s : E o n , E o f f , E r r [ m J /p u l s e ]Gate resistance : Rg [ Ω ]EoffErrEon0100200300400500600200400600800100012001400C o l l e c t o r c u r r e n t : I c [ A ]Collector - Emitter voltage : VCE [ V ]Transient thermal resistance (max.)Reverse recovery characteristics (typ.)Vcc=600V, VGE=±15V, Rg=3ΩForward current vs. Forward on voltage (typ.)chipTemperature characteristic (typ.)01002003004005006001234F o r w a r d c u r r e n t : I F [ A ]Forward on voltage : VF [ V ]Tj=125°CTj=25°C101001000100200300400500R e v e r s e r e c o v e r y c u r r e n t : I r r [ A ]R e v e r s e r e c o v e r y t i m e : t r r [ n s e c ]Forward current : IF [ A ]Irr (125°C)Irr (25°C)trr (125°C)trr (25°C)0.0010.0100.1001.0000.0010.0100.1001.000T h e r m a l r e s i s t a n s e : R t h (j -c ) [ °C /W ]Pulse width : Pw [ sec ]0.1110100-60-40-20020406080100120140160180Temperature [°C ]R e s i s t a n c e : R [ k Ω ]Outline Drawings, mmM6296MBI225U-120IGBT ModuleEquivalent Circuit Schematic[Thermister]135111210987246[Inverter]。

南天pr2技术参数Nantian PR-2E主要技术性能指标存储器特性8Mb FLASH闪速存储器内含西文字库和监控程序，支持“智能升级”功能128KByte RAM动态数据区256Byte EEPROM存储打印机配置参数和光电管设置参数16Mb掩膜EPROM GBK汉字库打印头特性打印头24针，菱形排列针直径0.25mm最大打印速度350字符/秒（10CPI）PTC过热温度保护纸边检测传感器打印精度成行度：<0.10mm(同向); <0.20mm(异向)成列度：<0.14mm(同向); <0.28mm(异向)打印头寿命> 4亿次/针打印特性打印方式点阵击打式，双向预测逻辑选距打印速度(最大值)高速草稿仿信函信函质量汉字(汉字/秒) 175 135 65 43ASCII(字符/秒) 350 260 130 86BIM（位映像图形方式）1220dps（点/秒）图形(位映象方式)点阵密度(点/英寸)水平方向Olivetti 8针：72(或96)，240，120，80，6024针：360，240，180，120，60IBM 60，120，240OKI 90，180LQ 90，180垂直方向Olivetti：180IBM：180OKI：180LQ：180打印字间距Olivetti ASCII字符5、10，12，13，15，16.6，17.1字符/英寸汉字：2.5，5，6，7.5，8.3，8.5汉字/英寸IBM ASCII字符10，12，15，17.1，20字符/英寸汉字：5，6，7.5，8.5，10汉字/英寸OKI ASCII字符10，12，13.8，16.6字符/英寸，汉字：13.8汉字/英寸LQ ASCII字符10，12，15字符/英寸，汉字：13.8汉字/英寸打印行间距Olivetti1/5、1/6，1/8，n/72，n/216，n/240 英寸IBM1/6，1/8，n/72，n/216 英寸OKI 1/6，1/8，n/120 英寸LQ1/6，1/8，n/180打印行长（字符/行）80、90、94打印属性正常、倍宽、倍高、三倍宽、三倍高、字符放大（西文最大：4 X 8、中文最大：4 X 4）、黑体、网底、斜体、中空、上标、下标、旋转、反白、上划线、下划线打印特征走纸进纸方式手动进纸纠偏方式光学传感器自动纠偏、自动对边最大进纸宽度245mm进纸器厚度2mm进纸速度大于26 厘米/秒对齐时间小于0.3秒打印厚度最大2mm进纸出错率纸张类型塞纸歪斜A4（80g/ m2）< 1/6000 1/6000（<1.5mm）多层拷贝（1+4）< 1/3000 1/3000（<1.5mm）存折本< 1/2000 1/500（<2mm）打印吞吐率（ECMA打印测试文本）打印质量打印吞吐率（页/小时）HSD（高速草稿）375DRAFT（草稿）280NLQ（仿信函）140LQ（信函）95仿真方式OLIVETTI PR2E、PR-2、PR-54、PR-50、PR-40、Nantian PR-50系列、Nantian PR-2系列、IBM PPDS、IBM PROPRINTER II、IBMPROPRINTER X24、OKI5330SC、OKI 5530SC、EPSON LQ1600K字体西文HSD、DRAFT、NLQ1、NLQ2、LQ、Native、Roman、Sans Serif、Italic、OCRA、OCRB汉字GBK宋体字符集ASCII 256个字符，96个半角字符GBK ISO—10646中、日、韩（C. J. K.）汉字，符合GB13000、GBK标准，共有24X24点阵的20902个汉字、1420个符号和101个扩充汉字IBM5550 1324个图形字符，6763个汉字用户造字223个ASCII字符，94个汉字国际字符组30组条形码标准UPC-A、UPC-E、EAN-8（JAN）、EAN-13（JAN）、Code 39、Code 128、Codabar（Monarch）、2/5 Interleaved、2/5Industrial可处理文本单页纸、连续纸、多页复写纸、存折本、票据、凭证纸张处理方式任意位置自动进纸、自动纠偏、自动对边、自动调整打印厚度文本打印规格单层或多层复写打印纸幅面宽允许值65mm - 245mm长允许值（OLIVETTI仿真）70mm - 450mm，最大推荐值：297mm（IBM、OKI、LQ仿真）：大于70mm最大打印区域（10CPI）：238mm垂直装订存折本存折本打开宽度：110mm - 241.3mm存折本长度：85mm - 220mm水平装订存折本存折本宽度110mm - 241.3mm存折本打开长度165mm - 220mm纸张厚度单层0.07mm - 0.28mm( 30 g/m2 —160g/m2)存折本存折本打开的最大厚度：1.8mm存折本页间最大厚度差：1.2mm存折本封面厚度：0.2—0.5 mm多层复写1+5页(原件40 g/m2 - 60 g/m2，复写纸20 g/m2 - 34 g/m2)多层复写最大纸重380 g/m2字符打印位置文本和存折本左右边界值LH/RH(字符边缘-页面边缘距离)：3.1mm±0.3mm文本和存折页顶标准(从字符底线测量)PR-2仿真= 4.23mmPR-50/40+、PR-54仿真= 7.4mmIBM PPII仿真= 4.23 mm文本页尾的最小值(从字符底线测)PR-2/PR-54+/PR-40+ = 3.1mmIBMPPII仿真= 10mm存折页尾的最小值(从字符底线测量)5mm 从装订线以上最末行字符基线到水平装订线的最小距离5mm 从装订线以下第一行字符基线到水平装订线的最小距离8mm 字符中心距垂直装订存折本的垂直装订线最小距离 5.08mm磁记录规范硬件水平磁条读写器选件，具有存折本和信用卡水平磁条读写功能磁条标准IBM 3604、IBM4746、DIN/ISO、ISO 7811、ISO 8484、ANSI、HITACHIBP仿真字符集标准标准1、标准2、标准3、标准4磁记录密度75BPI、105BPI、210BPI信用卡符合ISO7810标准的ID1卡，磁条长度为84毫米磁道位置第二、三磁道出错率< 1/10000传感检测开盖检测、前进纸槽纸张检测、纸对齐检测、纸宽检测、纸边检测、打印头复位位置检测通信接口标准接口总线接口（在主板上）可连接选件接口或其他设备串口1（在主板上）类型RS 232C串口相关标准V.24 RS232 C接口连接器9针D型接口波特率9600、4800、2400、1200校验奇校验、偶校验、无校验数据位8、7停止位1、2接收缓冲8Kbyte选件接口第二串口选件（串口2）：具有与串口1相同的特性并口选件（Parallel）类型Centronics相关标准IEEE 1284-1994操作模式SPP，nibble，byte接口连接器Centronics，36孔接收缓冲8KbyteDIN选件接口（伺服接口，在主板上）类型DIN类型6芯接口功能连接密码键盘、拖拉走纸器等USB选件接口（同时具有串口2和USB接口）类型终端类型相关标准USB rev1.1传输率200KBps色带规格特性长度22米颜色黑色寿命500 万字符电气参数电源类型开关电源电压（类型1）交流200—240V(±10%)电压（类型2）交流100—130V(±10%)频率50 Hz或60 Hz±0.5％功耗12 W (静态)-70W(动态)-170 W(最大)可靠性平均无故障时间(MTBF) ≥10，000小时安全认证标准CE、IMQ、CUL-US无线电干扰标准55022B、FCC A物理参数尺寸384mm×280mm×204mm重量9 kg （无磁条选件）Nantian PR9产品技术规格10 kg （带磁条选件）储存环境储存温度-10 ℃- 60 ℃相对湿度10% - 90％工作环境工作温度5 ℃- 3 5 ℃相对湿度15% - 85％(无霜)噪声小于54 Db应用软件Resource Kit集成环境应用软件功能：在线完成PR2E的版本“智能升级”；在线读取PR2E配置参数，并进行在线参数更改；可通过下载新的西文字符集进行字符集管理；管理宏定义命令和LOGO，通过在PR2E的64Kbyte FLASHEPROM中下载或删除宏定义命令或LOGO来管理用户标志或实现永久性用户造字功能，最多可以下载255个宏、LOGO或用户造字；Drivers驱动程序：IBM ProPrinter X24：并口连接，PR2E并口仿真设置为“南天—IBM”，IBM配置菜单下的仿真方式为“X24”，“AGM图形模式”设置为“是”，该驱动程序随WINDOWS提供；Olivetti驱动程序：串口连接，PR2仿真，垂直步距为1/216”，基于OLIVETTI协议设计，集成了工业标准应用可能涉及的所有特性。

F0149-BV REG.-Nr. 6106, Z E214025, b14385, B C0786Contact dataContact configuration 2 CO or 2 NOContact set single contactType of interruption micro disconnectionRated current8 A, UL: 10 ARated voltage / max.switching voltage AC 250/400VACLimiting continuous current UL: 10 AMaximum breaking capacity AC 2000 VALimiting making capacity, max 4 s, duty factor 10%15 AContact material AgNi 90/10, AgNi 90/10 gold plated, AgSnO26AC coil> 5 x 106cyclesRated frequency of operation with / without load 6 / 1200 min-1Contact ratingsType Load CyclesRT4248A, 250VAC, NO contact, 70°C, EN61810-1100x103RT4446(3)A, 250VAC, NO contact, 85°C; EN60730-1100x103RT4246(2)A, 250VAC, NO/NC contact, 85°C; EN60730-1100x103RT42410A, 250VAC, CO contact, 70°C; General purpose, UL50830x103RT4241/2hp @ 240VAC, 1/4hp @ 120VAC, UL508RT424Pilot duty B300, UL508RT4248A, 30VDC, General Purpose, UL508RT4244A, 230VAC, cosϕ=0.6, gas burner150x103Coil dataRated coil voltage range DC coil 5...110 VDCAC coil24...230 VACCoil power DC coil typ 400 mWAC coil typ 0,75 VAOperative range 2Coil insulation system according UL1446 class FCoil versions,DC-coilCoil Rated Operate Release Coil Rated coilcode voltage voltage voltage resistance powerVDC VDC VDC c mW0055 3.50.562+10%4030066 4.20.690+10%400012128.4 1.2360+10%4000242416.8 2.41440+10%4000484833.6 4.85520+10%4170606042.0 6.08570+12%42011011077.011.028800+12%420All figures are given for coil without preenergization, at ambient temperature +23°COther coil voltages on requestPCB layout / terminal assignmentBottom view on solder pinsS0163-BJ S0163-BKDimensionsS0272-BA *) With the recommended PCB hole sizes a grid pattern from 2.5mm to 2.54mm can be used.Coil versions,AC-coil 50HzCoil Rated Operate Release Coil Rated coil code voltage voltage voltage resistance power50Hz50Hz50Hz VAC VAC VAC c VA 5242418.0 3.6350+10%0.76 61511586.317.38100+15%0.76 62012090.018.08800+15%0.75 700200150.030.024350+15%0.76 730230172.534.532500+15%0.74 All figures are given for coil without preenergization, at ambient temperature +23°C Insulationrmsopen contact circuit1000 V rmsadjacent contact circuits2500 V rmsClearance / creepage coil-contact circuit W10 / 10 mmadjacent contact circuits W3 / 4 mmMaterial group of insulation parts W IIIaTracking index of relay base PTI 250 VInsulation to IEC 60664-1Type of insulation coil-contact circuit reinforcedopen contact circuit functionaladjacent contact circuits basicRated insulation voltage250 VPollution degree32Rated voltage system 240V400VOvervoltage category IIIOther dataRoHS - Directive 2002/95/EC compliant as per product date code 0413 Flammability class according to UL94 V-0GWIT to IEC 60335-1 (IEC 60695-2-13)> 755 °CAmbient temperature range -40...+70°COperate- / release time DC coil typ 7 / 2 msBounce time DC coil NO / NC contact typ 1 / 3 msVibration resistance (function) NO / NC contact20 / 5 g, 30 ... 300 HzShock resistance (destruction) 100 gCategory of protection RTII - flux proof, RTIII - wash tight Mounting pcb or on socketMounting distance DC / AC coils0 / 2.5 mmwash-tight version260°C / 5 sRelay weight13 gPackaging unit20 / 500 pcsAccessoriesFor details see datasheet accessories RT。

NTMD6N02R2Power MOSFET 6.0 Amps, 20 VoltsN−Channel Enhancement Mode Dual SO−8 PackageFeatures•Ultra Low R DS(on)•Higher Efficiency Extending Battery Life •Logic Level Gate Drive•Miniature Dual SO−8 Surface Mount Package •Diode Exhibits High Speed, Soft Recovery •Avalanche Energy Specified•SO−8 Mounting Information ProvidedApplications•DC−DC Converters•Low V oltage Motor Control•Power Management in Portable and Battery−Powered Products, forexample, Computers, Printers, Cellular and Cordless Telephones and PCMCIA CardsMAXIMUM RATINGS (T= 25°C unless otherwise noted)(1″ sq. 2 oz. Cu 0.06″ thick single sided), t < 10 seconds.2.Mounted onto a 2″ square FR−4 Board(1″ sq. 2 oz. Cu 0.06″ thick single sided), t = steady state.3.Minimum FR−4 or G−10 PCB, t = steady state.4.Pulse Test: Pulse Width = 10 m s, Duty Cycle = 2%.Device Package Shipping †ORDERING INFORMATIONNTMD6N02R2SO−82500/T ape & Reel†For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.MAXIMUM RATINGS (T= 25°C unless otherwise noted) (continued)ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (Note 5)6.Indicates Pulse Test: Pulse Width =300 m s max, Duty Cycle = 2%.7.Switching characteristics are independent of operating junction temperature.ELECTRICAL CHARACTERISTICS (T= 25°C unless otherwise noted) (continued) (Note 8)8.Handling precautions to protect against electrostatic discharge is mandatory.9.Indicates Pulse Test: Pulse Width =300 m s max, Duty Cycle = 2%.I D , D R A I N C U R R E N T (A M P S )Figure 3. On−Resistance versusGate−To−Source Voltage V GS , GATE−TO−SOURCE VOLTAGE (VOLTS)Figure 4. On-Resistance versus Drain Currentand Gate VoltageI D , DRAIN CURRENT (AMPS)R D S (o R D S (o n ), D R A I N −T O −S O U R C E R E S I S T A N C E (O H M S )Figure 5. On−Resistance Variation withTemperature T J , JUNCTION TEMPERATURE (°C)Figure 6. Drain−To−Source Leakage Currentversus VoltageV DS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)10010I D S S , L E A K A G E (n A )0.011000R D S (o n ), D R A I N −T O −S O U R C E R E S I S T A N C E 10.1(N O R M A L I Z E D )R G , GATE RESISTANCE (OHMS)2040V D S , D R A I N −T O −S O U R C E V O L T A G E (V O L T S )81216C , C A P A C I T A N C E (p F )Figure 9. Resistive Switching Time Variationversus Gate ResistanceDRAIN−TO−SOURCE DIODE CHARACTERISTICS12V SD , SOURCE−TO−DRAIN VOLTAGE (VOLTS)Figure 10. Diode Forward Voltage versus CurrentI S , S O U R C E C U R R E N T (A M P S )534Figure 11. Maximum Rated Forward BiasedSafe Operating AreaV DS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)0.11I D , D R A I N C U R R E N T (A M P S )10010Figure 12. Diode Reverse Recovery WaveformTIMETYPICAL ELECTRICAL CHARACTERISTICSFigure 13. Thermal Responset, TIME (s)R t h j a (t ), E F F E C T I V E T R A N S I E N T T H E R M A L R E S I S T A N C E10.10.01PACKAGE DIMENSIONSSTYLE 11:PIN 1.SOURCE 12.GATE 13.SOURCE 24.GATE 25.DRAIN 26.DRAIN 27.DRAIN 18.DRAIN 1SO−8CASE 751−07ISSUE ABNOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.6.751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.DIM A MIN MAX MIN MAX INCHES 4.80 5.000.1890.197MILLIMETERS B 3.80 4.000.1500.157C 1.35 1.750.0530.069D 0.330.510.0130.020G 1.27 BSC 0.050 BSC H 0.100.250.0040.010J 0.190.250.0070.010K 0.40 1.270.0160.050M 0 8 0 8 N 0.250.500.0100.020S5.806.200.2280.244YM0.25 (0.010)Z SXS____*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*ǒmm inchesǓSCALE 6:1ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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PACKAGING INFORMATIONOrderable Device Status (1)Package Type PackageDrawing Pins Package Qty Eco Plan (2)Lead/Ball FinishMSL Peak Temp (3)Samples(Requires Login)5962-9564001NXD ACTIVE SOIC D82500Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIM5962-9564001NXDR ACTIVE SOIC D82500Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 5962-9564001Q2A ACTIVE LCCC FK201TBD Call TI Call TI5962-9564001QHA ACTIVE CFP U101TBD Call TI Call TI5962-9564001QPA ACTIVE CDIP JG81TBD Call TI Call TI5962-9564002NYDR ACTIVE SOIC D142500Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 5962-9564002Q2A ACTIVE LCCC FK201TBD Call TI Call TI5962-9564002QCA ACTIVE CDIP J141TBD Call TI Call TI5962-9564002QDA ACTIVE CFP W141TBD Call TI Call TI5962-9564003NXD ACTIVE SOIC D82500Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIM5962-9564003NXDR ACTIVE SOIC D82500Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 5962-9564003Q2A ACTIVE LCCC FK201TBD Call TI Call TI5962-9564003QHA ACTIVE CFP U101TBD Call TI Call TI5962-9564003QPA ACTIVE CDIP JG81TBD Call TI Call TI5962-9564004NYDR ACTIVE SOIC D142500Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 5962-9564004Q2A ACTIVE LCCC FK201TBD Call TI Call TI5962-9564004QCA ACTIVE CDIP J141TBD Call TI Call TI5962-9564004QDA ACTIVE CFP W141TBD Call TI Call TI TLC2252AID ACTIVE SOIC D875Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252AIDG4ACTIVE SOIC D875Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252AIDR ACTIVE SOIC D82500Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252AIDRG4ACTIVE SOIC D82500Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAddendum-Page 1Orderable Device Status (1)Package Type PackageDrawing Pins Package Qty Eco Plan (2)Lead/Ball FinishMSL Peak Temp (3)Samples(Requires Login)TLC2252AIP ACTIVE PDIP P850Pb-Free (RoHS)CU NIPDAU N / A for Pkg Type TLC2252AIPE4ACTIVE PDIP P850Pb-Free (RoHS)CU NIPDAU N / A for Pkg Type TLC2252AIPW ACTIVE TSSOP PW8150Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252AIPWG4ACTIVE TSSOP PW8150Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC2252AIPWLE OBSOLETE TSSOP PW8TBD Call TI Call TITLC2252AIPWR ACTIVE TSSOP PW82000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252AIPWRG4ACTIVE TSSOP PW82000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC2252AMFKB ACTIVE LCCC FK201TBD POST-PLATE N / A for Pkg Type TLC2252AMJGB ACTIVE CDIP JG81TBD A42N / A for Pkg Type TLC2252AMUB ACTIVE CFP U101TBD A42N / A for Pkg Type TLC2252AQD ACTIVE SOIC D875Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252AQDG4ACTIVE SOIC D875Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252AQDR ACTIVE SOIC D82500Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252AQDRG4ACTIVE SOIC D82500Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252CD ACTIVE SOIC D875Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252CDG4ACTIVE SOIC D875Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252CDR ACTIVE SOIC D82500Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252CDRG4ACTIVE SOIC D82500Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC2252CP ACTIVE PDIP P850Pb-Free (RoHS)CU NIPDAU N / A for Pkg Type TLC2252CPE4ACTIVE PDIP P850Pb-Free (RoHS)CU NIPDAU N / A for Pkg Type TLC2252CPW ACTIVE TSSOP PW8150Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAddendum-Page 2Orderable Device Status (1)Package Type PackageDrawing Pins Package Qty Eco Plan (2)Lead/Ball FinishMSL Peak Temp (3)Samples(Requires Login)TLC2252CPWG4ACTIVE TSSOP PW8150Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252CPWLE OBSOLETE TSSOP PW8TBD Call TI Call TITLC2252CPWR ACTIVE TSSOP PW82000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252CPWRG4ACTIVE TSSOP PW82000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252ID ACTIVE SOIC D875Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252IDG4ACTIVE SOIC D875Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252IDR ACTIVE SOIC D82500Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252IDRG4ACTIVE SOIC D82500Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC2252IP ACTIVE PDIP P850Pb-Free (RoHS)CU NIPDAU N / A for Pkg Type TLC2252IPE4ACTIVE PDIP P850Pb-Free (RoHS)CU NIPDAU N / A for Pkg Type TLC2252MFKB ACTIVE LCCC FK201TBD POST-PLATE N / A for Pkg Type TLC2252MJGB ACTIVE CDIP JG81TBD A42N / A for Pkg Type TLC2252MUB ACTIVE CFP U101TBD A42N / A for Pkg Type TLC2252QD ACTIVE SOIC D875Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252QDG4ACTIVE SOIC D875Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252QDR ACTIVE SOIC D82500Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2252QDRG4ACTIVE SOIC D82500Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2254AID ACTIVE SOIC D1450Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2254AIDG4ACTIVE SOIC D1450Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMTLC2254AIDR ACTIVE SOIC D142500Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAddendum-Page 3。

主板常用场效应管参数
注：
1、在CPU供电处的MOS管要求功率比较大，而且导通电阻比较小，可以选择09N03、85N03、06N03等功率较大的MOS管；
2、在显卡供电、内存供电处的MOS管要求不是很高，功率不要太低就行，可以采用60N0
3、40N03、603AL等功率较一般（小）的MOS管；对于较高档次（功率较大）的独立显卡，也可选择功率稍大的MOS管，维修时比较放心。

显卡维修时，在未知参数的条件下，一般可直接将可用CPU供电的MOS管代换即可。

3、按理说，用指标高的要好，但指标高的只是一种浪费，够用就行了。

09N03：V DS=25V、I D=50A、P tot=63W（25 °C）06N03：V DS=25V、I D=50A、P tot=83W（25 °C）同时我还顺便下载了04N03的PDF：04N03：V DS=25V、I D=80A、P tot=107W（25°C）我发现N03前面的数字越小，这种管子的功率越高，不知道是不是这样。

听朋友说，在更换MOS管的时候，不同的主板，如果都是775的CPU，那么MOS管是可以互换的，上管之间也可以混用，下管之间也可以混用，以这样的原则来代换MOS管应该没问题吧。