XC7K160T-2FBG676I

XTP385 (v2.0) March 30, 2015OverviewTo ensure business continuity and enable high volume supply chain capabilities for all Virtex®-6 and selected 7 series FPGAs product families, Xilinx is qualifying an additional substrate supplier, Unimicron Technology Corporation (UMTC) for flip chip ball grid area (FCBGA) packages.For Virtex-6 FPGAs, this change affects all standard and specification control document (SCD) XC Commercial (C) and Industrial (I) grade devices. Hi-Rel “XQ” devices are not affected by this PCN.For Artix®-7, Zynq®-7000 All Programmable, Virtex®-7 and Kintex®-7 in the SB, FB, FF, SBG, FBG and FFG packages, this change affects all standard and specification control document (SCD) XC Commercial (C) grade, Extended (E) grade and Industrial (I) grade devices. Virtex-7 in the FL, FLG, FH and FHG packages, and Automotive “XA” devices for 7 series FPGAs are not affected by this PCN. Kintex®-7Q, Virtex®-7Q and Zynq®-7000Q All Programmable Hi-Rel “XQ” FPGAs RF flip chip packages are affected (Refer to XCN14013).This additional supplier will adhere to the same performance, quality and reliability specifications that apply to all product families proven through extensive qualification and testing. As a result, there is no change in form, fit, function, or reliability with this substrate supplier addition.FAQsQ: What is the change?Xilinx is qualifying an additional substrate supplier, Unimicron Technology Corporation (UMTC) for flip chip ball grid area (FCBGA) packages for all Virtex-6 and selected 7 series FPGAs product families. UMTC is a reputablecompany supplying component substrate and system printed circuit board to many semiconductor customers and original equipment make (OEM) customers for over 10 years. Q: Why is Xilinx making this change?This change ensures business continuity and enables high volume supply chain capabilities for Xilinx product families.Q: Why adding Phase 3?As a result of the successful implementation for Xilinx FPGAs (Virtex-6 FPGAs and 7-series), we are expanding this program to include SoC (Zynq-7000 All Programmable) to this change. Q: Which products are affected?For Virtex-6 FPGAs, this change affects all standard and specification control document (SCD) XC Commercial (C) and Industrial (I) grade devices. Hi-Rel “XQ” devices in the FFG1156 package are not affected by this PCN. For Artix-7, Zynq-7000 All Programmable, Virtex-7 and Kintex-7 in the SB, FB, FF, SBG, FBG and FFG packages, this change affects all standard and specification control document (SCD) XC Commercial (C) grade, Extended (E) grade and Industrial (I) grade devices. Virtex-7 in the FL, FLG, FH and FHG packages, and Automotive“XA” devices找FPGA ，上赛灵思半导体（深圳）有限公司FAQ: Transition Schedule for Substrate Supplier for Virtex-6 and 7 Series FPGAs Flip Chip PackagesXTP385 (v2.0) March 30, 2015for 7 series FPGAs are not affected by this PCN. Kintex-7Q, Virtex-7Q and Zynq-7000Q All Programmable Hi-Rel “XQ” FPGAs RF flip chip packages are affected (Refer to XCN14013).Affected device package-pin are listed in the Table 1, Table 2, Table 3, Table 4 and Table 5 below:FAQ: Transition Schedule for Substrate Supplier for Virtex-6 and 7 Series FPGAs Flip Chip PackagesXTP385 (v2.0) March 30, 2015Table 5: Zynq-7000 FPGAs Devices Package Product AffectedNotes:(1)Please refer to Table 6 Phase 1 cross-ship schedule (2)Please refer to Table 7 Phase 2 cross-ship schedule (3)Please refer to Table 8 Phase 3 cross-ship schedule*For inquiries about a specific part number, please contact your customer operations representative or CQE representative for any additional questions.Q: When will this change take effect?This change will take effect in Q1, CY2015. At that time, Xilinx will start cross shipping all Virtex-6 product families and selected 7 series FPGAs product families from UMTC. This will result in initial production device shipments to customers in the timelines indicated in Table 6 and Table 7 and Table 8 below.Table 6: Phase 1 - Virtex-6 and Kintex-7 Devices Qualification Completion and Cross-Ship ScheduleFAQ: Transition Schedule for Substrate Supplier for Virtex-6 and 7 Series FPGAs Flip Chip PackagesXTP385 (v2.0) March 30, 2015FAQ: Transition Schedule for Substrate Supplier for Virtex-6 and 7 Series FPGAs Flip Chip PackagesXTP385 (v2.0) March 30, 2015Revision HistoryThe following table shows the revision history for this document:。

遥控器蕊片对应CPU蕊片康佳遥控器遥控器型号遥控器蕊片对应CPU蕊片适应机型备注KK-Y01 M50462AP M50436-560SPKK-Y02 TC9012F-011KK-Y03 TC9012F-011 T914KK-Y05 SA3010T T2105 T2107 T2111AT2118A T2516KK-Y06 MN6014W ONWA T2106 T2106A T2510T2510B T2510N T2512/A/B/N T2610T2610N/B/A T2806/A T928/N T971N T2910A/N T2916A/NKK-Y07 M50462AP M50436-560SPKK-Y08 M50462AP M50436-560SP T2121KK-Y11 SA3010TKK-Y15 M50462AP M50436-560SP T1826 T5442E T835S T4733ES T2138D/AKK-Y16 MN3004LB1 ST6367 T2138A T2138AⅡ/DT4432ED T4733E3T4934E4 T5142ET5143E T953S T5428E T5435E T5441ET5442E T5445EKK-Y17 SAA3010TKK-Y19 M50462AP M50436-560SPKK-Y25 TC9028A-028KK-Y52 SAA3010T T2111 T2107 T2111A T2118 T2118A T2516KK-Y54 M50462AP M50436-560SP T2121KK-Y55 MN3004LAB1 ST6367 T953S T2138A/DT3731E T4733E3T5428E T5429ET5441E T5442EKK-Y59 SAA3010TKK-Y60 M50560-008P M34300-607SP T2588XKK-Y62 M50560-008P M37210M3-800S T2983 T2986XKK-Y72 GMS30012 T2131G T2135GKK-Y75 M50560-008P M34300-607SP T2518X T2583XKK-Y78 M50560-008P M34300-607SP T2131BKK-Y79 M50560-008P M34300-607SP T2588X2KK-Y84 MN3004LAB1KK-Y85 MN3004LAB1 T2517D T2518D T2519D T2530D1KK-Y86 M50560-008KK-Y93 M3004LAB1 ST6367 T953S 2138A 2138D 3731E 4733E3 5428E5429E 5441E 5442EKK-Y96 M50560-008 T2583 T2991KK-Y97 T3488 T2988P T2998NDKK-Y98 TC9028-021 T2983XKK-Y92 MN3004LAB1 T953SKK-Y100 MN3004LAB1 ST6368 T2977D1KK-Y101 M3004LAB1KK-Y102 M50560-008P T2991KK-Y104 M50560-008P T2983KK-Y107 LC7461-8103KK-Y112 MN3004LAB1 ST6368 T953D T2131D T2132DT2133D/S T2135DT2136D T2139D T2587D T2587D1KK-Y113 M50560-008P T2991H1KK-Y119 M34236N T2988HKK-Y125 TC9012F-011 T2988LKK-Y141 MN3004LAB1 ST6368 T2131D T2135D T2132D T2133D T2136D T2139DT2586D T2587D T2587D1T953D/G F953D T2131G T2132G T2135GKK-Y168 MN3004LAB1 F2139D4/G T2530D2KK-Y173 LC7461-8103 TF953DA F2519D3F2520D3 F2587D3T2137D3KK-Y175 M3004LABKK-Y180 CKP1201M P2989NKK-Y202 CKP1201M F2589CKK-Y211 LC7461 F953A2KK-Y215 PT2461-103 F2530DA F2980AY KK-218 T2988CKK-Y266A F2589CKK-Y168A T2988DKK-Y179 MN3004LAB1 F2139D5KK-Y181 T2991GKK-Y183 F2109EKK-Y225 TC9028-023KK-Y226A F2589CY6014A T918A T920C T653SFKK-Y186 M50560-008P T2131F T2132F T2133FT2135F长虹糸列遥控器遥控器型号遥控器蕊片对应CPU蕊片适用机蕊备注K1A TC9012-011 TMP47C433AN C1462 C1742 C1942CK44A CJKJ53B2 CJKJ56B2 CTV130K1B TC9012-011 TMP47C433AN C1861 C1862 C1863C1941 C2143 C2161C2262 CK56B2K1C TC9012F-011 TMP47C433AN-3849 C2162 C2163 C2263K1D TC9012F-011 TMP47C433AN C1865/Y C2165/YC2168 C2169 C2185K1G TC9012F TMP47C433AN C2164 C2166K1H TC9012F TMP47C433AN C2165P C2165TK1L TC9012F TMP47C433AN C2165F C2166 C2169K1Q TC9012F TMP47C433AN P2119K2A M50462AP M50436-560SP CK49A CK51A CK53AC2141 C2142K2B M50462AP M50436-560SP C2141 C2142K3B SAA3010T R2591A VK3D SAA3010T PCM84C640CH05001 C2115 C2191 C2192C2521 C2588Z C2591C2591A/V/A V/AZ C2593C2592/A V C2991 C2992D2523 D2965K3E SAA3010T PCM84C640 D2961/A D2962/AD2963A D2965AR2918DK3H SAA3010T PCM84C640 D2115A D2116AD2117A D2118AD2192 D2521A D2522AD2523A D2526A C2565C2526AK4A TC9028P-012 TMP47C1238ANCH02002 C2188 C2588 C2588AC2588K C2939KS C2919 C2939KE C2939KV C2988C2988P C3419K4B TC9028P-012 TMP47C1638AU353 C2518 C3418PN C3418PSC3418PS1K4K TC9028P-012 C2588PVK4C TC9028P-012BU2483-13 TMP47C1238AN C2588PV C2589PK4D TC9028P-012 TMP47C1638AU353 C2588P C2589P C2919FC2919P/PB/PK/PN/PS/PVC2920PN C2939AE/KSC2958A C2988P C3418PKC3418PN/PS C3419PNK4N TC9028P-012 C3419PDK4P C2588PKK5B LC7461 M34000N4-628/524P C2151 C2152 C2153K5C LC7461 LC864512V C2151ZK5D LC7461 B2111 B2112 B2113 B2115 B2117K6C LC7461K6C-1 LC7461 A2117 C2119A P2119AC2116 C2119K6D LC7461 A2528BK6E LC7461 A2118K6F LC7461 R2112AE R2113A/AE/FAR2115A/AE R2117AE R2118A/AEK6G LC7461 R2115AE R2116AE/FA C2120FAK6I LC7461 R2518A/AE R2918AEK7A G3898 G3899 G2966/A/BG2966C G2967/A/B/CPE29G88AK7B T2981/A T2982/AK8A TC9012F TMP47C433AN N2516 N2918K8B TC9012F TMP47C433AN C2588D R2516N R2518NR2518PN R2916PNR2918NK8D TC9012F TMP47C433AN 25N18 29N18K9C SAA3010 PCM84C640 R2512DK10B TC9012F TMP47C433AN R2112T R2115T C2126FBC2132FBK11B C2526FD C2938FD C2931FD R2586D C2939FD 29SD83 D2983 D2986 R2586D R2938DY-1 M50560-001P C1842 C1843 C1844 CK51ACJKJ51B1 CK51B/B2Y-3 TC9012F CJKJ53B2 CJKJ56B2K9DK8C TC9028-022K12D PT222-001K12A PT6122-001遥控器蕊片对应CPU蕊片日立遥控器遥控器型号遥控器蕊片对应CPU蕊片适应机型备注CLE-821 UPD1943 CADD-161D CTP-233D 237D 1838 1838D CMT-2085 2083 2083D CEP-3210 323D 327D CR D-451D HFC-238DX 2024CLE-860 CPT1801 2001 2008CLE-862 UPD1943G M50432-551SP 1803 1910 2024 2038 2038D 2103 2110 2125 2403 2403SFCLE-862E D6124A511CLE-865 M50560-123FP 2157SF/DU 同VM101CLE-865A M50560-123FP GMT2138 CPT2150 同VM101CLE-865B 2175 2157SF/DUCLE-866A D6124A 620 2159 2177SF/DC 2408 2518CLE-866B 2700 2908 2918 3300CLE-866C 2901CLE-866E D6124A 679 2918CLE-878 M50560-170FP 2992 21D8C 2159 CMT2195 25D8C 2192CLE-886 D6114A 355 C25M8A 21D8A 25D8A 29M8ACLE-891 M50560-170FP 2992 21D8C 2159 CMT2195 25D8C 2192CLE-893A D6124 2118 2518 21M8CCLE-894 D6124A CSC23CLE-898 50560-170FP 2195CLE-900A D6124A B24CLE-904 D6124ACSC46CLE-907 D6124ACS C47VM101 CPT-1435 1888 2105东芝遥控器CT-9199 198D6C 218D6C 218R8C2 2185 289CT-9200 288X6MCT-9335 219D8MCT-9369 M34300N-587P 219R9CCT-9396 21R92CT-9430 188D6C 198D6C 218D6C 2500XH 2806 289X6N 289X8MCT-9507 2104 9507CT-9599 TC2518KB 2518KTVCT-9631 2929KTPCT-9640 2125 2128CT-9643CT-9687 2940CT-9612 28W3DSH 28W3ME 28W3DXH三洋遥控器RC700 CTP69510 6953 6970华强三洋 CMK2089 2169 2176DK-00 2176DK-01 2179-00 2179-50 2179-60 2181 2189 CME2143C-00 CKP2 161D-00 CTP6951D-00 6069一（代号SN-101）M50462AP(BU5905) 对应CPU: M50436-560SP, 30频道，常用机型熊猫 (YKF-1 YKF-1A/B/C YKF-9 YKF-11) 2120 2138 3615 3615D 36313631A 3631B 3631C 3631D 3631M 3635 3636 3640B 3642 3642B3642A 3651 3653 3658 3659 54L2 54L5 54L2A 54P3 54P1754P10(带交流关机) C51P1M C51P1Z C51P3 C64P1 C64P88北京 541Y 2103C 2104C 8313 8316 8316-2 8343长虹 CK49A 53A 2141 2421上海 Z247-5C 249-1A 249-2A 249-5A 254-5A 254-5A1 651-1A654-2A 654-4A 654-4A1 656-5A海燕 CS54E-3-R CS54E-4-R CS54E-5-R CS54B-3-R CS54B-4-R HC-9012 黄河 HC-47 47-V1 47AVI 4402 4703 4708 4901 5401 5405 5405A 5406 5425 5602 44FS-1 44FS-II 54FS-I 54FS-II韶峰 CAD8903 SFC47-5B SFC54-4长城（画龙） 8148赣新 KQ5106 5186-3 5401 5401A 5406 5409 5416 5426鶯歌金星（J-HYF-3C J-HYF-4B J-HYF-05 J-HYF-06 J-HYF-08 J-HYF-16J-HYF-18 YKF-U18）C491 512 541 542 543 543-1 648 648-1 718 4717 4717A5438 5458 5488 6418飞跃（FY2 FY21 FY22 ）FY4701 5401 6402 6405 6405K 47C2Y2X-1 47C2Y2-6 54EY249C2Y21-1 51C2Y2-2 51C2Y21-2 54C2Y2-1 54C2Y-2 4C2Y21-154C2Y21-2福日（VP202） HFC1425 1725 1824 1824R 1925 2024R 2025 2125凯歌 4C4401 5101 5104 5401 5401-1 5404 5405孔雀（KQ-YKF-1 KQ-YKF-3 KQ-YKF-6 KQ-YKF-8 KQ-YKF-9）KQ44-38-1 47-39-5 49-39-1 51-38-4 51-39-5 51-39-7 54-38 54-38-1 54-39 54-39-2 54-39-5 54-39-5A 54-39-6 54-39-8A 64-39 1988 2150 2188D 2188G环宇 47C-2R 51C-4R 54C-2R 54C-2RA牡丹 47C10 49C1 51C1 51C5 51C5A 54C3 54C3A 54C4 54C4A宝声 21388 21389 21688 21688A 21689 21689A 25588 25689西湖（YKF-4L YKF-4P YKF-10）51CD5A 51CD5C 54CD6 54CD8A 63CD1A 6403成都 C47-851F 47-851FA 47-851K 51-851K 53-871 54-871 56-871A美乐 DS44C-1 47C-3 47C-3A1 51C-3 51CD5 51CD5A 53C-2 54C-254CD6 1808 2108 2188B 4F3A2B1虹美（YKF-3B YKF-4C） 4774 5155 6403乐华（YKF-3）TC541-2PD 511-3PD（R）III三元 44SYC-3 54SYC-3青岛 SR5417 4426 长风 CFC54-3FR 54-3FR1 54-7FR泰山 TS54C10 44C13 红岩 SC-543彩虹 CAD8903 3909 8913 春笋 CSD541黄山 AH5353C AH5353R 南声 ZY-5401如意 SGC-4403 5403A 5403C 菊花 FS531A FS531B金凤 C51SY C54SZ C54SZ1 天鹅 CS47-C3 54-S1沈阳 SDSY51-2 54-2 山茶 SC-L54EY1金鹊 53DC1 53DC13 华利 5140 5410日电 NEC5260PDH 5460PDH 5488PDH 飞鹿 54C2 54C3赛格 5140PDH 5410PDH 长飞附注：1，M50462AP遥控器模拟量的调节方式有两种：其一是模拟量分开单独调节，此类使用较多，如长虹熊猫北京等；其二是菜单调节方式，如康佳等；注意区别选用2，少量机型多几种功能，如孔雀KQ54-39-6带交流关机，KQ64-39带立体声二（SN-101A）M50462AP 对应CPU：M50436-560SP 或 CPU：Z86227系统 30频道，30键，模拟量菜单调节方式康佳（KK-Y01 KK-Y07 KK-Y08 KK-Y19）KK-T920D 920DI 953P 953PI 953PIII 953PII 953II 953III 953B1826 1926 2109 2110 2126 2128 2188 5402优拉纳斯 U49-39-1B U54-39-5B三（SN-102） 3010T CTV222，CTV320S，CTV322系统，对应CPU：PCA84C440/444/504/640/641，90频道，32键，常用机型，熊猫（YKF-5 YKF-15）C54P5 C54P6 C54P37 C64P2 C64P4 C74P2 C74P2M北京2162C 28” 8346-1菲利蒲（RC7802）4703F 21A9 21B9 25”虹美（YKF-1A） 4703 5109 5306 5445 5456 5456C飞跃（FY3 FY31） 44C3Y3-1 47C3-3 51C3-1 51C3F 51C3Y-2 51C3F3-2FY4702 5402凯歌 4C3705 4705-2 5105 5405 5405-3 5405-4 6405牡丹 44C1 CT-54G1D-G 54G1P-G 54G1P1-C乐华 TC374-2PD 542A-2PD（R） 542A-2PD/I（R） 542A-1R CP4928W 5428W5438W孔雀 KQ-54-38-2 2188 2188A 2529 2588 2588A 7188 7188A 7188B如意 SGC-4703 4703F 5303 5403 5403C 5403F上海 Z654-19A 664-1A 664-2A 664-3A 671-1A 671-1A1 671-1B 674-1A674-2A 674-2A1 674-D创维 CTV-8298WF TC-2140 莺歌 Y5412 C71-1海燕 CS47E-6B-R 金星 498 498-1 5128美乐 2508 西湖 54CD7 54CD9 54CD10黄河 HF51-V 长城画龙 G8153YF G8253YN环宇 47C-3 54C-3RA 黄山 5481C 5481R三元 54SYC-4B 菊花 FS531 531A 531B赣新 5418 百合花 CD47-6 49-6优拉纳斯 U2529 永固 C2108 C2118 C2189BP金塔 JW-D542 康立 CE5306梦寐 M9081D四（SN102B） SAA3010T CTV222S，CTV320S，CTV322系统，对应CPU：PCA84C440/444/504/640/641，90频道，29键，模拟量菜单方式调节长虹 C2115 C2191 C2521 C2588Z C2591 C2591A C2591V C2591AVC2591AZ C2592 C2592AV C2593 C2991 C2992康佳（KK-Y05 KK-Y17 KK-Y52）KK-T963A T963AIII T2101 T2103 T2104 T2105 T9121 T9421福日（VP101） HCF1475 1775 1975 2076 2101 2104 2111A 21132176王牌 TCL9321 9325 9329 9421五（SN130） TC9012F-011 东芝CTS-130A遥控系统对应CPU：TMP47C432/433/434AN，32频道，24键，常用机型东芝 51XC1 5103 2120HC 2120RCV 219D5C 510 541DRK长虹 CJK53B 53B2 53B2A 1861 1742 2161 2162 2163 2165 2168康佳（KK-Y02） KK-T920CII 920CIII 953H 953FSII 953FSIII 2808熊猫（YKF-3 YKF-3A YKF-12 YKF-13 YKF-18 REC2 YKF-27 YKF-28）3615B 3615C 3632 3636C 3640 3643 14C3 37P4 44P3 44P547P1 49P2 54L3 54P8 54P12 54P45 54S1 74C3北京 8320-3 8320IN佳丽彩 EC2103 2113R 2113AR-L889B 2123 2133 2188 2213AR快乐 HC2103R-L885 2104R 2104R（III） 2104R（II） 2136A 2138N海燕 CS47-6D-R 51-7A-R 51-7B-R 51-7C-R 51BR-A 54-6-R 56B-3-R56E-3-R虹美（YKF-4/A） 2482 4460 5409 5459 5482 5488福日 HFC1775 1957 1975 1976 2075 2175上海 Z651-6A 651-6A1 651-7A 654-6A 654-6A1 654-6A2 654-9A 654-12A 654-12B 牡丹 49C3C 49C5 54C9 54C10 54C10A 54C18 54C20 64C6黄山 AH2168C AH2168R AH5462I AH2588C AH2588R飞燕 E2013 2103 2113 DUC51-C2 DUC54-C1金星 C548 5418 5428 5423 高路华 2158星海 47CJ3Y 53CJ2Y 54CJ4Y 襄阳 51XC1 54XC1长城 JTC-532 G8363YN1 三键 MC-T953FSIII华日 C47J-3 C54J-1 C54J-2 C54J-3 春风 C54-1红岩 SC-511 531 金鹊 53EC1Y 53DC1B菊花 FS532A 长风 CFC47-3三洋 21-D7FF 6955 龙江 C54G-2厦华 XT5104 南宝 NC54-AR昆仑 S541-6A 日电（NEC） TC2023CX百花 EC2103R 美乐 M2188C DC51C-2 DC53C-1西湖 44CD2A 4709 5412 南声 ZT-T920CII东宝 C541DRK（A） 541DK 888牌 ND531A青岛 SR4715 宝石花 EC2103R神彩 SG-7101 皇冠 CT-9038C六（SN103A） TC9012F-011之二，对应CPU：TMP47C432/433/434AN等32频道，30键，综合多功能金星C548 C5418 C5423 C5428熊猫 C54P4A C54P8A 54P8C 54P41 C64P8孔雀（KQ-YKF-2） KQ54-39-1 56-39虹美 2482 4460 5409 5459 5482 5488黄山 2168C 2168R 2588C 2588R 5462华强 HQ-9154 长城 G8363YN1序号遥控器蕊片对应CPU蕊片适用机型频道数目1 M50462AP M50436-560SP 康隹长虹熊猫金星 302 SAA3010T PCA84C640/641 梦寐三森华亿 903 TC9012F011 TMP47C433AN 佳丽海燕北京金星牡丹 324 TC9012F011 TMP47C834AN 厦华 605 TC9012F011 TMP47C432N-8094 厦华 146 M50560-001SP M50431-101SP 莺歌长虹佳丽 307 M50560-001SP M34300N4-012 厦华牡丹 448 M50560-001SP M50436-600SP 三星 209 M708LB1 M491B1 金星孔雀成都 1610 M708LB1 M494 环宇韶峰上海 2011 MN6014A MN15245KWC 康隹金星黄山 3212 MN6014W MN15287KWEC 康隹长城安华 3213 UPD1986C UPD1937C 厦华虹美 1214 TC9148P TC9150P 康艺莺歌泰山 1215 LC7461-8103 LC864012L-5463 上海虹美环宇 4016 LC7461-8103 LC864012L-5D48 环宇永宝 10017 LC7462 M34300N4-628(721) 华强三洋高路华 3218 LC7462 MN15245SAY 牡丹韶峰昆仑 2819 M50560-003P M37102M8-ABDSP 佳丽25” 4420 M50560-003P M34300N4-500/501 佳丽21” 3021 M50560-003P M37210M3-508SP 熊猫 5022 M50560-003P 600105 熊猫 50彩电遥控器与机型对照表日立牌彩电遥控器对照表遥控型号芯片电视机型号VM101 M50560-123 CPT-1435, 1888 , 2105 /11 , 2137 /38/39 , 2112/50 CLE-860 UPD1943G CPT-1801 , 2001 , 2008 CLE-861 UPD1943G CEP323D,233D CLE-862 UPD1943G CPT1803 , 1901 , 2024/38/D , 2103 /10/25 , 2403 /SF CLE-865A/B UPD1943G CPT2157SF/DU , CMT2138 , CPT2150 CLE-866A UPD6142CA-620 CMT2518/19 ,2177SF/DC ,2408 CLE-866B CMT2700 , 2908 , 2918 , 3300 CLE-866C 2901 CLE-866E D6124CA670 2918 CLE-878 CMT2155 CLE886 M50560-170FP H-21D8A,25D8A,CMT2588 CLE-891 M50560-170FP H-21D8C,2159 , CMT2195 CLE-893A 25M8C CLE-898 H2195 CLE-900A D6124A索尼彩电遥控器对照表遥控型号芯片电视机型号RM-626A M50119 KV1432CH,1882CH , 2062CH RM-656A M50431-531 KV2181DC , 2182D , 2182DC , 2184D RM-677 KV2553 RM-681 RM-687 PCA84C640P/016 KV2184TC , 2510C RM-827S KV1485, 2185 , 2565/85/86 ,2593V1A , 2825 KV2965 , 2966 , F25MF1 RM-845P KV-29 RM-849S KV2189 , 2189TC RM-857S F29 , K29 RM-857A KV2184MTJ RM-870 34寸RM-643 KV2090 , 2092 RM-821 RM-J124A东芝牌彩电遥控器对照表遥控型号芯片电视机型号CT-9199 T-198D6C , 218D6C , 218R8C, 2185 , 289 CT-9200 T-288X6M2 CT-9335 T-329D8M CT-9369 T-219R9C CT-9396 T-21R9D CT-9340 T-188D6C , 198D6C ,21D6C , 2500XH , 2806 , 289X6N/8M CT-9507 T-2104 CT-9599 TC2518KB , 2518KTV CT-9619 T-2929KTV CT-9632 T-2929KTP CT-9640 T-2125 , 2128KTV CT-9684 T-1438XS CT-9687 T-2540XH,2840XH, 2940 CT-9712 T-28W3DSH , 28W3ME ,28W3DXH CT-9730 T-2938,2738DH CT-9734 T-2939XP,2988 CT-9760 T-2540XP,2840 CT-9777 T-2979UH CT-9778 T-28DW4UC CT-9782 T-2150XH CT-9787 T-2552XHC CT-9801 T-2979 CT-9818 T-2550XP CT-9828 T-28DW5UC CT-9840 T-2150XHC,2540 CT-9842 T-2950XHC CT-9843 T-2950XP CT-9844 T-2980XP CT-9851 T-2918KTV CT-9879 T-2560XHC 三洋牌彩电遥控器对照表遥控型号芯片电视机型号LC7462 LC7462 CMK2089,2169,2176DK,21,2181, 2189 CME2143C,CKP2161D, CTP6951,6099 JXV A UPD6124 SY-21” JXVP UPD6124 SY-25” RC700 UPD6124 SY-29”( CTP69510 , 6953 , 6970) RC700A UPD6010J HQ9012-011 TC9012-011 HPC2198 夏普电视机遥控系列遥控型号芯片电视机型号G0676CESA IX0773CE CV2100,2102,2106V1A,2108V1A,2122/DK,2162CK CV5405,21S11-A1/A2,21S21-A1 G0756CESA CV21N52,5407 G0771CESA LR314M CV2121/DK/CK,5407CK/CK1,1850CK,(虹美C-5403) G0392CESA M58484 CV2002GS,1836CK,2020CK,1835CK/DK,1885 M58484 DV5406/SPN/SPM G1077PESA CV14D-CM G1069PESA CV2500, 天鹅FS4L G1634SA SC73C020-002 飞利浦牌电视机遥控系列遥控型号芯片电视机型号RC7802S SAA3010 PH21A9, 21B9 RC7812 PCA84C122 PH21D9 , 25B9 , 29B9 , 21D8 RC-7952 PH21V8 , 25V7 RC7953 PH21V9 , 25V8 RC7954 PH29V8 RC7959 PH29V9,29H9 RC0772 PCA8521 PH-21V7,21B8,25A6,29A6,25B8,29B8 RC283501 M34280 21K PH25A6 , 29A6 , 21V7 , 21B8 JVC电视机遥控系列遥控型号芯片电视机型号RM300 50142 RM457 D6600 RM548 D6600 RM549 D6600 RM565 D6600 RM470 D6600 RM601 带录像功能其他彩电遥控器对照彩电牌子遥控型号芯片电视机型号嘉华(KA WA) JH-5 GMS30112 JH-25C1H,29C1H 创维2213 CW-29VS8800 创维9028 CW-2199A创维6C30 CW-25NX9000 创维CW-CH2213 2213 CW-29-NL90000(健康幻影) 春兰CL-7461W LC7461 CL-2108 金利普M50462 M50462 JLP-CD2538 长松RM-B通用9012 CS03 海尔26C SY400 红灯LC7461-8103 HD-2599 康力RS02 LC7461-8013 KL5415 YINGHONG M50462 Y2168 AMCOL SAA3010T 2168P 东宝MTR03 EUR50138 TC-2510B 乐华TC9028-023 RD21T 松下电视遥控器遥控型号芯片彩电型号TNQ2645 M50560-200P TC-2185 /86, 1870 /71 /72/73, 2070 /90 ,2163,2171/73,D21C,D25C TNQ10408 XRU2464-02 TC2110/40/50/60/98,2148/58R,1410,2550R/RZ,2177/87R,2188,2552G TNQ2678 M50560-117P TC2163/87, 2636 /78/87 , A V29C 3RQ UPD6124 TC25V30X/H,29V30H/X/XE,33V30H/X/XE TNQ10438 TC25V40R,25GF10R,29GF10R TNQ10449 TC29GF12G,29GF18G TNQE096 TC28WG100G,32WG100G TNQE098 TC29GF95G/H TNQE100 TC29GF92G EUR501105 TX29GF15R,32WG15G/R EUR501325 MX-3C TC2550R,2552 EUR511021 TC29GF85G,33GF85G EUR511023 TC29GF80R,29GF82G EUR50700 TC26V2H,29V2H EUR50701 TC29V1R EUR50707 TC33V30H,33V32H,25V30R EUR50708 TC29V30H,29V32H EUR51914 TC29GF30R,29GF32G,29GF35G EUR51918 TC28WG25G,32WG25G,32WG25H EUR51974 TC29GF72G EUR51975 TC29GF70R 小画王BU5814FTI CT-25V30R/X 25V33H 29V30H/X/XE/H/X 飞跃电视遥控器系列遥控型号芯片电视机型号FY-1 TC9012-011 FY-2/21/22 M50462AP FY-4C4701,5401 ,6402,6405K ,47CY2X-1, 54EY2 47C2Y2-6 , 49C2Y21-1, 51C2Y2-2 , 54C2Y-2 51C2Y21-2 , 54C2Y2-1/2 , 4C2Y21-1 , 54C2Y21-2 FY3，FY13 SAA3010 FY-44C3Y3-1 ,47C3-3 , 51C3-1 , 51C3F ,51C3-2 FY-51C3F3-2 , FY4702 , FY5402 FY-41 M3004 FY-4C4704 (同康佳Y-55) FY-51 LC7462 FY4707, 5101, 5428 , 5418 FY-71 M708-494 FY-51C2Y-1, 51C2Y-3 , 54C2Y-2 M708-491 M708-491 FY-47C2Y-3 M50560-001 M50560-001 FY-54CY4-3,5402 M50560-003 M50560-003 FY-6418 105-198D BU5777 FY6403 , 7401 , 7458 孔雀彩电遥控器对照遥控型号芯片电视机型号KQ-YKF-1 M50462APKQ-44-38-1,47-39-5,49-39/1,51-38-4,51-39-5/7,54-38/1 KQ-54-39,54-39-5 KQ-YKF-2 TC9012-011 KQ-54-39-1,56-39 16频道KQ-YKF-3 M50462AP KQ-54-39-2,54-39-5A KQ-YKF-4 M3006 KQ-3788,U3788 KQ-YKF-5 M50560-001 KQ5488 KQ-YKF-5B KQ-49-39-1B,54-39-5B KQ-YKF-6 M50462AP KQ-54-39-6 (AC OFF) KQ-YKF-7 M50462AP KQ-64-39 带立体声KQ-YKF-8 M50462AP KQ-54-39-8A,1988,2188D/G KQ-YKF-9 M50462AP KQ-2150D RMC-1 M708L-494 KQ-47-39-3 (同RM393) RMC-2 M50119 KQ-1882/CH,47-39-4,51-39-4 (同索尼RM626) RM-381 M708L-494 KQ-37-38-1,44-38 24键RM383 M708L-491 KQ-37-38-2,51-38-3 27键SAA3010 SAA3010 KQ-2188/A,2588/A,7188/A/A多模拟量选择M50560-003 M50560-003 KQ-2588KS1,2188B,5D4/A KQ-0313/60 KQ-2197 KQ-9012-011 MP434-3417 KQ-2550G,2950G,2EB 上海牌彩电遥控器对照遥控型号芯片电视机型号SH-M50462 M50462 Z247-5C,Z249-1A/7A/5A,Z254-5A/5A1,Z654-1A, Z654-2A/4A/4A1,Z656-5A SH-SAA3010 SAA3010 Z654-19A,Z674/1A,Z664-1A/2A/3A,Z671-1A/1A1,Z674-2A/2A2 SH-TC9012 TC9012-011 Z651-6A/6A1/7A,Z654-6A/6A2/9A/12A/12B SH-M50560-001 M50560-001 Z637-3A,644-2A/4A,Z647-4A/8A,Z664-4A,Z651-9A/9B Z654-6A/8A/8B/8F/8H SHM50560-001 M50431-101 Z651-2A SH-M708-494 M708-494 Z243-1A/1A1,Z247-5B/5B1,Z251-2A/3A SH-MN6014W MN6014W Z664-5A2,Z647-8A SH-TC9148 TC9148 SH-651-1A SH-LC7461 86P4012L-5711 SH-651-9B2,Z654-8H2 SH-LC7461 Z654-8B1/8H1 SH-LC7462 LC7462 Z654-14A SH-SAA1250 SAA1250 Z247-8A SH-M50142 M50412 Z647-2A,656-2A SH-M50460-001 M50460-001 Z651-2A福日彩电遥控器代码对照表遥控型号芯片电视机型号VM101 M50560-123 FR1814R , 2014R , 2111 , RGB3701 VM201 M50462AP FR1824R , 2024R , 2122 VM222 M50462AP FR1425 , 1725 , 2025 , 2125 VM231 FR2998 VM301 M50560-170FP FR2168 , 2169 , 2188 VM321 M50560-170FP FR2582 , 2591 VP101 SAA3010 FR1975 , 2175 , 2176 VP112 FR2174 VP121 SAA3010 FR2173 VP151 FR2179 VP 153 PCA84C122A T/093 FR2178 VS141 M3004LB1 FR2108, 2109 P6P1 SAA3010 FR21P60 , 21P61 , 21P63 , 21P66 FN111/112 D6124A FR29816 ,29910,2552 FN113 SAA1250 FR2553,HFC2122 FN211 FR2998。

Chapter2 Power Distribution SystemChapter 2:Power Distribution SystemTable 2-2 lists the PCB decoupling capacitor guidelines per V CC supply rail for Artix-7devices.CSGA324XC7S5001351111123124FTGB196XC7S5001351111113124FGGA484XC7S5001351111124124FGGA484XC7S7501471111137124FGGA676XC7S7501471111137124FGGA484XC7S10001581111137124FGGA676XC7S1001581111137124Notes:1.PCB capacitor specifications are listed in Table 2-5.2.Total includes all capacitors for all supplies. The values in this table account for the number of I/O banks in the device.3.One 47µF (or 100µF) capacitor is required for up to four V CCO banks when powered by the same voltage.4.Decoupling capacitors cover down to approximately 100KHz.PackageDeviceV CCINTV CCBRAMV CCAUXV CCO (per Bank)330µF 100µF 4.7µF 0.47µF 100µF 47µF 4.7µF 0.47µF 47µF 4.7µF 0.47µF47µF or100µF (3)4.7µF 0.47µFTable 2-2:Required PCB Capacitor Quantities per Device: Artix-7Devices (1)(2)PackageDeviceV CCINTV CCBRAM V CCAUXV CCO Bank 0V CCO all other Banks(per Bank)680µF 330µF 100µF 47µF 4.7µF 0.47µF 100µF 47µF 4.7µF 0.47µF 47µF 4.7µF 0.47µF 47µF47µF or100µF (3)4.7µF 0.47µFCPG238XC7A12T 00101201011121124CSG325XC7A12T 00101201011121124CPG236XC7A15TXA7A15T 0122111121124CPG238XC7A25T 00102301011121124CSG325XC7A25T 00102301011121124CPG236XC7A35T XA7A35T 0123111121124CPG236XC7A50T XA7A50T 01003510011121124FTG256XC7A15T 00102201011231124FTG256XC7A35T 00102301011231124FTG256XC7A50T 01003510011231124FTG256XC7A75T 01004610021231124FTG256XC7A100T 01006810021231124CSG324XC7A15T XA7A15T 0122111241124CSG324XC7A35T XA7A35T 00102301011241124CSG324XC7A50T XA7A50T01003510011241124FFG1930RF1930XC7VX980T XQ7VX980T 600110201010011FLG1930XC7VX1140T 600100211010011FLG1155XC7VH580T 300100111010011FLG1931XC7VH580T 300100111010011FLG1932XC7VH870T511161111Notes:1.PCB Capacitor specifications are listed in Table 2-5.2.Total includes all capacitors for all supplies, except for the MGT supplies MGTAVCC, MGTVCCAUX, and MGTAVTT, which are covered in UG476, 7 SeriesFPGAs GTX/GTH Transceivers User Guide . The values in this table account for the number of I/O banks in the device.3.See UG471, 7 Series FPGAs SelectIO Resources User Guide for a description of the VCCAUX_IO rail specification to see which I/O banks are grouped together ineach VCCAUX_IO group. See UG475, 7 Series FPGAs Packaging and Pinout Product Specification to see which I/O banks are grouped together in each VCCAUX_IO group.4.One 47µF (or 100µF) capacitor is required for up to four V CCO banks when powered by the same voltage.5.Decoupling capacitors cover down to approximately 100KHz.PackageDeviceV CCINT V CCBRAM V CCAUXV CCAUX_IO per Group (3)V CCO Bank 0V CCO all otherBanks (per Bank)680µF330µF 4.7µF 660µF 330µF 100µF 4.7µF 47µF 4.7µF 100µF 47µF 4.7µF 47µF 47µF or 100µF (4)Chapter 2:Power Distribution SystemTable 2-6 lists the capacitors present in the packages for Kintex-7devices.0.47µFC >0.47µF 06032-Terminal Ceramic X7R or X5R0.5nH1m Ω<ESR <20m Ω6.3VGRM188R70J474KA01Notes:1.Values can be larger than specified.2.Body size can be smaller than specified.3.ESR must be within the specified range.4.Voltage rating can be higher than specified.Table 2-5:PCB Capacitor Specifications (Continued)Ideal Value Value Range (1)Body Size (2)Type ESL Maximum ESR Range (3)Voltage Rating (4)Suggested Part Number Table 2-6:Package Capacitor Quantities per Device: Kintex-7Devices (1)Package DeviceV CCINT V CCAUX V CCAUX_IO per Group (2)V CCO per Bank (3)2.2μF 2.2μF 1.0μF 0.47μF FBG484FBV484XC7K70T 21N/A 1FBG484FBV484XC7K160T 21N/A 1FBG676FBV676XC7K70T 21N/A 1FBG676FBV676XC7K160T 21N/A 1FBG676FBV676XC7K325T 2111FBG676FBV676XC7K410T 2111FBG900FBV900XC7K325T 2111FBG900FBV900XC7K410T 2111FFG676FFV676XC7K160T XA7K160T 4211FFG676FFV676RF676XC7K325T XQ7K325T 4211FFG676FFV676RF676XC7K410T XQ7K410T4211。

General Description7series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7series FPGAs include:•Spartan®-7 Family: Optimized for low cost, lowest power, and high I/O performance. Available in low-cost, very small form-factorpackaging for smallest PCB footprint.•Artix®-7 Family: Optimized for low power applications requiring serial transceivers and high DSP and logic throughput. Provides the lowest total bill of materials cost for high-throughput, cost-sensitiveapplications.•Kintex®-7 Family: Optimized for best price-performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs.•Virtex®-7 Family: Optimized for highest system performance and capacity with a 2X improvement in system performance. Highestcapability devices enabled by stacked silicon interconnect (SSI)technology.Built on a state-of-the-art, high-performance, low-power (HPL), 28nm, high-k metal gate (HKMG) process technology, 7series FPGAs enable an unparalleled increase in system performance with 2.9Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.Summary of 7Series FPGA Features•Advanced high-performance FPGA logic based on real 6-input look-up table (LUT) technology configurable as distributed memory.•36Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.•High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.•High-speed serial connectivity with built-in multi-gigabit transceivers from 600Mb/s to max. rates of 6.6Gb/s up to 28.05Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.• A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors.•DSP slices with 25x18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetriccoefficient filtering.•Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter.•Quickly deploy embedded processing with MicroBlaze™ processor.•Integrated block for PCI Express® (PCIe), for up to x8 Gen3 Endpoint and Root Port designs.•Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.•Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flip-chip packaging offering easy migration between family members in the same package. All packages available in Pb-free and selected packages in Pb option.•Designed for high performance and lowest power with 28nm, HKMG, HPL process, 1.0V core voltage process technology and0.9V core voltage option for even lower power.7Series FPGAs Data Sheet: Overview DS180 (v2.6) February 27, 2018Product SpecificationTable 1:7Series Families ComparisonMax. Capability Spartan-7Artix-7Kintex-7Virtex-7Logic Cells102K215K478K1,955KBlock RAM(1) 4.2Mb13Mb34Mb68MbDSP Slices 1607401,9203,600DSP Performance(2)176 GMAC/s929GMAC/s2,845GMAC/s5,335GMAC/s MicroBlaze CPU(3)260 DMIPs303 DMIPs438 DMIPs441 DMIPs Transceivers–163296Transceiver Speed– 6.6Gb/s12.5Gb/s28.05Gb/sSerial Bandwidth–211Gb/s800Gb/s2,784Gb/sPCIe Interface–x4 Gen2x8 Gen2x8 Gen3Memory Interface800Mb/s1,066Mb/s1,866Mb/s1,866Mb/sI/O Pins400500500 1,200I/O Voltage 1.2V–3.3V 1.2V–3.3V 1.2V–3.3V 1.2V–3.3VPackage Options Low-Cost, Wire-Bond Low-Cost, Wire-Bond,Bare-Die Flip-Chip Bare-Die Flip-Chip and High-Performance Flip-ChipHighest PerformanceFlip-ChipNotes:1.Additional memory available in the form of distributed RAM.2.Peak DSP performance numbers are based on symmetrical filter implementation.3.Peak MicroBlaze CPU performance numbers based on microcontroller preset.赛灵思半导体（深圳）质量等级领域:宇航级IC、特军级IC、超军级IC、普军级IC、禁运IC、工业级IC，军级二三极管，功率管等;应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通信网络、电力工业以及大型工业设备祝您:工作顺利，生活愉快!以赛灵思半导体（深圳）有限公司提供的参数为例，以下为XC7K325T-1FBG676I的详细参数，仅供参考Spartan-7 FPGA Feature Summary Table 2:Spartan-7 FPGA Feature Summary by DeviceDevice LogicCellsCLBDSPSlices(2)Block RAM Blocks(3)CMTs(4)PCIe GT XADCBlocksTotal I/OBanks(5)Max UserI/O Slices(1)MaxDistributedRAM (Kb)18Kb36Kb Max(Kb)XC7S66,000938701010518020002100 XC7S1512,8002,00015020201036020002100 XC7S2523,3603,6503138090451,62030013150 XC7S5052,1608,150600120150752,70050015250 XC7S7576,80012,000832140180903,24080018400 XC7S100102,40016,0001,1001602401204,32080018400 Notes:1.Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.2.Each DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.3.Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.4.Each CMT contains one MMCM and one PLL.5.Does not include configuration Bank 0.Table 3:Spartan-7 FPGA Device-Package Combinations and Maximum I/OsPackage CPGA196CSGA225CSGA324FTGB196FGGA484FGGA676Size (mm)8 x 813 x 1315 x 1515 x 1523 x 2327 x 27Ball Pitch(mm)0.50.80.8 1.0 1.0 1.0 Device HR I/O(1)HR I/O(1)HR I/O(1)HR I/O(1)HR I/O(1)HR I/O(1)XC7S6100100100XC7S151********XC7S25150150100XC7S50210100250XC7S75338400XC7S100338400Notes:1.HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V.Device LogicCells Configurable Logic Blocks(CLBs)DSP48E1Slices(2)Block RAM Blocks(3)CMTs(4)PCIe(5)GTPsXADCBlocksTotal I/OBanks(6)Max UserI/O(7) Slices(1)MaxDistributedRAM (Kb)18Kb36Kb Max(Kb)XC7A12T12,8002,00017140402072031213150 XC7A15T16,6402,60020045502590051415250 XC7A25T23,3603,6503138090451,62031413150 XC7A35T33,2805,20040090100501,80051415250 XC7A50T52,1608,150600120150752,70051415250 XC7A75T75,52011,8008921802101053,78061816300 XC7A100T101,44015,8501,1882402701354,86061816300 XC7A200T215,36033,6502,88874073036513,14010116110500 Notes:1.Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.2.Each DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.3.Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.4.Each CMT contains one MMCM and one PLL.5.Artix-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2.6.Does not include configuration Bank 0.7.This number does not include GTP transceivers.Table 5:Artix-7 FPGA Device-Package Combinations and Maximum I/OsPackage(1)CPG236CPG238CSG324CSG325FTG256SBG484FGG484(2)FBG484(2)FGG676(3)FBG676(3)FFG1156 Size (mm)10 x 1010 x 1015 x 1515 x 1517 x 1719 x 1923 x 2323 x 2327 x 2727 x 2735 x 35 Ball Pitch(mm)0.50.50.80.8 1.00.8 1.0 1.0 1.0 1.0 1.0Device GTP(4)I/OGTP(4)I/OGTP(4)I/OGTP(4)I/OGTP(4)I/OGTPI/OGTP(4)I/OGTPI/OGTP(4)I/OGTPI/OGTPI/O HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)XC7A12T21122150XC7A15T21060210415001704250XC7A25T21124150XC7A35T21060210415001704250XC7A50T21060210415001704250XC7A75T0210017042858300XC7A100T0210017042858300XC7A200T42854285840016500 Notes:1.All packages listed are Pb-free (SBG, FBG, FFG with exemption 15). Some packages are available in Pb option.2.Devices in FGG484 and FBG484 are footprint compatible.3.Devices in FGG676 and FBG676 are footprint compatible.4.GTP transceivers in CP, CS, FT, and FG packages support data rates up to 6.25Gb/s.5.HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V.Device LogicCellsConfigurable LogicBlocks (CLBs)DSPSlices(2)Block RAM Blocks(3)CMTs(4)PCIe(5)GTXs XADCBlocksTotal I/OBanks(6)MaxUserI/O(7) Slices(1)MaxDistributedRAM (Kb)18Kb36Kb Max (Kb)XC7K70T65,60010,2508382402701354,86061816300 XC7K160T162,24025,3502,18860065032511,70081818400 XC7K325T326,08050,9504,00084089044516,02010116110500 XC7K355T356,16055,6505,0881,4401,43071525,740612416300 XC7K410T406,72063,5505,6631,5401,59079528,62010116110500 XC7K420T416,96065,1505,9381,6801,67083530,060813218400 XC7K480T477,76074,6506,7881,9201,91095534,380813218400 Notes:1.Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.2.Each DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.3.Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18 Kb blocks.4.Each CMT contains one MMCM and one PLL.5.Kintex-7 FPGA Interface Blocks for PCI Express support up to x8 Gen 2.6.Does not include configuration Bank 0.7.This number does not include GTX transceivers.Table 7:Kintex-7 FPGA Device-Package Combinations and Maximum I/OsPackage(1)FBG484 FBG676(2)FFG676(2) FBG900(3)FFG900(3)FFG901FFG1156 Size (mm)23 x 2327 x 2727 x 2731 x 3131 x 3131 x 3135 x 35 Ball Pitch(mm) 1.0 1.0 1.0 1.0 1.0 1.0 1.0Device GTX(4)I/O GTX(4)I/OGTXI/O GTX(4)I/OGTXI/OGTXI/OGTXI/OHR(5)HP(6)HR(5)HP(6)HR(5)HP(6)HR(5)HP(6)HR(5)HP(6)HR(5)HP(6)HR(5)HP(6)XC7K70T41851008200100XC7K160T418510082501508250150XC7K325T825015082501501635015016350150XC7K355T243000XC7K410T825015082501501635015016350150XC7K420T283800324000 XC7K480T283800324000 Notes:1.All packages listed are Pb-free (FBG, FFG with exemption 15). Some packages are available in Pb option.2.Devices in FBG676and FFG676are footprint compatible.3.Devices in FBG900and FFG900 are footprint compatible.4.GTX transceivers in FB packages support the following maximum data rates: 10.3Gb/s in FBG484; 6.6Gb/s in FBG676 and FBG900. Refer to Kintex-7 FPGAs Data Sheet:DC and AC Switching Characteristics (DS182) for details.5.HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V.6.HP = High-performance I/O with support for I/O voltage from 1.2V to 1.8V.Table 8:Virtex-7 FPGA Feature SummaryDevice(1)LogicCellsConfigurable LogicBlocks (CLBs)DSPSlices(3)Block RAM Blocks(4)CMTs(5)PCIe(6)GTX GTH GTZXADCBlocksTotal I/OBanks(7)MaxUserI/O(8)SLRs(9) Slices(2)MaxDistributedRAM (Kb)18Kb36Kb Max(Kb)XC7V585T582,72091,0506,9381,260 1,590795 28,6201833600117850N/A XC7V2000T1,954,560305,40021,5502,160 2,5841,29246,51224436001241,2004XC7VX330T326,40051,0004,3881,1201,50075027,0001420280114700N/A XC7VX415T412,16064,4006,5252,1601,76088031,6801220480112600N/A XC7VX485T485,76075,9008,1752,8002,0601,03037,0801445600114700N/A XC7VX550T554,24086,6008,7252,8802,3601,18042,4802020800116600N/A XC7VX690T693,120108,30010,8883,6002,9401,47052,92020308001201,000N/A XC7VX980T979,200153,00013,8383,6003,0001,50054,0001830720118900N/A XC7VX1140T1,139,200178,00017,7003,3603,7601,88067,68024409601221,1004XC7VH580T580,48090,7008,8501,6801,88094033,84012204881126002XC7VH870T876,160136,90013,2752,5202,8201,41050,76018307216163003 Notes:1.EasyPath™-7 FPGAs are also available to provide a fast, simple, and risk-free solution for cost reducing Virtex-7 T and Virtex-7 XT FPGA designs2.Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.3.Each DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.4.Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18 Kb blocks.5.Each CMT contains one MMCM and one PLL.6.Virtex-7 T FPGA Interface Blocks for PCI Express support up to x8 Gen 2. Virtex-7 XT and Virtex-7 HT Interface Blocks for PCI Express support up to x8 Gen 3, with theexception of the XC7VX485T device, which supports x8 Gen 2.7.Does not include configuration Bank 0.8.This number does not include GTX, GTH, or GTZ transceivers.9.Super logic regions (SLRs) are the constituent parts of FPGAs that use SSI technology. Virtex-7 HT devices use SSI technology to connect SLRs with 28.05 Gb/stransceivers.。

General DescriptionXilinx® 7series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7series FPGAs include:•Spartan®-7 Family: Optimized for low cost, lowest power, and high I/O performance. Available in low-cost, very small form-factorpackaging for smallest PCB footprint.•Artix®-7 Family: Optimized for low power applications requiring serial transceivers and high DSP and logic throughput. Provides the lowest total bill of materials cost for high-throughput, cost-sensitiveapplications.•Kintex®-7 Family: Optimized for best price-performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs.•Virtex®-7 Family: Optimized for highest system performance and capacity with a 2X improvement in system performance. Highestcapability devices enabled by stacked silicon interconnect (SSI)technology.Built on a state-of-the-art, high-performance, low-power (HPL), 28nm, high-k metal gate (HKMG) process technology, 7series FPGAs enable an unparalleled increase in system performance with 2.9Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.Summary of 7Series FPGA Features•Advanced high-performance FPGA logic based on real 6-input look-up table (LUT) technology configurable as distributed memory.•36Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.•High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.•High-speed serial connectivity with built-in multi-gigabit transceivers from 600Mb/s to max. rates of 6.6Gb/s up to 28.05Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.• A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors.•DSP slices with 25x18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetriccoefficient filtering.•Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter.•Quickly deploy embedded processing with MicroBlaze™ processor.•Integrated block for PCI Express® (PCIe), for up to x8 Gen3 Endpoint and Root Port designs.•Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.•Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flip-chip packaging offering easy migration between family members in the same package. All packages available in Pb-free and selected packages in Pb option.•Designed for high performance and lowest power with 28nm, HKMG, HPL process, 1.0V core voltage process technology and0.9V core voltage option for even lower power.7Series FPGAs Data Sheet: Overview DS180 (v2.6) February 27, 2018Product SpecificationTable 1:7Series Families ComparisonMax. Capability Spartan-7Artix-7Kintex-7Virtex-7Logic Cells102K215K478K1,955KBlock RAM(1) 4.2Mb13Mb34Mb68MbDSP Slices 1607401,9203,600DSP Performance(2)176 GMAC/s929GMAC/s2,845GMAC/s5,335GMAC/s MicroBlaze CPU(3)260 DMIPs303 DMIPs438 DMIPs441 DMIPs Transceivers–163296Transceiver Speed– 6.6Gb/s12.5Gb/s28.05Gb/sSerial Bandwidth–211Gb/s800Gb/s2,784Gb/sPCIe Interface–x4 Gen2x8 Gen2x8 Gen3Memory Interface800Mb/s1,066Mb/s1,866Mb/s1,866Mb/sI/O Pins400500500 1,200I/O Voltage 1.2V–3.3V 1.2V–3.3V 1.2V–3.3V 1.2V–3.3VPackage Options Low-Cost, Wire-Bond Low-Cost, Wire-Bond,Bare-Die Flip-Chip Bare-Die Flip-Chip and High-Performance Flip-ChipHighest PerformanceFlip-ChipNotes:1.Additional memory available in the form of distributed RAM.2.Peak DSP performance numbers are based on symmetrical filter implementation.3.Peak MicroBlaze CPU performance numbers based on microcontroller preset.Mixed-Mode Clock Manager and Phase-Locked LoopThe MMCM and PLL share many characteristics. Both can serve as a frequency synthesizer for a wide range of frequencies and as a jitter filter for incoming clocks. At the center of both components is a voltage-controlled oscillator (VCO), which speeds up and slows down depending on the input voltage it receives from the phase frequency detector (PFD).There are three sets of programmable frequency dividers: D, M, and O. The pre-divider D (programmable by configuration and afterwards via DRP) reduces the input frequency and feeds one input of the traditional PLL phase/frequency comparator. The feedback divider M (programmable by configuration and afterwards via DRP) acts as a multiplier because it divides the VCO output frequency before feeding the other input of the phase comparator. D and M must be chosen appropriately to keep the VCO within its specified frequency range. The VCO has eight equally-spaced output phases (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each can be selected to drive one of the output dividers (six for the PLL, O0 to O5, and seven for the MMCM, O0 to O6), each programmable by configuration to divide by any integer from 1 to 128. The MMCM and PLL have three input-jitter filter options: low bandwidth, high bandwidth, or optimized mode. Low-bandwidth mode has the best jitter attenuation but not the smallest phase offset. High-bandwidth mode has the best phase offset, but not the best jitter attenuation. Optimized mode allows the tools to find the best setting.MMCM Additional Programmable FeaturesThe MMCM can have a fractional counter in either the feedback path (acting as a multiplier) or in one output path. Fractional counters allow non-integer increments of 1/8 and can thus increase frequency synthesis capabilities by a factor of 8.The MMCM can also provide fixed or dynamic phase shift in small increments that depend on the VCO frequency. At 1600MHz, the phase-shift timing increment is 11.2ps.Clock DistributionEach 7series FPGA provides six different types of clock lines (BUFG, BUFR, BUFIO, BUFH, BUFMR, and the high-performance clock) to address the different clocking requirements of high fanout, short propagation delay, and extremely low skew.Global Clock LinesIn each 7series FPGA (except XC7S6 and XC7S15), 32 global clock lines have the highest fanout and can reach every flip-flop clock, clock enable, and set/reset, as well as many logic inputs. There are 12 global clock lines within any clock region driven by the horizontal clock buffers (BUFH). Each BUFH can be independently enabled/disabled, allowing for clocks to be turned off within a region, thereby offering fine-grain control over which clock regions consume power. Global clock lines can be driven by global clock buffers, which can also perform glitchless clock multiplexing and clock enable functions. Global clocks are often driven from the CMT, which can completely eliminate the basic clock distribution delay.Regional ClocksRegional clocks can drive all clock destinations in their region. A region is defined as an area that is 50 I/O and 50 CLB high and half the chip wide. 7series FPGAs have between two and twenty-four regions. There are four regional clock tracks in every region. Each regional clock buffer can be driven from any of four clock-capable input pins, and its frequency can optionally be divided by any integer from 1 to 8.I/O ClocksI/O clocks are especially fast and serve only I/O logic and serializer/deserializer (SerDes) circuits, as described in theI/O Logic section. The 7series devices have a direct connection from the MMCM to the I/O for low-jitter, high-performance interfaces.Block RAMSome of the key features of the block RAM include:•Dual-port 36Kb block RAM with port widths of up to 72•Programmable FIFO logic•Built-in optional error correction circuitryEvery 7series FPGA has between 5 and 1,880 dual-port block RAMs, each storing 36Kb. Each block RAM has two completely independent ports that share nothing but the stored data.Synchronous OperationEach memory access, read or write, is controlled by the clock. All inputs, data, address, clock enables, and write enables are registered. Nothing happens without a clock. The input address is always clocked, retaining data until the next operation. An optional output data pipeline register allows higher clock rates at the cost of an extra cycle of latency.During a write operation, the data output can reflect either the previously stored data, the newly written data, or can remain unchanged.Programmable Data WidthEach port can be configured as 32K×1, 16K×2, 8K×4, 4K×9 (or8), 2K×18 (or16), 1K×36 (or32), or 512×72 (or64). The two ports can have different aspect ratios without any constraints.Each block RAM can be divided into two completely independent 18Kb block RAMs that can each be configured to any aspect ratio from 16K×1 to 512×36. Everything described previously for the full 36Kb block RAM also applies to each of the smaller 18Kb block RAMs.Only in simple dual-port (SDP) mode can data widths of greater than 18bits (18Kb RAM) or 36bits (36Kb RAM) be accessed. In this mode, one port is dedicated to read operation, the other to write operation. In SDP mode, one side (read or write) can be variable, while the other is fixed to 32/36 or 64/72.Both sides of the dual-port 36Kb RAM can be of variable width.Two adjacent 36Kb block RAMs can be configured as one cascaded 64K×1 dual-port RAM without any additional logic. Error Detection and CorrectionEach 64-bit-wide block RAM can generate, store, and utilize eight additional Hamming code bits and perform single-bit error correction and double-bit error detection (ECC) during the read process. The ECC logic can also be used when writing to or reading from external 64- to 72-bit-wide memories.FIFO ControllerThe built-in FIFO controller for single-clock (synchronous) or dual-clock (asynchronous or multirate) operation increments the internal addresses and provides four handshaking flags: full, empty, almost full, and almost empty. The almost full and almost empty flags are freely programmable. Similar to the block RAM, the FIFO width and depth are programmable, but the write and read ports always have identical width.First word fall-through mode presents the first-written word on the data output even before the first read operation. After the first word has been read, there is no difference between this mode and the standard mode.7Series FPGA Ordering InformationTable12 shows the speed and temperature grades available in the different device families. Some devices might not be available in every speed and temperature grade.Table 12:7 Series Speed Grade and Temperature RangesDevice Family DevicesSpeed Grade, Temperature Range, and Operating VoltageCommercial (C)0°C to +85°CExtended (E)0°C to +100°CIndustrial (I)–40°C to +100°CExpanded (Q)–40°C to +125°CSpartan-7All -2C (1.0V)-2I (1.0V)-1C (1.0V)-1I (1.0V)-1Q (1.0V)-1LI (0.95V)Artix-7All-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V or 0.9V)-1C (1.0V)-1I (1.0V)-1LI (0.95V)Kintex-7XC7K70T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V or 0.9V)-1C (1.0V)-1I (1.0V) XC7K160TXC7K325TXC7K355TXC7K410TXC7K420TXC7K480T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V or 0.9V)-2LI (0.95V)-1C (1.0V)-1I (1.0V)Virtex-7 TXC7V585T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V) XC7V2000T-2C (1.0V)-2GE (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V)Virtex-7 XTXC7VX330TXC7VX415TXC7VX485TXC7VX550TXC7VX690T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V) XC7VX980T-2C (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V) XC7VX1140T-2C (1.0V)-2GE (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V)Virtex-7 HT All -2C (1.0V)-2GE (1.0V)-2LE (1.0V) -1C (1.0V)。

Chapter 1:Packaging OverviewPin DefinitionsTable1-12 lists the pin definitions used in 7series FPGAs packages.Note:There are dedicated general purpose user I/O pins listed separately in Table1-12. There are also multi-function pins where the pin names start with either IO_LXXY_ZZZ_# or IO_XX_ZZZ_#,where ZZZ represents one or more functions in addition to being general purpose user I/O. If notused for their special function, these pins can be user I/O.user I/O after stage 2 configuration is complete.Table 1-12:7Series FPGAs Pin DefinitionsPin Name Type Direction DescriptionUser I/O PinsIO_LXXY_# IO_XX_#Dedicated Input/OutputMost user I/O pins are capable of differential signalingand can be implemented as pairs. The top and bottom I/O pins are always single ended. Each user I/O is labeledIO_LXXY_#, where:°IO indicates a user I/O pin°L indicates a differential pair, with XX a unique pair inthe bank and Y = [P|N] for the positive/negative sidesof the differential pair°# indicates a bank numberConfiguration PinsFor more information, see the Configuration Pin Definitions table in UG470, 7Series FPGAs Configuration User Guide.CCLK_0Dedicated(1)Input/Output Configuration clock. Output in Master mode or input in Slave modeDONE_0Dedicated(1)Bidirectional DONE indicates successful completion of configuration(active High)INIT_B_0Dedicated(1)Bidirectional(open-drain)Indicates initialization of configuration memory (active Low)M0_0, M1_0, or M2_0Dedicated(1)Input Configuration mode selectionPROGRAM_B_0Dedicated(1)Input Asynchronous reset to configuration logic (active Low) TCK_0Dedicated(1)Input JTAG clockTDI_0Dedicated(1)Input JTAG data inputTDO_0Dedicated(1)Output JTAG data outputTMS_0Dedicated(1)Input JTAG mode selectChapter 2:7Series FPGAs Package FilesTo download all available Artix-7 FPGAs package/device/pinout files click here: Table 2-2:Artix-7 FPGAs Package/Device Pinout FilesChapter 3:Device DiagramsArtix-7 FPGAs Device DiagramsDeviceCP236CPG236CPG238CS324CSG324CS325CSG325FT256FTG256SB484SBG484SBV484RS484FG484FGG484FG676FGG676FB484FBG484RB484FB676FBG676RB676FF1156FFG1156XC7A12T page 100page 105XC7A15T page 98page 102page 109page 111page 113XC7A25T page 100page 107XC7A35T page 98page 102page 109page 111page 113XC7A50T page 98page 102page 109page 111page 113XC7A75T page 102page 111page 116page 119XC7A100T page 102page 111page 116page 119XC7A200T page 122page 125page 128page 131XA7A12T page 100page 105XA7A15T page 98page 102page 109page 113XA7A25T page 100page 107XA7A35T page 98page 102page 109XA7A50T page 98page 102page 109XA7A75T page 102page 116XA7A100Tpage 102page 116Table 5-1:Thermal Resistance Data—All DevicesPackage PackageBody Size DevicesθJB(°C/W)θJA(°C/W)θJC(°C/W)θJA-Effective (°C/W)(1)@250 LFM@500 LFM@750 LFMSpartan-7 FPGAsCPGA1968 x 8XC7S615.135.08.4630.128.627.9 CPGA1968 x 8XA7S615.135.08.4630.128.627.9 CPGA1968 x 8XC7S1515.135.08.4630.128.627.9 CPGA1968 x 8XA7S1515.135.08.4630.128.627.9 CSGA22513 x 13XC7S617.432.210.626.725.124.2 CSGA22513 x 13XA7S617.432.210.626.725.124.2 CSGA22513 x 13XC7S1517.432.210.626.725.124.2 CSGA22513 x 13XA7S1517.432.210.626.725.124.2 CSGA22513 x 13XC7S2515.630.69.427.123.524.4 CSGA22513 x 13XA7S2515.630.69.427.123.524.4 CSGA32415 x 15XC7S259.422.1 5.6518.116.716.2 CSGA32415 x 15XA7S259.422.1 5.6518.116.716.2 CSGA32415 x 15XC7S507.620.1 4.4715.914.814.1 CSGA32415 x 15XA7S507.620.1 4.4715.914.814.1 FTGB19615 x 15XC7S613.727.88.922.521.120.0 FTGB19615 x 15XC7S1513.727.88.922.521.120.0 FTGB19615 x 15XC7S2512.526.27.120.919.418.6 FTGB19615 x 15XC7S508.822.6 5.317.315.915.1 FGGA48423 x 23XC7S509.217.9 5.8513.812.712.1 FGGA48423 x 23XA7S509.217.9 5.8513.812.712.1 FGGA48423 x 23XC7S75 6.815.8 3.8512.111.010.4 FGGA48423 x 23XA7S75 6.815.8 3.8512.111.010.4 FGGA48423 x 23XC7S100 6.815.8 3.8512.111.010.4 FGGA48423 x 23XA7S100 6.815.8 3.8512.111.010.4 FGGA67627 x 27XC7S75 6.815.0 3.7111.210.29.7 FGGA67627 x 27XA7S75 6.815.0 3.7111.210.29.7 FGGA67627 x 27XC7S100 6.815.0 3.7111.210.29.7 FGGA67627 x 27XA7S100 6.815.0 3.7111.210.29.7 Artix-7 FPGAsCP/CPG23610 x 10XC7A15T7.924.8 5.2920.318.918.0 CPG23610 x 10XA7A15T7.924.8 5.2920.318.918.0 CP/CPG23610 x 10XC7A35T7.924.8 5.2920.318.918.0。

Thermal Management StrategyAs described in this section, Xilinx relies on a multi-pronged approach with regards to the heat-dissipating potential of 7series devices.Cavity-Up Plastic BGA PackagesBGA is a plastic package technology that utilizes area array solder balls at the bottom of the package to make electrical contact with the circuit board in the users system. The area array format of solder balls reduces package size considerably when compared to leaded products. It also results in improved electrical performance as well as having higher manufacturing yields. The substrate is made of a multi-layer BT (bismaleimide triazene) epoxy-based material. Power and GND pins are grouped together and signal pins are assigned to the perimeter for ease of routing on the board. The package is offered in a die-up format and contains a wire-bond device covered with a mold compound. As shown in the cross section of Figure 5-2, the BGA package contains a wire-bond die on a single-core printed circuit board with an overmold.The key features/advantages of cavity-up BGA packages are:•Low profile and small footprint •Enhanced thermal performance •Excellent board-level reliabilityWire-Bond PackagesWire-bond packages meet the demands required by miniaturization while offeringimproved performance. Applications for wire-bond packages are targeted to portable and consumer products where board space is of utmost importance, miniaturization is a key requirement, and power consumption/dissipation must be low. By employing 7series FPGA wire-bond packages, system designers can dramatically reduce board area requirements. Xilinx wire-bond packages are rigid BT-based substrates (see Figure 5-3).Figure 5-2:Cavity-Up Ball Grid Array PackageFigure 3-112:FB900, FBG900, and FBV900 Packages—XC7K325T and XC7K410TPower and GND PlacementFF676, FFG676, FFV676, and RF676 Packages—XC7K160T,XA7K160T, XC7K325T, and XC7K410T Array Figure 3-113:FF676, FFG676, FFV676, and RF676 Packages—XC7K160T, XA7K160T, XC7K325T, andXC7K410T Pinout DiagramFF901, FFG901, and FFV901 Packages—XC7K355TFigure 3-121:FF901, FFG901, and FFV901 Packages—XC7K355T Pinout Diagram。

Feature Summary•Density support°Support 8 Gb for component°Other densities for memory device support is available through custom part selection•8-bank support•x32 device support°x16 memory device support is available through custom part selection•8:1 DQ:DQS ratio support for all devices•8-word burst support•Support for 6 to 12 cycles of column-address strobe (CAS) latency (CL)•On-die termination (ODT) support•Support for 3 to 6 cycles of CAS write latency•JEDEC®-compliant LPDDR3 initialization support•Source code delivery in Verilog•4:1 memory to FPGA logic interface clock ratio•Open, closed, and transaction based pre-charge controller policy•Interface calibration and training information available through the Vivado® Design Suite hardware managerRDLVL_DBI_NQTR_RIGHT_RANK0_BYTE1 string true true050 RDLVL_DBI_NQTR_RIGHT_RANK0_BYTE2 string true true04f RDLVL_DBI_NQTR_RIGHT_RANK0_BYTE3 string true true050 RDLVL_DBI_NQTR_RIGHT_RANK0_BYTE4 string true true051 RDLVL_DBI_NQTR_RIGHT_RANK0_BYTE5 string true true051 RDLVL_DBI_NQTR_RIGHT_RANK0_BYTE6 string true true052 RDLVL_DBI_NQTR_RIGHT_RANK0_BYTE7 string true true050 RDLVL_DBI_NQTR_RIGHT_RANK0_BYTE8 string true true04c RDLVL_DBI_PQTR_CENTER_RANK0_BYTE0 string true true 000 RDLVL_DBI_PQTR_CENTER_RANK0_BYTE1 string true true 000 RDLVL_DBI_PQTR_CENTER_RANK0_BYTE2 string true true 000 RDLVL_DBI_PQTR_CENTER_RANK0_BYTE3 string true true 000 RDLVL_DBI_PQTR_CENTER_RANK0_BYTE4 string true true 000 RDLVL_DBI_PQTR_CENTER_RANK0_BYTE5 string true true 000 RDLVL_DBI_PQTR_CENTER_RANK0_BYTE6 string true true 000 RDLVL_DBI_PQTR_CENTER_RANK0_BYTE7 string true true 000 RDLVL_DBI_PQTR_CENTER_RANK0_BYTE8 string true true 000 RDLVL_DBI_PQTR_LEFT_RANK0_BYTE0 string true true000 RDLVL_DBI_PQTR_LEFT_RANK0_BYTE1 string true true000 RDLVL_DBI_PQTR_LEFT_RANK0_BYTE2 string true true000 RDLVL_DBI_PQTR_LEFT_RANK0_BYTE3 string true true000 RDLVL_DBI_PQTR_LEFT_RANK0_BYTE4 string true true000 RDLVL_DBI_PQTR_LEFT_RANK0_BYTE5 string true true000 RDLVL_DBI_PQTR_LEFT_RANK0_BYTE6 string true true000 RDLVL_DBI_PQTR_LEFT_RANK0_BYTE7 string true true000 RDLVL_DBI_PQTR_LEFT_RANK0_BYTE8 string true true000 RDLVL_DBI_PQTR_RIGHT_RANK0_BYTE0 string true true065 RDLVL_DBI_PQTR_RIGHT_RANK0_BYTE1 string true true05f RDLVL_DBI_PQTR_RIGHT_RANK0_BYTE2 string true true05b RDLVL_DBI_PQTR_RIGHT_RANK0_BYTE3 string true true061 RDLVL_DBI_PQTR_RIGHT_RANK0_BYTE4 string true true05d RDLVL_DBI_PQTR_RIGHT_RANK0_BYTE5 string true true05e RDLVL_DBI_PQTR_RIGHT_RANK0_BYTE6 string true true05e RDLVL_DBI_PQTR_RIGHT_RANK0_BYTE7 string true true067 RDLVL_DBI_PQTR_RIGHT_RANK0_BYTE8 string true true05e RDLVL_IDELAY_DBI_FINAL_BYTE0 string true true03b RDLVL_IDELAY_DBI_FINAL_BYTE1 string true true03a RDLVL_IDELAY_DBI_FINAL_BYTE2 string true true031 RDLVL_IDELAY_DBI_FINAL_BYTE3 string true true038 RDLVL_IDELAY_DBI_FINAL_BYTE4 string true true034 RDLVL_IDELAY_DBI_FINAL_BYTE5 string true true03a RDLVL_IDELAY_DBI_FINAL_BYTE6 string true true035 RDLVL_IDELAY_DBI_FINAL_BYTE7 string true true03c RDLVL_IDELAY_DBI_FINAL_BYTE8 string true true030 RDLVL_IDELAY_DBI_RANK0_BYTE0 string true true000 RDLVL_IDELAY_DBI_RANK0_BYTE1 string true true000 RDLVL_IDELAY_DBI_RANK0_BYTE2 string true true000 RDLVL_IDELAY_DBI_RANK0_BYTE3 string true true000 RDLVL_IDELAY_DBI_RANK0_BYTE4 string true true000 RDLVL_IDELAY_DBI_RANK0_BYTE5 string true true000 RDLVL_IDELAY_DBI_RANK0_BYTE6 string true true000 RDLVL_IDELAY_DBI_RANK0_BYTE7 string true true000 RDLVL_IDELAY_DBI_RANK0_BYTE8 string true true000Chapter 25:Designing with the Core44DQB24T2N0GCIO_P_1AT32–N1GCIO_N_1AU32 DQB19N2GCIO_P_2AT29 DQB20N3GCIO_N_2AU29 DQB22N4–AR32 DQB21N5–AR33 QKB1_P N6–AR28 QKB1_N N7–AT28 DQB23N8–AP30 DQB26N9–AR31 DQB25N10–AR30 DQB18N11–AT30–N12–AT3344DQB27T3N0–AN31 QVLDB1N1–AP31 DQB29N2–AN32 DQB33N3–AP33 DQB32N4–AP28 DQB34N5–AP29 DKB1_P N6–AM30 DKB1_N N7–AM31 DQB31N8–AM29 DQB35N9–AN29 DQB28N10–AL29 DQB30N11–AL30–N12–AN28Table 25-1:36-Bit QDR-IV Interface Contained in Three Banks (Cont’d)Bank Signal Name Byte Group Byte Group I/ONumberSpecialDesignation Pin Number。

General Description7series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7series FPGAs include:•Spartan®-7 Family: Optimized for low cost, lowest power, and high I/O performance. Available in low-cost, very small form-factorpackaging for smallest PCB footprint.•Artix®-7 Family: Optimized for low power applications requiring serial transceivers and high DSP and logic throughput. Provides the lowest total bill of materials cost for high-throughput, cost-sensitiveapplications.•Kintex®-7 Family: Optimized for best price-performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs.•Virtex®-7 Family: Optimized for highest system performance and capacity with a 2X improvement in system performance. Highestcapability devices enabled by stacked silicon interconnect (SSI)technology.Built on a state-of-the-art, high-performance, low-power (HPL), 28nm, high-k metal gate (HKMG) process technology, 7series FPGAs enable an unparalleled increase in system performance with 2.9Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.Summary of 7Series FPGA Features•Advanced high-performance FPGA logic based on real 6-input look-up table (LUT) technology configurable as distributed memory.•36Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.•High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.•High-speed serial connectivity with built-in multi-gigabit transceivers from 600Mb/s to max. rates of 6.6Gb/s up to 28.05Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.• A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors.•DSP slices with 25x18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetriccoefficient filtering.•Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter.•Quickly deploy embedded processing with MicroBlaze™ processor.•Integrated block for PCI Express® (PCIe), for up to x8 Gen3 Endpoint and Root Port designs.•Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.•Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flip-chip packaging offering easy migration between family members in the same package. All packages available in Pb-free and selected packages in Pb option.•Designed for high performance and lowest power with 28nm, HKMG, HPL process, 1.0V core voltage process technology and0.9V core voltage option for even lower power.7Series FPGAs Data Sheet: Overview DS180 (v2.6) February 27, 2018Product SpecificationTable 1:7Series Families ComparisonMax. Capability Spartan-7Artix-7Kintex-7Virtex-7Logic Cells102K215K478K1,955KBlock RAM(1) 4.2Mb13Mb34Mb68MbDSP Slices 1607401,9203,600DSP Performance(2)176 GMAC/s929GMAC/s2,845GMAC/s5,335GMAC/s MicroBlaze CPU(3)260 DMIPs303 DMIPs438 DMIPs441 DMIPs Transceivers–163296Transceiver Speed– 6.6Gb/s12.5Gb/s28.05Gb/sSerial Bandwidth–211Gb/s800Gb/s2,784Gb/sPCIe Interface–x4 Gen2x8 Gen2x8 Gen3Memory Interface800Mb/s1,066Mb/s1,866Mb/s1,866Mb/sI/O Pins400500500 1,200I/O Voltage 1.2V–3.3V 1.2V–3.3V 1.2V–3.3V 1.2V–3.3VPackage Options Low-Cost, Wire-Bond Low-Cost, Wire-Bond,Bare-Die Flip-Chip Bare-Die Flip-Chip and High-Performance Flip-ChipHighest PerformanceFlip-ChipNotes:1.Additional memory available in the form of distributed RAM.2.Peak DSP performance numbers are based on symmetrical filter implementation.3.Peak MicroBlaze CPU performance numbers based on microcontroller preset.赛灵思半导体（深圳）质量等级领域:宇航级IC、特军级IC、超军级IC、普军级IC、禁运IC、工业级IC，军级二三极管，功率管等;应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通信网络、电力工业以及大型工业设备祝您:工作顺利，生活愉快!以赛灵思半导体（深圳）有限公司提供的参数为例，以下为XC7K325T-2FBG900I的详细参数，仅供参考Spartan-7 FPGA Feature Summary Table 2:Spartan-7 FPGA Feature Summary by DeviceDevice LogicCellsCLBDSPSlices(2)Block RAM Blocks(3)CMTs(4)PCIe GT XADCBlocksTotal I/OBanks(5)Max UserI/O Slices(1)MaxDistributedRAM (Kb)18Kb36Kb Max(Kb)XC7S66,000938701010518020002100 XC7S1512,8002,00015020201036020002100 XC7S2523,3603,6503138090451,62030013150 XC7S5052,1608,150600120150752,70050015250 XC7S7576,80012,000832140180903,24080018400 XC7S100102,40016,0001,1001602401204,32080018400 Notes:1.Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.2.Each DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.3.Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.4.Each CMT contains one MMCM and one PLL.5.Does not include configuration Bank 0.Table 3:Spartan-7 FPGA Device-Package Combinations and Maximum I/OsPackage CPGA196CSGA225CSGA324FTGB196FGGA484FGGA676Size (mm)8 x 813 x 1315 x 1515 x 1523 x 2327 x 27Ball Pitch(mm)0.50.80.8 1.0 1.0 1.0 Device HR I/O(1)HR I/O(1)HR I/O(1)HR I/O(1)HR I/O(1)HR I/O(1)XC7S6100100100XC7S151********XC7S25150150100XC7S50210100250XC7S75338400XC7S100338400Notes:1.HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V.Artix-7 FPGA Feature SummaryTable 4:Artix-7 FPGA Feature Summary by DeviceDevice LogicCells Configurable Logic Blocks(CLBs)DSP48E1Slices(2)Block RAM Blocks(3)CMTs(4)PCIe(5)GTPsXADCBlocksTotal I/OBanks(6)Max UserI/O(7) Slices(1)MaxDistributedRAM (Kb)18Kb36Kb Max(Kb)XC7A12T12,8002,00017140402072031213150 XC7A15T16,6402,60020045502590051415250 XC7A25T23,3603,6503138090451,62031413150 XC7A35T33,2805,20040090100501,80051415250 XC7A50T52,1608,150600120150752,70051415250 XC7A75T75,52011,8008921802101053,78061816300 XC7A100T101,44015,8501,1882402701354,86061816300 XC7A200T215,36033,6502,88874073036513,14010116110500 Notes:1.Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.2.Each DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.3.Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.4.Each CMT contains one MMCM and one PLL.5.Artix-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2.6.Does not include configuration Bank 0.7.This number does not include GTP transceivers.Table 5:Artix-7 FPGA Device-Package Combinations and Maximum I/OsPackage(1)CPG236CPG238CSG324CSG325FTG256SBG484FGG484(2)FBG484(2)FGG676(3)FBG676(3)FFG1156 Size (mm)10 x 1010 x 1015 x 1515 x 1517 x 1719 x 1923 x 2323 x 2327 x 2727 x 2735 x 35 Ball Pitch(mm)0.50.50.80.8 1.00.8 1.0 1.0 1.0 1.0 1.0Device GTP(4)I/OGTP(4)I/OGTP(4)I/OGTP(4)I/OGTP(4)I/OGTPI/OGTP(4)I/OGTPI/OGTP(4)I/OGTPI/OGTPI/O HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)XC7A12T21122150XC7A15T21060210415001704250XC7A25T21124150XC7A35T21060210415001704250XC7A50T21060210415001704250XC7A75T0210017042858300XC7A100T0210017042858300XC7A200T42854285840016500 Notes:1.All packages listed are Pb-free (SBG, FBG, FFG with exemption 15). Some packages are available in Pb option.2.Devices in FGG484 and FBG484 are footprint compatible.3.Devices in FGG676 and FBG676 are footprint compatible.4.GTP transceivers in CP, CS, FT, and FG packages support data rates up to 6.25Gb/s.5.HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V.7Series FPGA Ordering InformationTable12 shows the speed and temperature grades available in the different device families. Some devices might not be available in every speed and temperature grade.Table 12:7 Series Speed Grade and Temperature RangesDevice Family DevicesSpeed Grade, Temperature Range, and Operating VoltageCommercial (C)0°C to +85°CExtended (E)0°C to +100°CIndustrial (I)–40°C to +100°CExpanded (Q)–40°C to +125°CSpartan-7All -2C (1.0V)-2I (1.0V)-1C (1.0V)-1I (1.0V)-1Q (1.0V)-1LI (0.95V)Artix-7All-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V or 0.9V)-1C (1.0V)-1I (1.0V)-1LI (0.95V)Kintex-7XC7K70T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V or 0.9V)-1C (1.0V)-1I (1.0V) XC7K160TXC7K325TXC7K355TXC7K410TXC7K420TXC7K480T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V or 0.9V)-2LI (0.95V)-1C (1.0V)-1I (1.0V)Virtex-7 TXC7V585T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V) XC7V2000T-2C (1.0V)-2GE (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V)Virtex-7 XTXC7VX330TXC7VX415TXC7VX485TXC7VX550TXC7VX690T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V) XC7VX980T-2C (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V) XC7VX1140T-2C (1.0V)-2GE (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V)Virtex-7 HT All -2C (1.0V)-2GE (1.0V)-2LE (1.0V) -1C (1.0V)The Spartan-7 FPGA ordering information is shown in Figure1. Refer to the Package Marking section of UG475, 7 Series FPGAs Packaging and Pinout for a more detailed explanation of the device markings.Figure 1:Spartan-7 FPGA Ordering InformationThe Artix-7, Kintex-7, and Virtex-7 FPGA ordering information, shown in Figure2, applies to all packages including Pb-Free. Refer to the Package Marking section of UG475, 7 Series FPGAs Packaging and Pinout for a more detailed explanation of the device markings.Figure 2:Artix-7, Kintex-7, and Virtex-7 FPGA Ordering InformationRevision HistoryThe following table shows the revision history for this document:Date Version Description of Revisions06/21/10 1.0Initial Xilinx release.07/30/10 1.1Added SHA-256 to authentication information. Updated Table5, Table7, Virtex-7 FPGA Device-Package Combinations and Maximum I/Os table (Virtex-7 T devices), and Table9 with ball pitchinformation and voltage bank information. Updated DSP and Logic Slice information in Table8.Updated Low-Power Gigabit Transceivers.09/24/10 1.2In General Description, updated 4.7TMACS DSP to 5.0TMACS DSP. In Table1, added Note 1;updated Peak DSP Performance for Kintex-7 and Virtex-7 families. In Table4, updated CMTinformation for XC7A175T and XC7A355T. In Table6, replaced XC7K120T with XC7K160T andreplaced XC7K230T with XC7K325T—and updated corresponding information. Also addedXC7K355T, XC7K420T, and XC7K480T. In Table7,replaced XC7K230T with XC7K325T. In Table8,updated XC7V450T Logic Cell, CLB, block RAM, and PCI information; updated XC7VX415T andXC7VX690T PCI information; updated XC7V1500T, and XC7V2000T block RAM information; andreplaced XC7VX605T with XC7VX575T, replaced XC7VX895T with XC7VX850T, and replacedXC7VX910T with XC7VX865T—and updated corresponding information. Updated Digital SignalProcessing — DSP Slice with operating speed of 640MHz.Removed specific transceiver type fromOut-of-Band Signaling. In Virtex-7 FPGA Device-Package Combinations and Maximum I/Os table(Virtex-7 T devices), replaced XC7VX605T with XC7VX575T and added table notes 2 and 3. InTable9, removed the FFG784 package for the XC7VX485T device; replaced XC7VX605T withXC7VX575T; replaced XC7VX895T with XC7VX850T; and replaced XC7VX910T with XC7VX865T.10/20/10 1.3In Table7, replaced XC7K120T with XC7K160T. Updated Digital Signal Processing — DSP Slice.11/17/10 1.4Updated maximum I/O bandwidth to 3.1 Tb/s in General Description. Updated Peak Transceiver Speedfor Virtex-7 FPGAs in Summary of 7Series FPGA Features and in Table1. Updated Peak DSPPerformance values in Table1 and Digital Signal Processing — DSP Slice. In Table7, updatedXC7K70T I/O information. In Table8, added XC7VH290T, XC7VH580T, and XC7VH870T devices andupdated total I/O banks information for the XC7V585T, XC7V855T, XC7V1500T, and XC7VX865Tdevices. In Table9, updated XC7VX415T, XC7VX485T, XC7VX690T, XC7VX850T, and XC7VX865Tdevice information. Added Table11. Updated Low-Power Gigabit Transceivers information, includingthe addition of the GTZ transceivers.02/22/11 1.5Updated Summary of 7Series FPGA Features and the Low-Power Gigabit Transceivers highlights andsection. In Table1, updated Kintex-7 FPGA, Artix-7 FPGA information. In Table4, updated XC7A175T.Also, updated XC7A355T.Added three Artix-7 FPGA packages to Table5: SBG325, SBG484, andFBG485, changed package from FGG784 to FBG784, and updated package information forXC7A175T and XC7A355T devices. In Table6, updated XC7K160T and added three devices:XC7K355T, XC7K420T, and XC7K480T. In Table7, updated XC7K70T package information and addedthree devices: XC7K355T, XC7K420T, and XC7K480T. In Table8, added note 1 (EasyPath FPGAs)and updated note 7 to include GTZ transceivers. In Virtex-7 FPGA Device-Package Combinations andMaximum I/Os table (Virtex-7 T devices), added two Virtex-7 FPGA packages: FHG1157 andFHG1761, and updated XC7V1500T (no FFG1157) and XC7V2000T (no FFG1761) packageinformation and removed the associated notes. Added CLBs, Slices, and LUTs. Updated Input/Output.Added EasyPath-7 FPGAs.03/28/11 1.6Updated G eneral Description, Summary of 7Series FPG A Features, Table1, Table4, Table5, Table6,Table7, Table8, Table9 (combined Virtex-7 T and XT devices in one table), and Table11. Updated theLow-Power Gigabit Transceivers highlights and section. Updated Block RAM, Integrated InterfaceBlocks for PCI Express Designs, Configuration, Encryption, Readback, and Partial Reconfiguration,XADC (Analog-to-Digital Converter), 7Series FPGA Ordering Information, and EasyPath-7 FPGAs.07/06/11 1.7Updated G eneral Description, Summary of 7Series FPG A Features, Table1, Table4, Table6, Table8,Table9 and Table11. Added Table10. Added Stacked Silicon Interconnect (SSI) Technology. UpdatedTransmitter, Configuration, and XADC (Analog-to-Digital Converter). Updated Figure1.09/13/11 1.8Updated General Description, Table1, Table4, Table5, Table8, CLBs, Slices, and LUTs,Configuration, and 7Series FPGA Ordering Information.01/15/12 1.9Updated General Description, Table1, Table4, Table5, Table6, Table7, Table8, Table10, Table11,Block RAM, Digital Signal Processing — DSP Slice, Low-Power Gigabit Transceivers, IntegratedInterface Blocks for PCI Express Designs, Configuration, EasyPath-7 FPGAs, and 7Series FPGAOrdering Information.Date Version Description of Revisions03/02/12 1.10Updated General Description, Table5, and Table12.05/02/12 1.11Updated Table7, Table9, Table10, Low-Power Gigabit Transceivers, and 7Series FPGA OrderingInformation. Added 7Series FPGA Ordering Information.10/15/12 1.12Updated overview with Artix-7 SL and SLT devices. Updated Table1, Table4, Table5, Table8, Table9,Table10, Table11, and Table12. Added Table 3. Updated Regional Clocks, Block RAM, IntegratedInterface Blocks for PCI Express Designs, Configuration, and 7Series FPGA Ordering Information.11/30/12 1.13Updated notes in Table4 and Table12. Updated XADC (Analog-to-Digital Converter).07/29/13 1.14Removed SL and SLT devices. Updated General Description, Table4, Table5, notes in Table6 andTable8, Regional Clocks, Input/Output, Low-Power Gigabit Transceivers, Integrated Interface Blocksfor PCI Express Designs, Configuration, and 7Series FPGA Ordering Information. Removed previousTable 3.02/18/14 1.15Changed document classification to Product Specification from Preliminary Product Specification.Updated HR I/O information for XC7A35T and XC7A50T in Table5. Updated XC7VH870T I/Oinformation in Table8. Updated Table11.10/08/14 1.16Added XC7A15T to Table4 and Table5. Removed HCG1931 and HCG1932 from Table11. UpdatedInput/Output Delay; Block RAM; Configuration; I/O Clocks; and Updated Table12 and Figure1.12/17/14 1.16.1Typographical edit.05/27/15 1.17Updated Table5, Table7, Table9, Table10, Table11, and Figure1.09/27/16 2.0Added Spartan-7 devices throughout document, including Table1, Table2, Table3, and Table12.Added two Artix-7 devices XC7A12T and XC7A25T throughout document, including Table4, Table5,and Table12. Updated General Description; Figure1, Table7, Regional Clocks, Block RAM,Integrated Interface Blocks for PCI Express Designs, Configuration, Encryption, Readback, and PartialReconfiguration, and XADC (Analog-to-Digital Converter).10/20/16 2.1Updated Table5.12/15/16 2.2Updated Table3.03/17/17 2.3Updated Table1, Table5, Table7, Table9, Table10, Table12, and I/O Electrical Characteristics.03/28/17 2.4Updated Table7.08/01/17 2.5Updated Table5 and Figure2.02/27/18 2.6Added MicroBlaze CPU information to the Summary of 7Series FPGA Features and Table1.Notice of DisclaimerThe information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. 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UltraScale Architecture-Based FPGAs Memory IP v1.4 PG150 January 21, 2021Chapter 38:DebuggingAnalyzing Calibration ResultsWhen data errors occur, the results of calibration should be analyzed to ensure that the results are expected and accurate. Each of the debugging calibration sections notes what the expected results are such as how many edges should be found, how much variance across byte groups should exist, etc. Follow these sections to capture and analyze the calibration results.Determining Window Size in psTo determine the window size in ps, first calculate the tap resolution and then multiply the resolution by the number of taps found in the read and/or write window. The tap resolution varies across process (down to variance at each nibble within a part).However, within a specific process, each tap within the delay chain is the same precise resolution.1.To compute the 90° offset in taps, take (BISC_PQTR – BISC_ALIGN_PQTR).2.To estimate tap resolution, take (1/4 of the memory clock period) / (BISC_PQTR –BISC_ALIGN_PQTR).3.The same then applies for NQTR.BISC is run on a per nibble basis for both PQTR and NQTR. The write tap results are given on a per byte basis. To use the BISC results to determine the write window, take the average of the BISC PQTR and NQTR results for each nibble. For example, ((BISC_NQTR_NIBBLE0 + BISC_NQTR_NIBBLE1 + BISC_PQTR_NIBBLE0 + BISC_PQTR_NIBBLE1) / 4).ConclusionIf this document does not help to resolve calibration or data errors, create a WebCase with Xilinx Technical Support (see Technical Support). Attach all of the captured waveforms, XSDB and debug signal results, and the details of your investigation and analysis.UltraScale Architecture-Based FPGAs Memory IP v1.4 PG150 January 21, 2021Chapter 26:Design Flow StepsThe I/O standard is chosen by the memory type selection and options in the Vivado IDE and by the pin type. A sample for qdriv_a[0] is shown here.set_property PACKAGE_PIN AK26 [get_ports {a[0]}]set_property IOSTANDARD POD12_DCI [get_ports {a[0]}]The system clock must have the period set properly:create_clock -name sys_clk_i -period 2.000 [get_ports sys_clk_p]Device, Package, and Speed Grade SelectionsThis section is not applicable for this IP core.Clock FrequenciesThis section is not applicable for this IP core.Clock ManagementFor more information on clocking, see Clocking, page369.Clock PlacementThis section is not applicable for this IP core.BankingThis section is not applicable for this IP core.Transceiver PlacementThis section is not applicable for this IP core.I/O Standard and PlacementThe QDR-IV SRAM tool generates the appropriate I/O standards and placement based onthe selections made in the Vivado IDE for the interface type and options.UltraScale Architecture-Based FPGAs Memory IP v1.4PG150 January 21, 2021Chapter 38:DebuggingTable 38-16 describes the signals and values adjusted or used during the Read Per-Bit Deskew stage of calibration. The values can be analyzed in both successful and failing calibrations to determine the resultant values and the consistency in results across resets. These values can be found within the Memory IP Core Properties within Hardware Manager or by executing the Tcl commands noted in the XSDB Debug section.Table 38-15:DDR_CAL_ERROR Decode for Read Deskew Calibration Per-Bit Deskew DDR_CAL_ERROR_CODEDDR_CAL_ERROR_1DDR_CAL_ERROR_0Description Recommended Debug Steps 0x1Nibble Bit No valid data found for a given bit in the nibble (deskew pattern)Check the BUS_DATA_BURST fields in XSDB. Check the dbg_rd_data, dbg_rd_data_cmp, and dbg_expected_data signals in the ILA. Check the pinout and look for any STUCK-AT-BITs, check vrp resistor, V REF resistor. Check BISC_PQTR, BISC_NQTR for starting offset between rising/falling clocks. Probe the board and check for the returning pattern to determine if the initial write to the DRAM happened properly, or if it is a read failure. Check ODT if it is a write issue.0xF Nibble BitTimeout error waiting for read data to return.Check the dbg_cal_seq_rd_cnt and dbg_cal_seq_cnt.Table 38-16:Signals of Interest for Read Deskew CalibrationSignalUsage Signal Description RDLVL_DESKEW_PQTR_NIBBLE*One per nibble Read leveling PQTR when left edge of read data valid window is detected during per bit read DQ deskew. RDLVL_DESKEW_NQTR_NIBBLE*One per nibble Read leveling NQTR when left edge of read data valid window is detected during per bit read DQ deskew.。

赛灵思半导体（深圳）7Series FPGAs Data Sheet: Overview Digital Signal Processing — DSP SliceSome highlights of the DSP functionality include:•25×18 two's complement multiplier/accumulator high-resolution (48bit) signal processor•Power saving pre-adder to optimize symmetrical filter applications•Advanced features: optional pipelining, optional ALU, and dedicated buses for cascadingDSP applications use many binary multipliers and accumulators, best implemented in dedicated DSP slices. All 7series FPGAs have many dedicated, full custom, low-power DSP slices, combining high speed with small size while retaining system design flexibility.Each DSP slice fundamentally consists of a dedicated 25×18 bit two's complement multiplier and a 48-bit accumulator, both capable of operating up to 741MHz. The multiplier can be dynamically bypassed, and two 48-bit inputs can feed a single-instruction-multiple-data (SIMD) arithmetic unit (dual 24-bit add/subtract/accumulate or quad 12-bitadd/subtract/accumulate), or a logic unit that can generate any one of ten different logic functions of the two operands. The DSP includes an additional pre-adder, typically used in symmetrical filters. This pre-adder improves performance in densely packed designs and reduces the DSP slice count by up to 50%. The DSP also includes a 48-bit-wide Pattern Detector that can be used for convergent or symmetric rounding. The pattern detector is also capable of implementing96-bit-wide logic functions when used in conjunction with the logic unit.The DSP slice provides extensive pipelining and extension capabilities that enhance the speed and efficiency of many applications beyond digital signal processing, such as wide dynamic bus shifters, memory address generators, wide bus multiplexers, and memory-mapped I/O register files. The accumulator can also be used as a synchronous up/down counter.Input/OutputSome highlights of the input/output functionality include:•High-performance SelectIO technology with support for 1,866Mb/s DDR3•High-frequency decoupling capacitors within the package for enhanced signal integrity•Digitally Controlled Impedance that can be 3-stated for lowest power, high-speed I/O operationThe number of I/O pins varies depending on device and package size. Each I/O is configurable and can comply with a large number of I/O standards. With the exception of the supply pins and a few dedicated configuration pins, all other package pins have the same I/O capabilities, constrained only by certain banking rules. The I/O in 7series FPGAs are classed as high range (HR) or high performance (HP). The HR I/Os offer the widest range of voltage support, from 1.2V to 3.3V. The HP I/Os are optimized for highest performance operation, from 1.2V to 1.8V.HR and HP I/O pins in 7 series FPGAs are organized in banks, with 50 pins per bank. Each bank has one common V CCO output supply, which also powers certain input buffers. Some single-ended input buffers require an internally generated or an externally applied reference voltage (V REF). There are two V REF pins per bank (except configuration bank 0). A single bank can have only one V REF voltage value.Xilinx 7series FPGAs use a variety of package types to suit the needs of the user, including small form factor wire-bond packages for lowest cost; conventional, high performance flip-chip packages; and bare-die flip-chip packages that balance smaller form factor with high performance. In the flip-chip packages, the silicon device is attached to the package substrate using a high-performance flip-chip process. Controlled ESR discrete decoupling capacitors are mounted on the package substrate to optimize signal integrity under simultaneous switching of outputs (SSO) conditions.质量等级领域:宇航级IC、特军级IC、超军级IC、普军级IC、禁运IC、工业级IC，军级二三极管，功率管等;应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通信网络、电力工业以及大型工业设备祝您:工作顺利，生活愉快!以赛灵思半导体（深圳）有限公司提供的参数为例，以下为XC7K160T-3FBG676E的详细参数，仅供参考maximum payload size of up to 1,024 bytes. The integrated block interfaces to the integrated high-speed transceivers for serial connectivity and to block RAMs for data buffering. Combined, these elements implement the Physical Layer, Data Link Layer, and Transaction Layer of the PCI Express protocol.Xilinx provides a light-weight, configurable, easy-to-use LogiCORE™ IP wrapper that ties the various building blocks (the integrated block for PCI Express, the transceivers, block RAM, and clocking resources) into an Endpoint or Root Port solution. The system designer has control over many configurable parameters: lane width, maximum payload size, FPGA logic interface speeds, reference clock frequency, and base address register decoding and filtering.Xilinx offers two wrappers for the integrated block: AXI4-Stream and AXI4 (memory mapped). Note that legacy TRN/Local Link is not available in 7series devices for the integrated block for PCI Express. AXI4-Stream is designed for existing customers of the integrated block and enables easy migration to AXI4-Stream from TRN. AXI4 (memory mapped) is designed for Xilinx Platform Studio/EDK design flow and MicroBlaze™ processor based designs..ConfigurationThere are many advanced configuration features, including:•High-speed SPI and BPI (parallel NOR) configuration•Built-in MultiBoot and safe-update capability•256-bit AES encryption with HMAC/SHA-256 authentication•Built-in SEU detection and correction•Partial reconfigurationXilinx 7series FPGAs store their customized configuration in SRAM-type internal latches. There are up to 450Mb configuration bits, depending on device size and user-design implementation options. The configuration storage is volatile and must be reloaded whenever the FPGA is powered up. This storage can also be reloaded at any time by pulling the PROGRAM_B pin Low. Several methods and data formats for loading configuration are available, determined by the three mode pins.The SPI interface (x1, x2, and x4 modes) and the BPI interface (parallel-NOR x8 and x16) are two common methods used for configuring the FPGA. Users can directly connect an SPI or BPI flash to the FPGA, and the FPGA's internal configuration logic reads the bitstream out of the flash and configures itself. The FPGA automatically detects the bus width on the fly, eliminating the need for any external controls or switches. Bus widths supported are x1, x2, and x4 for SPI, and x8 and x16 for BPI. The larger bus widths increase configuration speed and reduce the amount of time it takes for the FPGA to start up after power-on. Some configuration options such as BPI are not supported in all device-package combinations. Refer to UG470, 7 Series FPGAs Configuration User Guide for details.In master mode, the FPGA can drive the configuration clock from an internally generated clock, or for higher speed configuration, the FPGA can use an external configuration clock source. This allows high-speed configuration with the ease of use characteristic of master mode. Slave modes up to 32 bits wide are also supported by the FPGA that are especially useful for processor-driven configuration.The FPGA has the ability to reconfigure itself with a different image using SPI or BPI flash, eliminating the need for an external controller. The FPGA can reload its original design in case there are any errors in the data transmission, ensuring an operational FPGA at the end of the process. This is especially useful for updates to a design after the end product has been shipped. Customers can ship their products with an early version of the design, thus getting their products to market faster. This feature allows customers to keep their end users current with the most up-to-date designs while the product is already in the field.The dynamic reconfiguration port (DRP) gives the system designer easy access to the configuration and status registers of the MMCM, PLL, XADC, transceivers, and integrated block for PCI Express. The DRP behaves like a set of memory-mapped registers, accessing and modifying block-specific configuration bits as well as status and control registers.The Spartan-7 FPGA ordering information is shown in Figure1. Refer to the Package Marking section of UG475, 7 Series FPGAs Packaging and Pinout for a more detailed explanation of the device markings.Figure 1:Spartan-7 FPGA Ordering InformationThe Artix-7, Kintex-7, and Virtex-7 FPGA ordering information, shown in Figure2, applies to all packages including Pb-Free. Refer to the Package Marking section of UG475, 7 Series FPGAs Packaging and Pinout for a more detailed explanation of the device markings.Figure 2:Artix-7, Kintex-7, and Virtex-7 FPGA Ordering Information赛灵思半导体（深圳）。

General Description7series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7series FPGAs include:•Spartan®-7 Family: Optimized for low cost, lowest power, and high I/O performance. Available in low-cost, very small form-factorpackaging for smallest PCB footprint.•Artix®-7 Family: Optimized for low power applications requiring serial transceivers and high DSP and logic throughput. Provides the lowest total bill of materials cost for high-throughput, cost-sensitiveapplications.•Kintex®-7 Family: Optimized for best price-performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs.•Virtex®-7 Family: Optimized for highest system performance and capacity with a 2X improvement in system performance. Highestcapability devices enabled by stacked silicon interconnect (SSI)technology.Built on a state-of-the-art, high-performance, low-power (HPL), 28nm, high-k metal gate (HKMG) process technology, 7series FPGAs enable an unparalleled increase in system performance with 2.9Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.Summary of 7Series FPGA Features•Advanced high-performance FPGA logic based on real 6-input look-up table (LUT) technology configurable as distributed memory.•36Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.•High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.•High-speed serial connectivity with built-in multi-gigabit transceivers from 600Mb/s to max. rates of 6.6Gb/s up to 28.05Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.• A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors.•DSP slices with 25x18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetriccoefficient filtering.•Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter.•Quickly deploy embedded processing with MicroBlaze™ processor.•Integrated block for PCI Express® (PCIe), for up to x8 Gen3 Endpoint and Root Port designs.•Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.•Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flip-chip packaging offering easy migration between family members in the same package. All packages available in Pb-free and selected packages in Pb option.•Designed for high performance and lowest power with 28nm, HKMG, HPL process, 1.0V core voltage process technology and0.9V core voltage option for even lower power.7Series FPGAs Data Sheet: Overview DS180 (v2.6) February 27, 2018Product SpecificationTable 1:7Series Families ComparisonMax. Capability Spartan-7Artix-7Kintex-7Virtex-7Logic Cells102K215K478K1,955KBlock RAM(1) 4.2Mb13Mb34Mb68MbDSP Slices 1607401,9203,600DSP Performance(2)176 GMAC/s929GMAC/s2,845GMAC/s5,335GMAC/s MicroBlaze CPU(3)260 DMIPs303 DMIPs438 DMIPs441 DMIPs Transceivers–163296Transceiver Speed– 6.6Gb/s12.5Gb/s28.05Gb/sSerial Bandwidth–211Gb/s800Gb/s2,784Gb/sPCIe Interface–x4 Gen2x8 Gen2x8 Gen3Memory Interface800Mb/s1,066Mb/s1,866Mb/s1,866Mb/sI/O Pins400500500 1,200I/O Voltage 1.2V–3.3V 1.2V–3.3V 1.2V–3.3V 1.2V–3.3VPackage Options Low-Cost, Wire-Bond Low-Cost, Wire-Bond,Bare-Die Flip-Chip Bare-Die Flip-Chip and High-Performance Flip-ChipHighest PerformanceFlip-ChipNotes:1.Additional memory available in the form of distributed RAM.2.Peak DSP performance numbers are based on symmetrical filter implementation.3.Peak MicroBlaze CPU performance numbers based on microcontroller preset.赛灵思半导体（深圳）质量等级领域:宇航级IC、特军级IC、超军级IC、普军级IC、禁运IC、工业级IC，军级二三极管，功率管等;应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通信网络、电力工业以及大型工业设备祝您:工作顺利，生活愉快!以赛灵思半导体（深圳）有限公司提供的参数为例，以下为XC7K325T-3FFG676E的详细参数，仅供参考Spartan-7 FPGA Feature Summary Table 2:Spartan-7 FPGA Feature Summary by DeviceDevice LogicCellsCLBDSPSlices(2)Block RAM Blocks(3)CMTs(4)PCIe GT XADCBlocksTotal I/OBanks(5)Max UserI/O Slices(1)MaxDistributedRAM (Kb)18Kb36Kb Max(Kb)XC7S66,000938701010518020002100 XC7S1512,8002,00015020201036020002100 XC7S2523,3603,6503138090451,62030013150 XC7S5052,1608,150600120150752,70050015250 XC7S7576,80012,000832140180903,24080018400 XC7S100102,40016,0001,1001602401204,32080018400 Notes:1.Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.2.Each DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.3.Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.4.Each CMT contains one MMCM and one PLL.5.Does not include configuration Bank 0.Table 3:Spartan-7 FPGA Device-Package Combinations and Maximum I/OsPackage CPGA196CSGA225CSGA324FTGB196FGGA484FGGA676Size (mm)8 x 813 x 1315 x 1515 x 1523 x 2327 x 27Ball Pitch(mm)0.50.80.8 1.0 1.0 1.0 Device HR I/O(1)HR I/O(1)HR I/O(1)HR I/O(1)HR I/O(1)HR I/O(1)XC7S6100100100XC7S151********XC7S25150150100XC7S50210100250XC7S75338400XC7S100338400Notes:1.HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V.Device LogicCells Configurable Logic Blocks(CLBs)DSP48E1Slices(2)Block RAM Blocks(3)CMTs(4)PCIe(5)GTPsXADCBlocksTotal I/OBanks(6)Max UserI/O(7) Slices(1)MaxDistributedRAM (Kb)18Kb36Kb Max(Kb)XC7A12T12,8002,00017140402072031213150 XC7A15T16,6402,60020045502590051415250 XC7A25T23,3603,6503138090451,62031413150 XC7A35T33,2805,20040090100501,80051415250 XC7A50T52,1608,150600120150752,70051415250 XC7A75T75,52011,8008921802101053,78061816300 XC7A100T101,44015,8501,1882402701354,86061816300 XC7A200T215,36033,6502,88874073036513,14010116110500 Notes:1.Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.2.Each DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.3.Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.4.Each CMT contains one MMCM and one PLL.5.Artix-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2.6.Does not include configuration Bank 0.7.This number does not include GTP transceivers.Table 5:Artix-7 FPGA Device-Package Combinations and Maximum I/OsPackage(1)CPG236CPG238CSG324CSG325FTG256SBG484FGG484(2)FBG484(2)FGG676(3)FBG676(3)FFG1156 Size (mm)10 x 1010 x 1015 x 1515 x 1517 x 1719 x 1923 x 2323 x 2327 x 2727 x 2735 x 35 Ball Pitch(mm)0.50.50.80.8 1.00.8 1.0 1.0 1.0 1.0 1.0Device GTP(4)I/OGTP(4)I/OGTP(4)I/OGTP(4)I/OGTP(4)I/OGTPI/OGTP(4)I/OGTPI/OGTP(4)I/OGTPI/OGTPI/O HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)XC7A12T21122150XC7A15T21060210415001704250XC7A25T21124150XC7A35T21060210415001704250XC7A50T21060210415001704250XC7A75T0210017042858300XC7A100T0210017042858300XC7A200T42854285840016500 Notes:1.All packages listed are Pb-free (SBG, FBG, FFG with exemption 15). Some packages are available in Pb option.2.Devices in FGG484 and FBG484 are footprint compatible.3.Devices in FGG676 and FBG676 are footprint compatible.4.GTP transceivers in CP, CS, FT, and FG packages support data rates up to 6.25Gb/s.5.HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V.Device LogicCellsConfigurable LogicBlocks (CLBs)DSPSlices(2)Block RAM Blocks(3)CMTs(4)PCIe(5)GTXs XADCBlocksTotal I/OBanks(6)MaxUserI/O(7) Slices(1)MaxDistributedRAM (Kb)18Kb36Kb Max (Kb)XC7K70T65,60010,2508382402701354,86061816300 XC7K160T162,24025,3502,18860065032511,70081818400 XC7K325T326,08050,9504,00084089044516,02010116110500 XC7K355T356,16055,6505,0881,4401,43071525,740612416300 XC7K410T406,72063,5505,6631,5401,59079528,62010116110500 XC7K420T416,96065,1505,9381,6801,67083530,060813218400 XC7K480T477,76074,6506,7881,9201,91095534,380813218400 Notes:1.Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.2.Each DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.3.Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18 Kb blocks.4.Each CMT contains one MMCM and one PLL.5.Kintex-7 FPGA Interface Blocks for PCI Express support up to x8 Gen 2.6.Does not include configuration Bank 0.7.This number does not include GTX transceivers.Table 7:Kintex-7 FPGA Device-Package Combinations and Maximum I/OsPackage(1)FBG484 FBG676(2)FFG676(2) FBG900(3)FFG900(3)FFG901FFG1156 Size (mm)23 x 2327 x 2727 x 2731 x 3131 x 3131 x 3135 x 35 Ball Pitch(mm) 1.0 1.0 1.0 1.0 1.0 1.0 1.0Device GTX(4)I/O GTX(4)I/OGTXI/O GTX(4)I/OGTXI/OGTXI/OGTXI/OHR(5)HP(6)HR(5)HP(6)HR(5)HP(6)HR(5)HP(6)HR(5)HP(6)HR(5)HP(6)HR(5)HP(6)XC7K70T41851008200100XC7K160T418510082501508250150XC7K325T825015082501501635015016350150XC7K355T243000XC7K410T825015082501501635015016350150XC7K420T283800324000 XC7K480T283800324000 Notes:1.All packages listed are Pb-free (FBG, FFG with exemption 15). Some packages are available in Pb option.2.Devices in FBG676and FFG676are footprint compatible.3.Devices in FBG900and FFG900 are footprint compatible.4.GTX transceivers in FB packages support the following maximum data rates: 10.3Gb/s in FBG484; 6.6Gb/s in FBG676 and FBG900. Refer to Kintex-7 FPGAs Data Sheet:DC and AC Switching Characteristics (DS182) for details.5.HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V.6.HP = High-performance I/O with support for I/O voltage from 1.2V to 1.8V.Table 8:Virtex-7 FPGA Feature SummaryDevice(1)LogicCellsConfigurable LogicBlocks (CLBs)DSPSlices(3)Block RAM Blocks(4)CMTs(5)PCIe(6)GTX GTH GTZXADCBlocksTotal I/OBanks(7)MaxUserI/O(8)SLRs(9) Slices(2)MaxDistributedRAM (Kb)18Kb36Kb Max(Kb)XC7V585T582,72091,0506,9381,260 1,590795 28,6201833600117850N/A XC7V2000T1,954,560305,40021,5502,160 2,5841,29246,51224436001241,2004XC7VX330T326,40051,0004,3881,1201,50075027,0001420280114700N/A XC7VX415T412,16064,4006,5252,1601,76088031,6801220480112600N/A XC7VX485T485,76075,9008,1752,8002,0601,03037,0801445600114700N/A XC7VX550T554,24086,6008,7252,8802,3601,18042,4802020800116600N/A XC7VX690T693,120108,30010,8883,6002,9401,47052,92020308001201,000N/A XC7VX980T979,200153,00013,8383,6003,0001,50054,0001830720118900N/A XC7VX1140T1,139,200178,00017,7003,3603,7601,88067,68024409601221,1004XC7VH580T580,48090,7008,8501,6801,88094033,84012204881126002XC7VH870T876,160136,90013,2752,5202,8201,41050,76018307216163003 Notes:1.EasyPath™-7 FPGAs are also available to provide a fast, simple, and risk-free solution for cost reducing Virtex-7 T and Virtex-7 XT FPGA designs2.Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.3.Each DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.4.Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18 Kb blocks.5.Each CMT contains one MMCM and one PLL.6.Virtex-7 T FPGA Interface Blocks for PCI Express support up to x8 Gen 2. Virtex-7 XT and Virtex-7 HT Interface Blocks for PCI Express support up to x8 Gen 3, with theexception of the XC7VX485T device, which supports x8 Gen 2.7.Does not include configuration Bank 0.8.This number does not include GTX, GTH, or GTZ transceivers.9.Super logic regions (SLRs) are the constituent parts of FPGAs that use SSI technology. Virtex-7 HT devices use SSI technology to connect SLRs with 28.05 Gb/stransceivers.7Series FPGA Ordering InformationTable12 shows the speed and temperature grades available in the different device families. Some devices might not be available in every speed and temperature grade.Table 12:7 Series Speed Grade and Temperature RangesDevice Family DevicesSpeed Grade, Temperature Range, and Operating VoltageCommercial (C)0°C to +85°CExtended (E)0°C to +100°CIndustrial (I)–40°C to +100°CExpanded (Q)–40°C to +125°CSpartan-7All -2C (1.0V)-2I (1.0V)-1C (1.0V)-1I (1.0V)-1Q (1.0V)-1LI (0.95V)Artix-7All-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V or 0.9V)-1C (1.0V)-1I (1.0V)-1LI (0.95V)Kintex-7XC7K70T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V or 0.9V)-1C (1.0V)-1I (1.0V) XC7K160TXC7K325TXC7K355TXC7K410TXC7K420TXC7K480T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V or 0.9V)-2LI (0.95V)-1C (1.0V)-1I (1.0V)Virtex-7 TXC7V585T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V) XC7V2000T-2C (1.0V)-2GE (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V)Virtex-7 XTXC7VX330TXC7VX415TXC7VX485TXC7VX550TXC7VX690T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V) XC7VX980T-2C (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V) XC7VX1140T-2C (1.0V)-2GE (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V)Virtex-7 HT All -2C (1.0V)-2GE (1.0V)-2LE (1.0V) -1C (1.0V)The Spartan-7 FPGA ordering information is shown in Figure1. Refer to the Package Marking section of UG475, 7 Series FPGAs Packaging and Pinout for a more detailed explanation of the device markings.Figure 1:Spartan-7 FPGA Ordering InformationThe Artix-7, Kintex-7, and Virtex-7 FPGA ordering information, shown in Figure2, applies to all packages including Pb-Free. Refer to the Package Marking section of UG475, 7 Series FPGAs Packaging and Pinout for a more detailed explanation of the device markings.Figure 2:Artix-7, Kintex-7, and Virtex-7 FPGA Ordering InformationRevision HistoryThe following table shows the revision history for this document:Date Version Description of Revisions06/21/10 1.0Initial Xilinx release.07/30/10 1.1Added SHA-256 to authentication information. Updated Table5, Table7, Virtex-7 FPGA Device-Package Combinations and Maximum I/Os table (Virtex-7 T devices), and Table9 with ball pitchinformation and voltage bank information. Updated DSP and Logic Slice information in Table8.Updated Low-Power Gigabit Transceivers.09/24/10 1.2In General Description, updated 4.7TMACS DSP to 5.0TMACS DSP. In Table1, added Note 1;updated Peak DSP Performance for Kintex-7 and Virtex-7 families. In Table4, updated CMTinformation for XC7A175T and XC7A355T. In Table6, replaced XC7K120T with XC7K160T andreplaced XC7K230T with XC7K325T—and updated corresponding information. Also addedXC7K355T, XC7K420T, and XC7K480T. In Table7,replaced XC7K230T with XC7K325T. In Table8,updated XC7V450T Logic Cell, CLB, block RAM, and PCI information; updated XC7VX415T andXC7VX690T PCI information; updated XC7V1500T, and XC7V2000T block RAM information; andreplaced XC7VX605T with XC7VX575T, replaced XC7VX895T with XC7VX850T, and replacedXC7VX910T with XC7VX865T—and updated corresponding information. Updated Digital SignalProcessing — DSP Slice with operating speed of 640MHz.Removed specific transceiver type fromOut-of-Band Signaling. In Virtex-7 FPGA Device-Package Combinations and Maximum I/Os table(Virtex-7 T devices), replaced XC7VX605T with XC7VX575T and added table notes 2 and 3. InTable9, removed the FFG784 package for the XC7VX485T device; replaced XC7VX605T withXC7VX575T; replaced XC7VX895T with XC7VX850T; and replaced XC7VX910T with XC7VX865T.10/20/10 1.3In Table7, replaced XC7K120T with XC7K160T. Updated Digital Signal Processing — DSP Slice.11/17/10 1.4Updated maximum I/O bandwidth to 3.1 Tb/s in General Description. Updated Peak Transceiver Speedfor Virtex-7 FPGAs in Summary of 7Series FPGA Features and in Table1. Updated Peak DSPPerformance values in Table1 and Digital Signal Processing — DSP Slice. In Table7, updatedXC7K70T I/O information. In Table8, added XC7VH290T, XC7VH580T, and XC7VH870T devices andupdated total I/O banks information for the XC7V585T, XC7V855T, XC7V1500T, and XC7VX865Tdevices. In Table9, updated XC7VX415T, XC7VX485T, XC7VX690T, XC7VX850T, and XC7VX865Tdevice information. Added Table11. Updated Low-Power Gigabit Transceivers information, includingthe addition of the GTZ transceivers.02/22/11 1.5Updated Summary of 7Series FPGA Features and the Low-Power Gigabit Transceivers highlights andsection. In Table1, updated Kintex-7 FPGA, Artix-7 FPGA information. In Table4, updated XC7A175T.Also, updated XC7A355T.Added three Artix-7 FPGA packages to Table5: SBG325, SBG484, andFBG485, changed package from FGG784 to FBG784, and updated package information forXC7A175T and XC7A355T devices. In Table6, updated XC7K160T and added three devices:XC7K355T, XC7K420T, and XC7K480T. In Table7, updated XC7K70T package information and addedthree devices: XC7K355T, XC7K420T, and XC7K480T. In Table8, added note 1 (EasyPath FPGAs)and updated note 7 to include GTZ transceivers. In Virtex-7 FPGA Device-Package Combinations andMaximum I/Os table (Virtex-7 T devices), added two Virtex-7 FPGA packages: FHG1157 andFHG1761, and updated XC7V1500T (no FFG1157) and XC7V2000T (no FFG1761) packageinformation and removed the associated notes. Added CLBs, Slices, and LUTs. Updated Input/Output.Added EasyPath-7 FPGAs.03/28/11 1.6Updated G eneral Description, Summary of 7Series FPG A Features, Table1, Table4, Table5, Table6,Table7, Table8, Table9 (combined Virtex-7 T and XT devices in one table), and Table11. Updated theLow-Power Gigabit Transceivers highlights and section. Updated Block RAM, Integrated InterfaceBlocks for PCI Express Designs, Configuration, Encryption, Readback, and Partial Reconfiguration,XADC (Analog-to-Digital Converter), 7Series FPGA Ordering Information, and EasyPath-7 FPGAs.07/06/11 1.7Updated G eneral Description, Summary of 7Series FPG A Features, Table1, Table4, Table6, Table8,Table9 and Table11. Added Table10. Added Stacked Silicon Interconnect (SSI) Technology. UpdatedTransmitter, Configuration, and XADC (Analog-to-Digital Converter). Updated Figure1.09/13/11 1.8Updated General Description, Table1, Table4, Table5, Table8, CLBs, Slices, and LUTs,Configuration, and 7Series FPGA Ordering Information.01/15/12 1.9Updated General Description, Table1, Table4, Table5, Table6, Table7, Table8, Table10, Table11,Block RAM, Digital Signal Processing — DSP Slice, Low-Power Gigabit Transceivers, IntegratedInterface Blocks for PCI Express Designs, Configuration, EasyPath-7 FPGAs, and 7Series FPGAOrdering Information.Date Version Description of Revisions03/02/12 1.10Updated General Description, Table5, and Table12.05/02/12 1.11Updated Table7, Table9, Table10, Low-Power Gigabit Transceivers, and 7Series FPGA OrderingInformation. Added 7Series FPGA Ordering Information.10/15/12 1.12Updated overview with Artix-7 SL and SLT devices. Updated Table1, Table4, Table5, Table8, Table9,Table10, Table11, and Table12. Added Table 3. Updated Regional Clocks, Block RAM, IntegratedInterface Blocks for PCI Express Designs, Configuration, and 7Series FPGA Ordering Information.11/30/12 1.13Updated notes in Table4 and Table12. Updated XADC (Analog-to-Digital Converter).07/29/13 1.14Removed SL and SLT devices. Updated General Description, Table4, Table5, notes in Table6 andTable8, Regional Clocks, Input/Output, Low-Power Gigabit Transceivers, Integrated Interface Blocksfor PCI Express Designs, Configuration, and 7Series FPGA Ordering Information. Removed previousTable 3.02/18/14 1.15Changed document classification to Product Specification from Preliminary Product Specification.Updated HR I/O information for XC7A35T and XC7A50T in Table5. Updated XC7VH870T I/Oinformation in Table8. Updated Table11.10/08/14 1.16Added XC7A15T to Table4 and Table5. Removed HCG1931 and HCG1932 from Table11. UpdatedInput/Output Delay; Block RAM; Configuration; I/O Clocks; and Updated Table12 and Figure1.12/17/14 1.16.1Typographical edit.05/27/15 1.17Updated Table5, Table7, Table9, Table10, Table11, and Figure1.09/27/16 2.0Added Spartan-7 devices throughout document, including Table1, Table2, Table3, and Table12.Added two Artix-7 devices XC7A12T and XC7A25T throughout document, including Table4, Table5,and Table12. Updated General Description; Figure1, Table7, Regional Clocks, Block RAM,Integrated Interface Blocks for PCI Express Designs, Configuration, Encryption, Readback, and PartialReconfiguration, and XADC (Analog-to-Digital Converter).10/20/16 2.1Updated Table5.12/15/16 2.2Updated Table3.03/17/17 2.3Updated Table1, Table5, Table7, Table9, Table10, Table12, and I/O Electrical Characteristics.03/28/17 2.4Updated Table7.08/01/17 2.5Updated Table5 and Figure2.02/27/18 2.6Added MicroBlaze CPU information to the Summary of 7Series FPGA Features and Table1.Notice of DisclaimerThe information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRING EMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. 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Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at .Automotive Applications DisclaimerAUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIG N"). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.。

k6C5P 6.30.32508±3-8——9 2.220 6C6B 6.30.21209±2.7R k=220Ω——5525 6C7B 6.30.2250 4.5±1.3R k=400Ω——16465 6C16 6.30.315024R k=60Ω———24—6C31B-Q 6.30.225040±100——0.6520>13 6C32B-Q 6.30.162003±1.3R k=280Ω——28.5 3.5100 6N1 6.30.62507.5±2R k=600Ω——8 4.435 6N2 6.30.34250 2.3±0.9-1.5——46 2.197.5 6N3 6.30.351508.5-2—— 5.9 5.935 6N4 6.3/12.60.33/0.17250 2.3-1.5——46 2.197.5 6N5P 6.3 2.5±0.59060±3.5-30——450±150 4.5—6N6 6.30.7512030±10-2—— 1.81120±4 6N7P 6.30.83007±2-6——11 3.235 6N8P 6.30.62509-8——7.7 2.620 6N9P 6.30.3250 2.3-8——44 1.670 6N10 6.3/12.60.33/0.1625010.5R k=800Ω——7.7 2.217 6N11 6.30.349016R k=90Ω——21.612.527 6N12P 6.30.918023-7—— 2.4717 6N13P 6.3 2.59080±32-30——R i≤460Ω5—6N15 6.30.4510090R k=90Ω—— 6.8 5.638 6N16B 6.30.4100 6.3±1.9R k=325Ω——5525 6N17B 6.30.4100 3.3±1R k=325Ω——20 3.875 6N17B 6.30.4200 3.3±1R k=325Ω——20 3.875 6N21B-Q 6.30.4200 3.5±1.3R k=330Ω——21 4.290 6J1 6.30.171207R k=200Ω1203300 5.2—6J1B 6.30.21207.5R k=200Ω120 3.5— 4.8—6J2 6.30.17120 5.5R k=200Ω120 5.7130 3.7—6J2B 6.30.2120 5.5R k=200Ω120<6— 3.2—6J3 6.30.32507±3R k=200Ω150<37505—6J4 6.30.325011±3R k=68Ω150<6900 5.7—6NJ4P 6.30.4530010R k=160Ω150 2.5±1—9—6J5 6.30.4530010±4-2150<43509±3—6J8 6.30.22503-2±11400.5—2—6J8P 6.30.32503±1-31000.8— 1.7—6J9 6.30.315016R k=80Ω150<4.5—17.5—6J20 6.30.4515018+6——>3517—6J23 6.30.4415013.5R k=50Ω150<8—15±5—6J23B-Q 6.30.171206±2R k=200Ω120 1.4—6±2—12J1S12.675mA150 1.2~3.5075—— 1.0~2.5—6K1B 6.30.21207.5R k=200Ω120<4— 4.8—6K3P 6.30.32509-3100 2.5±1—2±0.4—6K4 6.30.325010±3R k=68Ω100<6850 4.4—6K5 6.30.325010±3R k=68Ω100<6850 4.4—12K3P 12.60.152509-3100 2.5±1—2±0.4—2P2 1.2/2.460mA/30mA 60 3.5±1.2-3.560<1.2—>0.9—2P3 1.4/2.80.2/0.113516±4-7.590≤3— 2.4—2P19B 2.20.11207.6-590<4— 1.7—2P29 2.20.111203045<1.2— 1.6—4P1S 4.20.3315060±20-3.5150≤6—6—6P1 6.30.525044±11-13250≤740 4.9—6P3P 6.30.925072-14250≤8 4.36—6P4P 6.30.925072-14250≤8—6—6P6P 6.30.4525045-12250≤7524—6P9P 6.30.6530030±10-3150 6.5—11.7—6P13P 6.3 1.320060-19200≤8258.5—6P14 6.30.7625048R k =120Ω250≤7389—6P15 6.30.7630030±8R k =75Ω150<610012256P25B 6.30.4511030±7-8110<4— 4.2—6P30B-Q 6.30.4712030±8R k =330Ω120<2— 4.5—6P31B-Q 6.30.4712030±8R k =330Ω120<3— 3.4—13P1P 130.752642±10026<4 1.57.5—6P27P 6.3 1.537538-14256<7—9—6S6 6.30.5415046±12R k =30Ω150<14834—6T1 6.30.415015±4R k =120Ω120<4606—6A26.30.32503±1-1.51007>0.3>0.3—6F1三极部分10013±5-2——45206F1五极部分17010-2170<4.5400 6.2(2)6F2三极部分15018±6R k =56Ω——58.5406F2五极部分25010±3R k =68Ω110<5.5400 5.2—6G2P二极部分0>0.2——————6G2P三极部分250 1.2-2——91 1.1100WE-300B 30062-61——0.74 5.3WE-300B 35060-74——0.795FU-5103±0.5 1.5k 74-10——— 4.5—FU-5F 12.622±2——-300—— 5.815±357~85FU-7 6.30.660036±12-293004—6±1—FU-13105±0.32k 50±15-100400——4±0.9—FU-17 6.3/12.60.8/0.430023±13—2006— 3.2±17FU-2512.60.4560036±12-293004—6±1—FU-29 6.3/12.6 2.2/1.125036±13-11/-10017513———FU-317.55—————10 3.335FU-32 6.3/12.6 1.6/0.825032±14-10/-100135<5.514——FU-331010±0.83k 100±40-50————35FU-15 4.4/2.20.68/1.3525090±30-14±6200<9— 4.7±1.3—FU-46 6.3 1.25±0.240080±16-40195<2546±1.2—FU-5012.60.7±0.180050-40±15250<7 3.33~5.2—FU-8012.6112k 200—600<200— 5.5±1—FU-811 6.34 1.5k 26±10-20——— 3.6160FU-250F 26.50.581k 150-38±73005—12—6336A 240—— 1.75—EL81 6.3 1.0520050-3.152004 2.5——8550 6.3 1.6600100-35300584510 3.251k 90-145—— 1.73.16.36.36.350.420.450.31.26CA7 6.3 1.54502*45-20450117092100——FD422 6.3 1.560050-6545 5.584510 3.251k 40-175—— 3.16.30.75250 1.2-3——52 1.3686.30.7515030R k =620Ω——0.92 5.456.30.7520024-8.5125 5.27010—6.30.751509.2-5——8.7 4.64018045180.1321020-3210<5.5—11—FC4 6.30.5250 2.2-3—— 2.715406C22D 6.30.13525018R k =75Ω——8.6 6.5566.3 1.6250140-148.86.3 1.6600115-3130045.56.3 1.6250140-148.86.3 1.645090-4568.8PL8121.50.320050-31.52004 2.5——EL34 6.3 1.525090-13.5250——11—EL84 6.30.763002*24-11300————2A3 2.5 2.525060-45——— 5.3—21110 3.25100-70——— 3.6—572B 6.342k 21-20——— 3.6—F-81010 4.5 1.2k 90-20——— 4.2—FU-812 6.34 1.2k 30-30———4.2—58816.30.925072-146—KT1006CY76CX86550g6.9 5.7350 2.75——6.9 5.7250 1.4——R g<1MΩ6.9 5.7300 1.45——R g<1MΩ6.9 5.7—4——7 5.7100 2.5——R g<1MΩ7 5.7250 4.5——R g<2MΩ7 5.7300 2.2——R g<1MΩ7 5.73001——R g<0.5MΩ7 5.7300 1.5——R g<1MΩ7 5.73001——R g<0.5MΩ6.9 5.725013——功率双极管7—300 4.8——R g<1MΩ6.9 5.73006——功放6.9 5.7330 2.75——R g<0.5MΩ6.9 5.7275 1.1——R g<0.5MΩ6.9/13.8 5.7/11.4250 2.5——6.9 5.71302——R g<1MΩ6.9 5.7300 4.2——R g<100kΩ6.9 5.730013——R g<1MΩ7 5.7300 1.6——R g<100kΩ6.9 5.72000.9——R g<1MΩ6.9 5.72500.9——R g<1MΩ6.9 5.72500.9——R g<1MΩ7 5.72501——R g<2MΩ7 5.7200 1.81500.55R g<1MΩ6.9 5.7150 1.21250.4R g<1MΩ7 5.7200 1.81500.9R g<1MΩ6.9 5.71500.91250.7R g<1MΩ7 5.7330 2.51650.55R g<1MΩ7 5.7300 3.51500.96.9 5.7330 3.3165—7 5.7300 3.61500.5R g<0.5MΩ7 5.730012000.2R g<2.2MΩ7 5.7330 2.81400.7R g<500kΩ7 5.7250316000.75R g<1MΩ7 5.7200 3.5——6.9 5.7150 2.5150 1.2R g<300kΩ7 5.7150 1.21500.5R g<1MΩ14.510.825022250.7P o≥0.4W6.9 5.7150 1.21250.3R g<1MΩ6.9 5.7300 4.41400.447 5.730031250.6R g<500kΩ7 5.730031250.6R g<500kΩ13.811.4330 4.41400.441.4/2.80.9/1.8900.490—P o ≥50mW 1.54/3.081.26/2.5215021350.5P o ≥0.5W 2.5 1.820011300.352.4220011200.34.7 3.92507.5250 1.5R g <500k Ω7 5.725012250 2.5R g <500k Ω7 5.740020330 2.7R g <500k Ω7 5.740020300 2.8P o ≥5W 6.9 5.735013310 2.2P o >3.6W 7 5.73309330 1.5P o >2.4W 6.9 5.745014—47 5.7300123002P o >3W 7 5.733012330 1.5R g <1M Ω6.9 5.7155 3.71550.7P o ≥0.75W 7 5.7250 5.52502R g <1M Ω7 5.7250 5.52502R a =2k Ω14.311.71106801P o =0.2~0.6W 7 5.7300123002P o >3W 6.9 5.72508.3250 2.3三极管接法 μ=366.9 5.7250 3.5165 1.8R g <100k Ω6.9 5.7330 1.1110 1.10.3mA/V 为变频互导250 1.5——R g <500k Ω250 2.51750.7括号中(z)为变频互导300 2.7——R g <1M Ω300 2.83000.5————I e >0.8mA 3300.5——330——状态Ⅰ360——状态Ⅱ10.59.5 1.5k 125——P o =150W 12.6—5k 2.5k ——P o =3.5kW 7 5.760025300 3.5F m ≥60MHz 10.59.52k 100400226.9/14 5.7/11.4400625031411.460025300 3.5P o =33W 7/14 5.7/11.4750402257两管U go 不同——1k 50——P o =95W 7.0/14 5.7/11.4500152505P o =7W 10.59.5 3.3k 300——P o =800W 4.8/2.4 4.0/2.0400152504P o ≥11W 6.9 5.775252503P o =55W 13.911.31k 402505P o ≥50W 13.411.83k 450600120P o >600W 6.66 1.2k 40——P o >130W 27.525.22k 160~2504008~12P o ≈200W P o =25W 75.730052501P o =20W P o =100W P o =24W(A类)6.96.96.95.5 5.75.75.75.7P o =40W P o =200W P o =50W 10.59.5——P o =75W(AB 1)6.9 5.7——第二组三极管6.9 5.7——第一组三极管6.9 5.7五极管部分6.9 5.7——三极管部分20 6.3R L =51k 五极管7 5.730015——R g <500k Ω6.9 5.730025——R g <100k Ω7 5.7P o =12单管甲类7 5.7PP(AB 1类)7 5.7P o =12单管甲类7 5.7P o =90PP(AB 1类)7 5.730052501PP(B类)6.9 5.7A类6.9 5.7三极管接法/AB1-PP2.7 2.3三极管10.59.5三极管7 5.7 2.2k 三极管10.59.5 1.5k 三极管6.9 5.8 1.5k 三极管6.9 5.7350束射四极管A类时,Po≈4W A类时,Po≈100W(AB1类PP)Po≈160W Po≈180W Po≈130W Po≈5.4。

Table 1-2 lists the 21 dedicated I/O pins.Serial Transceiver Channels by Device/PackageSpartan-7 FPGAs do not contain serial transceivers. Table 1-3 lists the quantity of GTP serial transceiver channels for the Artix-7 FPGAs.Table 1-2:7Series FPGAs I/O Pins in the Dedicated Configuration Bank (Bank0)DXP_0VCCBATT_0INIT_B_0M0_0TDO_0TDI_0GNDADC_0(1)DXN_0DONE_0VN_0M1_0TCK_0VREFN_0VCCADC_0(1)PROGRAM_B_0CCLK_0VP_0M2_0TMS_0VREFP_0CFGBVS_0Notes:1.In SSI technology devices, GNDADC and VCCADC do not have an _0 in the pin name.Table 1-3:Serial Transceiver Channels (GTPs) by Device/Package (Artix-7 FPGAs)DeviceGTP Channels by PackageCPG 236CPG 238CSG 324CSG 325FTG 256SBG SBV 484FGG 484FGG 676FBG FBV 484FBG FBV 676FFG FFV 1156RS 484RB 484RB 676XA7A12T –2–2––––––––––XC7A15T 2040–4–––––––XC7A25T –2–4–––––––––XC7A35T 2–040–4–––––––XC7A50T 2–040–4–––––––XC7A75T ––0–0–48––––––XC7A100T ––0–0–48––––––XC7A200T –––––4––4816–––XA7A12T –2–2––––––––––XA7A15T 2–040–4–––––––XA7A25T –2–4–––––––––XA7A35T 2–04––––––––––XA7A50T 2–04––––––––––XA7A75T ––0–––4–––––––XA7A100T ––0–––4–––––––XQ7A50T –––4––4–––––––XQ7A100T ––0–––4–––––––XQ7A200T–––––––––––448DeviceGTX Channels by PackageFBG484FBV484FBG676FBV676FBG900FBV900FFG676FFV676FFG900FFV900FFG901FFV901FFG1156FFV1156RF676RF900XC7K70T48–––––––XC7K160T48–8–––––XC7K325T–816816––––XC7K355T–––––24–––XC7K410T–816816––––XC7K420T–––––2832––XC7K480T–––––2832––XA7K160T–––8–––––XQ7K325T–––––––816 XQ7K410T–––––––816Device FFG1157FFG1761FLG1925FHG1761RF1157RF1761 XC7V585T2036––––XC7V2000T––1636––XQ7V585T––––2036Die Level Bank Numbering OverviewBanking and Clocking Summary•The center clocking backbone contains all vertical clock tracks and clock buffer connectivity.•The CMT backbone contains all vertical CMT connectivity and is located in the CMT column.•Not all banks are bonded out in every part/package combination.•GTP/GTX/GTH columns summary°One GT Quad=Four transceivers=Four GTPE2 or GTXE2 or GTHE2 primitives.°Not all GT Quads are bonded out in every package.•I/O banks summary°Each bank has four pairs of clock capable (CC) inputs for four differential or fourXC7A200T and XQ7A200T BanksFigure1-10 shows the I/O and transceiver banks.SBG484, SBV484, and RS484 Packages•HR I/O bank 13 is partially bonded out.•HR I/O banks 12, 32, 33, and 36 are not bonded out.•The GTP Quads 113, 116, and 213 are not bonded out.FBG484, FBV484, and RB484 Packages•HR I/O bank 13 is partially bonded out.•HR I/O banks 12, 32, 33, and 36 are not bonded out.•The GTP Quads 113, 116, and 213 are not bonded out.FBG676, FBV676, and RB676 Packages•HR I/O banks 32 and 36 are not bonded out.•The GTP Quads 113 and 116 are not bonded out.FFG1156 and FFV1156 Package (XC7A200T only)All HR I/O banks and the GTP Quads are fully bonded out in this package.Figure 1-10:XC7A200T and XQ7A200T Banks。

Product Discontinuation Notice for Selective FFV, FBV and SBV Device PackagesXCN20011 (v1.0) September 28, 2020Product Discontinuation NoticeOverviewThe purpose of this notification is to communicate that Xilinx ® is discontinuing selective FFV, FBV and SBV packages for Virtex ®-5, Virtex ®-6, Virtex ®-7, Artix ®-7, Kintex ®-7 and Zynq ®-7000 devices. This product discontinuation notice (PDN) is to streamline duplicate product offerings to customers since packages are fully compatible with FFG, FBG and SBG package products.DescriptionXilinx has fully transitioned to supply lead-free flip chip products denoted by the package code FFG, FBG, SBG (“G” packages) that comply with the European Union’s RoHS 2 directive (2011/95/EU) as stated in the product change notice released in 2016 (Refer to XCN16022).Therefore, these selective part numbers will be discontinued with replacement parts as shown in Table 1 through Table 6.This notice should be used in conjunction with previous discontinuance notices which can be found .Products AffectedThe products affected include all standard part numbers and specification control document (SCD) versions of the standard part numbers listed in this notice.Product Discontinuation Notice for Selective FFV, FBV and SBV Device PackagesProduct Discontinuation Notice for Selective FFV, FBV and SBV Device PackagesProduct Discontinuation Notice for Selective FFV, FBV and SBV Device PackagesProduct Discontinuation Notice for Selective FFV, FBV and SBV Device PackagesKey Dates and Ordering Information•Final orders (LTB) will be accepted until October 2nd, 2021, subject to material availability.•An order remaining open on or after August 2nd, 2021 will be deemed Non-Cancellable, Non-Returnable (NCNR).•Final deliveries (LTS) must occur on or before April 2nd, 2022.•Return Material Authorizations (RMA) for replacement devices due to quality issues will be accepted until October 2nd, 2022.Revision HistoryThe following table shows the revision history for this document.Date Version Revision09/28/2020 v1.0 Initial release.。