TD82795 datasheet

3W防失真、超低EMI立体声D类音频功放版本变更记录3W防失真、超低EMI立体声D类音频功放目录1. 特点 (3)2. 概述 (3)3. 应用领域 (4)4. 引脚 (4)4.1. 引脚定义 (4)4.2. 引脚描述 (4)5. 结构框图 (5)6. 典型应用电路 (6)7. 电气特性 (6)7.1 极限参数 (6)7.2 典型参数 (7)7.3 直流特性 (7)7.4 交流特性 (7)7.5 模拟特性 (8)8. 应用信息 (8)8.1工作模式 (8)8.2防失真功能（NCN） (9)8.3电源退耦 (10)8.4输入电容 (10)8.5模拟基准旁路电容（C BYP） (10)8.6电源开启/关闭时噼噗噪声 (11)8.7欠压锁定（UVLO） (11)8.8短路电流保护（SCP） (11)8.9过温保护（OTP） (11)8.10电磁辐射（EMI） (11)9. 封装尺寸 (12)3W防失真、超低EMI立体声D类音频功放EG8405芯片数据手册V1.01. 特点⏹防失真功能⏹宽的工作电源2.5V-5.5V⏹超优异的全带宽EMI抑制性能⏹免LC滤波器数字调制，直接驱动扬声器⏹高输出功率：3.0W@PVDD=VDD=5.0V,R L=4Ω，THD+N=10%⏹高效率：88%@PVDD=VDD=5.0V, R L=4Ω，P O=1W⏹低THD+N：0.1%@PVDD=VDD=5.0V, R L=4Ω，P O=1W⏹通道隔离度：80dB@f IN=1KHz,A V=18dB⏹高信噪比SNR: 90dB@ PVDD=VDD=5.0V, A V=18dB⏹优异的“噼噗-咔嗒”（Pop-Click）噪声抑制性能⏹关断功能⏹过流保护功能⏹过热保护功能⏹欠压保护功能⏹无铅SOP16封装2. 概述EG8405是一款带防失真功能且具有超低EMI的立体声免输出滤波器D类音频功率放大器。

在电源电压5V、THD+N=10%、4Ω负载的条件下，输出高达3W的功率，在性能与AB类放大器相媲美的同时，效率高达88%。

UTC LM79XXLINEAR INTEGRATED CIRCUITUTC UNISONIC TECHNOLOGIES CO., LTD.1QW-R101-007,B3 TERMINAL 1A NEGATIVE VOLTAGE REGULATORDESCRIPTIONThe UTC LM79XX series of three-terminal negativeregulators are available in TO-220 package and with several fixed output voltage, making them useful in a wide range of application. Each type employs internal current limiting, thermal shut-down and safe area protection, making it essentially indestructible.FEATURES*Output current up to 1A*-5V;-6V;-8V;-12V;-15V;-18V;-24V output voltage available *Thermal overload protection *Short circuit protection1:GND 2:Input 3:OutputBLOCK DIAGRAMUTC LM79XXLINEAR INTEGRATED CIRCUITUTC UNISONIC TECHNOLOGIES CO., LTD.2QW-R101-007,BABSOLUTE MAXIMUM RATINGS (Ta=25°C) PARAMETER SYMBOLVALUE UNITInput voltageVi -35 V Thermal resistance junction-airR θ JA 65 °C /W Thermal resistance junction-casesR θ JC 5 °C /W Operating Temperature Topr 0 ~ +125 °C Storage TemperatureTstg-65 ~ +150°CUTC7905 ELECTRICAL CHARACTERISTICS(Refer to test circuits, 0<Tj<125°C ,Io=500mA,Vi=-10V,Ci=33uF,Co=1uF, unless otherwise specified)PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITTj=25°C-4.80-5.0 -5.20 V Output voltageVo 5.0mA<Io<1.0A,Po<15W Vi=-7V to -20V -4.75 -5.25VLine regulation ∆Vo Tj =25°C,Vi=-7V to -25V 10 100 mV Tj=25°C,Vi=-8V to -12VmV Load regulation ∆Vo Tj =25°C,Io=5.0mA to 1.5A10 100 mV Tj=25°C,Io=250mA to 750mA 3 50 mV Quiescent current I Q Tj=25°C3 6 mA Quiescent current change ∆I QIo=5mA to 1.0A 0.05 0.5 mA Vi=-7V to -25V 0.1 1.3 mA Output voltage drift ∆Vo/∆T Io =5mA -0.4 mV/°C Output noise voltage V N f=10hz to 100kHz,Ta=25°C 100 µV Ripple rejection RR f=120Hz, Vi=-8V to -18V 54 60 dB Dropout voltage Vo Io=1.0A,Tj=25°C 2 V Short circuit current Isc Vi=-35V,Ta=25°C 300 mA peak current Ipk Tj=25°C2.2 AUTC7906 ELECTRICAL CHARACTERISTICS(Refer to test circuits, 0<Tj<125°C ,Io=500mA,Vi=-11V,Ci=2.2uF,Co=1uF,unless otherwise specified)PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITTj=25°C-5.76-6.00 -6.24 V Output voltageVo5.0mA<Io<1.0A,Po<15W Vi=-8V to -21V -5.70 -6.30 VLine regulation ∆Vo Tj =25°C,Vi=-8V to -25V10 120 mVTj=25°C,Vi=-9V to -13V5 60 mV Load regulation ∆Vo Tj =25°C,Io=5.0mA to 1.5A10 120 mVTj=25°C,Io=250mA to 750mA 3 60 mV Quiescent currentI Q Tj=25°C3 6 mA Quiescent current change ∆I QIo=5mA to 1.0A 0.5 mAVi=-8V to -25V 1.3 mAOutput voltage drift ∆Vo/∆T Io =5mA -0.5 mV/°COutput noise voltage V N f=10hz to 100kHz,Ta=25°C 130 µV Ripple rejection RR f=120Hz, Vi=-9V to -19V 54 60 dB Dropout voltage Vo Io=1.0A,Tj=25°C 2 V Short circuit current Isc Vi=-35V,Ta=25°C 300 mA peak currentIpk Tj=25°C2.2 AUTC LM79XX LINEAR INTEGRATED CIRCUITUTC UNISONIC TECHNOLOGIES CO., LTD.3QW-R101-007,BUTC7908 ELECTRICAL CHARACTERISTICS(Refer to test circuits, 0<Tj<125°C ,Io=500mA,Vi=-14V,Ci=2.2uF,Co=1uF,unless otherwise specified)PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITTj=25°C-7.68-8.0 -8.32 V Output voltageVo5.0mA<Io<1.0A,Po<15W Vi=-10.5V to -23V -7.60 -8.40 VLine regulation ∆Vo Tj =25°C,Vi=-10.5V to -25V 10 100 mV Tj=25°C,Vi=-11.5V to -17V5 80 mV Load regulation ∆Vo Tj =25°C,Io=5.0mA to 1.5A12 160 mV Tj=25°C,Io=250mA to 750mA4 80 mV Quiescent current I Q Tj=25°C3 6 mA Quiescent current change ∆I QIo=5mA to 1.0A 0.05 0.5 mA Vi=-11.5V to -25V 0.1 1.0 mA Output voltage drift ∆Vo/∆T Io =5mA -0.6 mV/°C Output noise voltage V N f=10hz to 100kHz,Ta=25°C 175 µV Ripple rejection RR f=120Hz, Vi=-11.5V to -21.5V 54 60 dB Dropout voltage Vo Io=1.0A,Tj=25°C 2 V Short citcuit current Isc Vi=-35V,Ta=25°C 300 mA peak current Ipk Tj=25°C2.2 AUTC7912 ELECTRICAL CHARACTERISTICS(Refer to test circuits, 0<Tj<125°C ,Io=500mA,Vi=-18V,Ci=2.2uF,Co=1uF,unless otherwise specified)PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITTj=25°C-11.52-12.0 -12.48 V Output voltageVo5.0mA<Io<1.0A,Po<15W Vi=-14.5V to -27V -11.40 -12.60 V Line regulation ∆Vo Tj =25°C,Vi=-14.5V to -30V12 240 mVTj=25°C,Vi=-16V to -22V6 120 mV Load regulation ∆Vo Tj =25°C,Io=5.0mA to 1.5A12 240 mVTj=25°C,Io=250mA to 750mA 4 120 mV Quiescent currentI Q Tj=25°C3 6 mA Quiescent current change ∆I QIo=5mA to 1.0A 0.05 0.5 mAVi=-14.5V to -30V 0.1 1.0 mAOutput voltage drift ∆Vo/∆T Io =5mA -0.8 mV/°COutput noise voltage V N f=10hz to 100kHz,Ta=25°C 200 µV Ripple rejection RR f=120Hz, Vi=-15V to -25V 54 60 dB Dropout voltage Vo Io=1.0A,Tj=25°C 2 V Short circuit current Isc Vi=-35V,Ta=25°C 300 mA peak currentIpk Tj=25°C2.2 AUTC LM79XX LINEAR INTEGRATED CIRCUITUTC UNISONIC TECHNOLOGIES CO., LTD.4QW-R101-007,BUTC7915 ELECTRICAL CHARACTERISTICS(Refer to test circuits, 0<Tj<125°C , Io=500mA,Vi=-23V,Ci=2.2uF,Co=1uF,unless otherwise specified)PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITTj=25°C-14.40-15.0 -15.60 V Output voltageVo5.0mA<Io<1.0A,Po<15W Vi=-17.5V to -30V -14.25 -15.75 VLine regulation ∆Vo Tj =25°C,Vi=-17.5V to -30V 12 300 mV Tj=25°C,Vi=-20V to -26V6 150 mV Load regulation ∆Vo Tj =25°C,Io=5.0mA to 1.5A 12 300 mV Tj=25°C,Io=250mA to 750mA 4 150 mV Quiescent current I Q Tj=25°C3 6 mA Quiescent current change ∆I QIo=5mA to 1.0A 0.05 0.5 mA Vi=-17.5V to -30.5V 0.1 1.0 mA Output voltage drift ∆Vo/∆T Io =5mA -0.9 mV/°C Output noise voltage V N f=10hz to 100kHz,Ta=25°C 250 µV Ripple rejection RR f=120Hz, Vi=-18.5V to -28.5V 54 60 dB Dropout voltage Vo Io=1.0A,Tj=25°C 2 V Short circuit current Isc Vi=-35V,Ta=25°C 300 mA peak current Ipk Tj=25°C2.2 AUTC7918 ELECTRICAL CHARACTERISTICS(Refer to test circuits, 0<Tj<125°C ,Io=500mA,Vi=-27V,Ci=2.2uF,Co=1uF,unless otherwise specified)PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITTj=25°C-17.28-18.0 -18.72 V Output voltageVo5.0mA<Io<1.0A,Po<15W Vi=-21V to -33V -17.10 -18.90 V Line regulation ∆Vo Tj =25°C,Vi=-21V to -33V15 360 mVTj=25°C,Vi=-24V to -30V8 180 mV Load regulation ∆Vo Tj =25°C,Io=5.0mA to 1.5A15 360 mVTj=25°C,Io=250mA to 750mA 5.0 180 mV Quiescent currentI Q Tj=25°C3 6 mA Quiescent current change ∆I QIo=5mA to 1.0A 0.5 mAVi=-21V to -32V 1.0 mAOutput voltage drift ∆Vo/∆T Io =5mA -1 mV/°COutput noise voltage V N f=10hz to 100kHz,Ta=25°C 300 µV Ripple rejection RR f=120Hz, Vi=-22V to -32V 54 60 dB Dropout voltage Vo Io=1.0A,Tj=25°C 2 V Short circuit current Isc Vi=-35V,Ta=25°C 300 mA peak currentIpk Tj=25°C2.2 AUTC LM79XX LINEAR INTEGRATED CIRCUITUTC UNISONIC TECHNOLOGIES CO., LTD.5QW-R101-007,BUTC7924 ELECTRICAL CHARACTERISTICS(Refer to test circuits, 0<Tj<125°C ,Io=500mA,Vi=-33V,Ci=2.2uF,Co=1uF,unless otherwise specified)PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITTj=25°C-23.04-24 -24.96 V Output voltageVo5.0mA<Io<1.0A,Po<15W Vi=-27V to -38V -22.80 -25.20 VLine regulation ∆Vo Tj 25°C,Vi=-27V to -38V15 480mVTj=25°C,Vi=-30V to -36V8 240 mV Load regulation ∆Vo Tj 25°C,Io=5.0mA to 1.5A15 480 mVTj=25°C,Io=250mA to 750mA 5.0 240 mV Quiescent currentI Q Tj=25°C3 6 mA Quiescent current change ∆I QIo=5mA to 1.0A 0.5 mAVi=-27V to -38V 1.0 mAOutput voltage drift ∆Vo/∆T Io =5mA -1 mV/°COutput noise voltage V N f=10hz to 100kHz,Ta=25°C 400 µV Ripple rejection RR f=120Hz, Vi=-28V to -38V 54 60 dB Dropout voltage Vo Io=1.0A,Tj=25°C 2 V Short circuit current Isc Vi=-35V,Ta=25°C 300 mA peak currentIpk Tj=25°C2.2 AAPPLICATION CIRCUITSFig.1 Fixed output regulatorFig.2 Split power supply(+-15V,1A)UTC LM79XX LINEAR INTEGRATED CIRCUITFig.3 Circuit for increasing output voltageUTC UNISONIC TECHNOLOGIES CO., LTD. 6QW-R101-007,B。

©2011 Fairchild Semiconductor CorporationRev. 1.0.1Features•No External Components Required •Output Current in Excess of 0.5A •Internal Thermal Overload•Internal Short Circuit Current Limiting •Output Transistor Safe Area Compensation•Output V oltages of -5V ,-6V ,-8V , -12V ,-15V ,-18V ,-24VDescriptionThe KA79MXX series of 3-Terminal medium currentnegative voltage regulators are monolithic integrated circuits designed as fixed voltage regulators. These regulators employ internal current limiting, thermal shutdown and safe area compensation making them essentially indestructible.TO-220D-PAK1. GND2. Input3. Output11Schematic DiagramQ1Q2Q3Q4Q5Q6Q7Q8Q9Q10Q11Q12Q13Q14Q15Q16Q17Q18Q19Q20Q21Q22Q23Q24Q25Q26Q27R1R2R3R4R5R6R7R8R9R10R11R12R13R15R14R16R17R18R19R20R21R22R23R24R25D1D2D3D4D5C1C2GNDOUTINKA79MXX3-Terminal 0.5A Negative Voltage RegulatorKA79MXX2Absolute Maximum RatingsElectrical Characteristics (KA79M05/KA79M05R)(Refer to test circuit, 0°C ≤T J ≤ +125°C, l O =350mA, V I =-10V,unless otherwise specified, C I =0.33μF,C O =0.1μF)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbol Value Unit Input Voltage(for V O = -5V to -18V)(for V O = -24V)V I V I -35-40V V Thermal Resistance Junction-Cases R θJC 5°C/W Thermal Resistance Junction-Air R θJA 65°C/W Operating Temperature Range T OPR 0 ~ +125°C Storage Temperature RangeT STG-65 ~ +150°CParameter Symbol ConditionsMin.Typ.Max.UnitOutput VoltageV OT J = +25°C -4.8-5-5.2V I O = 5mA to 350mA V I = -V7 to -25V -4.75-5-5.25Line Regulation (Note1)ΔV O T J =+25°CV I = -7V to -25V -7.050mV V I = -8V to -25V- 2.030Load Regulation (Note1)ΔV O I O = 5mA to 500mA T J = +25°C -30100mV Quiescent Current I Q T J = +25°C - 3.0 6.0mAQuiescent Current Change ΔI Q I O = 5mA to 350mA --0.4mA I O = 200mA V I = -8V to -25V --0.4Output Voltage Drift ΔVo/ΔT I O = 5mA--0.2-mV/°C Output Noise Voltage V N f = 10Hz to 100kHz, T A = +25°C -40-μV Ripple Rejection RR f = 120HzV J = -8Vto -18V 5460-dB Dropout Voltage V D T J =+25°C, I O = 500mA - 1.1-V Short Circuit Current I SC T J = +25°C, V I = -35V -140-mA Peak CurrentI PKT J = +25°C-650-mAKA79MXX3Electrical Characteristics (KA79M06) (Continued)(Refer to test circuit, 0°C ≤T J ≤ +125°C, l O =350mA, V I = -11V,unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.Parameter SymbolConditionsMin.Typ.Max.UnitOutput VoltageV OT J = +25°C-5.75-6.0-6.25V I O = 5mA to 350mA V I = -8.0V to -25V -5.7-6.0-6.3Line Regulation (Note1)ΔV O T J =+25°C V I = -8Vto -25V -7.060mV V I = -9V to -19V - 2.040Load Regulation (Note1)ΔV O T J = +25°C I O = 5.0mA to 500mA -30120mV Quiescent Current I Q T J = +25°C-36mAQuiescent Current Change ΔI Q I O = 5mA to 350mA --0.4mA V I = -8V to -25V --0.4Output Voltage Drift ΔV O /ΔT I O = 5mA-0.4-mV/°C Output Noise Voltage V N f = 10Hz to 100kHz, T A = +25°C -50-μV Ripple Rejection RR f = 120Hz,V I = -9V to -19V 5460-dB Dropout Voltage V D I O = 500mA, T J = +25°C - 1.1-V Short Circuit Current I SC V I = -35V, T J = +25°C -140-mA Peak CurrentI PKT J = +25°C-650-mAKA79MXX4Electrical Characteristics (KA79M08/KA79M08R) (Continued)(Refer to test circuit, 0°C ≤ T J ≤ +125°C, l O =350mA, V I = -14V,unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.Parameter SymbolConditionsMin.Typ.Max.UnitOutput VoltageV OT J = +25°C-7.7-8.0-8.3V I O = 5mA to 350mA V I = -10.5V to -25V -7.6-8.0-8.4Line Regulation (Note1)ΔV O T J = +25°C V I = -10.5V to -25V -7.080mV V I = -11V to -21V - 2.050Load Regulation (Note1)ΔV O T J = +25°C I O = 5.0mA to 500mA -30160mV Quiescent Current I Q T J = +25°C -36mAQuiescent Current Change ΔI Q I O = 5mA to 350mA --0.4mA V I = -8V to -25V --0.4Output Voltage Drift ΔV O /ΔT I O = 5mA--0.6-mV/°C Output Noise Voltage V N f = 10Hz to 100kHz, T A = +25°C -60-μV Ripple Rejection RR f = 120Hz,V I = -9V to -19V 5459-dB Dropout Voltage V D I O = 500mA, T J = +25°C - 1.1-V Short Circuit Current I SC V I = -35V, T J = +25°C -140-mA Peak CurrentI PKT J = +25°C-650-mAKA79MXX5Electrical Characteristics (KA79M12) (Continued)(Refer to test circuit, 0°C ≤ T J ≤ +125°C, l O =350mA, V I = -19V,unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.Parameter SymbolConditionsMin.Typ.Max.UnitOutput VoltageV OT J = +25°C-11.5-12-12.5V I O = 5mA to 350mA V I = -14.5V to -30V -11.4-12-12.6Line Regulation (Note1)ΔV O T J =+25°C V I = -14.5V to -30V -8.080mV V I = -15V to -25V - 3.050Load Regulation (Note1)ΔV O T J = +25°C I O = 5.0mA to 500mA -30240mV Quiescent Current I Q T J = +25°C -36mAQuiescent Current Change ΔI Q I O = 5mA to 350mA --0.4mA V I = -14.5V to -30V --0.4Output Voltage Drift ΔV O /ΔT I O = 5mA--0.8-mV/°C Output Noise Voltage V N f = 10Hz to 100kHz, T A = +25°C -75-μV Ripple Rejection RR f = 120Hz,V I = -15V to -25V 5460-dB Dropout Voltage V D I O = 500mA, T J = +25°C - 1.1-V Short Circuit Current I SC V I = -35V, T J = +25°C -140-mA Peak CurrentI PKT J = +25°C-650-mAKA79MXX6Electrical Characteristics (KA79M15) (Continued)(Refer to test circuit, 0°C ≤ T J ≤ +125°C, l O =350mA, V I = -23V,unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.Parameter SymbolConditionsMin.Typ.Max.UnitOutput VoltageV OT J = +25°C-14.4-15-15.6V I O = 5mA to 350mA V I = -17.5V to -30V -14.25-15-15.75Line Regulation (Note1)ΔV O T J =+25°C V I = -17.5Vto -30V -9.080mV V I = -18V to -28V - 5.050Load Regulation (Note1)ΔV O T J = +25°C I O = 5.0mA to 500mA -30240mV Quiescent Current I Q T J = +25°C -36mAQuiescent Current Change ΔI Q I O = 5mA to 350mA --0.4mA V I = -17.5V to -28V --0.4Output Voltage Drift ΔV O /ΔT I O = 5mA--1.0-mV/°C Output Noise Voltage V N f = 10Hz to 100kHz, T A = +25°C -90-μV Ripple Rejection RR f = 120Hz,V I = -18.5V to -28.5V 5459-dB Dropout Voltage V D I O = 500mA, T J = +25°C - 1.1-V Short Circuit Current I SC V I = -35V, T J = +25°C -140-mA Peak CurrentI PKT J = +25°C-650-mAKA79MXX7Electrical Characteristics (KA79M18) (Continued)(Refer to test circuit, 0°C ≤ T J ≤ +125°C, l O =350mA, V I = -27V,unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.Parameter SymbolConditionsMin.Typ.Max.UnitOutput VoltageV OT J = +25°C-17.3-18-18.7V I O = 5mA to 350mA V I = -21V to -33V -17.1-18-18.9Line Regulation (Note1)ΔV O T J =+25°C V I = -21V to -33V -9.080mV V I = -24V to -30V - 5.080Load Regulation (Note1)ΔV O T J = +25°C I O = 5.0mA to 500mA -30360mV Quiescent Current I Q T J = +25°C -36mAQuiescent Current Change ΔI Q I O = 5mA to 350mA --0.4mA V I = -21V to -33V --0.4Output Voltage Drift ΔV O /ΔT I O = 5mA--1.0-mV/°C Output Noise Voltage V N f = 10Hz to 100kHz, T A = +25°C -110-μV Ripple Rejection RR f = 120Hz,V I = -22V to -32V 5459-dB Dropout Voltage V D I O = 500mA, T J = +25°C - 1.1-V Short Circuit Current I SC V I = -35V, T J = +25°C -140-mA Peak CurrentI PKT J = +25°C-650-mAKA79MXX8Electrical Characteristics (KA79M24) (Continued)(Refer to test circuit, 0°C ≤ T J ≤ +125°C, l O =350mA, V I = -33V,unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.Parameter SymbolConditionsMin.Typ.Max.UnitOutput VoltageV OT J = +25°C-23-24-25V I O = 5mA to 350mA V I = -27V to -38V -22.8-24-25.2Line Regulation (Note1)ΔV O T J =+25°C V I = -27V to -38V -9.080mV V I = -30V to -36V - 5.070Load Regulation (Note1)ΔV O T J = +25°C I O = 5.0mA to 500mA -30300mV Quiescent Current I Q T J = +25°C -36mAQuiescent Current Change ΔI Q I O = 5mA to 350mA --0.4mA V I = -27V to -38V --0.4Output Voltage Drift ΔV O /ΔT I O = 5mA--1.0-mV/°C Output Noise Voltage V N f = 10Hz to 100kHz, T A = +25°C -180-μV Ripple Rejection RR f = 120Hz,V I = -28V to -38V 5458-dB Dropout Voltage V D I O = 500mA, T J = +25°C - 1.1-V Short Circuit Current I SC V I = -35V, T J = +25°C -140-mA Peak CurrentI PKT J = +25°C-650-mAKA79MXX9Typical ApplicationsFigure 1.Fixed Output RegulatorFigure 2.Variable OutputNote:1. Required for stability. For value given, capacitor must be solid tantalum. 25μF aluminum electrolytic may be substituted.2. C 2 improves transient response and ripple rejection. Do not increase beyond 50μF.KA79MXX1.0uF2.0uF312V IV OKA79MXXV OV IR 2R 1C 3SOLIDTANTALUM1uF_+C 12.2uF SOLID TANTALUM_+C 225uF_+KA79MXXMechanical DimensionsPackageDimensions in millimetersTO-22010KA79MXX Mechanical Dimensions (Continued)PackageDimensions in millimetersD-PAK11KA79MXX1/24/11 0.0m 001Stock#DS400023© 2011 Fairchild Semiconductor CorporationLIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can bereasonably expected to result in a significant injury of the user.2. A critical component in any component of a life supportdevice or system whose failure to perform can bereasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANYLIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.Ordering InformationProduct NumberPackageOperating TemperatureKA79M05TO-2200 ~ +125°CKA79M06KA79M08KA79M12KA79M15KA79M18KA79M24KA79M05R D-PAK KA79M08R KA79M12R。

October 2007Rev 31/82SD882NPN medium power transistorFeatures■High current■Low saturation voltage ■Complement to 2SB772Applications■Voltage regulation ■Relay driver ■Generic switch ■Audio power amplifier ■DC-DC converterDescriptionThe device is a NPN transistor manufactured by using planar technology resulting in rugged high performance devices. The complementary PNP type is 2SB772.Table 1.Device summaryOrder code Marking Package Packing 2SD882D882SOT -32T ubeAbsolute maximum ratings2SD882 1 Absolute maximum ratingsTable 2.Absolute maximum ratingSymbol Parameter Value UnitV CBO Collector-base voltage (I E = 0) 60VV CEO Collector-emitter voltage (I B = 0) 30VV EBO Collector-base voltage (I C = 0) 5VI C Collector current3AI CM Collector peak current (t P < 5ms)6AI B Base current1AI BM Base peak current (t P < 5ms)2AP TOT T otal dissipation at T c = 25°C12.5WT STG Storage temperature-65 to 150°CT J Max. operating junction temperature150°CTable 3.Thermal dataSymbol Parameter Value UnitR thJ-case Thermal resistance junction-case max10°C/W 2/83/82 Electrical characteristics(T CASE = 25°C; unless otherwise specified)Table 4.Electrical characteristicsSymbol ParameterTest conditions Min.Typ.Max.Unit I CES Collector cut-off current(V BE = 0)V CE = 60 V 10µA I CEO Collector cut-off current (I B = 0)V CE = 30 V 100µA I EBOEmitter cut-off current (I C = 0)V EB = 5 V10µAV (BR)CEO(1)Collector-emitter breakdownvoltage (I B = 0 )I C = 10 mA 30VV (BR)CBO Collector-base breakdownvoltage(I E = 0 )I C = 100 µA60VV (BR)EBO Emitter-base breakdownvoltage(I C = 0 )I E = 100 µA5V V CE(sat)(1)Collector-emitter saturationvoltageI C = 1 A I B = 50 mAI C = 2 A I B = 100 mAI C = 3 A I B = 150 mA 0.40.71.1V V V V BE(sat)(1)1.Pulsed duration = 300 ms, duty cycle ≤1.5%.Base-emitter saturation voltage I C = 2 A I B = 100 mA 1.2Vh FE DC current gain I C = 100 mA V CE = 2 V I C = 1 A V CE = 2 V I C = 3 A V CE = 2 V 1008030300f TTransition frequencyI C = 0.1 A V CE = 10 V100MHzcharacteristics (curves) 2.1 Typical4/82SD882Package mechanical data 3 Package mechanical dataIn order to meet environmental requirements, ST offers these devices in ECOPACK®packages. These packages have a Lead-free second level interconnect . The category ofsecond level interconnect is marked on the package and on the inner box label, incompliance with JEDEC Standard JESD97. The maximum ratings related to solderingconditions are also marked on the inner box label. ECOPACK is an ST trademark.ECOPACK specifications are available at: 5/8Package mechanical data2SD8826/82SD882Revision history7/84 Revision historyTable 5.Document revision historyDate RevisionChanges09-Sep-20052Final datasheet. New template 02-Oct-20073Updated mechanical data2SD8828/8Please Read Carefully:Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.All ST products are sold pursuant to ST’s terms and conditions of sale.Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.UNLESS O THERWISE SET FO RTH IN ST’S TERMS AND CO NDITIO NS O F SALE ST DISCLAIMS ANY EXPRESS O R IMPLIED WARRANTY WITH RESPECT TO THE USE AND/O R SALE O F ST PRO DUCTS INCLUDING WITHO UT LIMITATIO N IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPRO VED IN WRITING BY AN AUTHO RIZED ST REPRESENTATIVE, ST PRO DUCTS ARE NO T RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.ST and the ST logo are trademarks or registered trademarks of ST in various countries.Information in this document supersedes and replaces all information previously supplied.The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.© 2007 STMicroelectronics - All rights reservedSTMicroelectronics group of companiesAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America分销商库存信息: STM2SD882。

采用 DSO-12 封装的准谐振 800 V CoolSET ™产品亮点• 集成 800 V CoolMOS ™，雪崩能力强 • 创新型准谐振操作，其专有设计可降低 EMI• 可选进入和退出待机功率电平的增强型主动突发模式 • 主动突发模式，最低待机功率可小于 100 mW • 借助共源共栅配置实现快速启动 • 数字降频模式，提高整体系统效率 • 支持输入过压和欠压保护的可靠线路保护 • 完善的保护机制•无铅电镀、无卤模塑化合物，符合 RoHS 标准特性• 集成 800 V CoolMOS ™，雪崩能力强• 显著缩小高低压线路间的开关频率差，实现高效率和良好的 EMI 性能• 可选进入和退出待机功率电平的增强型主动突发模式 • 主动突发模式，最低待机功率可小于 100 mW • 借助共源共栅配置实现快速启动 • 数字降频技术，过零点可达 10 个 • 内置数字软启动 • 逐周期峰值电流限制• 最大导通/关断时间限制，以避免在启动和断电时产生噪音 • 支持输入过压和欠压保护的可靠线路保护•针对 VCC 过压、VCC 欠压、过载/开路、输入/输出过压及过温状况的自动重启模式保护• 受限的 VCC 短接至地的充电电流• 无铅电镀、无卤模塑化合物，符合 RoHS 标准应用• 适用于家用电器/白色家电、电视、电脑及服务器的辅助电源• 蓝光播放器、机顶盒和 LCD/LED 显示器描述准谐振 CoolSET ™ - (ICE5QRxx80BG) 是第五代准谐振集成电源 IC ，支持共源共栅配置，并针对离线开关模式电源进行了优化。

产品在单一封装中搭载了两个独立芯片，分别为控制器芯片和高压 MOSFET 芯片。

借助经改善的数字降频技术和专有的创新型准谐振操作，IC 可在实现低 EMI 效果时兼顾更高效率。

而增强型主动突发模式更是为待机功率范围的选择提供了灵活性。

此外， ICE5QRxx80BG 有宽的供电电压工作范围 (10.0～25.5 V)， 功耗较低。

ADS7950,ADS7951,ADS7952,ADS7953ADS7954,ADS7955,ADS7956,ADS7957ADS7958,ADS7959,ADS7960,ADS7961 SLAS605A–JUNE2008–REVISED JANUARY2010 12/10/8-Bit,1MSPS,16/12/8/4-Channel,Single-Ended,MicroPower,Serial Interface ADCs Check for Samples:ADS7950,ADS7951,ADS7952,ADS7953,ADS7954,ADS7955,ADS7956,ADS7957,ADS7958,ADS7959,ADS7960,ADS7961FEATURES DESCRIPTION•1-MHz Sample Rate Serial Devices The ADS79XX is a12/10/8-bit multichannelanalog-to-digital converter family.The following table •Product Family of12/10/8-Bit Resolutionshows all twelve devices from this product family.•Zero LatencyThe devices include a capacitor based SAR A/D •20-MHz Serial Interfaceconverter with inherent sample and hold.•Analog Supply Range:2.7to5.25VThe devices accept a wide analog supply range from •I/O Supply Range:1.7to5.25V2.7V to5.25V.Very low power consumption makes •Two SW Selectable Unipolar,Input Ranges:0these devices suitable for battery-powered andto2.5V and0to5V isolated power supply applications.•Auto and Manual Modes for Channel SelectionA wide1.7V to5.25V I/O supply range facilitates a •12,8,4-Channel Devices can Share16Channel glue-less interface with the most commonly used Device Footprint CMOS digital hosts.•Two Programmable Alarm Levels per Channel The serial interface is controlled by CS and SCLK for •Four Individually Configurable GPIOs for easy connection with microprocessors and DSP.TSSOP package devices.One GPIO for QFNThe input signal is sampled with the falling edge of devicesIt uses SCLK for conversion,serial data output,•Typical Power Dissipation:14.5mW(+VA=5V,and reading serial data in.The devices allow auto +VBD=3V)at1MSPS sequencing of preselected channels or manualselection of a channel for the next conversion cycle.•Power-Down Current(1m A)•Input Bandwidth(47MHz at3dB)There are two software selectable input ranges(0V-2.5V and0V-5V),four individually configurable •38-,30-Pin TSSOP and32-,24-Pin QFNGPIOs(in case of TSSOP package devices),and Packagestwo programmable alarm thresholds per channel.These features make the devices suitable for most APPLICATIONSdata acquisition applications.•PLC/IPCThe devices offer an attractive power-down feature.•Battery Powered SystemsThis is extremely useful for power saving when the •Medical Instrumentation device is operated at lower conversion speeds.•Digital Power SuppliesThe16/12-channel devices from this family are •Touch Screen Controllers available in a38-pin TSSOP and32pin QFN•High-Speed Data Acquisition Systems package and the4/8-channel devices are available in •High-Speed Closed-Loop Systems a30-pin TSSOP and24pin QFN packages.MICROPOWER MULTI-CHANNEL ADS79XX FAMILYRESOLUTIONNUMBER OFCHANNELS12BIT10BIT8BIT16ADS7953ADS7957ADS796112ADS7952ADS7956ADS79608ADS7951ADS7955ADS79594ADS7950ADS7954ADS7958Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2008–2010,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasSDI SCLK CSSDOADS7950,ADS7951,ADS7952,ADS7953ADS7954,ADS7955,ADS7956,ADS7957ADS7958,ADS7959,ADS7960,ADS7961SLAS605A –JUNE 2008–REVISED JANUARY 2010This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.ADS79XX BLOCK DIAGRAMNOTE:n*is number of channels (16,12,8,or 4)depending on the device from the ADS79XX product family.NOTE:4number of GPIO are available in TSSOP package devices only,QFN package devices offer only one GPIO.2Submit Documentation Feedback Copyright ©2008–2010,Texas Instruments IncorporatedADS7950,ADS7951,ADS7952,ADS7953ADS7954,ADS7955,ADS7956,ADS7957ADS7958,ADS7959,ADS7960,ADS7961 SLAS605A–JUNE2008–REVISED JANUARY2010ORDERING INFORMATION-12-BITMAXIMUM MAXIMUM NO MISSINGTRANSPORTPACKAGEINTEGRAL DIFFERENTIAL CODES AT NUMBER OF PACKAGE TEMPERATURE ORDERING MODEL MEDIA LINEARITY LINEARITY RESOLUTION CHANNELS DESIGNATOR RANGE INFORMATIONTYPE QTY (LSB)(LSB)(BIT)ADS7953SBDBT Tube,5038pin TSSOP DBTADS7953SBDBTR Reel,2000 ADS7953SB16ADS7953SBRHBT Tube,25032pin QFN RHBADS7953SBRHBR Reel,3000ADS7952SBDBT Tube,5038pin TSSOP DBTADS7952SBDBTR Reel,2000 ADS7952SB12ADS7952SBRHBT Tube,25032pin QFN RHBADS7952SBRHBR Reel,3000±1±112–40°C to125°CADS7951SBDBT Tube,5030pin TSSOP DBTADS7951SBDBTR Reel,2000 ADS7951SB8ADS7951SBRGET Tube,25024pin QFN RGEADS7951SBRGER Reel,3000ADS7950SBDBT Tube,5030pin TSSOP DBTADS7950SBDBTR Reel,2000 ADS7950SB4ADS7950SBRGET Tube,25024pin QFN RGEADS7950SBRGER Reel,3000ADS7953SDBT Tube,5038pin TSSOP DBTADS7953SDBTR Reel,2000 ADS7953S16ADS7953SRHBT Tube,25032pin QFN RHBADS7953SRHBR Reel,3000ADS7952SDBT Tube,5038pin TSSOP DBTADS7952SDBTR Reel,2000 ADS7952S12ADS7952SRHBT Tube,25032pin QFN RHBADS7952SRHBR Reel,3000±1.5±211–40°C to125°CADS7951SDBT Tube,5030pin TSSOP DBTADS7951SDBTR Reel,2000 ADS7951S8ADS7951SRGET Tube,25024pin QFN RGEADS7951SRGER Reel,3000ADS7950SDBT Tube,5030pin TSSOP DBTADS7950SDBTR Reel,2000 ADS7950S4ADS7950SRGET Tube,25024pin QFN RGEADS7950SRGER Reel,3000ORDERING INFORMATION-10-BITMAXIMUM MAXIMUM NO MISSINGNUMBER TRANSPORTPACKAGEINTEGRAL DIFFERENTIAL CODES AT PACKAGE TEMPERATURE ORDERING MODEL OF MEDIA LINEARITY LINEARITY RESOLUTION DESIGNATOR RANGE INFORMATIONTYPECHANNELS QTY (LSB)(LSB)(BIT)ADS7957SDBT Tube,5038pin TSSOP DBTADS7957SDBTR Reel,2000 ADS7957S16ADS7957SRHBT Tube,25032pin QFN RHBADS7957SRHBR Reel,3000ADS7956SDBT Tube,5038pin TSSOP DBTADS7956SDBTR Reel,2000 ADS7956S12ADS7956SRHBT Tube,25032pin QFN RHBADS7956SRHBR Reel,3000±0.5±0.510–40°C to125°CADS7955SDBT Tube,5030pin TSSOP DBTADS7955SDBTR Reel,2000 ADS7955S8ADS7955SRGET Tube,25024pin QFN RGEADS7955SRGER Reel,3000ADS7954SDBT Tube,5030pin TSSOP DBTADS7954SDBTR Reel,2000 ADS7954S4ADS7954SRGET Tube,25024pin QFN RGEADS7954SRGER Reel,3000 Copyright©2008–2010,Texas Instruments Incorporated Submit Documentation Feedback3ADS7950,ADS7951,ADS7952,ADS7953ADS7954,ADS7955,ADS7956,ADS7957ADS7958,ADS7959,ADS7960,ADS7961SLAS605A–JUNE2008–REVISED ORDERING INFORMATION-8-BITMAXIMUM MAXIMUM NO MISSINGTRANSPORTPACKAGEINTEGRAL DIFFERENTIAL CODES AT NUMBER OF PACKAGE TEMPERATURE ORDERING MODEL MEDIA LINEARITY LINEARITY RESOLUTION CHANNELS DESIGNATOR RANGE INFORMATIONTYPE QTY (LSB)(LSB)(BIT)ADS7961SDBT Tube,5038pin TSSOP DBTADS7961SDBTR Reel,2000 ADS7961S16ADS7961SRHBT Tube,25032pin QFN RHBADS7961SRHBR Reel,3000ADS7960SDBT Tube,5038pin TSSOP DBTADS7960SDBTR Reel,2000 ADS7960S12ADS7960SRHBT Tube,25032pin QFN RHBADS7960SRHBR Reel,3000±0.3±0.38–40°C to125°CADS7959SDBT Tube,5030pin TSSOP DBTADS7959SDBTR Reel,2000 ADS7959S8ADS7959SRGET Tube,25024pin QFN RGEADS7959SRGER Reel,3000ADS7958SDBT Tube,5030pin TSSOP DBTADS7958SDBTR Reel,2000 ADS7958S4ADS7958SRGET Tube,25024pin QFN RGEADS7958SRGER Reel,3000ABSOLUTE MAXIMUM RATINGS(1)VALUE UNIT AINP or CHn to AGND–0.3to+VA+0.3V+VA to AGND,+VBD to BDGND–0.3to+7.0V Digital input voltage to BDGND–0.3to(7.0)V Digital output to BDGND–0.3to(+VA+0.3)V Operating temperature range–40to125°C Storage temperature range–65to150°C Junction temperature(T J Max)150°C Power dissipation(T J Max–T A)/q JAq JA thermal impedance,DBT Package100.6°C/Wq JA thermal impedance,RHB Package34°C/Wq JA thermal impedance,RGE Package38°C/W DBT packaged versions of ADS79XX family devices are rated for MSL2260°C perthe JSTD-020specifications and the RGE and RHB packaged versions of ADS79XXfamily devices are rated for MSL3260C per JSTD-020specifications(1)Stresses above those listed under“Absolute Maximum Ratings”may cause permanent damage to the device.Exposure to absolutemaximum conditions for extended periods may affect device reliability.4Submit Documentation Feedback Copyright©2008–2010,Texas Instruments IncorporatedADS7950,ADS7951,ADS7952,ADS7953ADS7954,ADS7955,ADS7956,ADS7957ADS7958,ADS7959,ADS7960,ADS7961 SLAS605A–JUNE2008–REVISED JANUARY2010 ELECTRICAL CHARACTERISTICS,ADS7950/51/52/53+VA=2.7V to5.25V,+VBD=1.7V to5.25V,V ref=2.5V±0.1V,T A=-40°C to125°C,f sample=1MHz(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTRange10VrefFull-scale input span(1)VRange2while2Vref≤+VA02*Vref–0.20VREFRange1+0.20Absolute input range V–0.202*VREFRange2while2Vref≤+VA+0.20Input capacitance15r F Input leakage current T A=125°C61nA SYSTEM PERFORMANCEResolution12BitsADS795XSB(2)12No missing codes BitsADS795XS(2)11ADS795XSB(2)–1±0.51Integral linearity LSB(3)ADS795XS(2)–1.5±0.75 1.5ADS795XSB(2)–1±0.51 Differential linearity LSBADS795XS(2)–2±0.75 1.5Offset error(4)–3.5±1.1 3.5LSBRange1–2±0.22Gain error LSBRange2±0.2Total unadjusted error(TUE)±2LSB SAMPLING DYNAMICSConversion time20MHz sclk800nSec Acquisition time325nSec Maximum throughput rate20MHz sclk 1.0MHz Aperture delay5nsec Step response150nsec Over voltage recovery150nsec DYNAMIC CHARACTERISTICSTotal harmonic distortion(5)100kHz–82dB Signal-to-noise ratio100kHz,ADS795XSB(2)7071.7dB100kHz,ADS795XS(2)7071.7Signal-to-noise+distortion100kHz,ADS795XSB(2)6971.3dB100kHz,ADS795XS(2)6871.3Spurious free dynamic range100kHz84dB Small signal bandwidth At–3dB47MHzAny off-channel with100kHz,Full-scale input tochannel being sampled with DC input(isolation–95crosstalk).Channel-to-channel crosstalk dBFrom previously sampled to channel with100kHz,Full-scale input to channel being sampled with DC–85input(memory crosstalk).EXTERNAL REFERENCE INPUT(1)Ideal input span;does not include gain or offset error.(2)ADS795X,where X indicates0,1,2,or3(3)LSB means Least Significant Bit.(4)Measured relative to an ideal full-scale input(5)Calculated on the first nine harmonics of the input frequency.Copyright©2008–2010,Texas Instruments Incorporated Submit Documentation Feedback5ADS7950,ADS7951,ADS7952,ADS7953ADS7954,ADS7955,ADS7956,ADS7957ADS7958,ADS7959,ADS7960,ADS7961SLAS605A–JUNE2008–REVISED ELECTRICAL CHARACTERISTICS,ADS7950/51/52/53(continued)+VA=2.7V to5.25V,+VBD=1.7V to5.25V,V ref=2.5V±0.1V,T A=-40°C to125°C,f sample=1MHz(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V ref reference voltage at REFP(6) 2.0 2.5 3.0V Reference resistance100kΩALARM SETTINGHigher threshold range0FFC Hex Lower threshold range0FFC Hex DIGITAL INPUT/OUTPUTLogic family CMOSV IH0.7*(+VBD)V IL+VBD=5V0.8Logic level V IL+VBD=3V0.4V V OH At I source=200m A Vdd-0.2V OL At I sink=200m A0.4Data format MSB first MSB FirstPOWER SUPPLY REQUIREMENTS+VA supply voltage 2.7 3.3 5.25V+VBD supply voltage 1.7 3.3 5.25VAt+VA=2.7to3.6V and1MHz throughput 1.8mAAt+VA=2.7to3.6V static state 1.05mA Supply current(normal mode)At+VA=4.7to5.25V and1MHz throughput 2.33mAAt+VA=4.7to5.25V static state 1.1 1.5mA Power-down state supply current1m A+VBD supply current+VA=5.25V,f s=1MHz1mA Power-up time1m Sec Invalid conversions after power up or1Number reset s TEMPERATURE RANGESpecified performance–40125°C (6)Device is designed to operate over V ref=2.0V to3.0V.However one can expect lower noise performance at V ref<2.4V.This is due toSNR degradation resulting from lowered signal range.ELECTRICAL CHARACTERISTICS,ADS7954/55/56/57+VA=2.7V to5.25V,+VBD=1.7V to5.25V,V ref=2.5V±0.1V,T A=-40°C to125°C,f sample=1MHz(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTRange10VrefFull-scale input span(1)VRange2while2Vref≤+VA02*VrefVREFRange1–0.20+0.20Absolute input range V2*VREFRange2while2Vref≤+VA–0.20+0.20Input capacitance15r F Input leakage current T A=125°C61nA SYSTEM PERFORMANCEResolution10BitsNo missing codes10Bits (1)Ideal input span;does not include gain or offset error.6Submit Documentation Feedback Copyright©2008–2010,Texas Instruments IncorporatedADS7950,ADS7951,ADS7952,ADS7953ADS7954,ADS7955,ADS7956,ADS7957ADS7958,ADS7959,ADS7960,ADS7961 SLAS605A–JUNE2008–REVISED JANUARY2010 ELECTRICAL CHARACTERISTICS,ADS7954/55/56/57(continued)+VA=2.7V to5.25V,+VBD=1.7V to5.25V,V ref=2.5V±0.1V,T A=-40°C to125°C,f sample=1MHz(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Integral linearity–0.5±0.20.5LSB(2) Differential linearity–0.5±0.20.5LSB Offset error(3)–1.5±0.5 1.5LSBRange1–1±0.11Gain error LSBRange2±0.1SAMPLING DYNAMICSConversion time20MHz SCLK800nSec Acquisition time325nSec Maximum throughput rate20MHz SCLK 1.0MHz Aperture delay5nsec Step response150nsec Over voltage recovery150nsec DYNAMIC CHARACTERISTICSTotal harmonic distortion(4)100kHz–80dB Signal-to-noise ratio100kHz60dB Signal-to-noise+distortion100kHz60Spurious free dynamic range100kHz82dB Full power bandwidth At–3dB47MHzAny off-channel with100kHz,Full-scale input to–95channel being sampled with DC input.Channel-to-channel crosstalk dBFrom previously sampled to channel with100kHz,–85Full-scale input to channel being sampled with DCinput.EXTERNAL REFERENCE INPUTV ref reference voltage at REFP 2.0 2.5 3.0V Reference resistance100kΩALARM SETTINGHigher threshold range000FFC Hex Lower threshold range000FFC Hex DIGITAL INPUT/OUTPUTLogic family CMOSV IH0.7*(+VBD)V IL+VBD=5V0.8Logic level V IL+VBD=3V0.4V V OH At I source=200m A Vdd-0.2V OL At I sink=200m A0.4Data format MSB first MSB FirstPOWER SUPPLY REQUIREMENTS+VA supply voltage 2.7 3.3 5.25V+VBD supply voltage 1.7 3.3 5.25VAt+VA=2.7to3.6V and1MHz throughput 1.8mAAt+VA=2.7to3.6V static state 1.051mA Supply current(normal mode)At+VA=4.7to5.25V and1MHz throughput 2.33mAAt+VA=4.7to5.25V static state 1.1 1.5mA(2)LSB means Least Significant Bit.(3)Measured relative to an ideal full-scale input(4)Calculated on the first nine harmonics of the input frequency.Copyright©2008–2010,Texas Instruments Incorporated Submit Documentation Feedback7ADS7950,ADS7951,ADS7952,ADS7953ADS7954,ADS7955,ADS7956,ADS7957ADS7958,ADS7959,ADS7960,ADS7961SLAS605A–JUNE2008–REVISED ELECTRICAL CHARACTERISTICS,ADS7954/55/56/57(continued)+VA=2.7V to5.25V,+VBD=1.7V to5.25V,V ref=2.5V±0.1V,T A=-40°C to125°C,f sample=1MHz(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power-down state supply current1m A+VBD supply current+VA=5.25V,f s=1MHz1mA Power-up time1m Sec Invalid conversions after power up or1Numbers resetTEMPERATURE RANGESpecified performance–40125°C ELECTRICAL CHARACTERISTICS,ADS7958/59/60/61+VA=2.7V to5.25V,+VBD=1.7V to5.25V,V ref=2.5V±0.1V,T A=-40°C to125°C,f sample=1MHz(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTRange10VrefFull-scale input span(1)VRange2while2Vref≤+VA02*VrefVREFRange1–0.20+0.20Absolute input range V2*VREFRange2while2Vref≤+VA–0.20+0.20Input capacitance15r F Input leakage current T A=125°C61nA SYSTEM PERFORMANCEResolution8BitsNo missing codes8Bits Integral linearity–0.3±0.10.3LSB(2) Differential linearity–0.3±0.10.3LSB Offset error(3)–0.5±0.20.5LSBRange1–0.6±0.10.6Gain error LSBRange2±0.1SAMPLING DYNAMICSConversion time20MHz SCLK800nSec Acquisition time325nSec Maximum throughput rate20MHz SCLK 1.0MHz Aperture delay5nsec Step response150nsec Over voltage recovery150nsec DYNAMIC CHARACTERISTICSTotal harmonic distortion(4)100kHz–75dB Signal-to-noise ratio100kHz49dB Signal-to-noise+distortion100kHz49Spurious free dynamic range100kHz–78dB Full power bandwidth At–3dB47MHz(1)Ideal input span;does not include gain or offset error.(2)LSB means Least Significant Bit.(3)Measured relative to an ideal full-scale input(4)Calculated on the first nine harmonics of the input frequency.8Submit Documentation Feedback Copyright©2008–2010,Texas Instruments IncorporatedADS7950,ADS7951,ADS7952,ADS7953ADS7954,ADS7955,ADS7956,ADS7957ADS7958,ADS7959,ADS7960,ADS7961 SLAS605A–JUNE2008–REVISED JANUARY2010 ELECTRICAL CHARACTERISTICS,ADS7958/59/60/61(continued)+VA=2.7V to5.25V,+VBD=1.7V to5.25V,V ref=2.5V±0.1V,T A=-40°C to125°C,f sample=1MHz(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITAny off-channel with100kHz,Full-scale input to–95channel being sampled with DC input.Channel-to-channel crosstalk dBFrom previously sampled to channel with100kHz,Full-scale input to channel being sampled with DC–85input.ETERNAL REFERENCE INPUTVref reference voltage at REFP 2.0 2.5 3.0V Reference resistance100kΩALARM SETTINGHigher threshold range000FF Hex Lower threshold range000FF Hex DIGITAL INPUT/OUTPUTLogic family CMOSV IH0.7*(+VBD)V IL+VBD=5V0.8Logic level V IL+VBD=3V0.4V V OH At I source=200m A Vdd-0.2V OL At I sink=200m A0.4Data format MSB FirstPOWER SUPPLY REQUIREMENTS+VA supply voltage 2.7 3.3 5.25V+VBD supply voltage 1.7 3.3 5.25VAt+VA=2.7to3.6V and1MHz throughput 1.8mAAt+VA=2.7to3.6V static state 1.05mA Supply current(normal mode)At+VA=4.7to5.25V and1MHz throughput 2.33mAAt+VA=4.7to5.25V static state 1.1 1.5mA Power-down state supply current1m A+VBD supply current+VA=5.25V,f s=1MHz1mA Power-up time1m Sec Invalid conversions after power up or1Numbers resetTEMPERATURE RANGESpecified performance–40125°C TIMING REQUIREMENTS(see Figure45,Figure46,Figure47,and Figure48)All specifications typical at–40°C to125°C,+VA=2.7V to5.25V(unless otherwise specified)PARAMETER TEST CONDITIONS(1)(2)MIN TYP MAX UNIT+VBD=1.8V16t conv Conversion time+VBD=3V16SCLK+VBD=5V16+VBD=1.8V40Minimum quiet sampling time needed from bust q+VBD=3V40ns 3-state to start of next conversion+VBD=5V40(1) 1.8V specifications apply from1.7V to1.9V,3V specifications apply from2.7V to3.6V,5V specifications apply from4.75V to5.25V.(2)With50-pF loadCopyright©2008–2010,Texas Instruments Incorporated Submit Documentation Feedback9ADS7950,ADS7951,ADS7952,ADS7953ADS7954,ADS7955,ADS7956,ADS7957ADS7958,ADS7959,ADS7960,ADS7961SLAS605A–JUNE2008–REVISED TIMING REQUIREMENTS(see Figure45,Figure46,Figure47,and Figure48)(continued)All specifications typical at–40°C to125°C,+VA=2.7V to5.25V(unless otherwise specified)PARAMETER TEST CONDITIONS(1)(2)MIN TYP MAX UNIT+VBD=1.8V38t d1Delay time,CS low to first data(DO–15)out+VBD=3V27ns+VBD=5V17+VBD=1.8V8t su1Setup time,CS low to first rising edge of SCLK+VBD=3V6ns+VBD=5V4+VBD=1.8V35t d2Delay time,SCLK falling to SDO next data bit valid+VBD=3V27ns+VBD=5V17+VBD=1.8V7t h1Hold time,SCLK falling to SDO data bit valid+VBD=3V5ns+VBD=5V3+VBD=1.8V26t d3Delay time,16th SCLK falling edge to SDO3-state+VBD=3V22ns+VBD=5V13+VBD=1.8V2t su2Setup time,SDI valid to rising edge of SCLK+VBD=3V3ns+VBD=5V4+VBD=1.8V12t h2Hold time,rising edge of SCLK to SDI valid+VBD=3V10ns+VBD=5V6+VBD=1.8V20t w1Pulse duration CS high+VBD=3V20ns+VBD=5V20+VBD=1.8V24t d4Delay time CS high to SDO3-state+VBD=3V21ns+VBD=5V12+VBD=1.8V20t wh Pulse duration SCLK high+VBD=3V20ns+VBD=5V20+VBD=1.8V20t wl Pulse duration SCLK low+VBD=3V20ns+VBD=5V20+VBD=1.8V20 Frequency SCLK+VBD=3V20MHz+VBD=5V2010Submit Documentation Feedback Copyright©2008–2010,Texas Instruments IncorporatedGPIO2GPIO3REFM REFP +VA AGND MXO AINP AINM AGND NC CH3NC CH2NCGPIO1GPIO0+VBD BDGND SDO SDI SCLK CS AGND +VA CH0NC CH1NC NCGPIO2GPIO3REFM REFP +VA AGND MXO AINP AINM AGND CH7CH6CH5CH4NCGPIO1GPIO0+VBD BDGND SDO SDI SCLK CS AGND +VA CH0CH1CH2CH3NCGPIO2GPIO3REFM REFP +VA AGND MXO AINP AINM AGND NC NC NC NCCH11CH10CH9CH8AGNDGPIO2GPIO3REFM REFP +VA AGND MXO AINP AINM AGND CH15CH14CH13CH12CH11CH10CH9CH8AGNDGPIO1GPIO0+VBD BDGND SDO SDI SCLK CS AGND +VA CH0CH1CH2CH3CH4CH5CH6CH7AGNDAGND AINM AINP MXO CH15CH12CH13CH14SCLK +VA AGNDCS CH0CH3CH2CH1C H 11C H 10C H 9C H 8C H 7C H 6C H 5C H 4+V AR E F PR E F MG P I O+V B DB D G N DS D OS D IDEVICE INFORMATIONPIN CONFIGURATION (TOP VIEW)AGND AINM AINP MXO NC CH10CH11NC SCLK +VA AGNDCS NC CH1CH0NC C H 9C H 8C H 7C H 6C H 5C H 4C H 3C H 2+V AR E F PR E F MG PI O+V B DB D G N DS D OS D I+VA AINP MXO AGND AINM SDI AGND CS SCLK +VA CH0C H 6C H 5C H 4C H 3C H 2C H 1R E F PR E F MGP I O+V B DB D G N DS D O +VA AINP MXO AGND AINM NCSDI AGND CS SCLK +VA NCN CC H 3C H C H C H N C R E F PR E F MG P I O+V B DB D G N D S D O TERMINAL FUNCTIONS -TSSOP PACKAGESDEVICE NAMEADS7953ADS7952ADS7951ADS7950ADS7957ADS7956ADS7955ADS7954PIN NAMEI/OFUNCTIONADS7961ADS7960ADS7959ADS7958PIN NO.REFERENCE4444REFP I Reference input 3333REFMIReference groundDEVICE NAMEADS7953ADS7952ADS7951ADS7950ADS7957ADS7956ADS7955ADS7954PIN NAME I/O FUNCTIONADS7961ADS7960ADS7959ADS7958PIN NO.ADC ANALOG INPUT8888AINP I Signal input to ADC9999AINM I ADC input groundMULTIPLEXER7777MXO O Multiplexer output28282020Ch0I Analog channels for multiplexer27271918Ch1I26261814Ch2I25251712Ch3I242414-Ch4I232313-Ch5I222212-Ch6I212111-Ch7I1818--Ch8I1717--Ch9I1616--Ch10I1515--Ch11I14---Ch12I13---Ch13I12---Ch14I11---Ch15IDIGITAL CONTROL SIGNALS31312323CS I Chip select input32322424SCLK I Serial clock input33332525SDI I Serial data input34342626SDO O Serial data outputGENERAL PURPOSE INPUTS/OUTPUTS:These pins have programmable dual functionality.Refer to Table8for functionality programming37372929GPIO0I/O General purpose input or outputHigh alarm or O Active high output indicating high alarm or high/lowHigh/Low alarm depending on programmingalarm38383030GPIO1I/O General purpose input or outputLow alarm O Active high output indicating low alarm 1111GPIO2I/O General purpose input or outputRange I Selects range:High->Range2/Low->Range1 2222GPIO3I/O General purpose input or outputPD I Active low power down inputPOWER SUPPLY AND GROUND5,295,295,215,21+VA—Analog power supply6,10,19,6,10,19,6,10,226,10,22AGND—Analog ground20,3020,3036362828+VBD—Digital I/O supply35352727BDGND—Digital groundNC PINSDEVICE NAMEADS7953ADS7952ADS7951ADS7950ADS7957ADS7956ADS7955ADS7954PIN NAME I/O FUNCTIONADS7961ADS7960ADS7959ADS7958PIN NO.—11,12,13,15,1611,13,15,——Pins internally not connected,do not float these pins 1416,17,19TERMINAL FUNCTIONS-QFN PACKAGESDEVICE NAMEADS7953ADS7952ADS7951ADS7950ADS7957ADS7956ADS7955ADS7954PIN NAME I/O FUNCTIONADS7961ADS7960ADS7959ADS7958PIN NO.REFERENCE31312424REFP I Reference input30302323REFM I Reference groundADC ANALOG INPUT3344AINP I Signal input to ADC4455AINM I ADC input groundMULTIPLEXER2233MXO O Multiplexer output20181311Ch0I Analog-input channels for multiplexer19171210Ch1I1816119Ch2I1715108Ch3I16149-Ch4I15138-Ch5I14127-Ch6I13116-Ch7I1210--Ch8I119--Ch9I108--Ch10I97--Ch11I8---Ch12I7---Ch13I6---Ch14I5---Ch15IDIGITAL CONTROL SIGNALS23231616CS I Chip select input24241717SCLK I Serial clock input25251818SDI I Serial data input26261919SDO O Serial data outputGENERAL PURPOSE INPUT/OUTPUT:This pin has programmable dual functionality.Refer to Table8for functionality programming 29292222GPIO0I/O General purpose input or outputHigh alarm or O Active high output indicating high alarm or high/lowHigh/Low alarm depending on programmingalarmPOWER SUPPLY AND GROUND21,3221,321,141,14+VA—Analog power supplyDEVICE NAMEADS7953ADS7952ADS7951ADS7950ADS7957ADS7956ADS7955ADS7954PIN NAME I/O FUNCTIONADS7961ADS7960ADS7959ADS7958PIN NO.1,221,222,152,15AGND—Analog ground28282121+VBD—Digital I/O supply27272020BDGND—Digital groundNC PINS—5,6,19,—6,7,12,13——Pins internally not connected,do not float these pins 2022.22.42.62.833.23.4-401570125T - Free-Air Temperature - °CA +V A - S u p p l y C u r r e n t - mA11.522.533.52.73.44.1 4.85.5+VA - Supply Voltage - V+V A - S u p p l y C u r r e n t - mA0.911.11.21.31.41.52.73.44.1 4.85.5+V A - S u p p l y C u r r e n t - m A+VA- Supply Voltage - V+V A - S u p p l y C u r r e n t - m Af - Sample Rate - KSPSS0.511.522.52004006008001000f - Sample Rate - KSPSS +V A - S u p p l y C u r r e n t - m A1.071.0751.081.0851.091.0951.11.1051.111.115-401570125T - Free-Air Temperature - °CA +V A -S u p p l y C u r r e n t - m ATYPICAL CHARATERISTICS (all ADS79XX Family Devices)SUPPLY CURRENTSTATIC SUPPLY CURRENTSUPPLY CURRENTvsvsvsSUPPLY VOLTAGESUPPLY VOLTAGE FREE-AIR TEMPERATUREFigure 1.Figure 2.Figure 3.STATIC SUPPLY CURRENTSUPPLY CURRENTSUPPLY CURRENTvsvsvsFREE-AIR TEMPERATURESAMPLE RATESAMPLE RATEFigure 4.Figure 5.Figure 6.-1-0.8-0.6-0.4-0.200.20.40.60.812.73.2 3.74.2 4.75.2D N L - D i f f e r e n t i a l N o n l i n e a r i t y - L S B s5.5+VA - Supply Voltage - V-1-0.8-0.6-0.4-0.200.20.40.60.812.73.2 3.74.2 4.75.2I N L - I n t e g r a l N o n l i n e a r i t y - L S Bs+VA - Supply Voltage - V-1-0.8-0.6-0.4-0.200.20.40.60.81-401570125T - Free-Air Temperature - °CA D N L - D i f f e r e n t i a l N o n l i n e a r i t y - L SB s-1-0.8-0.6-0.4-0.200.20.40.60.81-401570125I N L - I n t e g r a l N o n l i n e a r i t y - L S B sT - Free-Air Temperature - °CA 00.20.40.60.811.21.41.61.822.73.44.1 4.85.5O f f s e t E r r o r - L S B s+VA - Supply Voltage - V00.20.40.60.811.21.41.61.821.82.32.83.3 3.84.3 4.85.5+VBD - Interace Supply - VO f f s e t E r r o r - L S B s5.3-1-0.8-0.6-0.4-0.200.20.40.60.811.82.32.83.3 3.84.3 4.85.35.5+VBD - Interace Supply - VG a i n E r r o r - L S B s-1-0.8-0.6-0.4-0.200.20.40.60.812.73.44.1 4.85.5G a i n E r r o r - L S B s+VA - Supply Voltage - V00.20.40.60.811.21.41.61.82-401570125T - Free-Air Temperature - °CA O f f s e t E r r o r - L SB sTYPICAL CHARACTERISTICS (12-Bit Devices Only)Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curvesDIFFERENTIAL NONLINEARITYINTEGRAL NONLINEARITYDIFFERENTIAL NONLINEARITYvsvsvsSUPPLY VOLTAGESUPPLY VOLTAGEFREE-AIR TEMPERATUREFigure 7.Figure 8.Figure 9.INTEGRAL NONLINEARITYOFFSET ERROROFFSET ERRORvsvsvsFREE-AIR TEMPERATURESUPPLY VOLTAGEINTERFACE SUPPLY VOLTAGEFigure 10.Figure 11.Figure 12.GAIN ERRORGAIN ERROROFFSET ERRORvsvsvsSUPPLY VOLTAGEINTERFACE SUPPLY VOLTAGEFREE-AIR TEMPERATUREFigure 13.Figure 14.Figure 15.。

11/20/02 1ADVANCED ANALOGHYBRID-HIGH RELIABILITY DC/DC CONVERTERSATO28XXT SERIESDescriptionn 16 to 40 VDC Input Range (28VDC Nominal)n 5V, ±12V or 5V, ±15V Outputs Available n Indefinite Short Circuit and Overload Protectionn 15 Watts Output Powern Fast Loop Response for Superior Transient Characteristicsn Operating T emperature Range from -55°C to +125°C Availablen Popular Industry Standard Pin-outn Resistance Seam Welded Case for Superior Long Term Hermeticity n Efficiencies up to 81%n Shutdown from External Signal n 200,000 Hour MTBF at 85°CFeaturesATO28V Input, Triple OutputThree standard temperature grades are offered. Refer to Part Number section. They are provided in a stan-dard plug-in package for PC mounting or in a flanged package for more severe environments.These converters are manufactured in a facility fully qualified to MIL-STD-1772. All processes used to manu-facture these converters have been qualified to enable Advanced Analog to deliver compliant devices. Two screening grades are available to satisfy a wide range of requirements. The CH grade converters are fully compliant to MIL-PRF-38534 for class H. The HB grade converters are processed to full class H screening re-quirements but do not have class H element evalua-tion as directed by MIL-PRF-39534. Both grades are fully tested and operate over the full military tempera-ture range without derating of output power. Variations in electrical, mechanical and screening can be accom-modated. Extensive computer simulation using com-plex modeling enables modest design modifications to be accommodated. Contact Advanced Analog withspecific requirements.PD - 94582The ATO28XXT Series of DC/DC converters feature high power density and an extended temperature range for use in military and industrial applications. Designed to the nominal input requirements of MIL-STD-704D,these devices have nominal 28VDC inputs with +5V and ±12V or +5V and ±15V triple outputs to satisfy a wide range of requirements. The circuit design incor-porates a pulse width modulated push-pull topology operating in the feed-forward mode at a nominal switch-ing frequency of 250KHz. Input to output isolation is achieved through the use of transformers in the for-ward and feedback circuits.The advanced feedback design provides fast loop re-sponse for superior line and load transient characteris-tics and offers greater reliability and radiation toler-ance than devices incorporating optical feedback cir-cuits.查询ATO2812T供应商ATO28XXT Series SpecificationsT CASE = -55°C to +85°C, V IN = +28V ± 5% unless otherwise specifiedNotes to SpecificationsABSOLUTE MAXIMUM RATINGSInput Voltage -0.5V to 50VPower Output Internally limited, 17.5W typical Soldering 300°C for 10 secondsTemperature Range 6 Operating -55°C to +115°C case Storage -65°C to +135°C1.Tested at each output.2.Parameter guaranteed by line and load regulation tests.3.At least 20 percent of the total output power should be taken from the (+5V volt) main output.4.Bandwidth guaranteed by design. Tested for 20KHz to 2MHz.5.An overload is that condition with a load in excess of the rated load but less than that necessary to trigger the short circuit protection and is the condition of maximum power dissipation.6.Above 85°C case temperature, derate output power linearly to 0 at 115°C case.ATO2812TATO2815T TESTSYMBOLCondition-55°C ≤ T C ≤ +85°C, V IN = 28 V DC ±5%, C L =0unless otherwise specifiedMin MaxMinMaxUnitsSTATIC CHARACTERISTICSOUTPUTVoltage V I = 0 (main)I = 0 (dual) TC = 25°COver TempTC = 25°C Over Temp 4.95 4.90 ±11.88 ±11.76 5.05 5.10 ±12.12 ±12.24 4.95 4.90 ±14.85 ±14.70 5.05 5.10 ±15.15±15.30V V V V Current I V = 16, 28, and 40 VDC (main) 0.0 2000 0.0 2000 mAV = 16, 28, and 40 VDC (dual)V = 16, 28, and 40 VDC (dual) 0.0 ±208 80 0.0 ±16780mA mVp-p Ripple VoltageVBW = DC to 2 MHz (main) V = 16, 28, and 40 VDC BW = DC to 2 MHz (dual))4040mVp-pPower P V = 16, 28, and 40 VDC (main)(+dual) (-dual) (total)10 2.5 2.5 15 10 2.5 2.5 15 WW W W REGULATIONLine Load VR VR V = 16, 28, and 40 VDC I = 0, 1000, 2000mA (main) V = 16, 28, and 40 VDC (dual) I = 0, ±84, ±167mA (dual) V = 16, 28, and 40 VDCI = 0, 1000, 2000mA (main) V = 16, 28, and 40 VDC I = 0, ±84, ±167mA (dual)TC = 25°C Over Temp 25 ±30 ±60 50 ±6025 ±35±7550±75 mV mV mV mV mV INPUTCurrentRipple Current I I I = 0, Inhibit (pin 8) Tied to input return (pin 10) I = 0, inhibit (pin 2) = openI = 2000 mA (main)I = ±167mA (dual) BW = DC to 2MHz15405015 40 50 mA mA mAp-p EFFICIENCY E I = 2000mA (main)I = ±167mA (dual)TC = 25°C 76 76 % ISOLATION ISO Input to output or any pin tocase (except pin 7) at 500 VDC,TC = 25°C 100 100 M ΩLoad Fault Power Dissipation P Overload Short Circuit TC = 25°C8 6 8 6 WWSwitching Frequency F I = 2000mA (main)I = ±167mA (dual)225 275 225 275 KHzInhibit Open Circuit VoltageV913913V3ATO28XXT SeriesT CASE = -55°C to +105°C, V IN = +28V ± 5% unless otherwise specifiedSpecificationsABSOLUTE MAXIMUM RATINGSInput Voltage -0.5V to 50VPower Output Internally limited, 17.5W typical Soldering 300°C for 10 secondsTemperature Range 6 Operating -55°C to +125°C case Storage -65°C to +135°C1.Tested at each output.2.Parameter guaranteed by line and load regulation tests.3.At least 20 percent of the total output power should be taken from the (+5V volt) main output.4.Bandwidth guaranteed by design. Tested for 20KHz to 2MHz.5.An overload is that condition with a load in excess of the rated load but less than that necessary to trigger the short circuit protection and is the condition of maximum power dissipation.6.Above 105°C case temperature, derate output power linearly to 0 at 125°C caseNotes to SpecificationsATO2812T/ESATO2815T/ESTESTSYMBOLCondition-55°C ≤ T C ≤ +105°C, V IN = 28 V DC ±5%, C L =0unless otherwise specified Min Max Min Max UnitsSTATICCHARACTERISTICSOUTPUTVoltageVI = 0 (main)I = 0 (dual)TC = 25°COver TempTC = 25°COver Temp 4.95 4.90 ±11.88 ±11.76 5.05 5.10 ±12.12 ±12.24 4.95 4.90 ±14.85 ±14.70 5.05 5.10 ±15.15 ±15.30V V V V Current I V = 16, 28, and 40 VDC (main) 0.0 2000 0.0 2000 mARipple Voltage V V = 16, 28, and 40 VDC (dual)V = 16, 28, and 40 VDC 0.0 ±208 80 0.0 ±16780mA mVp-pBW = DC to 2 MHz (main) V = 16, 28, and 40 VDC BW = DC to 2 MHz (dual))4040mVp-pPower P V = 16, 28, and 40 VDC (main)(+dual) (-dual) (total)10 2.5 2.5 15 10 2.5 2.5 15 WW W WREGULATION Line Load VR VR V = 16, 28, and 40 VDC I = 0, 1000, 2000mA (main) V = 16, 28, and 40 VDC (dual) I = 0, ±84, ±167mA (dual) V = 16, 28, and 40 VDCI = 0, 1000, 2000mA (main) V = 16, 28, and 40 VDC I = 0, ±84, ±167mA (dual)TC = 25°C Over Temp 25 ±30 ±60 50 ±6025 ±35±7550±75mVmV mV mV mV INPUTCurrentRipple CurrentI I I = 0, Inhibit (pin 8) Tied to input return (pin 10) I = 0, inhibit (pin 2) = open I = 2000 mA (main) I = ±167mA (dual) BW = DC to 2MHz15 40 50 15 40 50mA mA mAp-pEFFICIENCY E I = 2000mA (main)I = ±167mA (dual) TC = ±25°CTC = 25°C 76 76 %ISOLATION ISO Input to output or any pin tocase (except pin 7) at 500 VDC, TC = +25°CTC = 25°C 100 100 M Ω Load FaultPower Dissipation P Overload, TC = +25°CShort Circuit, TC = +25°CTC = 25°C8 68 6 W W Switching FrequencyFI = 2000mA (main) I = ±167mA (dual)225 275225275KHzInhibit Open Circuit VoltageV 9 13 9 13 VATO28XXT Series T CASE = -55°C to +125°C, V IN = +28V ± 5% unless otherwise specifiedSpecificationsABSOLUTE MAXIMUM RATINGSInput Voltage -0.5V to 50VPower Output Internally limited, 17.5W typical Soldering 300°C for 10 secondsTemperature Range 6 Operating -55°C to +135°C case Storage -65°C to +135°CNotes to Specifications1.Tested at each output.2.Parameter guaranteed by line and load regulation tests.3.At least 20 percent of the total output power should be taken from the (+5V volt) main output.4.Bandwidth guaranteed by design. Tested for 20KHz to 2MHz.5.An overload is that condition with a load in excess of the rated load but less than that necessary to trigger the short circuit protection and is the condition of maximum power dissipation.6.Above 125°C case temperature, derate output power linearly to 0 at 135°C caseTESTSYMBOLCondition-55°C ≤ T C ≤+125°C, V IN = 28 V DC ±5%, C L =0unless otherwise specifiedATO2812T/HBATO2815T/HBMin Max Min Max UnitsSTATICCHARACTERISTICSOUTPUTVoltageVI = 0 (main)I = 0 (dual)TC = 25°COver TempTC = 25°COver Temp 4.95 4.90 ±11.88 ±11.76 5.05 5.10 ±12.12 ±12.24 4.95 4.90 ±14.85 ±14.70 5.05 5.10 ±15.15 ±15.30 V V V V CurrentI V = 16, 28, and 40 VDC (main) 0.0 2000 0.0 2000 mARipple Voltage V V = 16, 28, and 40 VDC (dual)V = 16, 28, and 40 VDC 0.0 ±208 80 0.0 ±16780mA mVp-pBW = DC to 2 MHz (main) V = 16, 28, and 40 VDC BW = DC to 2 MHz (dual))4040mVp-pPower P V = 16, 28, and 40 VDC (main)(+dual) (-dual) (total)10 2.5 2.5 15 10 2.5 2.5 15 WW W WREGULATIONLine Load VR VR V = 16, 28, and 40 VDC I = 0, 1000, 2000mA (main) V = 16, 28, and 40 VDC (dual) I = 0, ±84, ±167mA (dual) V = 16, 28, and 40 VDCI = 0, 1000, 2000mA (main) V = 16, 28, and 40 VDC I = 0, ±84, ±167mA (dual)TC = 25°C Over Temp 25 ±30 ±60 50 ±6025 ±35±7550±75mVmV mV mV mV INPUTCurrentRipple Current I II = 0, Inhibit (pin 8) Tied to input return (pin 10) I = 0, inhibit (pin 2) = open I = 2000 mA (main) I = ±167mA (dual) BW = DC to 2MHz15 40 50 15 40 50mA mA mAp-pEFFICIENCY E I = 2000mA (main)I = ±167mA (dual) TC = ±25°CTC = 25°C 76 76 %ISOLATION ISO Input to output or any pin tocase (except pin 7) at 500 VDC, TC = +25°CTC = 25°C 100 100 M Ω Load Fault Power Dissipation P Overload, TC = +25°CShort Circuit, TC = +25°CTC = 25°C8 68 6 W W Switching FrequencyFI = 2000mA (main) I = ±167mA (dual)225 275225275KHzInhibit Open Circuit VoltageV 9 13 9 13 V5ATO28XXT SeriesATO28XXT Block DiagrameturnATO28XXT SeriesPin DesignationATO28XXT Case OutlinePart NumberingATO 28 15 T / CHM odelInput V oltage28 = 28VO utputsT = TripleO utput V oltages15 = 5V, ± 15V12 = 5V, ± 12VS creening Level—, E S, H B , C HPin No.Designation1 + Input 2+ 5V DC Input3 Output Return4 -Dual Output5 + Dual Output6 N/C7 Case Ground 8 Enable Input 9 N/C 10 Input ReturnOutput7ATO28XXT SeriesAvailable Standard Military Drawing (SMD) Cross ReferenceWORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331ADVANCED ANALOG: 2270 Martin Av., Santa Clara, California 95050, Tel: (408) 727-0500Visit us at for sales contact information .Data and specifications subject to change without notice. 11/02Available Screening Levels and Process Variations for ATO28XXT Series* Per Commercial StandardsStandardized Vendor Vendor Military Drawing CAGE SimilarPin Code Pin5962-9095401HXX 52467 ATO2815T/CH 5962-9095401HZX 52467 ATO2815TF/CH 5962-9160201HXX 52467 ATO2812T/CH 5962-9160201HZX 52467 ATO2812TF/CHRequirement MIL-STD-883 MethodNo Suffix ES Suffix HB Suffix CH Suffix Temperature Range-55°C to +85°C-55°C to +125°C-55°C to +125°C-55°C to +125°CElement Evaluation MIL-PRF-38534 Internal Visual 2017 ¬ Yes Yes Yes Temperature Cycle 1010, Cond C Cond A Yes Yes Constant Acceleration 2001, Cond A500g5,000g5,000gBurn-in 1015 48 hrs @ 85ºC48hrs @ 105°C160hrs @ 125°C 160hrs @ 125°C Final Electrical (Group A)MIL-PRF-38534 & Specification25°C25°C-55, +25, +125°C-55, +25, +125°CSeal, Fine & Gross 1014 Yes Yes YesExternal Visual2009¬Yes Yes Yes。

1.General descriptionThe TDA8295 is an alignment-free digital multistandard vision and sound low IF signal PLL demodulator for positive and negative video modulation including AM and FM mono sound processing. It can be used in all countries worldwide for M/N, B/G/H, I, D/K,L and L-accent standard.CVBS and SSIF/mono audio is provided via two DACs.FM radio preprocessing is included for simple interfacing with demodulator/stereo decoder backends.The IC is especially suited for the application with the NXP Silicon Tuner TDA8275A or TDA1827x.All the processing is done in the digital domain.The chip has an ‘easy programming’ mode to make the I 2C-bus protocol very simple. In principle, only one bit sets the proper standard with recommended content. However, if this is not suitable, free programming is always possible.2.FeaturesI Digital IF demodulation for all analog TV standards worldwide (M/N, B/G/H, D/K, I,L and L-accent standard)I Multistandard true synchronous demodulation with active carrier regeneration I Alignment-freeI 16MHz typical reference frequency input (from low IF tuner) or operating as crystal oscillatorI Internal PLL synthesizer which allows the use of a low-cost crystal (typically 16MHz)I Especially suited for the NXP Silicon Tuner TDA8275A or TDA1827x I No SAW filter neededI Low application effort and external component count in combination with the TDA8275A or TDA1827xI Pin compatible with predecessor TDA8290I Simple upgrade of TDA8290 possibleI 12-bit IF ADC on chip running with 54MHz or 27MHz I Two 10-bit DACs on chip for CVBS and SSIF or audio I Easy programming for I 2C-busI High flexibility due to various I 2C-bus programming registersI I 2C-bus interface and I 2C-bus feed-through for tuner programming I Four I 2C-bus addresses selectable via two external pinsTDA8295Digital global standard low IF demodulator for analog TV and FM radioRev. 01 — 4 February 2008Product data sheetI Gated IF AGC acting on black level by using H/V PLL or peak IF AGC (I2C-busselectable)I Internal digital logarithmic IF AGC amplifier with up to 48dB gain and 68dB controlrangeI Peak search tuner IF AGC for optimal adaptive drive of the IF ADCI Switchable IF PLL and IF AGC loop bandwidthsI Precise AFC and lock detectorI Accurate group delay equalization for all standardsI Very robust IF demodulator coping with adverse field conditionsI Wide PLL pull-in range up to±1660kHz (I2C-bus selectable)I CVBS and SSIF or audio output with simple postfilter (capacitor only)I CVBS gain levelling stage to provide nearly constant signal amplitude duringovermodulationI Video equalizer with eight settingsI Nyquist filter in video basebandI Excellent video S/N (typically 62dB weighted)I High selectivity video low-pass filter for all standardsI Low video into sound crosstalkI Sound performance comparable to QSS single reference conceptsI AM/FM mono sound demodulatorI Switchable de-emphasisI Excellent FM soundI Good AM soundI High FM Deviation mode for ChinaI Preprocessing of FM radio (mono and stereo) with highly selective digital band-passfilterI No ceramic filter or external components needed for FM radioI FM radio available in monoI Automatic or forced mute for mono soundI Automatic or forced blank for videoI Mostly digital FIR filter implementation (NSC notches and video low-pass filters)I Three GPIO pinsI Low total power dissipation (typically 324mW)I Standby mode (typically 7mW)I40-pin HVQFN packageI CMOS technology (0.12µm 1.2V and 3.3V)3.ApplicationsI PC TV applicationsI DVD recorders4.Quick reference dataTable 1.Quick reference dataPower supplies3.3V,1.2V;T amb=25°C;PC/SC1for L and M=10dB,all others13dB;residual picture carrier for L=3%, all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure12) with 16MHz crystal frequency, loaded with 75Ω (CVBS) and 1kΩ (SSIF/audio). Values are meant for ‘easy programming’settings(recommended)except internal mono audio and IF demodulation.The low IF spectrum is delivered by a professional downconverter.Symbol Parameter Conditions Min Typ Max Unit Power supplyV DD(1V2)supply voltage (1.2V)digital and analog 1.08 1.2 1.32VV DD(3V3)supply voltage (3.3V)digital and analog 2.97 3.3 3.63VI DD(tot)(1V2)total supply current (1.2V)-2833mAI DD(tot)(3V3)total supply current (3.3V)[1]-125136mAP tot total power dissipation default settings; 75Ω drive;f s=54MHz at ADC; including DACloads; R RSET=1kΩ[1]-434490mWPower-save mode; f s=54MHz atADC; including DAC loads;R RSET=2kΩ; see Section13.6[2]-324369mWStandby mode-710mWIF inputV i(p-p)peak-to-peak input voltage for full-scale ADC input (0dBFS) 1.8 2.0 2.2VV i input voltage operational input related to ADC fullscale; all standards; sum of all signals−3−3−3dBFS f i input frequency PC / SC1M/N standard- 5.75 / 1.25-MHzB standard- 6.75 / 1.25-MHzG/H standard-7.75 / 2.25-MHzI standard-7.75 / 1.75-MHzDK and L standard-7.75 / 1.25-MHzL-accent standard- 1.25 / 7.75-MHzFM radio- 1.25-MHz Carrier recovery FPLLB−3dB(cl)closed-loop−3dBbandwidthwide606060kHz∆f pullin pull-in frequency range[3]±830±830±830kHzm over(PC)picture carrierovermodulation index black for L/L-accent standard;flatfieldwhite else115117-%IF demodulation (video equalizer in Flat mode)αsup(stpb)stop-band suppression video low-pass filter (M/N, B/G/H, I,D/K, L/L-accent standard)-−60-dBt ripple(GDE)group delay equalizerripple time peak value for B/G/H half, D/K half,Iflat, M(FCC) full, L/L-accent fullstandard-2040nsCVBS outputV o(p-p)peak-to-peak output voltagenegative PC modulation (all standards except L/L-accent); 75Ω DC load;sync-white modulation 90% (nominal)0.81.01.2Vpositive PC modulation (L/L-accent standard); 75ΩDC load; sync-white modulation 97% (nominal)0.81.01.2VB video(−3dB)−3dB video bandwidthoverall video response; CVBS equalizer flatall standards except M/N 4.8 4.85-MHz M/N standard3.94.05-MHz αresp(f)frequency response video equalizer; 8equally spaced settings; value at 3.9MHz−5-+4.5dB G dif differential gain “ITU-T J.63 line 330”- 1.53%ϕdif differential phase “ITU-T J.63 line 330”- 1.53deg (S/N)wweighted signal-to-noise ratioall standards; unified weighting filter (“ITU-T J.61”); PC at −6dBFS 5862-dBSSIF/mono sound outputV o(SSIF)(RMS)RMS SSIF output voltage1k Ω DC or AC load; no modulation;PC /SC1=13dB; scaled linearly for all other ratiosall standards except B/G/H 303540mV B/G/H standard 273237mV FM radio (single carrier)460530610mV V o(AF)(RMS)RMS AF output voltage 1k Ω DC or AC loadM standard; 54% modulation degree (±13.5kHz FM deviation before pre-emphasis)125143165mVB, G/H, I, D, K standard; 54%modulation degree (±27kHzFM deviation before pre-emphasis)125143165mVαhr(AF)AF headroom before clipping; 1k Ω DC or AC load M standard; related to ±25kHzpeak deviation before pre-emphasis 777dB B, G/H, I, D, K standard; related to ±50kHz peak deviation before pre-emphasis777dBTHD total harmonic distortionFM; for 50kHz deviation beforepre-emphasis (25kHz for M standard)-0.10.2%AM; m =80%-0.61%Table 1.Quick reference data …continuedPower supplies 3.3V ,1.2V;T amb =25°C;PC /SC1for L and M =10dB,all others 13dB;residual picture carrier for L =3%,all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with 16MHz crystal frequency, loaded with 75Ω (CVBS) and 1k Ω (SSIF/audio). Values are meant for ‘easy programming’settings (recommended)except internal mono audio and IF demodulation.The low IF spectrum is delivered by a professional downconverter.Symbol ParameterConditionsMinTypMaxUnit[1]50% ADC current; 100% video DAC current; 50% sound DAC current.[2]50% ADC current; 50% video DAC current; 25% sound DAC current.[3]The pull-in range can be doubled to ±1660kHz by I 2C-bus register like described in T able 16. Then the AFC read-out has 256steps.5.Ordering informationB AF(−3dB)−3dB AF bandwidth AM 2027-kHz FM4050-kHz(S/N)w(AF)AF weightedsignal-to-noise ratiovia internal mono sound demodulator;“ITU-R BS.468-4”;FM mode related to 27kHz deviation before pre-emphasis;10% residual PC; SC1color bar picture5458-dBvia internal mono sound demodulator;“ITU-R BS.468-4”;AM;m =54%;3%residual PC; SC1color bar picture4346-dBTable 1.Quick reference data …continuedPower supplies 3.3V ,1.2V;T amb =25°C;PC /SC1for L and M =10dB,all others 13dB;residual picture carrier for L =3%,all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with 16MHz crystal frequency, loaded with 75Ω (CVBS) and 1k Ω (SSIF/audio). Values are meant for ‘easy programming’settings (recommended)except internal mono audio and IF demodulation.The low IF spectrum is delivered by a professional downconverter.Symbol ParameterConditions Min Typ Max Unit Table 2.Ordering informationType numberPackage NameDescriptionVersion TDA8295HNHVQFN40plastic thermal enhanced very thin quad flat package; no leads;40terminals; body 6×6×0.85mmSOT618-1xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x xTDA8295_1© NXP B.V . 2008. All rights reserved.Product data sheet Rev. 01 — 4 February 20086 of 77NXP SemiconductorsTDA8295Digital global standard low IF demodulator for analog TV and FM radio6.Functional diagramFig 1.Functional diagram of TDA82952001aah354analog CVBSanalog SSIFormono soundlow IF signaltuner IF AGC I 2C-busGATED AGC DETECTORANDINTEGRATORH/V PLLVIDEO DACUPSAMPLERVIDEO/GROUP DELAY EQUALIZERVIDEO LOW-PASS FILTER SWITCH I 2C-BUSUPSAMPLERSOUND DACNYQUIST SLOPEPLLDEMODULATOR FILTERS ANDAGC AMPLIFIERPEAK DETECTORANDINTEGRATORBIT STREAMDACcrystal or frequency referenceCLOCK PROCESSOR AND PLL SUPPL Y , REFERENCEANDDECOUPLINGIF ADCSSIF AND FM RADIO BAND-P ASS FILTERS CORDIC AM/FMSOUND DEMODULATOR元器件交易网7.Pinning information7.1PinningFig 2.Pin configuration for HVQFN40Table 3.Pin allocation table Pin Symbol Pin Symbol 1IF_POS 2IF_NEG 3V DDA(ADC)(3V3)4V DDD1(1V2)5V SSD16i.c.7V DDA(PLL)(1V2)8XIN 9XOUT 10V SSA(PLL)11RSET 12V SSA(DAC)13V_IOUTN 14V_IOUTP 15V DDA(DAC1)(3V3)16S_IOUTN 17S_IOUTP 18V DDA(DAC2)(3V3)19SADDR020SADDR121RST_N 22TDO 23TDI 24TMS 25V DDD2(1V2)26V SSD227TCK 28SCL 29SDA30TRST_N008aaa095TDA8295HNRST_NXOUTV SSA(PLL)TDO XIN TDI V DDA(PLL)(1V2)TMS i.c.V DDD2(1V2)V SSD1V SSD2V DDD1(1V2)TCK V DDA(ADC)(3V3)SCL IF_NEGSDA IF_POS TRST_N R S E T V S S A (D A C )V _I O U T N V _I O U T P V D D A (D A C 1)(3V 3)S _I O U T N S _I O U T P V D D A (D A C 2)(3V 3)S A D D R 0S A D D R 1V S S A (A D C )V D D D (A D C )(3V 3)i.c .I F _A G Ci.c .V S S D RV D D D R (3V 3)G P I O 0/V S Y N CG P I O 1/S C L _OG P I O 2/S D A _O10219228237246255264273282291301112131415161718192040393837363534333231terminal 1index areaT ransparent top view7.2Pin description31GPIO2/SDA_O 32GPIO1/SCL_O 33GPIO0/VSYNC 34V DDDR(3V3)35V SSDR 36i.c.37IF_AGC 38i.c.39V DDD(ADC)(3V3)40V SSA(ADC)Table 3.Pin allocation table …continued Pin Symbol Pin Symbol Table 4.Pin descriptionSymbol PinType [1][2]DescriptionReset RST_N21IThe RST_N input is asynchronous and active LOW, and clears the TDA8295.When RST_N goes LOW, the circuit immediately enters its Reset mode and normal operation will resume four XIN signal falling edges later after RST_N returns HIGH. Internal register contents are all initialized to their default values.The minimum width of RST_N at LOW level is four XIN clock periods.Reference XIN8ICrystal oscillator input pin. In Slave mode (typically), the XIN input simply receives a 16MHz clock signal from an external device (typically from theTDA8275A or TDA1827x). In Oscillator mode, a fundamental 16MHz (typically)crystal is connected between pin XIN and pin XOUT .XOUT 9OCrystal oscillator output pin. In Slave mode, the XOUT output is not connected.In Oscillator mode a fundamental 16MHz (typically) crystal is connected between pin XIN and pin XOUT.I 2C-bus SDA 29I/O, OD I 2C-bus bidirectional serial data. SDA is an open-drain output and therefore requires an external pull-up resistor (typically 4.7k Ω).SCL 28I I 2C-bus clock input. SCL is nominally a square wave with a maximum frequency of 400kHz. It is generated by the system I 2C-bus master.SADDR019I These two bits allow to select four possible I 2C-bus addresses, and therefore permits to use several TDA8295 in the same application and/or to avoid conflict with other ICs. The complete I 2C-bus address is: 1, 0, 0, SADDR1, 0, 1,SADDR0 (see also Section 9.1).SADDR120II 2C-bus feed-through switch or GPIO GPIO2/SDA_O31I/O, ODSDA_O is equivalent to SDA but can be 3-stated by I 2C-bus programming. It is the output of a switch controlled by I2CSW_EN parameter. SDA_O is an open-drain output and therefore requires an external pull-up resistor (see Section 9.3.20).GPIO1/SCL_O 32I/O, ODSCL_O is equivalent to SCL input but can be 3-stated by I 2C-bus programming.SCL_O is an open-drain output and therefore requires an external pull-upresistor (see Section 9.3.20).For proper functioning of the I 2C-bus feed-through,a capacitor C =33pF to GND must be added (see Section 13.6).V-sync or GPIO GPIO0/VSYNC 33I/O, ODvertical synchronization pulse needed for the NXP Silicon Tuner (see Section 9.3.20)Tuner IF AGC IF_AGC37I/O, OD, T tuner IF AGC outputTable 4.Pin description …continuedSymbol Pin Type[1][2]DescriptionBoundary scanTMS24I T est mode select provides the logic levels needed to change the T AP controllerfrom state to state during the boundary scan test.TRST_N30I T est reset is used to reset the TAP controller (active LOW). Grounding ismandatory in Functional mode.TCK27I Test clock is used to drive the T AP controller.TDI23I T est data input is the serial data input for the test data instruction.TDO22O T est data output is the serial test data output pin. The data is provided on thefalling edge of TCK.ADCIF_POS1AI IF positive analog input for internal ADCIF_NEG2AI IF negative analog input for internal ADCDACV_IOUTP14AO positive analog current output of the video outputV_IOUTN13AO negative analog current output of the video outputS_IOUTP17AO positive analog current output of the SSIF/mono sound outputS_IOUTN16AO negative analog current output of the SSIF/mono sound outputRSET11I External bias setting of the DACs. An external resistor (1kΩ typical) has to beconnected between RSET and the analog ground of the board. This resistorgenerates the current into the DACs and also defines the full scale outputcurrent.The total parasitic capacitance seen externally from the RSET pin has tobe lower than 20pF.Supplies and groundsV DDA(DAC1)(3V3)15PS DAC1 (video DAC) and DAC reference module analog supply voltage (3.3Vtypical)V DDA(DAC2)(3V3)18PS DAC2 (sound DAC) analog supply voltage (3.3V typical)V SSA(DAC)12GND DAC reference module analog ground supply voltage (0V typical)V DDA(ADC)(3V3)3PS IF ADC analog supply voltage (3.3V typical)V DDD(ADC)(3V3)39PS IF ADC digital supply voltage (3.3V typical)V SSA(ADC)40GND ADC analog ground supply voltage (0V typical)V DDD1(1V2)4PS ADC, PLL and DACs digital supply voltage (1.2V typical)V SSD15GND ADC, PLL and DACs digital ground supply voltage (0V typical)V DDA(PLL)(1V2)7PS crystal oscillator and clock PLL analog supply voltage (1.2V typical)V SSA(PLL)10GND crystal oscillator and clock PLL analog ground supply voltage (0V typical)V DDD2(1V2)25PS core digital supply voltage (1.2V typical)V SSD226GND core digital ground supply voltage (0V typical)V DDDR(3V3)34PS ring digital supply voltage (3.3V typical)V SSDR35GND ring digital ground supply voltage (0V typical)Other pinsi.c.36I internally connected; connect to groundi.c.38I internally connected; connect to groundi.c.6I internally connected; connect to ground[1]All digital inputs are 5V tolerant (except pin XIN).[2]The pin types are defined in Table5.Table 5.Pin type descriptionType DescriptionAI analog inputAO analog outputGND groundI digital inputI/O digital input and outputO digital outputOD open-drain outputPS power supplyT3-state8.Functional description8.1IF ADCThe low IF spectrum (1MHz to 10MHz) from the Silicon Tuner TDA8725A or TDA1827xis fed symmetrically to the 12-bit IF ADC of the TDA8295, where it is sampled with54MHz or 27MHz. All the anti-aliasing filtering is already done in the Silicon Tuner.8.2FiltersThe internalfilters permit to reduce the sampling rate to13.5MHz,and to form a complexsignal to ease the effort of further signal processing. Before this, the DC offset (comingfrom the ADC) is removed.In addition, standard dependent notch filters for the adjacent sound carriers protect thepicture carrier PLL from malfunctioning and avoid disturbances (i.e. moire) becomingvisible in the video output.8.3PLL demodulatorThe second-order PLL is the core block of the whole IC. It is very robust against adversefield conditions, like excessive overmodulation, no residual carrier presence or unwantedphase or frequency modulation of the picture carrier.The PLL output is the synchronouslydemodulated channel.The AFC data is available via the I2C-bus.8.4Nyquist filter, video low-pass filter, video and group delay equalizer,video levelingThe afore-mentioned down-mixed complex signal at the mixer CORDIC output, alreadyconsisting of the demodulated content of the picture carrier together with the soundcarriers (the so-called intercarriers), is running through a Nyquist filter to get a flat videoresponse and is made real.Afterwards, a video low-pass filter suppresses the sound carriers and other disturbers.Next comes the equalizer circuit to remove the transmitter group delay predistortion.A video leveling stage follows, which brings the output within the SCART specification(3dB overall), despite heavy overmodulation. The response time is made very slow.Finally, a video equalizer allows to compensate the perhaps non-flat frequency response from the tuner or to change the overall video response according to customer wish (i.e.peaking or early roll-off).8.5Upsampler and video DACThe filtered and compensated CVBS signal is connected to the oversampled 10-bit video DAC(f s=108MHz)via an interpolation stage.The strong oversampling replaces a former complicated LCR postfiltering by a simplefirst-order RC low-passfilter to remove the DAC image frequencies sufficiently. This holds also for the sound DAC, described inSection8.6.8.6SSIF/mono sound processingThe complex signal is routed via a band-pass and interpolation filter to the 10-bit sound DAC for the recovery of the second sound carriers(SSIF).A very sharp band-passfilter at5.5MHz is added in the FM Radio mode to remove neighbor channels. This also easesthe dynamic burden on the following ADC in the demodulator/decoder chip. Theafore-mentioned high-selectivity band-pass, which replaces the former ceramic filter, is located behind a frequency shifter. In there, the incoming wanted FM radio channel from the Silicon T uner is changed from 1.25MHz to 5.5MHz.Moreover, the complex signal is demodulated in a linear CORDIC detector and low-pass filtered to attenuate the video spectrum and the second sound carrier, respectively other disturbers above the intercarrier. The output of the linear CORDIC (phase information) is differentiated for getting the demodulated FM audio.The AM demodulation is executed ina synchronous fashion by using a narrow-band PLL demodulator.A de-emphasis filter is implemented for FM standards, before the audio is interpolated to108MHz as in the CVBS case.The mono audio is made available in the sound DAC via an I2C-bus controlled selector in case the intercarrier path is not used for driving an external stereo demodulator.However, if the mono audio output has to meet the SCART specification, an externalcheap operational amplifier with 12dB gain becomes necessary, because the low supply voltage for the TDA8295 doesn’t allow such high levels like 2V(RMS) maximum.8.7Tuner IF AGCThis AGC controls the tuner IF AGC amplifier in the TDA8275A or TDA1827x in such a way,that the IF ADC is always running with a permanent headroom of3dB for the sum of all signals present at the ADC input. This ensures an always optimal exploitation of the dynamic range in the IF ADC.The detection is done in peak Search mode during afield period.The attack time is made much faster than the decay time in order to avoid transient clipping effects in the IF ADC.This can happen during channel change or airplane flutter conditions.The above wideband, slowly acting AGC loop (uncorrelated) is of first-order integralaction. It is closed via the continuous tuner IF AGC amplifier in the Silicon Tuner via abit stream DAC (PWM signal at 13.5MHz, 27MHz or 54MHz) and an external anduncritical first-order RC low-pass.8.8Digital IF AGCCommon to both IF AGC concepts is the peak search algorithm as long as the H/V PLL isnot locked.This is of advantage for the acquisition by avoiding hang-ups due to excessiveoverloading, so being able to leave the saturated condition by reducing the gain.Two Detection modes are made available in the IC via I2C-bus.•Black level gated AGC:The first mode uses an IF AGC detector which is gated with a very robust andwell-proven H/V sync PLL block on board. Gating occurs on the black level (most ofthe time on the back porch) of the video signal and the control is delivered after anerror integration and exponential weighting to the internal IF AGC amplifier. ThisIF AGC amplifier, in fact a multiplier, has a control range of−20dB to +48dB.•Peak AGC:A fast attack and slow decay action cares for a good and nearly clip-free transientbehavior. This proved to be more robust for non-standard signals, like sync clippingalong the transmitter/receiver chain.With respect to the IF AGC speed generally, only the gated black level or peak syncIF AGC can be made fast.However the peak search one,used for positive modulationstandards(L and L-accent standard),is rather slow because the VITS is present onlyonce in a field.The correlated or narrow-band AGC loop, closed via the continuous IF AGC amplifierin the TDA8295, is of first-order integral action and settles at a constant IF input levelwith a permanent headroom of 12dB (picture carrier). This headroom is needed forthe own sound carriers and the leaking neighbor (N−1) spectrum.8.9Clock generationFinally, either an external reference frequency (i.e. from the Silicon Tuner) or an ownon-chip crystal oscillator in the TDA8295 feeds the internal PLL synthesizer to generatethe necessary clock signals.9.I2C-bus control9.1Protocol of the I2C-bus serial interfaceThe TDA8295 internal registers are accessible by means of the I2C-bus serial interface.The SDA bidirectional pin is used as the data input/output pin and SCL as the clock inputpin. The highest SCL speed is 400kHz.9.1.1Write modeFig 3.I 2C-bus Write mode Table 6.Address format7654321010SADDR11SADDR0R/WTable 7.I 2C-bus transfer descriptionField Bit Description S -START condition Byte 17 to 5device address 4SADDR13 and 2device address 1SADDR0R/W =0 for write action A -acknowledge Byte 27 to 0start index A -acknowledge Byte 37 to 0data 1A -acknowledge :Byte n 7 to 0data n A -acknowledge P-STOP conditiona.Address 84h, write 02h in register 01hb.Address 84h, write 05h in register 02h and 04h in register 03h Fig 4.Examples I 2C-bus Write mode001aad381BYTE 1BYTE 2BYTE 3BYTE n S A A A A P address 0start indexdata 1data nstartackackack....ackstop001aah355BYTE 1S A 1000 0100BYTE 20000 0001BYTE 30000 0010startackA ackA ackP stop001aah356BYTE 1S 1000 0100BYTE 20000 0010BYTE 30000 0101BYTE 40000 0100startA ackA ackA ackA ackP stop9.1.2Read modeFig 5.I2C-bus Read mode 001aad423BYTE 1 Saddress 0BYTE 2start indexBYTE 3address 1BYTE 4value 1BYTE nvalue nstartAackAackAackAack....AackPstopSstartTable 8.I2C-bus transfer descriptionField Bit DescriptionS-START conditionByte 17 to 5device address4SADDR13 and 2device address1SADDR00R/W=0 for write actionA-acknowledgeByte 27 to 0start indexA-acknowledgeS-START condition (without stop before) Byte 37 to 5device address4SADDR13 and 2device address1SADDR00R/W=1 for read actionA-acknowledgeByte 47 to 0value 1A-acknowledge:Byte n7 to 0value nA-acknowledgeP-STOP conditionAddress 84h, read register 02h with value 05h and read register 03h with value 04h Fig 6.Example I2C-bus Read mode 001aah357BYTE 1 S1000 0100BYTE 20000 0010BYTE 31000 0101BYTE 40000 0101BYTE 50000 0100startAackAackAackAackAackPstopSstart9.2Register overviewThe TDA8295internal registers are accessible by means of the I2C-bus serial interface as described in Section9.1. In Table9 and T able10 an overview of all the registers is given, the register description can be found in Section9.3.xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxTDA8295_1© NXP B.V . 2008. All rights reserved.Product data sheet Rev. 01 — 4 February 200816 of 77NXP SemiconductorsTDA8295Digital global standard low IF demodulator for analog TV and FM radioTable 9.I 2C-bus registersIndex Name7 (MSB)6543210 (LSB)00h STANDARD ST ANDARD[7:0]01h EASY_PROG -------ACTIVE 02h DIV_FUNC AGC_SEL AGC_TRI --0POL_DET VID_MOD IF_SWAP 03h ADC_HEADR ----ADC_HEADR[3:0]04h PC_PLL_FUNC PC_PLL_BW[4:0]PLL_ONPULL_INCAR_DET05h PC_PLL_THRES ----PH_ERR_THRES[3:0]06h PC_PLL_WGT PHASE_PER PHASE_GAIN[6:0]07h PC_FLL_FUNC FLL_ON LIM_ON FLL_LIM[5:0]08h CARDET_LEVEL ---CAR_DET_LVL[4:0]09h DTO_PC_LOW DTO_PC[7:0]0Ah DTO_PC_MID DTO_PC[15:8]0Bh DTO_PC_HIGH DTO_PC[23:16]0Ch DTO_SC_LOW DTO_SC[7:0]0Dh DTO_SC_MID DTO_SC[15:8]0Eh DTO_SC_HIGH DTO_SC[23:16]0Fh FILTERS_1VID_FILT[2:0]NOTCH_FILT[4:0]10h FILTERS_2---DC_NOTCH SBP[3:0]11h GRP_DELAY ---GRP_DEL[4:0]12h D_IF_AGC_SET_1D_IF_AGC_CORRD_IF_AGC_MODED_IF_AGC_AVG[4:0]RST_INT13h D_IF_AGC_SET_2D_AGC_ERR_LIM D_IF_AGC_BW[6:0]14h D_IF_AGC_FORCE D_FORCE D_FORCE_VAL[6:0]15h T_IF_AGC_SET POL_TIF T_IF_AGC_SPEED[6:0]16h T_IF_AGC_LIM UP_LIM[3:0]LOW_LIM[3:0]17h T_IF_AGC_FORCE T_FORCE T_FORCE_VAL[6:0]18h T_IF_AGC_FS -----T_IF_AGC_FS[2:0]19h to 1Bh reservedreserved1Ch V_SYNC_DEL VS_WIDTH[1:0]VS_POL VS_DEL[4:0]1DhCVBS_SET-----FOR_BLKAUTO_BLKVID_LVL。

November 2016 DocID2143 Rev 34 1/54This is information on a product in full production.L78Positive voltage regulator ICsDatasheet - production dataFeatures∙ Output current up to 1.5 A∙ Output voltages of 5; 6; 8; 8.5; 9; 12; 15; 18; 24 V∙ Thermal overload protection ∙ Short circuit protection∙ Output transition SOA protection∙ 2 % output voltage tolerance (A version) ∙ Guaranteed in extended temperature range (A version)DescriptionThe L78 series of three-terminal positiveregulators is available in TO-220, TO-220FP, D²PAK and DPAK packages and several fixed output voltages, making it useful in a wide range of applications.These regulators can provide local on-card regulation, eliminating the distribution problems associated with single point regulation. Each type embeds internal current limiting, thermal shut-down and safe area protection, making it essentially indestructible. If adequate heat sinking is provided, they can deliver over 1 A output current. Although designed primarily as fixed voltage regulators, these devices can be used with external components to obtain adjustable voltage and currents.Contents L78 Contents1Diagram (3)2Pin configuration (4)3Maximum ratings (5)4Test circuits (6)5Electrical characteristics (7)6Application information (23)6.1Design consideration (23)7Typical performance (31)8Package information (33)8.1TO-220 (dual gauge) package information (34)8.2TO-220 (single gauge) package information (36)8.3TO-220FP package information (38)8.4TO-220 packing information (40)8.5DPAK package information (41)8.6D²PAK (SMD 2L STD-ST) type A package information (44)8.7D²PAK (SMD 2L Wooseok-subcon.) package information (46)8.8D²PAK and DPAK packing information (49)9Ordering information (52)10Revision history (53)L78 Diagram1 DiagramFigure 1: Block diagramPin configuration L782 Pin configurationFigure 2: Pin connections (top view)L78Maximum ratings3 Maximum ratingsAbsolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.Figure 4: Application circuitsTest circuits L784 Test circuitsFigure 5: DC parameter5 Electrical characteristicsV I = 10 V, I O = 1 A, T J = 0 to 125 °C (L7805AC), T J = -40 to 125 °C (L7805AB), unlessotherwise specified aNotes:(1)Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.a Minimum load current for regulation is 5 mA.otherwise specified aNotes:(1)Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.a Minimum load current for regulation is 5 mA.otherwise specified aNotes:(1)Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.a Minimum load current for regulation is 5 mA.otherwise specified aNotes:(1)Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.a Minimum load current for regulation is 5 mA.otherwise specified aNotes:(1)Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.a Minimum load current for regulation is 5 mA.otherwise specified aNotes:(1)Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.a Minimum load current for regulation is 5 mA.otherwise specified aNotes:(1)Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.a Minimum load current for regulation is 5 mA.unless otherwise specified aNotes:(1)Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.a Minimum load current for regulation is 5 mA.unless otherwise specified aNotes:(1)Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.a Minimum load current for regulation is 5 mA.unless otherwise specified aNotes:(1)Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.a Minimum load current for regulation is 5 mA.Refer to the test circuits, T J = 0 to 125 °C, V I = 14.5 V, I O = 500 mA, C I = 0.33 µF,C O = 0.1 µF unless otherwise specified aNotes:(1)Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.a Minimum load current for regulation is 5 mA.unless otherwise specified aNotes:(1)Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.a Minimum load current for regulation is 5 mA.unless otherwise specified aNotes:(1)Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.a Minimum load current for regulation is 5 mA.unless otherwise specified aNotes:(1)Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.a Minimum load current for regulation is 5 mA.unless otherwise specified aNotes:(1)Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.a Minimum load current for regulation is 5 mA.unless otherwise specified aNotes:(1)Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.a Minimum load current for regulation is 5 mA.6 Application information6.1 Design considerationThe L78 Series of fixed voltage regulators are designed with thermal overload protectionthat shuts down the circuit when subjected to an excessive power overload condition,internal short-circuit protection that limits the maximum current the circuit will pass, andoutput transistor safe-area compensation that reduces the output short-circuit current asthe voltage across the pass transistor is increased. In many low current applications,compensation capacitors are not required. However, it is recommended that the regulatorinput be bypassed with capacitor if the regulator is connected to the power supply filter withlong lengths, or if the output load capacitance is large. An input bypass capacitor should beselected to provide good high frequency characteristics to insure stable operation under allload conditions. A 0.33 µF or larger tantalum, mylar or other capacitor having low internalimpedance at high frequencies should be chosen. The bypass capacitor should bemounted with the shortest possible leads directly across the regulators input terminals.Normally good construction techniques should be used to minimize ground loops and leadresistance drops since the regulator has no external sense lead.The addition of an operational amplifier allows adjustment to higher or intermediate valueswhile retaining regulation characteristics. The minimum voltage obtained with thearrangement is 2 V greater than the regulator voltage.The circuit of Figure 13: "High current voltage regulator" can be modified to provide supplyprotection against short circuit by adding a short circuit sense resistor, RSC, and anadditional PNP transistor. The current sensing PNP must be able to handle the short circuitcurrent of the three terminal regulator Therefore a four ampere plastic power transistor isspecified.1. Although no output capacitor is need for stability, it does improve transient response.2. Required if regulator is located an appreciable distance from power supply filter.Figure 14: High output current with short circuit protectionFigure 16: Split power supply (± 15 V - 1 A)* Against potential latch-up problems.Figure 21: High input and output voltageFigure 22: Reducing power dissipation with dropping resistorThe circuit performs well up to 100 kHz.Figure 25: Adjustable output voltage with temperature compensationQ2 is connected as a diode in order to compensate the variation of the Q1 V BE with the temperature. C allows a slow rise time of the V O.Figure 26: Light controllers (VO(min) = VXX + VBE)Application with high capacitance loads and an output voltage greater than 6 volts need an external diode (see Figure 22: "Reducing power dissipation with dropping resistor") to protect the device against input short circuit. In this case the input voltage falls rapidly while the output voltage decrease slowly. The capacitance discharges by means of the base-emitter junction of the series pass transistor in the regulator. If the energy is sufficiently high, the transistor may be destroyed. The external diode by-passes the current from the IC to ground.7 Typical performance8 Package informationIn order to meet environmental requirements, ST offers these devices in different grades ofECOPACK® packages, depending on their level of environmental compliance. ECOPACK®specifications, grade definitions and product status are available at: .ECOPACK® is an ST trademark.8.1 TO-220 (dual gauge) package information8.2 TO-220 (single gauge) package information8.3 TO-220FP package information8.4 TO-220 packing information8.5 DPAK package information8.6 D²PAK (SMD 2L STD-ST) type A package information8.7 D²PAK (SMD 2L Wooseok-subcon.) package information8.8 D²PAK and DPAK packing informationFigure 47: Tape outlineFigure 48: Reel outline。

FDS8958B Dual N & P-Channel PowerTrench ® MOSFETPin 1SO-8D1D1D2D2S2S1G1MOSFET Maximum Ratings T C = 25 °C unless otherwise noted® MOSFETDynamic CharacteristicsSwitching CharacteristicsDS(on)V GS = -10 V, I D = -4.5 A V GS = -4.5 V, I D = -3.3 AV GS = -10 V, I D = -4.5 A, T J = 125 °C Q2386053518072g FSForward Transconductance V DD = 5 V, I D = 6.4 A V DD = -5 V, I D = -4.5 AQ1Q22010SC iss Input Capacitance Q1V DS = 15 V, V GS = 0 V, f = 1 MHZ Q2V DS = -15 V, V GS = 0 V, f = 1 MHZQ1Q2 405570540760pF C oss Output CapacitanceQ1Q2 75115100155pF C rss Reverse Transfer Capacitance Q1Q25510080150pF R gGate ResistanceQ1Q22.44.4Ωt d(on)Turn-On Delay Time Q1V DD = 15 V, I D = 6.4 A, V GS = 10 V, R GEN = 6 ΩQ2V DD = -15 V, I D = -4.5 A, V GS = -10 V, R GEN = 6 ΩQ1Q2 4.36.01012ns t r Rise TimeQ1Q2 2.06.01012ns t d(off)Turn-Off Delay Time Q1Q2 12172230ns t f Fall TimeQ1Q2 2.07.01014ns Q g(TOT)Total Gate Charge V GS = 10 V V GS = -10 V Q1V DD = 15 V, I D = 6.4 A Q2V DD = -15 V, I D = -4.5 AQ1Q28.3141219nC Q g(TOT)Total Gate Charge V GS = 4.5 V V GS = -4.5 VQ1Q2 4.17.0 5.89.6nC Q gs Gate to Source Charge Q1Q2 1.31.9nC Q gdGate to Drain “Miller” ChargeQ1Q21.73.6nC®MOSFET2. Pulse Test: Pulse Width < 300 µs, Duty cycle < 2.0%.3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.4. UIL condition: Starting T J = 25 °C, L = 1 mH, I AS = 6 A, V DD = 27 V, V GS = 10 V . (Q1)Starting T J = 25 °C, L = 1 mH, I AS = -4 A, V DD = -27 V, V GS = -10 V. (Q2)MOSFETMOSFETMOSFETMOSFETMOSFETMOSFETFDS8958B Dual N & P-Channel PowerTrench ® MOSFETANTI-COUNTERFEITING POLICYFairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Farichild’s Anti-Counterfeiting Policy is also stated on our external website, , under Sales Support .Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed application, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts. Farichild strongly encourages customers to purchase Farichild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Farichild’s full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Farichild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors.PRODUCT STATUS DEFINITIONS Definition of Terms* EZSWITCH™ and FlashWriter ® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:1. Life support devices or systems are devices or systems which, (a) areintended for surgical implant into the body or (b) support or sustain life,and (c) whose failure to perform when properly used in accordance withinstructions for use provided in the labeling, can be reasonablyexpected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.Build it Now™CorePLUS™CorePOWER™CROSSVOLT ™CTL™Current Transfer Logic™EcoSPARK ®EfficentMax™EZSWITCH™ *™Fairchild ®Fairchild Semiconductor ®FACT Quiet Series™FACT ®FAST ®FastvCore™FlashWriter ® *FPS™F-PFS™FRFET ®Global Power Resource SM Green FPS™Green FPS™ e-Series™GTO™IntelliMAX™ISOPLANAR™MegaBuck™MICROCOUPLER™MicroFET™MicroPak™MillerDrive™MotionMax™Motion-SPM™OPTOLOGIC ®OPTOPLANAR ®®PDP SPM™Power-SPM™PowerTrench ®PowerXS™Programmable Active Droop™QFET ®QS™Quiet Series™RapidConfigure™™Saving our world, 1mW /W /kW at a time™SmartMax™SMART START™SPM®STEALTH™SuperFET™SuperSOT™-3SuperSOT™-6SuperSOT™-8SupreMOS™SyncFET™®The Power Franchise ®TinyBoost™TinyBuck™TinyLogic ®TINYOPTO™TinyPower™TinyPWM™TinyWire™µSerDes™UHC ®Ultra FRFET™UniFET™VCX™VisualMax™XS™®Datasheet Identification Product Status DefinitionAdvance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.Datasheet contains preliminary data; supplementary data will be published at a later date.分销商库存信息: FAIRCHILDFDS8958B。

TDA7295 80V - 80W DMOS AUDIO AMPLIFIER WITH MUTE/ST-BY VERY HIGH OPERATING VOLTAGE RANGE(±40V)DMOS POWER STAGEHIGH OUTPUT POWER (UP TO 80W MUSICPOWER)MUTING/STAND-BY FUNCTIONSNO SWITCH ON/OFF NOISENO BOUCHEROT CELLSVERY LOW DISTORTIONVERY LOW NOISESHORT CIRCUIT PROTECTIONTHERMAL SHUTDOWNDESCRIPTIONThe TDA7295 is a monolithic integrated circuit in Multiwatt15 package, intended for use as audio class AB amplifier in Hi-Fi field applications (Home Stereo, self powered loudspeakers, Top-class TV). Thanks to the wide voltage range and to the high out current capability it is able to sup-ply the highest power into both 4Ω and 8Ω loads even in presence of poor supply regulation, with high Supply Voltage Rejection.The built in muting function with turn on delay simplifies the remote operation avoiding switching on-off noises.April 2003®IN-2R2680ΩC222µFC1 470nFIN+R1 22KR62.7ΩC10100nF 3R3 22K-+MUTESTBY4VM VSTBY109IN+MUTEMUTESTBYR4 22KTHERMALSHUTDOWNS/CPROTECTION R5 10KC3 10µF C4 10µF1STBY-GNDC522µF713146158-Vs-PWVsBOOT-STRAPOUT+PWVs+VsC9 100nF C8 1000µF-VsD93AU011+VsC7 100nF C6 1000µFNote: The Boucherot cell R6, C10, normally not necessary for a stable operation it couldbe needed in presence of particular load impedances at V S <±25V.Figure 1: Typical Application and Test CircuitMultiwatt 15ORDERING NUMBER: TDA7295 MULTIPOWER BCD TECHNOLOGY1/13BLOCK DIAGRAMABSOLUTE MAXIMUM RATINGSSymbol ParameterValue Unit V S Supply Voltage±40V I O Output Peak Current6A P tot Power Dissipation T case = 70°C 50W T op Operating Ambient Temperature Range 0 to 70°C T stg , T jStorage and Junction Temperature150°CPIN CONNECTION(Top view)THERMAL DATASymbol Description Value Unit R th j-case Thermal Resistance Junction-case Max 1.5°C/WELECTRICAL CHARACTERISTICS (Refer to the Test Circuit V S = ±30V, R L = 8Ω, G V = 30dB;R g = 50 Ω; T amb = 25°C, f = 1 kHz; unless otherwise specified.Symbol Parameter Test Condition Min.Typ.Max.Unit V S Operating Supply Range±10±40VI q Quiescent Current203065mAI b Input Bias Current500nAV OS Input Offset Voltage+10mVI OS Input Offset Current+100nAP O RMS Continuous Output Power d = 0.5%:V S = ± 30V, R L = 8ΩV S = ± 26V, R L = 6ΩςS = ± 22V, R L = 4Ω454545505050WWWMusic Power (RMS) (*)∆t = 1s d = 10%;R L = 8Ω ; V S = ±34V(***) R L = 4Ω; V S = ±26V8080WWd Total Harmonic Distortion (**)P O = 5W; f = 1kHzP O = 0.1 to 30W; f = 20Hz to 20kHz 0.0050.1%%V S = ±22V, R L = 4Ω:P O = 5W; f = 1kHzP O = 0.1 to 30W; f = 20Hz to 20kHz 0.010.1%%SR Slew Rate710V/µs G V Open Loop Voltage Gain80dB G V Closed Loop Voltage Gain243040dBe N Total Input Noise A = curvef = 20Hz to 20kHz 125µVµVf L, f H Frequency Response (-3dB)P O = 1W20Hz to 20kHzR i Input Resistance 100kΩSVR Supply Voltage Rejection f = 100Hz; V ripple = 0.5Vrms6075dB T S Thermal Shutdown145°C STAND-BY FUNCTION (Ref: -V S or GND)V ST on Stand-by on Threshold 1.5V V ST off Stand-by off Threshold 3.5V ATT st-by Stand-by Attenuation7090dBI q st-by Quiescent Current @ Stand-by13mA MUTE FUNCTION (Ref: -V S or GND)V Mon Mute on Threshold 1.5V V Moff Mute off Threshold 3.5V ATT mute Mute AttenuatIon6080dBNote (*):MUSIC POWER is the maximal power which the amplifier is capable of producing across the rated load resistance (regardless of non linearity) 1 sec after the application of a sinusoidal input signal of frequency 1KHz.Note (**): Tested with optimized Application Board (see fig. 2)Note (***): Limited by the max. allowable out currentFigure 2: P.C.B. and components layout of the circuit of figure 1. (1:1 scale)Note:The Stand-by and Mute functions can be referred either to GND or -VS.On the P.C.B. is possible to set both the configuration through the jumper J1.APPLICATION SUGGESTIONS (see Test and Application Circuits of the Fig. 1)The recommended values of the external components are those shown on the application circuit of Fig-ure 1. Different values can be used; the following table can help the designer.COMPONENTS SUGGESTED VALUE PURPOSE LARGER THANSUGGESTEDSMALLER THANSUGGESTEDR1 (*)22k INPUT RESISTANCE INCREASE INPUTIMPRDANCE DECREASE INPUT IMPEDANCER2680ΩCLOSED LOOP GAINSET TO 30dB (**)DECREASE OF GAIN INCREASE OF GAINR3 (*)22k INCREASE OF GAIN DECREASE OF GAINR422k ST-BY TIMECONSTANT LARGER ST-BYON/OFF TIMESMALLER ST-BYON/OFF TIME;POP NOISER510k MUTE TIMECONSTANT LARGER MUTEON/OFF TIMESMALLER MUTEON/OFF TIMEC10.47µF INPUT DCDECOUPLING HIGHER LOW FREQUENCY CUTOFFC222µF FEEDBACK DCDECOUPLING HIGHER LOW FREQUENCY CUTOFFC310µF MUTE TIMECONSTANT LARGER MUTEON/OFF TIMESMALLER MUTEON/OFF TIMEC410µF ST-BY TIMECONSTANT LARGER ST-BYON/OFF TIMESMALLER ST-BYON/OFF TIME;POP NOISEC522µF BOOTSTRAPPING SIGNALDEGRADATION ATLOW FREQUENCYC6, C81000µF SUPPLY VOLTAGEBYPASSDANGER OF OSCILLATIONC7, C90.1µF SUPPLY VOLTAGEBYPASSDANGER OF OSCILLATION(*) R1 = R3 FOR POP OPTIMIZATION(**) CLOSED LOOP GAIN HAS TO BE ≥ 24dBFigure 3:Output Power vs. Supply Voltage.Figure 5:Output Power vs. Supply VoltageFigure 4:Distortion vs. Output PowerFigure 8: Distortion vs. FrequencyTYPICAL CHARACTERISTICS(Application Circuit of fig 1 unless otherwise specified)Figure 6:Distortion vs. Output PowerFigure 7: Distortion vs. FrequencyFigure 14:Power Dissipation vs. Output PowerFigure 13:Power Dissipation vs. Output PowerFigure 11: Mute Attenuation vs. Vpin10Figure 12: St-by Attenuation vs. Vpin9Figure 10: Supply Voltage Rejection vs. FrequencyTYPICAL CHARACTERISTICS(continued)Figure 9:Quiescent Current vs. Supply VoltageINTRODUCTIONIn consumer electronics, an increasing demand has arisen for very high power monolithic audio amplifiers able to match, with a low cost the per-formance obtained from the best discrete de-signs.The task of realizing this linear integrated circuit in conventional bipolar technology is made ex-tremely difficult by the occurence of 2nd break-down phenomenon. It limits the safe operating area (SOA) of the power devices, and as a con-sequence, the maximum attainable output power, especially in presence of highly reactive loads. Moreover, full exploitation of the SOA translates into a substantial increase in circuit and layout complexity due to the need for sophisticated pro-tection circuits.To overcome these substantial drawbacks, the use of power MOS devices, which are immune from secondary breakdown is highly desirable. The device described has therefore been devel-oped in a mixed bipolar-MOS high voltage tech-nology called BCD 100.1) Output StageThe main design task one is confronted with while developing an integrated circuit as a power op-erational amplifier, independently of the technol-ogy used, is that of realising the output stage. The solution shown as a principle schematic by Fig 15 represents the DMOS unity-gain output buffer of the TDA7295.This large-signal, high-power buffer must be ca-pable of handling extremely high current and volt-age levels while maintaining acceptably low har-monic distortion and good behaviour over fre-quency response; moreover, an accurate control of quiescent current is required.A local linearizing feedback, provided by differen-tial amplifier A, is used to fullfil the above require-ments, allowing a simple and effective quiescent current setting.Proper biasing of the power output transistors alone is however not enough to guarantee the ab-sence of crossover distortion.While a linearization of the DC transfer charac-teristic of the stage is obtained, the dynamic be-haviour of the system must be taken into account.A significant aid in keeping the distortion contrib-uted by the final stage as low as possible is pro-vided by the compensation scheme, which ex-ploits the direct connection of the Miller capacitor at the amplifier’s output to introduce a local AC feedback path enclosing the output stage itself.2) ProtectionsIn designing a power IC, particular attention must be reserved to the circuits devoted to protection of the device from short circuit or overload condi-tions.Due to the absence of the 2nd breakdown phe-nomenon, the SOA of the power DMOS transis-tors is delimited only by a maximum dissipation curve dependent on the duration of the applied stimulus.In order to fully exploit the capabilities of the power transistors, the protection scheme imple-mented in this device combines a conventional SOA protection circuit with a novel local tempera-ture sensing technique which " dynamically" con-trols the maximum dissipation.Figure 15:Principle Schematic of a DMOS unity-gain buffer.In addition to the overload protection described above, the device features a thermal shutdown circuit which initially puts the device into a muting state (@ Tj = 145 o C) and then into stand-by (@Tj = 150 o C).Full protection against electrostatic discharges on every pin is included.3) Other FeaturesThe device is provided with both stand-by and mute functions, independently driven by two CMOS logic compatible input pins.The circuits dedicated to the switching on and off of the amplifier have been carefully optimized to avoid any kind of uncontrolled audible transient at the output.The sequence that we recommend during the ON/OFF transients is shown by Figure 16.The application of figure 17 shows the possibility of using only one command for both st-by and mute functions. On both the pins, the maximum applicable range corresponds to the operating supply voltage.1N414810K30K 20K10µF10µF MUTESTBYD93AU014MUTE/ST-BYFigure 17: Single Signal ST-BY/MUTE ControlCircuitPLAYOFF ST-BYMUTEMUTEST-BY OFFD93AU0135V5V+Vs (V)+35-35V MUTE PIN #10(V)V ST-BYPIN #9(V)-Vs V IN (mV)I P (mA)V OUT (V)Figure 16: Turn ON/OFF Suggested SequenceBRIDGE APPLICATIONAnother application suggestion is the BRIDGE configuration, where two TDA7295 are used, as shown by the schematic diagram of figure 25.In this application, the value of the load must not be lower than 8 Ohm for dissipation and current capability reasons.A suitable field of application includes HI-FI/TV subwoofers realisations.The main advantages offered by this solution are:- High power performances with limited supply voltage level.- Considerably high output power even with high load values (i.e. 16 Ohm).The characteristics shown by figures 20 and 21,measured with loads respectively 8 Ohm and 16Ohm.With Rl= 8 Ohm, Vs = ±22V the maximum output power obtainable is 100W, while with Rl=16 Ohm,Vs = ±30V the maximum Pout is 100W.22K0.56µF2200µF0.22µF+-22µF 22K68022K 314137+VsVi8152146109+-30.56µF22K14214622µF 22K68010922µF158-Vs 2200µF0.22µF22µF 20K 10K 30K1N4148ST-BY/MUTE137D93AU015AFigure 18: Bridge Application CircuitFigure 20: Distortion vs. Output Power Figure 19: Frequency Response of the BridgeApplicationFigure 21: Distortion vs. Output PowerMultiwatt15 VDIM.mm inch MIN.TYP.MAX.MIN.TYP.MAX.A50.197B2.650.104C1.60.063D10.039E0.490.550.0190.022F0.660.750.0260.030G1.02 1.27 1.520.0400.0500.060G117.5317.7818.030.6900.7000.710H119.60.772H220.20.795L21.922.222.50.8620.8740.886L121.722.122.50.8540.8700.886L217.6518.10.6950.713L317.2517.517.750.6790.6890.699L410.310.710.90.4060.4210.429L72.65 2.90.1040.114M4.25 4.55 4.850.1670.1790.191M14.635.08 5.530.1820.2000.218S1.92.60.0750.102S11.92.60.0750.102Dia13.65 3.850.1440.152OUTLINE ANDMECHANICAL DATAInformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronics© 2003 STMicroelectronics – Printed in Italy – All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco -Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.。

TAS5705................................................................................................................................................SLOS549A–JUNE2008–REVISED SEPTEMBER2009 20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRCCheck for Samples:TAS5705FEATURES Sample Rates•Audio Input/Output–Thermal and Short-Circuit Protection –20-W Into an8-ΩLoad From an18-V Supply•Benefits–Wide Power-Supply Range From(8V to–EQ:Speaker Equalization Improves Audio 23V)Performance–Efficient Class-D Operation Eliminates–DRC:Dynamic Range Compression.Need for Heat Sinks Enables Power Limiting,SpeakerProtection,Easy Listening,Night-Mode –Requires Only Two Power-Supply RailsListening–Two Serial Audio Inputs(Four Audio–Autobank Switching:Preload Coefficients Channels)for Different Sample Rates.No Need to –Supports32-kHz–192-kHz Sample RatesWrite Any Coefficients to the Part When (LJ/RJ/I2S)Sample Rate Changes.–Headphone PWM Outputs–Autodetect:Automatically Detects –Subwoofer PWM Outputs Sample-Rate Changes.No Need for •Audio/PWM Processing External Microprocessor Intervention –Independent Channel Volume Controls With24-dB to–100-dB Range DESCRIPTION–Soft Mute(50%Duty Cycle)The TAS5705is a20-W,efficient,digital audio poweramplifier for driving stereo bridge-tied speakers.Two –Programmable Dynamic Range Controlserial data inputs allow processing of up to four –16Adaptable Biquads for Speaker EQdiscrete audio channels and seamless integration to –Seven Biquads for Left and Right most digital audio processors and MPEG decoders.Channels The device accepts a wide range of input data andclock rates.A fully programmable data path allows –Two Biquads for Subwoofer Channelthese channels to be routed to the internal speaker –Adaptive Coefficients for DRC Filtersdrivers or output via the line-level subwoofer or –Programmable Input and Output Mixers headphone PWM outputs.–DC Blocking FiltersThe TAS5705is a slave-only device receiving clocks –Loudness Compensation for Subwoofer from external sources.The TAS5705operates at a384-kHz switching rate for32-,48-,96-,and192-kHz –Automatic Sample Rate Detection anddata and352.8-kHz switching rate for44.1-,88.2-Coefficient Banking for DRC and EQand176.4-kHz data.The8×oversampling combined •General Featureswith the fourth-order noise shaper provides a flat –Serial Control Interface Operational Without noise floor and excellent dynamic range from20Hz MCLK to20kHz.–Factory-Trimmed Internal OscillatorEnables Automatic Detection of IncomingPlease be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Digital is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date.Copyright©2008–2009,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.TAS5705SLOS549A–JUNE2008–REVISED SIMPLIFIED APPLICATION DIAGRAMB0264-012Submit Documentation Feedback Copyright©2008–2009,Texas Instruments IncorporatedProduct Folder Link(s):TAS5705TAS5705 ................................................................................................................................................SLOS549A–JUNE2008–REVISED SEPTEMBER2009 FUNCTIONAL VIEWCopyright©2008–2009,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):TAS5705TAS5705SLOS549A–JUNE2008–REVISED Figure1.Power Stage Functional Block Diagram4Submit Documentation Feedback Copyright©2008–2009,Texas Instruments IncorporatedProduct Folder Link(s):TAS5705BKND_ERR VALIDDVDDD V S SD V S S O S D I N 1S D I N 2L R C L K S C L K MCLK M U TE H P S E L O S C _R E SP D N S D A S C L V R _D I GV R E G _E N S T E S T T E S T 2HPL_PWM HPR_PWM SUB_PWM–SUB_PWM+GNDGND GVDD_CD V D D _B V D D _B V D D _C V D D _C PVDD_D PVDD_D G N D _A BG N D _A B G N D _C D G N D _C D VREG U T _AU T _B U T _B U T _C U T _C OUT_D U T _DS T _B S T _C BST_D P0071-01PAP Package (Top View)TAS5705 ................................................................................................................................................SLOS549A –JUNE 2008–REVISED SEPTEMBER 200964-PIN,HTQFP PACKAGE (TOP VIEW)TERMINAL FUNCTIONSTERMINAL TYPE5-V TERMINATIONDESCRIPTION(1)TOLERANT(2)NAME NO.AVDD 10P 3.3-V analog power supply.Needs close decoupling capacitor.AVSS 11P Analog 3.3-V supply groundBKND_ERR35DIPullupActive-low.A back-end error sequence is generated by applying logic LOW to this terminal.This pin is connected to an external power stage.If no external power stage is used,connect this pin directly to DVDD.BST_A 4P High-side bootstrap supply for half-bridge A BST_B 57P High-side bootstrap supply for half-bridge B BST_C 56P High-side bootstrap supply for half-bridge C BST_D 45PHigh-side bootstrap supply for half-bridge D(1)TYPE:A =analog;D =3.3-V digital;P =power/ground/decoupling;I =input;O =output(2)All pullups are 20-μA weak pullups and all pulldowns are 20-μA weak pulldowns.The pullups and pulldowns are included to assure proper input logic levels if the terminals are left unconnected (pullups →logic 1input;pulldowns →logic 0input).Devices that drive inputs with pullups must be able to sink 50μA while maintaining a logic-0drive level.Devices that drive inputs with pulldowns must be able to source 50μA while maintaining a logic-1drive level.Copyright ©2008–2009,Texas Instruments IncorporatedSubmit Documentation Feedback5Product Folder Link(s):TAS5705TAS5705SLOS549A–JUNE2008–REVISED TERMINAL FUNCTIONS(continued)TERMINAL TYPE5-V TERMINATIONDESCRIPTION(1)TOLERANT(2)NAME NO.DVDD15,33P 3.3-V digital power supplyDVSS20P Digital groundDVSSO26P Oscillator groundFAULT9DO Pullup Overtemperature,overcurrent,and undervoltage fault reporting.Active-low indicates fault.If high,normal operation.GND41,42P Analog ground for power stageGVDD_AB5P Gate drive internal regulated output for AB channelsGVDD_CD44P Gate drive internal regulated output for CD channelsHPL_PWM37DO Headphone left-channel PWM output.HPR_PWM38DO Headphone right-channel PWM output.HPSEL30DI5-V Headphone select,active-high.When a logic high is applied,deviceenters headphone mode and speakers are MUTED(HARD MUTE).When a logic LOW is applied,device is in speaker mode andheadphone outputs become line outputs or are disabled.When in lineout mode,this terminal functionality is disabled(see system controlregister2.LRCLK22DI5-V Input serial audio data left/right clock(sampling rate clock)MCLK34DI5-V MCLK is the clock master input.The input frequency of this clock canrange from4.9MHz to49.2MHz.MUTE21DI5-V Pullup Performs a soft mute of outputs,active-low.A logic low on this pinsets the outputs equal to50%duty cycle.A logic high on this pinallows normal operation.The mute control provides a noiselessvolume ramp to silence.Releasing mute provides a noiseless ramp toprevious volume.OC_ADJ8AO Analog overcurrent programming.Requires22-kΩresistor to ground. OSC_RES19AO Oscillator trim resistor.Connect an18.2-kΩ,1%tolerance resistor toDVSSO.OUT_A1,64O Output,half-bridge AOUT_B60,61O Output,half-bridge BOUT_C52,53O Output,half-bridge COUT_D48,49O Output,half-bridge DPDN17DI5-V Pullup Power down,active-low.PDN powers down all logic,stops all clocks,and stops output switching whenever a logic low is applied.WhenPDN is released,the device powers up all logic,starts all clocks,andperforms a soft start that returns to the previous configurationdetermined by register settings.PGND_AB62,63P Power ground for half-bridges A and BPGND_CD50,51P Power ground for half-bridges C and DPLL_FLTM12AO PLL negative loop filter terminalPLL_FLTP13AI PLL positive loop filter terminalPVDD_A2,3P Power supply input for half-bridge output A(8V–23V)PVDD_B58,59P Power supply input for half-bridge output B(8V–23V)PVDD_C54,55P Power supply input for half-bridge output C(8V–23V)PVDD_D46,47P Power supply input for half-bridge output D(8V–23V)RESET16DI5-V Pullup Reset,active-low.A system reset is generated by applying a logiclow to this terminal.RESET is an asynchronous control signal thatrestores the DAP to its default conditions,sets the VALID outputslow,and places the PWM in the hard-mute state(stops switching).Master volume is immediately set to full attenuation.Upon the releaseof RESET,if PDN is high,the system performs a4–5-ms deviceinitialization and sets the volume at mute.SCL29DI5-V I2C serial control clock input6Submit Documentation Feedback Copyright©2008–2009,Texas Instruments IncorporatedProduct Folder Link(s):TAS5705TAS5705 ................................................................................................................................................SLOS549A–JUNE2008–REVISED SEPTEMBER2009TERMINAL FUNCTIONS(continued)TERMINAL TYPE5-V TERMINATIONDESCRIPTION(1)TOLERANT(2)NAME NO.SCLK23DI5-V Serial audio data clock(shift clock).SCLK is the serial audio portinput data bit clock.SDA28DIO5-V I2C serial control data interface input/outputSDIN125DI5-V Serial audio data1input is one of the serial data input ports.SDIN1supports three discrete(stereo)data formats.SDIN224DI5-V Serial audio data2input is one of the serial data input ports.SDIN2supports three discrete(stereo)data formats.SSTIMER6AI Controls ramp time of OUT_X for pop-free operation.Leave this pinfloating for BD mode.Requires capacitor of2.2nF to GND in ADmode.The capacitor determines the ramp time of PWM outputs from0%to50%.For2.2nF,start/stop time is~10ms.STEST31DI Test pin.Connect directly to GND.SUB_PWM–39DO Subwoofer negative PWM outputSUB_PWM+40DO Subwoofer positive PWM outputTEST17DI Test pin.Connect directly to GND.TEST232DI Test pin.Connect directly to DVDD.VALID36DO Output indicating validity of ALL PWM channels,active-high.This pinis connected to an external power stage.If no external power stage isused,leave this pin floating.VR_ANA14P Internally regulated1.8-V analog supply voltage.This terminal mustnot be used to power external devices.VR_DIG27P Internally regulated1.8V digital supply voltage.This terminal must notbe used to power external devices.VREG43P 3.3Regulator output.Not to be used as s supply or connected to anyother components other than decoupling caps.Add decouplingcapacitors with pins42and41.VREG_EN18DI Pulldown Voltage regulator enable.Connect directly to GND.ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range(unless otherwise noted)(1)VALUE UNIT DVDD,AVDD–0.3to3.6V Supply voltagePVDD_X–0.3to30VOC_ADJ–0.3to4.2VInput voltage 3.3-V digital input–0.5to DVDD+0.5V 5-V tolerant(2)digital input–0.5to DVDD+2.5VOUT_x to PGND_X32(3)VBST_x to PGND_X43(3)VInput clamp current,I IK(V I<0or V I>1.8V)±20mA Output clamp current,I OK(V O<0or V O>1.8V)±20mA Operating free-air temperature0to85°C Operating junction temperature range0to150°C Storage temperature range,T stg–40to125°C (1)Stresses beyond those listed under absolute ratings may cause permanent damage to the device.These are stress ratings only andfunctional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are not implied.Exposure to absolute-maximum conditions for extended periods may affect device reliability.(2)5-V tolerant inputs are SCLK,LRCLK,MCLK,SDIN1,SDIN2,SDA,SCL,and HPSEL.(3)DC voltage+peak ac waveform measured at the pin should be below the allowed limit for all conditions.Copyright©2008–2009,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):TAS5705TAS5705SLOS549A–JUNE2008–REVISED DISSIPATION RATINGSDERATING FACTOR T A≤25°C T A=70°C T A=85°C PACKAGEABOVE T A=25°C POWER RATING POWER RATING POWER RATING10-mm×10-mm QFP40mW/°C5W 3.2W 2.6W RECOMMENDED OPERATING CONDITIONSMIN NOM MAX UNIT Digital/analog supply voltage DVDD,AVDD3 3.3 3.6VHalf-bridge supply voltage PVDD_X823VV IH High-level input voltage 3.3-V TTL,5-V tolerant2 5.5VV IL Low-level input voltage 3.3-V TTL,5-V tolerant0.8VT A Operating ambient temperature range085°CT J Operating junction temperature range0150°CR L(BTL)68Load impedance Output filter:L=15μH,C=0.68μFΩR L(SE) 3.24L O(BTL)10Minimum output inductance underOutput-filter inductanceμHshort-circuit conditionL O(SE)10PWM OPERATION AT RECOMMENDED OPERATING CONDITIONSPARAMETER TEST CONDITIONS MODE VALUE UNIT32–kHz data rate±2%12×sample rate384kHz Output sample rate2×–1×44.1-,88.2-,176.4-kHz data rate±2%8×,4×,and2×sample rates352.8kHz oversampled48-,96-,192-kHz data rate±2%8×,4×,and2×sample rates384kHz PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTSPARAMETER TEST CONDITIONS MIN TYP MAX UNITf MCLKI Frequency,MCLK(1/t cyc2) 4.949.2MHzMCLK duty cycle40%50%60%MCLK minimum high time8nsMCLK minimum low time8nsLRCLK allowable drift before LRCLK reset4MCLKs External PLL filter capacitor C1SMD0603Y5V47nFExternal PLL filter capacitor C2SMD0603Y5V 4.7nFExternal PLL filter resistor R SMD0603,metal film470Ω8Submit Documentation Feedback Copyright©2008–2009,Texas Instruments IncorporatedProduct Folder Link(s):TAS5705TAS5705 ................................................................................................................................................SLOS549A–JUNE2008–REVISED SEPTEMBER2009 ELECTRICAL CHARACTERISTICSDC CharacteristicsT A=25°,PVCC_X=18V,DVDD=AVDD=3.3V,R L=8Ω,BTL mode(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITV OH High-level output voltage 3.3-V TTL and5-V tolerant(1)I OH=–4mA 2.4VV OL Low-level output voltage 3.3-V TTL and5-V tolerant(1)I OL=4mA0.5V3.3-V TTL V I=V IL±2I IL(2)Low-level input currentμA5-V tolerant(1)V I=0V,DVDD=3V±23.3-V TTL V I=V IH±2I IH(2)High-level input currentμA5-V tolerant V I=5.5V,DVDD=3V±20Normal Mode6583Digital supply voltage(DVDD,Power down(PDN=823I DD Digital supply current mAAVDD)low)Reset(RESET=low)2338.5I PVDD Analog supply current No load(all PVDD inputs)3060Power down(PDN=5 6.3I PVDD(PDN)Power-down current No load(all PVDD inputs)mAlow)I PVDD(RESET)Reset current No load(all PVDD inputs)Reset(RESET=low)5 6.3Drain-to-source resistance,180T J=25°C,includes metallization resistanceLSr DS(on)mΩDrain-to-source resistance,T J=25°C,includes metallization resistance180HSI/O ProtectionV uvp Undervoltage protection limit PVDD falling7.2VV uvp,hyst Undervoltage protection limit PVDD rising7.6V OTE(3)Overtemperature error150°C Extra temperature dropOTE HYST(3)required to recover from30°C errorOLPC Overload protection counter f PWM=384kHz0.63msResistor—programmable,max.current, 4.5I OC Overcurrent limit protection AR OCP=22kΩI OCT Overcurrent response time150nsResistor tolerance=5%for typical value;the minimumOC programming resistorR OCP resistance should not be less than20kΩ.This value is2022kΩrangenot adjustable.It must be fixed at22kΩ.Internal pulldown resistor at Connected when RESET is active to provide bootstrapR PD3kΩthe output of each half-bridge capacitor charge.(1)5-V tolerant inputs are PDN,RESET,MUTE,SCLK,LRCLK,MCLK,SDIN1,SDIN2,SDA,SCL,and HPSEL.(2)I IL or I IH for pins with internal pullup can go up to50μA.(3)Specified by designCopyright©2008–2009,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Link(s):TAS5705TAS5705SLOS549A–JUNE2008–REVISED AC Characteristics(BTL)PVDD_X=18V,BTL mode,R L=8Ω,R OC=22KΩ,C BST=33nF,audio frequency=1kHz,AES17filter,f PWM=384kHz,T A=25°C(unless otherwise noted).All performance is in accordance with recommended operating conditions,unless otherwise specified.PARAMETER TEST CONDITIONS MIN TYP MAX UNITPVDD=18V,10%THD,1-kHz input signal20.0PVDD=18V,7%THD,1-kHz input signal18.6PVDD=12V,10%THD,1-kHz input9signalP O Power output per channel WPVDD=12V,7%THD,1-kHz input signal8.3PVDD=8V,10%THD,1-kHz input signal 3.9PVDD=8V,7%THD,1-kHz input signal 3.7PVDD=18V;P O=10W(half-power)0.12%THD+N Total harmonic distortion+noise PVDD=12V;P O=4.5W(half-power)0.1%PVDD=8V;P O=2W(half-power)0.24%V n Output integrated noise A-weighted50μV Crosstalk P O=1W,f=1kHz–73dBA-weighted,f=1kHz,maximum power atSNR Signal-to-noise ratio(1)105dBTHD<0.1%P D Power dissipation due to idle losses(I PVDD_X)P O=0W,4channels switching(2)0.6W(1)SNR is calculated relative to0-dBFS input level.(2)Actual system idle losses are affected by core losses of output inductors.AC Characteristics(Single-Ended Output)PVDD_X=18V,SE mode,R L=4Ω,R OC=22kΩ,C BST=33-nF,audio frequency=1kHz,AES17filter,f PWM=384kHz, ambient temperature=25°C(unless otherwise noted).All performance is in accordance with recommended operating conditions,unless otherwise specified.PARAMETER TEST CONDITIONS MIN TYP MAX UNITPVDD=18V,10%THD10PVDD=18V,7%THD9P O Power output per channel WPVDD=12V,10%THD 4.5PVDD=12V,7%THD4PVDD=18V,Po=5W(half-power)0.2THD+Total harmonic distortion+noise%N PVDD=12V,Po=2.25W(half-power)0.2V n Output integrated noise A-weighted50μV SNR Signal-to-noise ratio(1)A-weighted105dB DNR Dynamic range A-weighted,input level=–60dBFS using TAS5086modulator105dBPower dissipation due to idleP D P O=0W,4channels switching(2)0.6W losses(IPVDD_X)(1)SNR is calculated relative to0-dBFS input level.(2)Actual system idle losses are affected by core losses of output inductors.10Submit Documentation Feedback Copyright©2008–2009,Texas Instruments IncorporatedProduct Folder Link(s):TAS5705SERIAL AUDIO PORTS SLAVE MODEover recommended operating conditions(unless otherwise noted)TESTPARAMETER MIN TYP MAX UNITCONDITIONSf SCLKIN Frequency,SCLK32×f S,48×f S,64×f S C L=30pF 1.02412.288MHz t su1Setup time,LRCLK to SCLK rising edge10ns t h1Hold time,LRCLK from SCLK rising edge10ns t su2Setup time,SDIN to SCLK rising edge10ns t h2Hold time,SDIN from SCLK rising edge10ns LRCLK frequency3248192kHz SCLK duty cycle40%50%60%LRCLK duty cycle40%50%60%SCLK SCLK rising edges between LRCLK rising edges3264edgest(edge)SCLK LRCLK clock edge with respect to the falling edge of SCLK–1/41/4periodFigure2.Slave Mode Serial Data Interface TimingSCLSDAT0027-01 SCLSDAStart ConditionStopConditionT0028-01I2C SERIAL CONTROL PORT OPERATIONTiming characteristics for I2C Interface signals over recommended operating conditions(unless otherwise noted)PARAMETER TEST CONDITIONS MIN MAX UNIT f SCL Frequency,SCL No wait states400kHz t w(H)Pulse duration,SCL high0.6μs t w(L)Pulse duration,SCL low 1.3μs t r Rise time,SCL and SDA300ns t f Fall time,SCL and SDA300ns t su1Setup time,SDA to SCL100ns t h1Hold time,SCL to SDA0ns t(buf)Bus free time between stop and start condition 1.3μs t su2Setup time,SCL to start condition0.6μs t h2Hold time,start condition to SCL0.6μs t su3Setup time,SCL to stop condition0.6μs C L Load capacitance for each bus line400pFFigure3.SCL and SDA TimingFigure4.Start and Stop Conditions TimingRESETVALIDtStart systemSystem initialization.Enable via I C.2T0029-05PDNVALIDt T0030-04RESET TIMING (RESET)Control signal parameters over recommended operating conditions (unless otherwise noted)PARAMETERMIN TYP MAX UNIT t d(VALID_LOW)Time to assert VALID (reset to power stage)low 100ns t w(RESET)Pulse duration,RESET active 100200ns t d(I2C_ready)Time to enable I 2C3.5ms t d(run)Device start-up time (after start-up command via I 2C)10msNOTE:On power up,it is recommended that the TAS5705be held LOW for at least 100μs after DVDD has reached3.0V.RESET assertion is ignored if applied while part is powered downFigure 5.Reset TimingPOWER-DOWN (PDN)TIMINGControl signal parameters over recommended operating conditions (unless otherwise noted)PARAMETERMINTYP MAXUNIT t d(VALID_LOW)Time to assert VALID (reset to power stage)low 725μs t d(STARTUP)Device startup time650μs t wMinimum pulse duration required1μsNOTE:PDNZ assertion is ignored if applied when part is in RESETFigure 6.Power-Down TimingDVDD PVDDT0317-01DVDDRESETPDNT0318-01Figure7.Power Up and Power Down of Power SuppliesNOTE:t power_down=time to wait before powering down the supplies after assertion=725μs+power-stage stop time defined by register0x1AFigure8.Terminal Control and DVDDBKND_ERRVALIDVOLUMEMUTET0032-03BACK-END ERROR (BKND_ERR)Control signal parameters over recommended operating conditions (unless otherwise noted)PARAMETERMIN TYP MAX UNIT t w(ER)Minimum pulse duration,BKND_ERR active (active-low)350nst p(valid_high)Programmable.Time to stay in the VALID (reset to the power stage)low state.After t p(valid_high),the TAS5705attempts to bring the system out of the VALID low state if 300ms BKND_ERR is high.t p(valid_low)Time TAS5705takes to bring VALID (reset to the power stage)low after BKND_ERR ns400assertion.Figure 9.Error Recovery TimingMUTE TIMING Control signal parameters over recommended operating conditions (unless otherwise noted)PARAMETERMINTYP MAXUNIT Volume ramp time (=number of steps ×step size).Number of steps is defined by volume t d(VOL)configuration register 0x0E (see Volume Configuration Register ).Step size =4LRCLKs if 1024stepsf S ≤48kHz;else 8LRCLKs if f S ≤96kHz ;else 16LRCLKsFigure 10.Mute TimingHP VolumeHPSELVALIDSpkr VolumeSpkr VolumeHPSELVALIDHP VolumeHEADPHONE SELECT (HPSEL)PARAMETERMIN MAX UNIT t w(MUTE)Pulse duration,HPSEL active 350ns t d(VOL)Soft volume update timeSee(1)ms t (SW)Switch-over time (controlled by start/stop period register,0x1A)0.2ms(1)Defined by the volume slew rate setting (see the volume configuration register ,0x0E).Figure 11and Figure 12show functionality when bit 4in the HP configuration register is set to DISABLE (not in line-out mode).See register 0x05for details.If bit 4is not set,than the HP PWM outputs are not disabled when HPSEL is brought low.Figure 11.HPSEL Timing for Headphone InsertionFigure 12.HPSEL Timing for Headphone Extractionf − Frequency − Hz 201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %20kG0030.0010.01100.11f − Frequency − Hz 201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %20kG0020.0010.01100.11f − Frequency − Hz201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %20kG0010.0010.01100.11P O − Output Power − W0.010.1110T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %40G006TYPICAL CHARACTERISTICS,BTL CONFIGURATIONTOTAL HARMONIC DISTORTION +NOISE (BTL)TOTAL HARMONIC DISTORTION +NOISE (BTL)vsvsFREQUENCYFREQUENCYFigure 13.Figure 14.TOTAL HARMONIC DISTORTION +NOISE (BTL)TOTAL HARMONIC DISTORTION +NOISE (BTL)vsvsFREQUENCY OUTPUT POWERFigure 15.Figure 16.P O − Output Power − W 0.010.111040G005P O − Output Power − W 0.010.111040G004P O − Total Output Power − W0.00.51.01.52.02.53.0510152025303540G008P O − Output Power (Per Channel) − W010203040506070809010002468101214161820E f f i c i e n c y − %G007TOTAL HARMONIC DISTORTION +NOISE (BTL)TOTAL HARMONIC DISTORTION +NOISE (BTL)vsvsOUTPUT POWEROUTPUT POWERFigure 17.Figure 18.EFFICIENCYSUPPLY CURRENTvsvsOUTPUT POWERTOTAL OUTPUT POWERFigure 19.Figure 20.PVDD − Supply Voltage − V051015202568101214161820P O − O u t p u t P o w e r − WG009−100−95−90−85−80−75−70−65−60 f − Frequency − Hz C r o s s t a l k − d BG012201001k10k 20kOUTPUT POWERCROSSTALKvsvsSUPPLY VOLTAGEFREQUENCYFigure 21.Figure 22.f − Frequency − Hz 201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %0.0011020k0.1G01210.01f − Frequency − Hz 201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %0.0011020k0.1G01210.01V CC − Supply Voltage − V369121518510152025P O − O u t p u t P o w e r − WG014P O − Output Power − W 0.010.111040G013TYPICAL CHARACTERISTICS,SE CONFIGURATIONTOTAL HARMONIC DISTORTION +NOISETOTAL HARMONIC DISTORTION +NOISEvsvsFREQUENCYFREQUENCYFigure 23.Figure 24.TOTAL HARMONIC DISTORTION +NOISEOUTPUT POWERvsvsOUTPUT POWER SUPPLY VOLTAGEFigure 25.Figure 26.TAS5705 ................................................................................................................................................SLOS549A–JUNE2008–REVISED SEPTEMBER2009DETAILED DESCRIPTIONPOWER SUPPLYTo facilitate system design,the TAS5705needs only a3.3-V digital supply in addition to the(typical)18-V power-stage supply.An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally,all circuitry requiring a floating voltage supply,e.g.,the high-side gate drive,is accommodated by built-in bootstrap circuitry requiring only a few external capacitors.In order to provide good electrical and acoustical characteristics,the PWM signal path for the output stage is designed as identical,independent half-bridges.For this reason,each half-bridge has separate bootstrap pins (BST_X),and power-stage supply pins(PVDD_X).The gate drive voltages(GVDD_AB and GVDD_CD)are derived from the PVDD voltage.Separate,internal voltage regulators reduce and regulate the PVDD voltage to a voltage appropriate for efficient gave drive operation.Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible.In general,inductance between the power-supply pins and decoupling capacitors must be avoided.For a properly functioning bootstrap circuit,a small ceramic capacitor must be connected from each bootstrap pin (BST_X)to the power-stage output pin(OUT_X).When the power-stage output is low,the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin(GVDD_X)and the bootstrap pin.When the power-stage output is high,the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver.In an application with PWM switching frequencies in the range from352kHz to384kHz,it is recommended to use33-nF ceramic capacitors, size0603or0805,for the bootstrap supply.These33-nF capacitors ensure sufficient energy storage,even during minimal PWM duty cycles,to keep the high-side power stage FET(LDMOS)fully turned on during the remaining part of the PWM cycle.Special attention should be paid to the power-stage power supply;this includes component selection,PCB placement,and routing.As indicated,each half-bridge has independent power-stage supply pins(PVDD_X).For optimal electrical performance,EMI compliance,and system reliability,it is important that each PVDD_X pin is decoupled with a100-nF ceramic capacitor placed as close as possible to each supply pin.The TAS5705is fully protected against erroneous power-stage turnon due to parasitic gate charging.SYSTEM POWER-UP/POWER-DOWN SEQUENCEPowering UpThe outputs of the H-bridges remain in a low-impedance state until the internal gate-drive supply voltage (GVDD_XY)and external VREG voltages are above the undervoltage protection(UVP)voltage threshold(see the DC Characteristics section of this data sheet).It is recommended to hold PVDD_X low until DVDD(3.3V)is powered up while powering up the device.This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.The output impedance is approximately3kΩ. This means that the TAS5705should be held in reset for at least100μs to ensure that the bootstrap capacitors are charged.This also assumes that the recommended0.033-μF bootstrap capacitors are used.Changes to bootstrap capacitor values change the bootstrap capacitor charge time.See Figure7and Figure8.Powering DownApply PDN(assert low).Wait for the power stage to shut down.Power down PVDD.Then power down DVDD. Then de-assert See Figure8for recommended timing.ERROR REPORTINGThe pin is an active-low,open-drain output.Its function is for protection-mode signaling to a system-control device.Any fault resulting in device shutdown is signaled by the pin going low(see Table1).。

Data SheetAP2805General DescriptionThe AP2805 is an integrated high-side power switchthat consists of N-Channel MOSFET, charge pump, over current & temperature and other related protection circuits. The switch’s low RDS (ON), 60m Ω, design easily to meet USB voltage drop requirements. It includes soft-start to limit inrush current, over-current protection, load short protection with fold-back, and thermal shutdown to avoid switch failure during hot plug-in. Under voltage lockout (UVLO) function is used to ensure the device remain off unless there is a valid input voltage present. A Flag output is available to indicate fault conditions to the local USB controller.The AP2805 is available in standard packages of SOIC-8 and MSOP-8.Features•Low MOSFET on Resistance:60m Ω@V IN =5.0V•Compliant to USB Specifications•Operating Voltage Range: 2.7V to 5.5V •Low Supply Current: 60µA (Typ.)•Low Shutdown Current: 1.0µA (Max)•Guarantee 0.5A Continuous Load•Current Limit: 0.7A (Min), 1.4A (Max)•Under-voltage Lockout•Logic Level Enable Pin: Available in Active-high or Active-low Version •Over-current Protection•Over Temperature Protection•Load Short Protection with Fold-back •No Reverse Current When Power Off •Deglitched Flag Output with Open Drain •With Output Shutdown Pull-low Resistor for A/C Versions•UL Approved (File No. E339337)•Nemko CB Scheme IEC60950-1, Ref. Certif No. NO67288Applications•USB Power Management •USB Bus/Self Powered Hubs •Hot-plug Power Supplies •Battery-charger Circuits•Notebooks, Motherboard PCsFigure 1. Package Types of AP2805SOIC-8 MSOP-8N O T R E C O M M E N D E D F O R N E W D E S I G NNOT RECOMMENDED FOR NEW DESIGN - USE AP2141D/AP2151DAP2805Pin ConfigurationM/MM Package （SOIC-8/MSOP-8）Figure 2. Pin Configuration of AP2805 (Top View)Pin DescriptionsPin NameFunctionGND VINChip enable control input, active low or highFault flag pin, output with open drain, need a pull-up resistor in application, active low to indicate OCP or OTP VOUTN E C O M M E N D E D F O R N D E S I G NAP2805Functional Block DiagramFigure 3. Functional Block Diagram of AP2805N O T R E C O M M E N D E D F O R N E W D E S I G NAP2805Ordering InformationAP2805-Product Package ConditionTemperature Range Part NumberMarking IDPacking TypeGreenGreenAP2805ASOIC-8Active High with Auto Discharge -40 to 85°CAP2805AM-G1 2805AM-G1 TubeAP2805AMTR-G12805AM-G1Tape & ReelMSOP-8 AP2805AMM-G1 2805AMM-G1 Tube AP2805AMMTR-G12805AMM-G1Tape & ReelAP2805BSOIC-8Active Highwithout Auto Discharge-40 to 85°CAP2805BM-G12805BM-G1TubeAP2805BMTR-G1 2805BM-G1 Tape & ReelMSOP-8AP2805BMM-G1 2805BMM-G1 TubeAP2805BMMTR-G12805BMM-G1Tape & ReelAP2805CSOIC-8Active Lowwith Auto Discharge-40 to 85°CAP2805CM-G12805CM-G1TubeAP2805CMTR-G1 2805CM-G1 Tape & ReelMSOP-8AP2805CMM-G1 2805CMM-G1 TubeAP2805CMMTR-G12805CMM-G1Tape & ReelAP2805DSOIC-8Active Lowwithout Auto Discharge-40 to 85°CAP2805DM-G1 2805DM-G1 TubeAP2805DMTR-G12805DM-G1Tape & ReelMSOP-8AP2805DMM-G1 2805DMM-G1 TubeAP2805DMMTR-G12805DMM-G1Tape & ReelBCD Semiconductor's Pb-free products, as designated with "G1" suffix in the part number, are RoHS compliantand Green.N O T R E C O M M E N F O R N E W D E S I G NAP2805Absolute Maximum Ratings (Note 1)ParameterSymbolValueUnitPower Supply VoltageV IN 6.0V Operating Junction Temperature RangeT J 150ºC Storage Temperature Range T STG-65 to 150ºC Lead Temperature (Soldering,10 sec) T LEAD 260ºCThermal Resistance (Junction to Ambient)θJASOIC-8135oC /W MSOP-8150ESD (Machine Model)200V ESD (Human Body Model)2000VNote 1: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to “Absolute Maximum Ratings” for extended periods may affect device reliability.Recommended Operating ConditionsParameterSymbol MinMax UnitSupply VoltageV IN 2.7 5.5VOperating Ambient Temperature RangeT A-4085 °CNO T R E C O M M E N D E D F O R N E W D E S I G NAP2805Electrical Characteristics(V IN =5.0V , C IN =2.2µF, C OUT =1.0µF, Typical T A =25°C, unless otherwise specified)ParameterSymbol Conditions Min Typ Max UnitInput V oltage Range V IN 2.7 5.5 V Switch On Resistance R DS(ON)V IN =5.0V , I OUT =0.5A60 80m ΩCurrent LimitI LIMIT V OUT = 4.0V0.7 1.0 1.4ASupply CurrentI SUPPL YV IN = 5.0V , No Load60 80 µAFold-back Short CurrentI SHORT V OUT =0V0.7 AShutdown Supply CurrentI SHUTDOWN Chip Disable, Shutdown Mode0.11µAEnable High Input Threshold V ENH 1.6 5.5 V Enable Low Input Threshold V ENL 0 1.0 VEnable Pin Input CurrentI ENForce 0V to 5.0V at EN Pin -1.0 1.0µA Under V oltage LockoutThreshold V oltage V UVLOV IN Increasing from 0V2.22.52.7V Under V oltage Hysteresis V UVLOHY0.2VReverse CurrentI REVERSE Chip Disable, V OUT >V IN0.1 1.0 µAOutput Pull Low Resistanceafter Shutdown R DISCHARGE AP2805A, AP2805C only100 200 ΩOutput Turn-on Time t ON From Enable Active to 90% ofOutput500 µsFlag Delay Timet DFLGFrom Fault Condition to Flag Active5 10 15 msFlag Low V oltageV FLG I SINK = 5.0mA35 70 mVFlag Leakage Current I LEAKAGE FLAG Disable, Force 5.0V1.0µAThermalShutdownTemperatureT OTSD150 o CThermal Shutdown HysteresisT HYOTSD30oCN O T R E C O M M E N D E D F O R N E W D E S I G NAP2805Typical Performance CharacteristicsFigure 4. Supply Current vs. Ambient TemperatureFigure 5. Supply Current vs. Supply VoltageFigure 6. Current Limit vs. Supply VoltageFigure 7. Current Limit vs. Ambient Temperature0102030405060708090100S u p p l y C u r r e n t (μA )Ambient Temperature (oC)1.01.52.0 2.53.0 3.54.0 4.55.0 5.5-100102030405060708090100S u p p l y C u r r e n t (μA )Supply Voltage (V)0.50.60.70.80.91.01.11.21.31.41.5C u r r e n t L i m i t (A )Ambient Temperature (oC)0.50.60.70.80.91.01.11.21.31.41.5C u r r e n t L i m i t (A )Supply Voltage (V)N M M F D E S IAP2805Typical Performance Characteristics (Continued)Figure 8. Output Short Current vs.Figure 9. Output Short Current vs.Input Voltage Ambient TemperatureFigure 10. Shutdown Current vs. Ambient Temperature Figure 11. Reverse Current vs. Ambient Temperature3.0 3.54.0 4.55.0 5.50.400.450.500.550.600.650.700.750.80O u t p u t S h o r t C u r r e n t (A )Input Voltage (V)-40-20020406080O u t p u t S h o r t C u r r e n t (A )Ambient Temperature (oC)-40-20020406080-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0S h u t d o w n C u r r e n t (μA )Ambient Temperature (oC)-40-20020406080-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0R e v e r s e C u r r e n t (μA )Ambient Temperature (oC)O M M F D E S IAP2805Typical Performance Characteristics (Continued)Figure 12. Switch On Resistance vs.Figure 13. Switch On Resistance vs.Ambient Temperature Supply VoltageFigure 14. Under Voltage Lockout Threshold VoltageFigure 15. Flag Delay Time During Over Currentvs. Ambient Temperature vs. Ambient Temperature-40.0-20.00.020.040.060.080.00102030405060708090100S w i t c h O n R e s i s t a n c e (m Ω)Ambient Temperature (OC)3.0 3.54.0 4.55.0 5.530405060708090100S w i t c h O n R e s i s t an c e (m Ω)Supply Voltage (V)-40.0-20.00.020.040.060.080.02.202.252.302.352.402.452.502.552.602.652.70Ambient Temperature (OC)U n d e r V o l t a g e L o c k o u t T h r e s h o l d V o l t a g e (V )-40.0-20.00.020.040.060.080.056789101112131415F l a g D e l a y T i m e D u r i n g O v e r C u r r e n t (m S )Ambient Temperature (O C)C O M MDE S IAP2805Typical Performance Characteristics (Continued)Figure 16. Flag Delay Time During Over CurrentFigure 17. Enable Threshold Voltagevs. Supply Voltage vs. Ambient TemperatureTime(500µs/div)Figure 18. Enable Threshold VoltageFigure 19. Output Turn ON and Rise Timevs. Supply Voltage (C IN =1.0μF,C OUT =1.0μF,No Load)V ENV OUT 3.0 3.5 4.0 4.5 5.0 5.568101214Supply Voltage (V)F l a g D e l a y T i m e D u r i n g O v e r C u r r e n t (m S )-40.0-20.00.020.040.060.080.01.01.11.21.31.41.51.6Ambient Temperature (O C)E n a b l e T h r e s h o l d V o l t a g e (V )3.0 3.54.0 4.55.0 5.50.70.80.91.01.11.21.31.41.51.61.7Supply Voltage (V)E n a b l e T h r e s h o l d V o l t a g e (V )C O M MDE S IAP2805Typical Performance Characteristics (Continued)Time(500µs/div)Time(500µs/div)Figure 20. Output Turn ON and Rise TimeFigure 21. Output Turn ON and Rise Time(C IN =1.0μF,C OUT =1.0μF,R L =6.6Ω)(C IN =1.0μF,C OUT =47μF,No Load)Time(5ms/div) Time(5ms/div)Figure 22. Output Turn OFF and Falling TimeFigure 23. Output Turn OFF and Falling Time (V IN =5V,C IN =1.0μF,No Load)(V IN =5V,C IN =1.0μF,C OUT=470μF,R L =6.6Ω)V EN (5V/div)I INRUSH (500mA/ div) V OUT (1V/div)V EN (5V/div)I INRUSH(1A/div) V OUT (1V/div)V EN (5V/div) V OUT (1V/div) I OUT (1A/div)V EN (5V/div)V OUT (1V/div)F=220μFOUT =470N O T R E C O M M E N D E D F O R N E W D E S I G NAP2805Typical Performance Characteristics (Continued)Time(100ms/div)Time(5ms/div)Figure 24. Output Short to GND CurrentFigure 25. FLAG Response During Over Current(V IN =5V,C IN =1.0μF)(V IN =5V,C IN =1.0μF,C OUT =470μF)Time(5ms/div)Figure 26. FLAG Response During Over Temperature(V IN =5V,C IN =1.0μF,COUT =220μF,R L =6.6Ω)V EN (5V/div) V OUT (1V/div) I OUT (1A/div)V FLAG (1V/div)V OUT (1V/div) I OUT (1A/div)V FLAG (1V/div)V OUT (1V/div) I OUT (1A/div)N O T R E C O M M E N D E D F O R N E W D E S I G NAP2805TypicalApplicationNote 2: 2.2µF input capacitor is enough in most application cases.If the VOUT is short to ground frequently during usage, large size input capacitor is necessary, recommend 22µF.Figure 27. Typical Application of AP2805N O T R E C O M M E N D E D F O R N E W D E S I G NAP2805 Mechanical DimensionsSOIC-8Unit: mm(inch)Note: Eject hole, oriented hole and mold mark is optional.AP2805 Mechanical Dimensions (Continued)MSOP-8Unit: mm(inch).(.).2(.8)NOTRECOMDED FORNEWDESIGNIMPORTANT NOTICEBCD Semiconductor Manufacturing Limited reserves the right to make changes without further notice to any products or specifi-cations herein. BCD Semiconductor Manufacturing Limited does not assume any responsibility for use of any its products for any particular purpose, nor does BCD Semiconductor Manufacturing Limited assume any liability arising out of the application or use of any its products or circuits. BCD Semiconductor Manufacturing Limited does not convey any license under its patent rights or other rights nor the rights of others.- Wafer FabShanghai SIM-BCD Semiconductor Manufacturing Co., Ltd.800 Yi Shan Road, Shanghai 200233, China Tel: +86-21-6485 1491, Fax: +86-21-5450 0008MAIN SITEREGIONAL SALES OFFICEShenzhen OfficeShanghai SIM-BCD Semiconductor Manufacturing Co., Ltd., Shenzhen Office Taiwan OfficeBCD Semiconductor (Taiwan) Company Limited USA OfficeBCD Semiconductor Corp.- HeadquartersBCD Semiconductor Manufacturing LimitedNo. 1600, Zi Xing Road, Shanghai ZiZhu Science-based Industrial Park, 200241, China Tel: +86-21-24162266, Fax: +86-21-24162277N O T R E C O M M E N D E D F O R N E W D E S I G N。

AN_SY8253Rev.0.9Silergy Corp.Confidential-prepared for Internal Use Only 1General DescriptionApplication Note:SY8253High Efficiency,500kHz,3A,23V InputSynchronous Step Down RegulatorFeaturesThe SY8253is a high efficiency 500kHz synchronous step-down DC-DC converter capable of delivering 3A current.The SY8253operates over a wide input voltage range from 4.5V to 23V and integrates main switch and synchronous switch with very low R DS(ON)to minimize the conduction loss.Low output voltage ripple and small external inductor and capacitor sizes are achieved with 500kHz switching frequency.It adopts the instant PWM architecture to achieve fast transient responses for high step down applicationsOrdering Information∙low R DS(ON)for internal switches (top/bottom):105mΩ/50mΩ∙ 4.5-23V input voltage range ∙3A output current capability ∙500kHz switching frequency∙Instant PWM architecture to achieve fast transient responses.∙Cycle-by-cycle peak current limitation∙Internal softstart limits the inrush current∙Hic-cup mode output short circuit protection ∙±1.5%0.6V reference∙Power good indicator (SY8253AIC only)∙TSOT23-8/TSOT23-6packageSY8253□(□□)□Temperature Code Package CodeOptional Spec Code Applications∙Set Top Box ∙Portable TV∙Access Point Router ∙DSL Modem ∙LCD TVTypical ApplicationsFigure 1.Schematic Diagram (SY8253AIC)Ordering Number Package type Note SY8253AIC TSOT23-8--SY8253ADCTSOT23-6--SY8253AN_SY8253Rev.0.9Silergy Corp.Confidential-prepared for Internal Use Only2 Figure2.Schematic Diagram(SY8253ADC)SY8253AN_SY8253Rev.0.9SilergyCorp.Confidential-preparedfor InternalUseOnly 3Pinout (top view)BS LX GND IN FBEN(TSOT23-8)(TSOT23-6)Part Number Package type Top Mark ①SY8253AIC TSOT23-8XU xyz SY8253ADC TSOT23-6XT xyzNote ①：x=year code,y=week code,z=lot number code.Pin Name TSOT23-8TSOT23-6Pin DescriptionBS 11Boot-Strap Pin.Supply high side gate driver.Decouple this pin to LX pin with 0.1uF ceramic cap.GND 22Ground pinFB 33Output Feedback Pin.Connect this pin to the center point of the output resistor divider (as shown in Figure 1)to program the output voltage:Vout=0.6*(1+R1/R2)SS 4/Softstart programming pin.Connect a capacitor from this pin to ground to program the softstart time.Tss=Css*0.6V/4uA.Leave thispin open for default 1ms soft-start.PG 5/Power good Indicator.Open drain output.EN 64Enable control.Pull high to turn on.Do not float.IN 75Input pin.Decouple this pin to GND pin with at least 1uF ceramic cap LX86Inductor pin.Connect this pin to the switching node of inductorAbsolute Maximum Ratings (Note 1)Supply Input Voltage------------------------------------------------------------------------------------------------------------------V BS-LX,SS-------------------------------------------------------------------------------------------------------------------------------V All other pins----------------------------------------------------------------------------------------------------------------VIN +0.3V Power Dissipation,PD @TA =25°C,TSOT23-8/TSOT23-6-----------------------------------------------------------1.5W Package Thermal Resistance (Note 2)θJA------------------------------------------------------------------------------------------------------------------------66°C /W θJC------------------------------------------------------------------------------------------------------------------------15°C /W Junction Temperature Range---------------------------------------------------------------------------------------------------150°C Lead Temperature (Soldering,10sec.)--------------------------------------------------------------------------------------260°C Storage Temperature Range-----------------------------------------------------------------------------------------65°C to 150°CRecommended Operating Conditions (Note 3)Supply Input Voltage---------------------------------------------------------------------------------------------------4.5V to 23V Junction Temperature Range-----------------------------------------------------------------------------------------40°C to 125°C Ambient Temperature Range------------------------------------------------------------------------------------------40°C to 85°CSY8253AN_SY8253Rev.0.9Silergy Corp.Confidential-prepared for Internal Use Only 4Electrical Characteristics(V IN =12V,V OUT =3.3V,L =4.7uH,C OUT =47uF,T A =25°C,I OUT =1A unless otherwise specified)ParameterSymbol Test Conditions Min Typ Max Unit Input Voltage Range V IN 4.523V Quiescent Current I QI OUT =0,V FB =V REF *105%100µA Shutdown Current I SHDN EN=0510µA Feedback Reference VoltageV REF 0.5910.60.609V FB Input Current I FBV FB =3.3V-5050nA Top FET RONR DS(ON)1105mΩTop FET Peak Current LimitI LIM,TOP 5.16 6.9A Bottom FET RON R DS(ON)250mΩBottom FET Valley Current LimitI LIM,BOT 3.0 3.74.5A EN Rising Threshold V ENH 1.5V EN Falling Threshold V ENL 0.4V Power Good ThresholdV PGV FB falling,PG from high to low 90%V REF V FB rising,PG from low to high 95%V REF V FB rising,PG from high to low 115%V REF V FB falling,PG from low to high 110%V REF Power Good Delay Time T PG_F PG falling edge 10µs T PG_R PG rising edge60µs Output OVP Response TimeT OVP 10µs Output OVP Off Time t OFF,OVP 1000µs Soft-start Charging CurrentI SS 4µA Short Circuit Protection Wait Timet WAIT,SCP 1.9ms Short Circuit Protection Off Timet OFF,SCP 15msInput UVLO Threshold V UVLO 4.5V Input UVLO Hysteresis V HYS 0.3V Min ON Time 80ns Min OFF Time 160ns Thermal Shutdown TemperatureT SD 150℃Thermal Shutdown HysteresisT HYS15℃Note 1:Stresses beyond the “Absolute Maximum Ratings”may cause permanent damage to the device.These are stress ratings only.Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification is not implied.Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Note 2:θJA is measured in the natural convection at T A =25°C on a two-layer Silergy Evaluation Board.Note 3:The device is not guaranteed to function outside its operating conditions.SY8253AN_SY8253Rev.0.9SilergyCorp.Confidential-prepared forInternalUse Only5Block Diagram(SY8253AIC)INBSENFB(SY8253ADC)LXGNDCurrent Sense1.5V0.6Vrent SenseInput UVLO 4.5VInternal PowerThermal ProtectionInternal SST PWM Control &Protect LogicCurSY8253AN_SY8253Rev.0.9SilergyCorp.Confidential-prepared forInternalUseOnly6VIN =7V,VOUT=5VV IN=12V,VOUT =5V V IN =19V,V OUT =5V V IN =23V,V OUT =5VV IN =5V,V OUT =1.2V V IN =12V,V OUT =1.2V V IN =19V,V OUT =1.2V V IN =23V,V OUT =1.2VTypical Performance CharacteristicsEfficiency vs.Load Current1009080706050403020100110100100010000Load Current (mA)Efficiency vs.Load CurrentEfficiency vs.LoadCurrentV IN =5V,V OUT =3.3V V IN =12V,V OUT =3.3V V IN =19V,V OUT =3.3V V IN =23V,V OUT =3.3V110100100010000Load Current (mA)1009080706050403020100110100100010000Load Current (mA)SY8253 AN_SY8253Rev.0.9Silergy Corp.Confidential-prepared for Internal Use Only7 Short Circuit Protection(V IN=12V,V OUT=3.3V,0A to Short)Short Circuit Protection(V IN=12V,V OUT=3.3V,3A to Short)V OUT2V/divI L2A/divV OUT2V/divI L2A/divTime(10ms/div)Time(10ms/div)SY8253AN_SY8253Rev.0.9Silergy Corp.Confidential-prepared for Internal Use Only 8OperationThe SY8253is a high efficiency 500kHz synchronous step-down DC-DC converter capable of delivering 3A current.The SY8253operates over a wide input voltage range from 4.5V to 23V and integrates main switch and synchronous switch with very low R DS(ON)to minimize the conduction loss.Low output voltage ripple and small external inductor and capacitor sizes are achieved with 500kHz switching frequency.It adopts the instant PWM architecture to achieve fast transient responses for high step down applicationsApplications InformationBecause of the high integration in the SY8253IC,the application circuit based on this regulator IC is rather simple.Only input capacitor C IN ,output capacitor C OUT ,output inductor L and feedback resistors (R 1and R 2)need to be selected for the targeted applications specifications.Feedback resistor dividers R 1and R 2:Choose R 1and R 2to program the proper output voltage.To minimize the power consumption under light loads,it is desirable to choose large resistance values for both R 1and R 2.A value of between 10kΩand 1MΩis highly recommended for both resistors.If V OUT is 3.3V,R 1=100k is chosen,then using following equation,R 2can be calculated to be 22.1k:Output capacitor C OUT :The output capacitor is selected to handle the output ripple noise requirements.Both steady state ripple and transient requirements must be taken into consideration when selecting this capacitor.For the best performance,it is recommended to use X5R or better grade ceramic capacitor greater than 22uF capacitance.Output inductor L:There are several considerations in choosing this inductor.1)Choose the inductance to provide the desired ripple current.It is suggested to choose the ripple current to be about 40%of the maximum output current.The inductance is calculated as:L =V OUT (1-V OUT /V IN,MAX )F SW ⨯I OUT,MAX ⨯40%where Fsw is the switching frequency and I OUT,MAX is the maximum load current.The SY8253regulator IC is quite tolerant of different ripple current amplitude.Consequently,the final choice of inductance can be slightly off the calculation value without significantly impacting the performance.2)The saturation current rating of the inductor must be selected to be greater than the peak inductor current under full load conditions.I SAT ,MIN >I OUT ,MAX +V OUT (1-V OUT /V IN ,MAX )R 2=V0.6V-0.6V R 1.2⋅F SW ⋅L3)The DCR of the inductor and the core loss at the OUTInput capacitor C IN :The ripple current through input capacitor is calculated as ：switching frequency must be low enough to achieve the desired efficiency requirement.It is desirable to choose an inductor with DCR<50mΩto achieve a good overall efficiency.External Bootstrap CapThis capacitor provides the gate driver voltage for internal high side MOSEFET.A 100nF low ESR CIN _RMS OUT D(1-D).ceramic capacitor connected between BS pin and LX pin is recommended.To minimize the potential noise problem,place a typical X5R or better grade ceramic capacitor really close to the IN and GND pins.Care should be taken to minimize the loop area formed by C IN ,and IN/GND pins.In this case,a 10uF low ESR ceramic capacitor is recommended.CB 100nF V OUT R 1R 20.6V FB GNDI =I ⋅BSLXSY8253AN_SY8253Rev.0.9SilergyCorp.Confidential-prepared for Internal Use Only 9Load Transient Considerations:The SY8253regulator IC integrates the compensation components to achieve good stability and fast transient responses.In some applications,adding a ceramic capacitor in parallel with R1may further speed up the load transient responses and it is recommended for applications with large load transient step requirements.3)The PCB copper area associated with LX pin must be minimized to avoid the potential noise problem.4)The components R 1and R 2,and the trace connecting to the FB pin must NOT be adjacent to the LX net on the PCB layout to avoid the noise problem.5)If the system chip interfacing with the EN pin has a high impedance state at shutdown mode and the IN pin is connected directly to a power source such as a Li-Ion battery,it is desirable to add a pull down 1Mohm resistor between the EN and GND pins to prevent the noise from falsely turning on the regulator at shutdown mode.PCB Layout Suggestion:Soft-Start:The SY8253provides programmable soft-start time feature.The minimum soft-start time is 1ms typically when SS pin is floating.Connect a capacitor across SS pin and GND to program the soft-start time.Tss(ms)=Css(nF)*0.6V/4uA Layout Design:The layout design of SY8253regulator is relatively simple.For the best efficiency and minimum noise problem,we should place the following components close to the IC:C IN ,L,R1and R2.1)It is desirable to maximize the PCB copper area connecting to GND pin to achieve the best thermal and noise performance.If the board space allowed,a ground plane is highly desirable.2)C IN must be close to Pins IN and GND.The loop area formed by CINand GND must be minimized.(SY8253AIC)SY8253AN_SY8253Rev.0.9Silergy Corp.Confidential-prepared for Internal Use Only 10TSOT23-8Package Outline DrawingTop view Side view ASide view BNotes:All dimension in MM and exclude mold flash &metalburrSY8253AN_SY8253Rev.0.9Silergy Corp.Confidential-prepared for Internal Use Only110.3-0.62.80-3.100.300.1-0.200.01-0.11.90TSOT23-6L Package Outline Drawing-0.50Recommended Pad Layout1.00(max)0.95TYP1.90TYPNotes:All dimension in MMAll dimension don’t not include mold flash &metal burr0.25R EF0.950.62.401.002.70-3.001.50-1.70SY8253AN_SY8253Rev.0.9Silergy Corp.Confidential-prepared for Internal Use Only 12Taping &Reel Specification1.Taping orientationTSOT23-8Feeding directionTSOT23-6Feeding direction2.Carrier Tape &Reel specification for packagesSY8253AN_SY8253Rev.0.9Silergy Corp.Confidential-prepared for Internal Use Only 13Reel Size3.Others:NAReel WidthPackage types Tape width (mm)Pocket pitch(mm)Reel size (Inch)Reel width(mm)Trailer length(mm)Leader length(mm)Qty per reel TSOT23-88478.44001603000TSOT23-68478.44001603000。

SILICONMICROSTRUCTURES I N C O R P O R A T E DSM5812/SM5852Amplified Pressure Sensor• N OW WITH ACCESS TO D IGITAL T EMPERATURE AND C ORRECTED D IGITAL P RESSURE • L OW -COST , FULLY AMPLIFIED , CALIBRATED , AND COMPENSATED IN A SINGLE PACKAGE• A VAILABLE FOR D IFFERENTIAL , S INGLE -ENDED DIFFERENTIAL , G AGE & A BSOLUTE APPLICATIONS •M ULTIPLE PRESSURE RANGES AVAILABLE TO MEASURE PRESSURE DOWN TO 0.15 PSI FULL -SCALEAND UP TO 100 PSI FULL -SCALEDESCRIPTIONThe Silicon Microstructures SM5812 and SM5852 series of OEM pressure sensors combines state-of-the-art pressure sensor technology with CMOS digital signal processing technology to produce an amplified, fully conditioned, multi-order pressure and temperature compensated sensor in a dual in-line package (DIP) configuration.Combining the pressure sensor with acustom signal conditioning ASIC in a single package simplifies the use of advanced silicon micromachined pressure sensors. Now, the pressure sensor can be mounted directly to a standard printed circuit board and an amplified, high level, calibrated pressure signal can be acquired from the digital interface or analog output. This eliminates the need of additional circuitry, such as a compensation network or micro-controller containing a custom correction algorithm.The SM5812/SM5852 Series pressure sensors are based on SMI's highly stable, piezoresistive pressure sensor chips mounted on a ceramic substrate. An electronically programmable ASIC iscontained in the same package to provide calibration and temperature compensation.The model SM5812 is designed foroperating pressure ranges from 0-5 PSI up to 0-100 PSI. The model SM5852 isdesigned for operating pressure ranges from 0-0.15 PSI up to 0-3 PSI. For both models, the sensor output is ratiometric with the supply voltage.FEATURES• Amplified, calibrated, fully signalconditioned output span of 4.0 VDC FS (0.5 to 4.5 V signal)• Digital temperature and calibratedpressure available through I 2C interface • Output ratiometric with supply voltage • Multi-order correction for pressure non-linearity (factory programmed)• Multi-order correction for temperature coefficient of span and offset (factory programmed)• Gage, differential, and absolute versions •SMI’s unique low-pressure die allows for a full-scale pressure range of 0-0.15 PSITYPICAL APPLICATIONS• Barometric measurement • Medical instrumentation • Pneumatic control • Gas flow• Respirators and ventilators•Heating, Ventilation and Air Conditioning (HVAC)查询SM5812-005-A-3-L供应商SM5812/SM5852THEORY OF OPERATIONThe operation of the signal processor is depicted in the block diagram below. The external pressure sensor is a piezoresistive bridge. This transduces the applied pressure into an electronic signal, which is then inputted into the integrating amplifier of the ASIC. During the amplification step an offset correction factor is added in order to allow maximum gain for a given pressure while minimizing the offset error.The signal is then passed to an 11-bit analog to digital converter (ADC). The ADC samples the signal multiple times and uses the sum of those samples as a 13-bit word.A digital signal processor (DSP) is then used to correct and calibrate the pressure signal. The DSP provides multi-order correction of both pressure and temperature non-linearity through the use of factory-programmed coefficients. A combined total of twenty coefficients are available for correcting pressure and temperature non-linearity. The unique coefficients are determined during a calibration process performed at the factory. Factory calibration is the last step performed which means the effect of the package on the pressure signal will also be taken into account. This provides a great advantage over conventional laser-trimming approaches.The DSP outputs a corrected digital word, which travels to a 12-bit digital to analog converter (DAC) to provide a calibrated analog output. In addition to the analog output, the corrected pressure signal is accessible through an I2C digital interface. See SMI application note AN05-001 for a detailed description of how to read out the digital corrected pressure signal using theI2C bus interface.Analog OutputSDA SCLSILICONMICROSTRUCTURES I N C O R P O R A T E DSM5812/SM5852CHARACTERISTICS FOR SM5812/SM5852 – SPECIFICATIONSAll parameters are measured at room temperature while applying 5.000V supply, unless otherwise specified.Absolute 1, Gage & Single 2DifferentialMIN TYP MAX MIN TYP MAX UNITS NOTES Zero output (absolute and gauge) 0.42 0.50 0.58 V 3 Zero output (differential)2.422.502.58V3Output Span3.924.00 4.08 1.96 2.00 2.04 V FS 3, 40.15 PSI 3.80 4.00 4.20 1.90 2.00 2.10 V FS 3, 4 Linearity -0.5 +0.5 -0.5 +0.5 %FS 5 0.15 PSI-2.5+2.5-2.5+2.5%FS5 Pressure hysteresis 5812 -0.1 +0.1 -0.1 +0.1 %FS5852 -0.3+0.3 -0.3 +0.3 %FS Temperature coefficient - Zero-1.0 +1.0 -1.0 +1.0 %FS 0.15 PSI-2.5 +2.5 -2.5 +2.5 %FS Temperature coefficient – Span-1.0 +1.0 -1.0 +1.0 %FS 0.15 PSI-2.0 +2.0 -2.0 +2.0 %FS Thermal hysteresis -0.1 +0.1 -0.1 +0.1 %FS Response Time 2 2 msec Supply voltage 4.75 5.00 5.25 4.75 5.00 5.25 V 3, 7Current consumption10 10 mAOverpressure 5812 3X 3X %FS 65852 15X15X %FS 6 Operating temperature range -40 25 +125 -40 25 +125 °C Compensated temperature range 0 25 +70 0 25 +70 °CStorage temperature range -5525+135-5525+135°CMedia compatibility 8Weight 3 3 gramNotes: 1. Absolute parts are only offered in the SM5812 Series.2. Single-ended parts (Pressure Type - S) have 2 ports and are for higher gain differential applications where the differential pressure is always positive.3. Sensor output is ratiometric to supply.4.Full-scale (FS) is defined as zero pressure to rated pressure; differential parts can be used ±FS. Absolute and Gauge zero output is 0.5 V typical and full-scale output is 4.5 V. Span is the difference between Full-scale output and zero output, (4 V). For Differential parts, the negative full-scale is typically at 0.5 V, zero is typically 2.5 V, and positive full-scale is 4.5 volts to give a span of ±2.0 V.5. Defined as best fit straight line for positive pressure applied to the part6. Or 225 PSI, whichever is less. Output amplifier will saturate at about 0.25 V for applied pressure below the rated Zero and at about 4.75 V for applied pressure above the rated Full-scale.7. A 100 nF filter capacitor must be placed between Vsupply and Ground.8.Clean, dry gas compatible with wetted materials. Wetted materials include Pyrex glass, silicon, alumina ceramic, epoxy, RTV, gold, aluminum, and nickel.SM5812/SM5852ADDITIONAL INFORMATIONFull-Scale Pressure RangesSM5812 PSI [kPa] SM5852 PSI [kPa]005 5 [34.5] 001 0.15 [1.0] 015 15 [103.4]003 0.30 [2.1] 030 30 [206.8]008 0.80 [5.5] 060 60 [413.7]015 1.50 [10.3] 100 100[689.5]030 3.00 [20.7]。