IMS-2_07中文资料

目录第一部分概述 (1)1.验收依据 (1)2.内容介绍 (1)3.验收项目编号说明 (1)4.注意事项 (1)第二部分操纵指引 (3)T01 根本业务 (3)T01-01 注册 (3)T01-02 注销 (3)T01-03 语音呼唤 (3)T01-04 视频呼唤 (4)T02 增补业务 (4)T02-01 主叫线号码显示 (4)T02-02 主叫线显示限制 (4)T02-03 无条件前转 (5)T02-04 遇忙前转 (6)T02-05 无应答前转 (7)T02-06 欠费限呼 (8)T02-07 呼唤转移（通话态转移） (8)T02-08 呼唤转移（振铃态转移） (9)T02-09 呼唤期待 (9)T02-10 呼唤保持 (10)T02-11 免打搅 (11)T02-12 三方通话 (12)T03 融合Centrex (13)T03-01 群内IMS用户短号互拨 (13)T03-02 群内IMS用户和移动2G用户短号互拨 (13)T03-03 群内IMS用户拨打群外用户 (14)T04 互通 (15)T04-01 IMS用户乐成呼唤铁通PSTN用户 (15)T04-02 IMS用户呼唤铁通PSTN用户，被叫忙 (15)T04-03 铁通PSTN用户乐成呼唤IMS用户 (16)T04-04 铁通PSTN用户呼唤IMS用户，被叫忙 (16)T04-05 IMS用户乐成呼唤移动2G用户 (17)T04-06 IMS用户呼唤移动2G用户，被叫忙 (17)T04-07 移动2G用户乐成呼唤IMS用户 (18)T04-08 移动2G用户呼唤IMS用户，被叫忙 (18)T05 硬件测试 (19)T05-01 验证各单板指示灯能否正常指示 (19)T05-02 验证各电扇盒上电后正常事情 (19)T05-03 查询单板状态 (19)T05-04 查询单板CPU占用率 (20)T05-05 查询单板网口信息 (20)T06 OMS2600设备验收 (20)T06-01 查察虚拟设备面板 (20)T06-02 查询网元版本 (21)T06-03 查察告警 (21)T07 CSC3300(CSCF)设备验收 (22)T07-01 查询用户在CSCF网元注册状态 (22)T07-02 在CSCF上可以进行用户消息跟踪 (22)T07-03 在CSCF上可以进行Diamter消息跟踪 (22)T08 HSS9820设备验收 (23)T08-01 用户开户 (23)T08-02 查询用户开户数据 (23)T08-03 在HSS上可以进行Diameter消息跟踪 (24)T09 MRC6600(MRFC)设备验收 (24)T09-01 在MRFC上可以进行H248消息跟踪 (24)T09-02 在MRFC上可以进行SIP消息跟踪 (25)T10 MRP6600(MRFP)设备验收 (25)T10-01 在MRFP上可以进行H248消息跟踪 (25)T11 UGC3200(MGCF)设备验收 (26)T11-01 在MGCF上可以进行用户消息跟踪 (26)T11-02 在MGCF上可以进行SIP消息跟踪 (26)T11-03 在MGCF上可以进行BICC消息跟踪 (27)T12 UMG8900(MGW)设备验收 (27)T12-01 在MGW上可以进行H248消息跟踪 (27)T13 SE2300(SBC)设备验收 (28)T13-01 在SBC上查询用户注册状态 (28)第三部分客户验收签字表 (28)第一部分概述1. 验收依据本手册主要依据ITU-T的有关发起和IETF的相关标准并结合华为公司设备的实际情况而编写的。

1 ESN（这个码应该叫‎做机器码的，国外的机卡一‎体机在国外入‎网的时候，一般将机器自‎带的机身ES‎N码提供给运‎营商的，运营商就是根‎据用户的机身‎e sn为基础‎，然后加入其它‎的数据使电话‎正常使用的，我们在国内见‎到的cdma‎机器都有ES‎N码的，但是这个ES‎N不是我们所‎理解的esn‎码，因为国内的是‎机卡分离的机‎器，属于用户的e‎s n码是写在‎U IM卡中的‎）+ Q8 p; J8 Q& w+ r; i. m2 _2 {2 imsi国际‎移动用户识别‎码（IMSI）国际上为唯一‎识别一个移动‎用户所分配的‎号码。

imsi码即‎我们的手机号‎码，但是电信分配‎的内部识别号‎码，外部就是我们‎的133xx‎x手机号码IMSI共有‎15位，其结构如下：i, c Z# R( j _MCC+MNC+MIN- T. `4 U# G% QMCC：Mobile‎Countr‎y Code，移动国家码，共3位，中国为460‎;- \* H+ ` s4 N9 BMNC:Mobile‎Networ‎k Code，移动网络码，共2位，联通CDMA‎系统使用03‎，一个典型的I‎M SI号码为‎460 03 091212‎1001;3 AKEY码（鉴权码）顾名思义，就是手机登录‎网络时候校验‎用的' X# i$ h8 K4 g+ }9 Q5 {1 `- K正规的一体机‎写号，实际就是把i‎m si和a-key写入手‎机，并在电信内部‎系统登记三个‎码的对应关系‎。

手机登录网络‎，把一体机或u‎i m卡上的这‎三个码和交换‎机上的三码进‎行校验，正确及为合法‎用户。

（这种写号方法‎我不了解，看似可行，但肯定对硬件‎做了改动，故不作评论）7）8）已有号码的，两种情况0 l- [5 m4 W) G" G6 q# qa）读取老手机的‎e sn和im‎s i号，通过关系获得‎a-key（绝非通过关系‎换算，如果不是通过‎某种方式直接‎读用户的UI‎M卡，剩下的可能我‎就不说了，嘿嘿）4 Q" W S1 r9 L" Xb）读取老手机的‎e sn和im‎s i号，通过关系关闭‎鉴权（即取消了a-key和其他‎两个码的对应‎关系），写入这两个号‎就可以了，但存在孖机风‎险。

IMS概念IMS即IP Multimedia Subsystem，中文意义为IP多媒体子系统，是由朗讯（Lucent）提出的下一代通信网（NGN）实现大融合方案的网络架构，贝尔实验室在IMS关键领域的创新——业物增强层的各种专利技术，决定了朗讯IMS融合解决方案的先进性。

IMS解决方案相对于软交换的解决方案有着非常多的优势，在NGN市场正占据越来越重要的角色。

截至2003年，国际权威标准组织普遍将IMS作为NGN网络融合以及业务和技术创新的核心标准。

对于大规模商用部署而言，IMS从技术本身已足够成熟。

IMS不仅可以实现最初的VoIP业务，更重要的是IMS将更有效地对网络资源、用户资源及应用资源进行管理，提高网络的智能，使用户可以跨越各种网络并使用多种终端，感受融合的通信体验。

IMS作为一个通信架构，开创了全新的电信商业模式，拓展了整个信息产业的发展空间。

在北美五大电信运营商中，迄今已有四家部署了朗讯的IMS技术，对于无线和有线融合有着极为重要的象征性意义，标志着IMS在全球的部署进入到一个新的阶段。

当然此项技术系统生长依然将注意力放在基础运营服务上，实现全球的网络统一还有很多需要改变的地方。

IP Multimedia Subsystem基本信息中文译名：IP多媒体子系统IMS，即IP Multimedia Subsystem，中文意义为IP多媒体子系统，本质上说是一种网络结构。

该项技术植根于移动领域，最初是3GPP为移动网络定义的，而在NGN的框架下，IMS应同时支持固定接入和移动接入。

目前涵盖IMS增强特性的3GPPR6已经基本冻结，这标志着IMS技术已经走向成熟。

在NGN的框架中，终端和接入网络是各种各样的，而其核心网络只有一个IMS，它的核心特点是采用SIP协议和与接入的无关性。

顺应网络IP化的趋势，IMS系统采用SIP协议进行端到端的呼叫控制。

IP技术在互联网上的应用已经非常成熟，是Internet的主导技术，它能方便而灵活地提供各种信息服务，并能根据客户的需要快捷地创建新的服务。

中国联通IMS技术试验测试规范（V1.0）中国联通公司发布目次前言 (VIII)引言 (9)1 范围 (9)2 规范性引用文件 (9)3 缩略语 (11)4 测试环境要求 (12)4.1 IMS标准体系结构 (12)4.2 IMS试验逻辑结构图 (13)5 业务测试（在测试用例中体现不同接入） (13)5.1 基本业务（见《中国联通IMS技术试验测试规范V0.1-基本业务补充业务分册》） (13)5.1.1 语音呼叫 (13)5.1.2 点对点视频呼叫 (13)5.1.3 异常呼叫 (14)5.2 补充业务（见《中国联通IMS技术试验测试规范V0.1-基本业务补充业务分册》） (14)5.2.1 无条件前转主叫号码识别显示(CLIP) (14)5.2.2 主叫号码识别限制(CLIR) (14)5.2.3 被连号码识别显示(COLP) (14)5.2.4 无条件呼叫前转(CFU) (14)5.2.5 遇用户忙呼叫前转(CFB) (14)5.2.6 遇无应答呼叫前转(CFNRy) (14)5.2.7 遇用户不可及呼叫前转(CFNRc) (14)5.2.8 呼叫等待(CW) (14)5.2.9 呼叫保持(HOLD) (14)5.2.10 多方通话 (14)5.2.11 ODB (14)5.3 VPMN业务 (14)5.3.1 主叫流程(网内呼叫) (14)5.3.2 主叫流程（网外号码组） (14)5.3.3 主叫流程（网外号码） (14)5.3.4 主叫流程（普通呼叫） (14)5.3.5 被叫流程 (14)5.3.6 被叫流程（网外号码组） (14)5.3.7 被叫流程（网外号码） (14)5.3.8 附加业务 (14)5.3.9 管理流程 (14)其它 (14)5.4 多媒体彩铃见《中国联通IMS技术试验测试规范V0.1-IMS彩铃业务测试规范》 (14)5.4.1 拨打测试 (14)5.4.2 运营商业务管理 (14)5.4.3 用户业务管理 (14)其它 (14)5.5 多媒体彩像见《中国联通IMS技术试验测试规范V0.1-IMS彩像业务测试规范》 (14)5.5.1 拨打测试 (14)5.5.2 运营商业务管理 (14)5.5.3 用户业务管理 (14)其它 (14)5.6 IP Centrex 见《中国联通IMS技术试验测试规范V0.1-Centrex业务分册》 (14)5.6.1 群内呼叫 (14)5.6.2 热线电话 (14)5.6.3 群外呼叫限制 (14)其它 (14)5.7 Message 见《中国联通IMS技术试验测试规范V0.1-即时消息业务接口测试规范》 (15)5.7.1 1对1 (15)5.7.2 群发 (15)5.7.3 离线 (15)5.7.4 发送状态报告 (15)5.7.5 定时消息 (15)5.7.6 系统广播 (15)其它 (15)5.8 Presence 见《中国联通IMS技术试验测试规范V0.1-Presence业务接口测试规范》 (15)5.8.1 信息发步 (15)5.8.2 信息订阅 (15)5.8.3 策略设置 (15)5.8.4 通知 (15)5.8.5 资源列表测试 (15)其它 (15)5.9 Group 见《中国联通IMS技术试验测试规范V0.1-Group业务接口测试规范》 (15)5.9.1 个人信息管理 (15)5.9.2 联系列表管理 (15)5.9.3 群组管理 (15)其它 (15)5.10 多媒体会议见《中国联通IMS技术试验测试规范V0.1-多媒体会议接口测试规范》 (15)5.10.1 会议创建 (15)5.10.2 会议管理 (15)5.10.3 数据协同 (15)其它 (15)5.11 互通业务 (15)5.12 基本语音见《中国联通IMS技术试验测试规范V0.1-基本业务补充业务分册》 (15)5.12.1 视频互通 (15)5.12.2 短消息互通见《中国联通IMS技术试验测试规范V0.1-短消息互通测试用例》 (15)5.12.3 漫游测试 (15)其它 (15)5.13 POC（可选） (15)5.13.1 对-1 PoC会话建立 (15)5.13.2 临时（Ad-hoc）PoC群组会话 (15)5.13.3 预定义PoC群组 (15)5.13.4 聊天PoC群组会话 (15)5.13.5 Talk Burst控制 (15)其它 (15)5.14 流媒体（选测） (16)5.15 紧急呼叫（选测） (16)5.16 VCC（选测） (16)5.17 CSI（选测） (16)5.18 Portal接口测试（选测） (16)5.19 厂家特色业务 (16)6 单元测试 (16)6.1 P-CSCF 见《中国联通IMS技术试验测试规范V0.1-CSCF分册》 (16)6.1.1 注册过程测试（含注销过程） (16)6.1.1.1 用户初始注册 (16)6.1.1.2 用户隐式注册 (16)6.1.1.3 用户重注册 (16)6.1.1.4 第三方注册 (16)6.1.1.5 注册状态订阅 (16)6.1.1.6 用户发起的注销 (16)6.1.1.7 注册定时器超时注销 (16)6.1.2 认证过程测试 (16)6.1.2.1 注册过程用户鉴权 (16)6.1.2.2 会话过程中用户鉴权（主要针对固网） (16)6.1.3 会话控制过程测试 (16)6.1.3.1 用户始发会话建立 (16)6.1.3.2 用户终结会话 (16)6.1.3.3 网络发起会话终结 (16)6.1.3.4 会话刷新 (16)6.1.4 计费信息测试 (16)6.1.4.1 (16)6.1.5 SIP信令压缩/解压缩 (17)6.1.5.1 (17)6.1.6 异常流程处理测试 (17)6.1.6.1 (17)6.1.7 业务可扩展性测试 (17)6.1.7.1 (17)6.1.8 支持防火墙穿越的用户接入功能 (17)6.1.8.1 (17)6.2 S-CSCF见《中国联通IMS技术试验测试规范V0.1-CSCF分册》 (17)6.2.1 注册过程测试（含注销过程） (17)6.2.1.1 用户初始注册 (17)6.2.1.2 用户隐式注册 (17)6.2.1.3 用户重注册 (17)6.2.1.4 第三方注册 (17)6.2.1.5 注册状态订阅 (17)6.2.1.6 用户发起的注销 (17)6.2.1.7 网络发起的注销 (17)6.2.1.8 (17)6.2.2 认证过程测试 (17)6.2.3 会话控制过程测试 (17)6.2.3.1 用户始发会话建立 (17)6.2.3.2 用户终结会话 (17)6.2.3.3 未注册用户终结会话 (17)6.2.3.4 用户发起会话释放 (17)6.2.3.5 网络发起会话释放 (17)6.2.3.6 iFC触发流程 (17)6.2.3.7 串行fork（查标准，再确认） (17)6.2.3.8 并行fork (17)6.2.3.9 成功会话 (17)6.2.3.10 不成功会话 (17)6.2.3.11 (18)6.2.4 异常流程处理测试 (18)6.2.4.1 用户未知 (18)6.2.4.2 用户未注册 (18)6.2.4.3 用户忙 (18)6.2.4.4 未授权的媒体类型和编码方案 (18)6.2.4.5 用户签约信息刷新测试 (18)6.2.5 计费信息测试 (18)6.3 I-CSCF 见《中国联通IMS技术试验测试规范V0.1-CSCF分册》 (18)6.3.1 普通用户/漫游用户注册过程 (18)6.3.1.1 S-CSCF指配-HSS返回能力集 (18)6.3.1.2 S-CSCF指配-HSS返回S-CSCF名 (18)6.3.1.3 I-CSCF选择S-CSCF (18)6.3.1.4 S-CSCF重指配 (18)6.3.1.5 PSI归属AS定位 (18)6.3.1.6 漫游禁止测试 (18)6.3.1.7 (18)6.3.2 拓扑隐藏功能测试 (18)6.3.3 被叫路由查询功能测试 (18)6.3.4 计费信息测试 (18)6.4 BGCF 见《中国联通IMS技术试验测试规范V0.1-CSCF分册》 (18)6.4.1 选路能力测试 (18)6.4.1.1 域内MGCF选择测试 (18)6.4.1.2 到域外BGCF选路测试 (18)6.4.2 与PSTN/PLMN CS域的互通测试 (19)6.4.3 计费信息测试 (19)6.5 MGCF 见《中国联通IMS技术试验测试规范V0.1-MGCFMGW分册》 (19)6.5.1 与WCDMA CS域软交换互通测试 (19)6.5.2 与CDMA2000 CS域软交换测试 (19)6.5.3 与传统PLMN/PSTN互通测试 (19)6.5.4 异常测试 (19)6.5.5 多种Codec支持、转换测试 (19)6.5.6 计费测试 (19)6.5.7 H.323互通测试（可选） (19)6.6 IM-MGW 见《中国联通IMS技术试验测试规范V0.1-MGCFMGW分册》 (19)6.6.1 与WCDMA CS域软交换互通测试 (19)6.6.2 与CDMA2000 CS域软交换测试 (19)6.6.3 与传统PLMN/PSTN互通测试 (19)6.6.4 多种Codec支持、转换测试 (19)6.6.5 回声抑止测试 (20)6.6.6 静音抑制/舒适噪音测试 (20)6.7 HSS 见《中国联通IMS技术试验测试规范V0.1-HSS分册》 (20)6.7.1 用户管理测试 (20)6.7.1.1 放号功能测试 (20)6.7.1.2 签约信息管理测试 (20)6.7.1.3 隐式注册集的测试 (20)6.7.1.4 用户数据查询 (20)6.7.1.5 用户数据更新 (20)6.7.1.6 用户增加 (20)6.7.1.7 用户删除 (20)6.7.1.8 (20)6.7.2 注册/认证过程测试 (20)6.7.3 移动性管理测试 (20)6.7.3.1 用户注册通知处理测试 (20)6.7.3.2 初始注册-隐式注册 (20)6.7.3.3 注册超时-用户重新注册 (20)6.7.3.4 注册失败由于非法密码 (20)6.7.3.5 注册失败由于Unknown PUID (20)6.7.3.6 注册失败由于错误的NAI (20)6.7.3.7 被禁止用户注册失败 (20)6.7.3.8 数据库信息不匹配 (20)6.7.3.9 IMSUE注册失败 (20)6.7.3.10 用户未注册作为被叫时的通知 (20)6.7.3.11 用户发起的注销通知 (20)6.7.3.12 HSS发起的注销－注销原因为PERMANENT_TERMINATION (20)6.7.3.13 用户注册权限控制 (20)6.7.3.14 用户存在其它已注册的IMPU的注册状态查询 (20)6.7.3.15 用户状态为unregistered的位置查询 (20)6.7.3.16 (20)6.7.4 异常请求测试 (21)6.7.5 多用户ID测试 (21)6.7.6 会话过程测试 (21)6.8 PDF（PDF的测试用例分UMTS以及EVDO两种接入方式来编写） (21)6.8.1 SBLP过程测试（含建立和释放过程） (21)6.8.2 计费协调，支持ICID交换和GCID交换测试 (21)6.8.3 支持策略门控功能，控制用户的媒体流是否允许经过GGSN测试 (21)6.8.4 支持分叉功能，识别带分叉指示的授权请求处理以及呼叫应答时授权信息的更新测试 (21)6.8.5 异常测试 (21)6.9 RACS（可选） (21)6.10 MRF（含MRFC和MRFP）（查标准）见《中国联通IMS技术试验测试规范V0.1-MRF分册》 (21)6.10.1 放音、收号测试 (21)6.10.2 混音功能测试 (21)6.10.3 会以控制测试 (21)6.10.4 录音测试 (22)6.11 IM-SSF 见《中国联通IMS技术试验测试规范V0.1-IM－SSF分册》 (22)6.12 Parlay网关见《中国联通IMS技术试验测试规范V0.1-ParlayAPI测试规范》 (22)6.13 SBC测试见《中国联通IMS技术试验测试规范V0.1-SBC分册》 (22)6.13.1 SIP信令和媒体的NAT的穿越 (22)6.13.2 重叠的地址空间 (22)6.13.3 拓扑的隐藏 (22)6.13.4 媒体定时器----长时间无媒体流 (22)6.13.5 媒体定时器----超长呼叫处理 (22)6.13.6 QoS标签----SIP消息 (22)6.13.7 RTP分组的QoS标签----音频呼叫 (22)6.13.8 RTP分组的QoS标签----视频呼叫 (22)6.13.9 会话带宽控制 (22)6.13.10 会话容量控制 (22)6.13.11 (22)6.14 SLF（可选）见《中国联通IMS技术试验测试规范V0.1-SLF分册》 (22)6.15 ALG与TrGW（可选） (22)6.16 负载均衡测试（在下一阶段测试，请提出相应的测试建议） (22)6.17 过载保护测试（在下一阶段测试，请提出相应的测试建议） (22)6.18 可靠性测试（多机备份）（在下一阶段测试，请提出相应的测试建议） (22)7 接口测试（按照中国联通要求12月15号前提供） (23)7.1 ISC接口（必测，要求提供具体测试用例） (23)7.2 Gm接口（必测，要求提供具体测试用例） (23)7.3 Mw接口（必测，要求提供具体测试用例） (23)7.4 Mg接口（必测，要求提供具体测试用例） (23)7.5 Mi接口（必测，要求提供具体测试用例） (23)7.6 Mj接口（必测，要求提供具体测试用例） (23)7.7 Mr接口（必测，要求提供具体测试用例） (23)7.8 Cx接口（必测，要求提供具体测试用例） (23)7.9 Sh接口（必测，要求提供具体测试用例） (23)7.10 Rf接口（必测，要求提供具体测试用例） (23)7.11 Gq接口（必测，要求提供具体测试用例） (23)7.12 Go接口（必测，要求提供具体测试用例） (23)7.13 Sr接口（选测，但要求提供具体测试用例） (23)7.14 Mk接口（选测，但要求提供具体测试用例） (24)7.15 Mm接口（选测，由厂家建议具体测试用例） (24)7.16 Mx接口（选测，由厂家建议具体测试用例） (24)7.17 Mp接口（选测，由厂家建议具体测试用例） (24)7.18 Mn接口（选测，由厂家建议具体测试用例） (24)7.19 Mb接口（选测，由厂家建议具体测试用例） (24)7.20 Ut接口（选测，由厂家建议具体测试用例） (24)7.21 Dx接口（选测，由厂家建议具体测试用例） (24)7.22 Si接口（选测，由厂家建议具体测试用例） (24)7.23 Dh接口（选测，由厂家建议具体测试用例） (24)7.24 与Ro接口（选测，由厂家建议具体测试用例） (24)7.25 Ty接口（3GPP2，选测，由厂家建议具体测试用例） (24)7.26 固网RACS相关接口 (24)7.27 Ix接口（本阶段暂不测试） (24)8 安全测试（必测，要求提供具体测试用例） (24)9 计费测试见《中国联通IMS技术试验测试规范V0.1-计费网管分册》 (24)9.1 离线计费完整工作流程计费测试 (24)9.2 在线计费完整工作流程计费测试（可选） (25)9.3 错误场景计费消息测试（具体内容参看3GPP 32.260 第5.2.2.2章节） (25)9.4 计费采集信息测试 (25)9.5 CDF/CCF计费信息处理测试 (25)9.6 跨IMS运营商之间IMS会话计费话单产生测试。

中国电信集团公司发布保密等级：目录1范围 (1)2规范性引用文件 (1)3符号及缩写 (1)4传真和MODEM业务在IMS网络中适用的场景 (2)5传真和MODEM业务基本技术要求 (2)5.1 基本要求 (2)5.2 传真和M ODEM设备的类型 (2)6传真和MODEM业务事件描述 (3)6.1 传真业务 (3)6.1.1 T.38传真 (3)6.1.2 G.711传真 (3)6.2 M ODEM业务 (4)7传真业务实现描述 (4)7.1 业务场景 (4)7.2 低速传真设备之间的互通 (4)7.3 高速传真设备之间的互通 (4)7.4 高速传真设备与低速传真设备之间的业务互通 (5)7.4.1 业务原则 (5)7.4.2 高速传真设备首先检测到传真事件 (5)7.4.3 低速传真设备首先检测到传真事件 (5)8 MODEM业务实现描述 (5)8.1 业务场景 (5)8.2 低速M ODEM设备之间互通 (6)8.3 高速M ODEM设备之间互通 (6)8.4 高速M ODEM设备与低速M ODEM设备之间互通 (6)8.4.1 业务原则 (6)8.4.2 高速Modem设备首先检测到Modem事件 (6)8.4.3 低速Modem设备首先检测到传真事件 (6)9 AG CF设备控制下的H.248网关行为描述 (6)附录A 业务实现信令流程（规范性附录） (7)A.1传真业务实现流程 (7)A.1.1 低速传真设备业务互通信令流程 (7)A.1.1.1 传真成功建立 (7)A.1.1.2 会话结束 (9)A.1.2 高速传真设备业务互通信令流程 (9)A.1.1.1 传真成功建立 (9)A.1.1.2 会话结束 (10)A.1.3 高、低速传真设备业务互通信令流程 (10)A.1.1.1 传真成功建立 (10)A.1.1.1.1高速传真设备首先检测到传真信号 (10)A.1.1.1.2 低速传真设备首先检测到传真信号 (13)A.1.1.2 会话结束 (13)A.2M ODEM业务实现流程 (14)A.2.1 低速Modem设备业务互通信令流程 (14)A.2.1.1 Modem成功建立 (14)A.2.1.2 会话结束 (15)A.2.2 高速Modem设备业务互通信令流程 (16)A.2.2.1 Modem业务成功建立 (16)A.2.2.2 Modem结束 (16)A.2.3 高、低速Modem设备业务互通信令流程 (17)A.2.3.1 Modem成功建立 (17)A.2.3.1.1 高速Modem设备首先检测到Modem信号 (17)A.2.3.1.2 低速Modem设备首先检测到Modem信号 (17)A.2.3.2 Modem结束 (17)前言本标准以行业标准、ITU相关标准为基础，结合中国电信网络的实际情况，并综合中国电信集团公司对IMS网络的实验成果而制定。

缩略语英文中文查询呼叫会话控制功能I-CSCF Interrogating Call SessionControl Function服务呼叫会话控制功能S-CSCF Serving Call Session ControlFunction紧急呼叫会话控制功能E-CSCF Emergency Call Session ControlFunction中断出口网关控制功能BGCF Breakout Gateway ControlFunction代理呼叫会话控制功能P-CSCF Proxy Call Session ControlFunctionSBC Session Border Controller会话边界控制器HSS Home Subscriber Server归属用户服务器SLF Subscribe Location Function用户位置功能MGCF Media Gateway Control Function媒体网关控制功能IM-MGW IMS Media Gateway IMS媒体网关VIG video interworking gateway视频互通网关VIG-MGW video interworking gateway-视频互通媒体网关Media GatewayCCF Charging Collection Function计费收集功能ENUM/DNS E.164 number and DNS E.164号码及域名系统ENUM E.164 Number E.164号码DNS Domain Name System域名系统ATS Multiple Multimedia TelephonyMMTEL业务应用服务器Application ServerAS Application Server业务应用服务器多媒体资源控制功能MRFC Multimedia Resource FunctionControllerMRFP Multimedia Resource Function多媒体资源处理功能ProcessingCentrex CENTRal Exchange虚拟用户交换机CTD Click To Dial点击拨号ISBG I-CSCF/S-CSCF/E-CSCF/BGCF合设节点SPG Service ProvisionningGateway功能说明I-CSCF是IMS归属网络的入口点。

14446fTYPICAL APPLICATIONFEATURESAPPLICATIONSDESCRIPTIONLow Side N-ChannelMOSFET DriverThe L TC ®4446 is a high frequency high voltage gate driver that drives two N-channel MOSFETs in a DC/DC converter with supply voltages up to 100V . The powerful driver ca-pability reduces switching losses in MOSFETs with high gate capacitance. The L TC4446’s pull-up for the top gate driver has a peak output current of 2.5A and its pull-down has an output impedance of 1.2Ω. The pull-up for the bot-tom gate driver has a peak output current of 3A and the pull-down has an output impedance of 0.55Ω.The L TC4446 is confi gured for two supply-independent inputs. The high side input logic signal is internally level-shifted to the bootstrapped supply, which may function at up to 114V above ground.The L TC4446 contains undervoltage lockout circuits that disable the external MOSFETs when activated. The L TC4446 is available in the thermally enhanced 8-lead MSOP package.The L TC4446 does not have adaptive shoot-through pro-tection. For similar drivers with adaptive shoot-through protection, please refer to the chart below.PARAMETER L TC4446L TC4444L TC4444-5Shoot-Through Protection No Yes Yes Absolute Max TS 100V 100V 100V MOSFET Gate Drive 7.2V to 13.5V 7.2V to 13.5V 4.5V to 13.5VV CC UV +6.6V 6.6V 4V V CC UV– 6.15V 6.15V 3.55V nBootstrap Supply Voltage Up to 114V n Wide V CCVoltage: 7.2V to 13.5V n 2.5A Peak Top Gate Pull-Up Current n 3A Peak Bottom Gate Pull-Up Current n 1.2Ω Top Gate Driver Pull-Down n 0.55Ω Bottom Gate Driver Pull-Down n 5ns Top Gate Fall Time Driving 1nF Load n 8ns Top Gate Rise Time Driving 1nF Load n 3ns Bottom Gate Fall Time Driving 1nF Load n 6ns Bottom Gate Rise Time Driving 1nF Loadn Drives Both High and Low Side N-Channel MOSFETs n Undervoltage Lockoutn Thermally Enhanced 8-Pin MSOP PackagenDistributed Power Architecturesn Automotive Power Supplies n High Density Power Modules n Telecommunication SystemsT wo Switch Forward ConverterL TC4446 Driving a 1000pF Capacitive LoadL , L T , L TC and L TM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6677210.V BINP 5V/DIVBG 10V/DIV TINP 5V/DIV TG-TS 10V/DIV20ns/DIV4446 TA01b/24446fPIN CONFIGURATIONABSOLUTE MAXIMUM RATINGSSupply VoltageV CC.........................................................–0.3V to 14V BOOST – TS ...........................................–0.3V to 14V TINP Voltage .................................................–2V to 14V BINP Voltage .................................................–2V to 14V BOOST Voltage ........................................–0.3V to 114V TS Voltage ...................................................–5V to 100V Operating Temperature Range (Note 2)....–40°C to 85°C Junction Temperature (Note 3) .............................125°C Storage Temperature Range ...................–65°C to 150°C Lead Temperature (Soldering, 10 sec) ..................300°C(Note 1)1234TINP BINP V CC BG8765TS TG BOOST NCTOP VIEW9MS8E PACKAGE 8-LEAD PLASTIC MSOPT JMAX = 125°C, θJA = 40°C/W , θJC = 10°C/W (NOTE 4)EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCBORDER INFORMATIONELECTRICAL CHARACTERISTICSSYMBOL PARAMETER CONDITIONSMIN TYP MAX UNITS Gate Driver Supply, V CC V CC Operating Voltage7.213.5V I VCCDC Supply Current TINP = BINP = 0V350550μA UVLO Undervoltage Lockout ThresholdV CC Rising V CC Falling Hysteresis l l6.005.606.606.154507.206.70V V mV Bootstrapped Supply (BOOST – TS)I BOOSTDC Supply Current TINP = BINP = 0V 0.12μA Input Signal (TINP , BINP)V IH(BG)BG Turn-On Input Threshold BINP Ramping High l 2.25 2.75 3.25V V IL(BG)BG Turn-Off Input Threshold BINP Ramping Low l 1.85 2.3 2.75V V IH(TG)TG Turn-On Input Threshold TINP Ramping High l 2.25 2.75 3.25V V IL(TG)TG Turn-Off Input Threshold TINP Ramping Lowl 1.852.3 2.75V I TINP(BINP)Input Pin Bias Current ±0.01±2μA High Side Gate Driver Output (TG)V OH(TG)TG High Output Voltage I TG = –10mA, V OH(TG) = V BOOST – V TG 0.7V V OL(TG)TG Low Output Voltage I TG = 100mA, V OL(TG) = V TG –V TSl 120220mV I PU(TG)TG Peak Pull-Up Current l 1.72.5A R DS(TG)TG Pull-Down Resistance l1.22.2ΩThe l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. V CC = V BOOST = 12V , V TS = GND = 0V , unless otherwise noted.LEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION TEMPERATURE RANGE L TC4446EMS8E#PBF L TC4446EMS8E#TRPBF L TDPZ 8-Lead Plastic MSOP –40°C to 85°C L TC4446IMS8E#PBFL TC4446IMS8E#TRPBFL TDPZ8-Lead Plastic MSOP–40°C to 85°CConsult L TC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container .Consult L TC Marketing for information on non-standard lead based fi nish parts.For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear .com/tapeandreel//34446fNote 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: The L TC4446E is guaranteed to meet specifi cations from 0°C to 85°C. Specifi cations over the –40°C to 85°C operatingtemperature range are assured by design, characterization and correlationELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operatingtemperature range, otherwise specifi cations are at T A = 25°C. V CC = V BOOST = 12V , V TS = GND = 0V , unless otherwise noted.SYMBOL PARAMETERCONDITIONSMINTYP MAXUNITS Low Side Gate Driver Output (BG)V OH(BG)BG High Output Voltage I BG = –10mA, V OH(BG) = V CC – V BG0.7VV OL(BG)BG Low Output Voltage I BG = 100mAl 55110mV I PU(BG)BG Peak Pull-Up Current l 23A R DS(BG)BG Pull-Down Resistance l0.55 1.1ΩSwitching Time (BINP (TINP) is Tied to Ground While TINP (BINP) is Switching. Refer to Timing Diagram)t PLH(TG)TG Low-High (Turn-On) Propagation Delay l 2545ns t PHL(TG)TG High-Low (Turn-Off) Propagation Delay l 2240ns t PLH(BG)BG Low-High (Turn-On) Propagation Delay l 1935ns t PHL(BG)BG High-Low (Turn-Off) Propagation Delay l 1430ns t DM(BGTG)Delay Matching BG Turn-Off and TG Turn-On l –151035ns t DM(TGBG)Delay Matching TG Turn-Off and BG Turn-On l –25–325ns t r(TG)TG Output Rise Time 10% – 90%, C L = 1nF 10% – 90%, C L = 10nF880ns ns t f(TG)TG Output Fall Time 10% – 90%, C L = 1nF 10% – 90%, C L = 10nF550ns ns t r(BG)BG Output Rise Time 10% – 90%, C L = 1nF 10% – 90%, C L = 10nF660ns ns t f(BG)BG Output Fall Time 10% – 90%, C L = 1nF 10% – 90%, C L = 10nF 330ns nswith statistical process controls. The L TC4446I is guaranteed over the full –40°C to 85°C operating temperature range.Note 3: T J is calculated from the ambient temperature T A and power dissipation P D according to the following formula: T J = T A + (P D • θJA °C/W)Note 4: Failure to solder the exposed back side of the MS8E package to the PC board will result in a thermal resistance much higher than 40°C/W .TYPICAL PERFORMANCE CHARACTERISTICSV CC Supply Quiescent Current vs VoltageBOOST-TS Supply Quiescent Current vs VoltageV CC Supply Current vs TemperatureV CC SUPPL Y VOL TAGE (V)00Q U I E S C E N T C U R R E N T (μA )501502002506789101112134504446 G011001234514300350400BOOST SUPPL Y VOL TAGE (V)00Q U I E S C E N T C U R R E N T (μA )501502002506789101112134004446 G021001234514300350TEMPERATURE (°C)V C C S U P P L Y C U R R E N T (μA )3503603704446 G03330300–40–25–105203550658095110125380340320310/44446fTYPICAL PERFORMANCE CHARACTERISTICSBoost Supply Current vs TemperatureOutput Low Voltage (V OL ) vs Supply VoltageOutput High Voltage (V OH ) vs Supply VoltageInput Thresholds (TINP , BINP) vs Supply VoltageInput Thresholds (TINP , BINP) vs TemperatureInput Thresholds (TINP , BINP) Hysteresis vs VoltageInput Thresholds (TINP , BINP) Hysteresis vs TemperatureV CC Undervoltage Lockout Thresholds vs TemperatureRise and Fall Time vs V CC Supply VoltageTEMPERATURE (°C)B O O S T S U P P L YC U R R E N T (μA )2503003504446 G041500–40–25–10520355065809511012540020010050SUPPL Y VOL TAGE (V)7O U T P U T V O L T A G E (m V )140104446 G058040891120016012010060121314SUPPL Y VOL TAGE (V)75T G O R B G O U T P U T V O L T A G E (V )689101512911124446 G0671314118101314SUPPL Y VOL TAGE (V)72.1T G O R B G I N P U T T H R E S H O L D (V )2.22.42.52.63.12.8911124446 G072.32.93.02.78101314TEMPERATURE (°C)–25T G O R B G I N P U T T H R E S H O L D (V )2.62.83.0954446 G082.42.22.52.72.92.32.12.053565–10–40110205080125SUPPL Y VOL TAGE (V)78375T G O R B G I N P U T T H R E S H OL D H Y S T E R E S I S (m V )425500911124446 G09400475450101314TEMPERATURE (°C)–40–25375T G O R B G I N P U T T H R E S H O L D H Y S T E R E S I S(m V )425500–105205065804446 G104004754503511095125TEMPERATURE (°C)–406.0V C C S U P L L Y V O L T A G E (V )6.16.36.46.56.7–2535654446 G116.26.62095125110–1055080SUPPL Y VOL TAGE (V)7R I S E /F A L L T I M E (n s )122830222632911124446 G12820161024618148101314/54446fTYPICAL PERFORMANCE CHARACTERISTICSRise and Fall Time vs Load CapacitancePeak Driver (TG, BG) Pull-Up Current vs TemperatureOutput Driver Pull-Down Resistance vs TemperaturePropagation Delay vs V CC Supply VoltagePropagation Delay vs TemperatureLOAD CAPACITANCE (nF)1R I S E /F A L L T I M E (n s )40506094445 G1330200357210468108070TEMPERATURE (°C)–402.0P U L L -U P C U R R E N T (A )2.22.62.83.03.4–2535654446 G142.43.22095125110–1055080TEMPERATURE (°C)–25O U T P U T D R I V E R P U L L -D O W N R E S I S T A C N E (Ω)1.21.62.0954446 G150.80.41.01.41.80.60.253565–10–40110205080125SUPPL Y VOL TAGE (V)710P R O P A G A T I O N D E L A Y (n s )121618203024911124444 G16142628228101314TEMPERATURE (°C)–402P R O P A G A T I O N D E L A Y (n s )717222737–2535654446 G1712322095125110–1055080Switching Supply Current vs Input FrequencySwitching Supply Current vs Load CapacitanceSWITCHING FREQUENCY (kHz)S U P P L Y C U R R E N T (m A )1.52.02.560010004446 G181.00.502004008003.03.54.0LOAD CAPACITANCE (nF)1S U P P L Y C U R R E N T (m A )1010013450.127896104446 G19/64446fPIN FUNCTIONSBLOCK DIAGRAMTINP (Pin 1): High Side Input Signal. Input referenced to GND. This input controls the high side driver output (TG).BINP (Pin 2): Low Side Input Signal. This input controls the low side driver output (BG).V CC (Pin 3): Supply. This pin powers input buffers, logic and the low side gate driver output directly and the high side gate driver output through an external diode con-nected between this pin and BOOST (Pin 6). A low ESR ceramic bypass capacitor should be tied between this pin and GND (Pin 9).BG (Pin 4): Low Side Gate Driver Output (Bottom Gate). This pin swings between V CC and GND.NC (Pin 5): No Connect. No connection required.BOOST (Pin 6): High Side Bootstrapped Supply. An ex-ternal capacitor should be tied between this pin and TS (Pin 8). Normally, a bootstrap diode is connected between V CC (Pin 3) and this pin. Voltage swing at this pin is from V CC – V D to V IN + V CC – V D , where V D is the forward volt-age drop of the bootstrap diode.TG (Pin 7): High Side Gate Driver Output (Top Gate). This pin swings between TS and BOOST .TS (Pin 8): High Side MOSFET Source Connection (Top Source).Exposed Pad (Pin 9): Ground. Must be soldered to PCB ground for optimal thermal performance.TIMING DIAGRAMTINP (BINP)BG (TG)BINP (TINP)TG (BG)/OPERATIONOverviewThe L TC4446 receives ground-referenced, low voltage digi-tal input signals to drive two N-channel power MOSFETs in a synchronous buck power supply confi guration. The gate of the low side MOSFET is driven either to V CC or GND, depending on the state of the input. Similarly, the gate of the high side MOSFET is driven to either BOOST or TS by a supply bootstrapped off of the switching node (TS). Input StageThe L TC4446 employs CMOS compatible input thresholds that allow a low voltage digital signal to drive standard power MOSF ETs. The LTC4446 contains an internal voltage regulator that biases both input buffers for high side and low side inputs, allowing the input thresholds (V IH = 2.75V, V IL = 2.3V) to be independent of variations inV CC. The 450mV hysteresis between V IH and V IL eliminates false triggering due to noise during switching transitions. However, care should be taken to keep both input pins (TINP and BINP) from any noise pickup, especially in high frequency, high voltage applications. The L TC4446 input buffers have high input impedance and draw negligible input current, simplifying the drive circuitry required for the inputs.Output StageA simplifi ed version of the L TC4446’s output stage is shown in Figure 1. The pull-up devices on the BG and TG outputs are NPN bipolar junction transistors (Q1 and Q2). The BG and TG outputs are pulled up to within an NPN V BE (~0.7V) of their positive rails (V CC and BOOST, respectively). Both BG and TG have N-channel MOSFET pull-down devices (M1 and M2) which pull BG and TG down to their nega-tive rails, GND and TS. The large voltage swing of the BG and TG output pins is important in driving external power MOSFETs, whose R DS(ON) is inversely proportional to the gate overdrive voltage (V GS − V TH).Rise/Fall TimeThe L TC4446’s rise and fall times are determined by the peak current capabilities of Q1 and M1. The predriver that drives Q1 and M1 uses a nonoverlapping transition scheme to minimize cross-conduction currents. M1 is fully turned off before Q1 is turned on and vice versa.Since the power MOSFET generally accounts for the ma-jority of the power loss in a converter, it is important to quickly turn it on or off, thereby minimizing the transition time in its linear region. An additional benefi t of a strong pull-down on the driver outputs is the prevention of cross- conduction current. For example, when BG turns the low side (synchronous) power MOSFET off and TG turns the high side power MOSFET on, the voltage on the TS pin will rise to V IN very rapidly. This high frequency positive voltage transient will couple through the C GD capacitance of the low side power MOSFET to the BG pin. If there is an insuffi cient pull-down on the BG pin, the voltage on the BG pin can rise above the threshold voltage of the low side power MOSFET, momentarily turning it back on. With Figure 1. Capacitance Seen by BG and TG During Switching/74446fOPERATIONboth the high side and low side MOSFETs conducting, signifi cant cross-conduction current will fl ow through the MOSFETs from V IN to ground and will cause substantial power loss. A similar effect occurs on TG due to the C GS and C GD capacitances of the high side MOSFET.The powerful output driver of the L TC4446 reduces the switching losses of the power MOSFET, which increase with transition time. The L TC4446’s high side driver is capable of driving a 1nF load with 8ns rise and 5ns fall times using a bootstrapped supply voltage V BOOST-TS of 12V while its low side driver is capable of driving a 1nF Power DissipationTo ensure proper operation and long-term reliability, the L TC4446 must not operate beyond its maximum tem-perature rating. Package junction temperature can be calculated by:T J = T A + P D (θJA)where:T J = Junction temperatureT A = Ambient temperatureP D = Power dissipationθJA = Junction-to-ambient thermal resistance Power dissipation consists of standby and switching power losses:P D = P DC + P AC + P QGwhere:P DC = Quiescent power lossP AC = Internal switching loss at input frequency, f INP QG = Loss due turning on and off the external MOSFET with gate charge QG at frequency f IN load with 6ns rise and 3ns fall times using a supply volt-age V CC of 12V.Undervoltage Lockout (UVLO)The L TC4446 contains an undervoltage lockout detector that monitors V CC supply. When V CC falls below 6.15V, the output pins BG and TG are pulled down to GND and TS, respectively. This turns off both external MOSFETs. When V CC has adequate supply voltage, normal operation will resume.APPLICATIONS INFORMATIONThe L TC4446 consumes very little quiescent current. TheDC power loss at V CC = 12V and V BOOST-TS = 12V is only(350μA)(12V) = 4.2mW.At a particular switching frequency, the internal power lossincreases due to both AC currents required to charge anddischarge internal node capacitances and cross-conduc-tion currents in the internal logic gates. The sum of thequiescent current and internal switching current with noload are shown in the Typical Performance Characteristicsplot of Switching Supply Current vs Input Frequency.The gate charge losses are primarily due to the large ACcurrents required to charge and discharge the capacitanceof the external MOSFETs during switching. For identicalpure capacitive loads C LOAD on TG and BG at switchingfrequency f IN, the load losses would be:P CLOAD = (C LOAD)(f)[(V BOOST-TS)2 + (V CC)2]In a typical synchronous buck confi guration, V BOOST-TSis equal to V CC – V D, where V D is the forward voltagedrop across the diode between V CC and BOOST. If thisdrop is small relative to V CC, the load losses can beapproximated as:P CLOAD = 2(C LOAD)(f IN)(V CC)2/84446fAPPLICATIONS INFORMATIONUnlike a pure capacitive load, a power MOSF ET’s gate capacitance seen by the driver output varies with its V GS voltage level during switching. A MOSFET’s capacitive load power dissipation can be calculated using its gate charge, Q G. The Q G value corresponding to the MOSFET’s V GS value (V CC in this case) can be readily obtained from the manufacturer’s Q G vs V GS curves. For identical MOSFETs on TG and BG:P QG = 2(V CC)(Q G)(f IN)To avoid damage due to power dissipation, the L TC4446 includes a temperature monitor that will pull BG and TG low if the junction temperature rises above 160°C. Normal operation will resume when the junction temperature cools to less than 135°C.Bypassing and GroundingThe LTC4446 requires proper bypassing on the V CC and V BOOST-TS supplies due to its high speed switching (nanoseconds) and large AC currents (Amperes). Careless component placement and PCB trace routing may cause excessive ringing.To obtain the optimum performance from the L TC4446: A. Mount the bypass capacitors as close as possible between the V CC and GND pins and the BOOST and TS pins. The leads should be shortened as much as possible to reduce lead inductance.B. Use a low inductance, low impedance ground plane to reduce any ground drop and stray capacitance. Remember that the L TC4446 switches greater than 3A peak currents and any signifi cant ground drop will degrade signal integrity.C. Plan the power/ground routing carefully. Know where the large load switching current is coming from and going to. Maintain separate ground return paths for the input pin and the output power stage.D. Keep the copper trace between the driver output pin and the load short and wide.E. Be sure to solder the Exposed Pad on the back side of the L TC4446 package to the board. Correctly soldered to a 2500mm2 doublesided 1oz copper board, the L TC4446 has a thermal resistance of approximately 40°C/W for the MS8E package. Failure to make good thermal contact between the exposed back side and the copper board will result in thermal resistances far greater than 40°C/W./94446f104446fTYPICAL APPLICATIONL T C 3722/L T C 4446 420W 36V -72V I N t o 12V /35A I s o l a t e d F u l l -B r i d g e S u p p l yL 1V I –V I 36V T /分销商库存信息:LINEAR-TECHNOLOGYLTC4446EMS8E#PBF LTC4446EMS8E#TRPBF LTC4446IMS8E#PBF LTC4446IMS8E#TRPBF。

Product Technical SpecificationsProject Name: IMS2Author:Revision: 1.4Revision Date: 2017/10/18Contact InformationRevision HistoryTHIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN IS PROPRIETARY AND IS EXCLUSIVE PROPERTY AND SHALL NOT BE DISTRIBUTED, REPRODUCED, OR DISCLOSED IN WHOLE OR IN PART WITHOUT PRIOR WRITTEN PERMISSION. LIMITATION OF LIABILITYTHIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN IS PURELY FOR DESIGN REFERENCE AND SUBJECT TO REVISION AT ANY TIME. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY WARRANTY OR RIGHT TO USE THE MATERIAL CONTAINED HEREIN WITHOUT PRIOR EXPRESS WRITTEN CONSENT. WE SHALL NOT BE LIABLE FOR ANY USE, APPLICATION OR DEVELOPMENT DERIVED FROM THE MATERIAL WITHOUT SUCH PRIOR EXPRESS WRITTEN CONSENT.ContentsContact Information (2)Revision History (2)1Introduction (6)1.1 General Features (6)1.2 Architecture (8)1.3 Connection Interface (8)1.4 Environmental Specifications and Certifications (8)1.4.1 Environmental Specifications (8)1.4.2 Certifications (9)1.4.3 Green Product Compliance (9)2Pin Definitions (10)2.1 LGA Module Pin Diagram (10)2.2 LGA Module Pin Definitions (10)3Electrical Specifications (14)3.1 Power Supply (14)3.2 Power Consumption (14)3. 3 Control Interfaces (15)3. 3.1 Power-on Signal (15)3. 3.2 Wake-up Interface (15)3. 3.3 Reset Signal (15)3.4 UART Interface (16)3.5 UIM Interface (16)3.6 I/O Characteristics (17)3.7 JTAG Interface (18)3.8 ADC Interface (18)3.9 RFDATA (19)3.10 RF Interface (19)3. 10.1 Bandwidth Support (19)3. 10.2 RF Transmission Specifications (20)3. 10.3 RF Receiver Specifications (20)4Mechanical Information (21)4.1 Physical Dimensions (21)4.2 Pin Dimensions (21)4.3 Marking Information (23)5Packing Information (24)5.1 Tape-and-Reel Package (24)5.2 Single Packaging for Samples (25)6Design Guide (26)6.1 Power Trace Design (26)6.2 RF Pad Design (26)6.3 RF Matching Guide (27)6.4 Interference and Sensitivity (27)6.5 Mounting Considerations (28)6.6 PCB Pad Design (29)6.7 Stencils (30)6.8 LTE Power Saving Mode (31)7 Safety Recommendation (32)Initialisms (33)1 IntroductionThe IMS2 module includes the Sequans SQN3330 Cat. M1 baseband, a complete LTE RF front-end, memory, and required circuitry to fulfill 3GPP E-UTRA (Long Term Evolution - LTE, Rel-13 specifications) and AT&T Wireless LTE Cat. M1 UEspecifications. The following table enumerates the frequencies supported by the IMS2 module.Table 1-1. Band supportLTE Band 21,850–1,910 1,930–1,990LTE Band 41,710–1,755 2,110–2,155LTE Band 12699–716 729–7461.1 General FeaturesThe table below summarizes the IMS2 module features.Table 1-2. General features of the IMS2General interfaces • JTAG • USIM • GPIO • UARTSupported frequency bands • LTE Band 2 • LTE Band 4 • LTE Band 12Operating voltage • V CC (range: from 3.3 V to 4.2 V)Packaging • LGA module• 104 pads (21.5 mm × 16.5 mm × 2.3 mm) • RoHS compliantTable 1-3. LTE-related features of the IMS2 Standardscompliance• 3GPP E-UTRA Rel-13PHY • One UL and one DL transceiver • Support s HD-FDD duplexing • Category M1 UE• Normal cyclic prefix• Support s MPDCCH• Modulation- DL: QPSK, 16 QAM- UL: QPSK, 16 QAM• All coding schemes corresponding to modulations• All channel coding (turbo-coding with inter-leaver, tail biting convolutional coding, block and repetition coding) and CRC lengths• All power control schemes and DL power allocation schemes • UEPCOP (from 3GPP Rel-12) Power Saving ModeMAC • Random access procedure in normal sub-frames• Scheduling request, buffer status reporting, and power headroom reporting• Discontinuous reception (DRX, eDRX) with long and short cycles• Fast scanning• IPv4, IPv6RLC • ARQ modes: UM, AM, and TMPDCP • Ciphering and deciphering: NULL, AES, SNOW 3G • Integrity and protection: AES, SNOW 3GRRC • MIB and new SIB1bis• Supports up to eight data radio bearersNAS and above • NAS• SMS over SG s • LWM2M client1.2 ArchitectureThe architecture block diagram of the IMS2 is presented in Figure 1-1 below.Figure 1-1. IMS2 block diagram1.3 Connection InterfaceThe IMS2 module is an LGA device. All electrical and mechanical connections are made through the 104 pads on the bottom side of the PCB.1.4 Environmental Specifications and Certifications1.4.1 Environmental SpecificationsThe environmental specifications for both operating and storage conditions are defined in the table below.1.4.2 CertificationsThe IMS2 module is compliant with the following regulations: PTCRB, FCC, IC and AT&T TA.1.4.3 Green Product ComplianceRoHS (2011/65/EU)2 Pin Definitions2.1 LGA Module Pin DiagramThe IMS2 LGA module pin layout is illustrated below.Figure 2-1. IMS2 LGA module pin layout (top view) 2.2 LGA Module Pin DefinitionsThe signals and all the related details are listed in the below table.①: Pull pin100 to VREF with a 10 kΩ resistor; this pin cannot be used as a GPIO.Recommend reserve a test point for emergency firmware download mode.②: Leave pin142 floating; the module can turn on automatically when a power supply exists.③: Pin144 can be used as a wake-up as the module enters deep-sleep status. The default configuration is active high to wake up the LGA module.④: The VREF voltage will turn off when entering the deep sleep state.3 Electrical Specifications3.1 Power SupplyThe IMS2 module is supplied through the power signal with the followingcharacteristics.3.2 Power ConsumptionThis section describes the typical power consumption of the IMS2 (for reference).Table 3-2. LTE power consumption3. 3 Control InterfacesThis section describes the power-on/off, wake-up, and reset interface for controlling the module.3. 3.1 Power-on SignalThe function is not available in the present firmware; the module will be turned on automatically when the power supply exists. Set this pin as “floating” or use 0 Ω as a reserve.3. 3.2 Wake-up InterfaceThere are two methods to wake up the module when the module enters a deep-sleep state.1. The m odules will be automatically awakened when the T3412 time has el apsed.1.Pin144 can be used as a wake up module; the user can connect it to a key or hostcontrol signal.The default setting is a high level wake-up; it is not possible to use the VR EF as a pull-up powe r.3. 3.3 Reset SignalThe module will reset automatically when the power supply voltage is applied on the power inputs. If requiring an external hardware reset, the user can connect the module to a key or host control signal. A low pulse will reset the module. The duration of the low pulse must be at least 100 µs. The module has a pull-up resistor; therefore the reset signal does not require an external pull-up resistor.3.4 UART InterfaceThere are three UART interfaces; these interfaces are 4 bit for high-speed data transfer, and the UART definitions of IMS2 are illustrated in the following figure. The UART interface support 1.8V.1.UART0 for LTE data and AT command; the default baud rate is 921,600 bps.2.UART1 for software firmware upgrade3.UART2 for debug console; the default baud rate is 115.200 bps.Figure 3-1. UART interface (example)3.5 UIM InterfaceIMS2 modules provide a UIM_DETECT input pin for UIM connectors to detect a UIM card. When a UIM card is present, UIM_DETECT should be high (1.8 V). If the UIM card is absent, UIM_DETECT should be low. This is required to pull UIM_DETECT to VREF with a 470 kΩ resistor. We recommend placing a 0.1 μF and a 33 pF capacitor between UIM_VCC and Ground in-parallel and a 33 pF capacitor between UIM_RESET, UIM_CLK, and UIM_DATA and Ground in parallel.An electrostatic discharge (ESD) protection circuit is also recommended near the UIM socket as close as possible, and the Ground pin of the ESD protection component must be well connected to the Ground plane.The following figure illustrates an example UIM card circuit. The default configuration is active high.Figure 3-2. Example UIM card circuit3.6 I/O CharacteristicsThe voltage and current characteristics of the various IO pads of the IMS2 versus IO bank supply voltage are illustrated in Table 3-3 below.3.7 JTAG InterfaceThe IMS2 series contains one JTAG interface; leave JTAG pins floating if they are not used.Figure 3-3. JTAG schematic3.8 ADC InterfaceThe IMS2 series contains two ADC ports; the specifications are listed below.when the IMS2 is in sleep mode, then an external analog switch (such as FET) must be connected to each ADC input pin to prevent any current leakage while the module is in the PMU sleeping state.3.9 RFDATAThe RFDATA5/6/7 pins can implement the function requiring a high-precision time-stamped GPIO.3.10 RF InterfaceEach IMS2 module has only one RF pad; developers must connect it via 50 Ω traces to the main board.Main antenna pad (Pin15) – Primary RX/TX path3. 10.1 Bandwidth Support3. 10.2 RF Transmission Specifications2. Complies with 3GPP test standards.3. 10.3 RF Receiver Specifications2. Compliant with 3GPP test standards4 Mechanical Information4.1 Physical DimensionsDevice dimensions are illustrated in Figure 4-1 and Figure 4-2 below.Figure 4-1. Top view Figure 4-2. Right view4.2 Pin DimensionsThe dimensions are illustrated in Figure 4-3, Figure 4-4, and Figure 4-5 below.Figure 4-3. Pin dimensions (bottom view)Figure 4-4. Pin dimensionsFigure 4-5. Pin dimensions4.3 Marking InformationThe IMS2 series module label is illustrated below.P/N: Variable; for the specific customer (Ex.: 60IMS201.0G1)S/N: Variable; unique for each moduleIMEI: Variable; unique for each moduleFCC: NKRIMS2IC : 4441A-IMS2If customers request their own S/Ns and IMEIs, they should inform us before production. The S/N and IMEI only can be written once onto each unit.5 Packing Information5.1 Tape-and-Reel PackageThe module is delivered in tape-and-reel based on MPQ (500 pcs./reel).4 reel/carton.5.2 Single Packaging for Samples50 pcs./box; no vacuum packaging; must be baked for 8 hours at 85 °C before SMT6 Design Guide6.1 Power Trace DesignPower trace layout suggestion: At least 22 μF, 0.1 μF, and 100 pF capacitors are required; place the capacitors as close to the power pins as possible. Power trace should possess sufficient line width to withstand its respective current listed in the table below:of the module.6.2 RF Pad DesignWe recommend that a ground not be present under the surface of the RF pads in the layout. Details are included below. Layer 2 has the same exclusion area as Layer 1.Figure 6-1. Sample RF pad layout6.3 RF Matching Guide1. Reserve the matching circuit as depicted in the topological structure below.2. The matching circuit should be as close The impedance (S11) should be close to 50 Ω, VSWR < 1.5.Figure 6-2. RF Matching guide6.4 Interference and SensitivityThis section includes tips to help developers identify interferences that may affect the IMS2 module when used in systems.⏹ Interference from other wireless devices– We highly recommend checking the RX performance of entire systems within the shielding environment.– Good isolation (ex.: Wi-Fi antenna, GPS antenna) is requiredbetween the other wireless system antenna and the IMS2 module LTE antenna. ⏹ Interference from the host interface– High-speed signal-switching elements in systems can easily couple noise into the module (ex.: DDR memory, LCD modules, DC-TO-DC converters, PCM signals). ⏹ Methods to avoid sources of interference– Antenna location is important; we recommend directing theantenna away from high-speed switching signals. Furthermore, the trace from the module to the antenna should be as short as possible and must be shielded by complete grounding.– The IMS2 module is well shielded; high-speed elements (Ex.: DDR memory, LCD modules, DC-to-DC converters, PCM signals) on a system should have shielding reserved during the early stages of development.6.5 Mounting ConsiderationsThis section details the recommended reflow profile when the module is mounted onto other boards.Process limit:6.6 PCB Pad DesignWe recommend a non-solder mask defined (NSMD) type for the solder pads of the PCB on which IMS2 modules will be mounted. This type of design enables high soldering reliability during the SMT process.We recommend not placing via or micro-via not covered by solder resistance within 0.3 mm around the pads unless it carries the same signal of the pad itself. Refer to the following figure.Holes in pad are allowed only for blind holes and not for through holes.6.7 StencilsWe suggest a stencil-foil thickness of ≥ 0.12 mm for module SMTs and the use of a diagonal pattern to prevent voids during reflow.Stencil-foil drawing6.8 LTE Power Saving ModeNote: Details will be provided in a future revision of this document.7 Safety RecommendationBe sure the use of this product is allowed in the country and in the environment required. The use of this product may be dangerous and must be avoided in thefollowing areas:⏹Where it can interfere with other electronic devices in environments suchas hospitals, airports, and aircraft⏹Where there is a risk of explosion such as gasoline stations and oilrefineriesThe user is responsible for compliance with the legal and environmental regulations of their location of use.Do not disassemble the product; any evidence of tampering will compromise the warranty’s validity.We recommend following the instructions of the hardware user guides for a correct wiring of the product. The product must be supplied with a stabilized voltage source, and the wiring must conform to relevant security and fire-prevention regulations.This product must be handled with care; avoid any contact with the pins because electrostatic discharge may damage the product. Exercise the same level of caution regarding the UIM card; carefully check the instructions for its use. Do not insert or remove the UIM when the product is in power-saving mode.The system integrator is responsible for the functioning of the final product;therefore, care must be taken for the external components of the module as well as for project or installation issues—there may be a risk of disturbing the GSM network or external devices or of impacting device security. If you have any questions, refer to the technical documentation and the relevant regulations in-force.Every module must be equipped with a proper antenna with specific characteristics.The antenna must be installed with care in order to avoid any interference withother electronic devices.Initialisms。