QuickLogic® EOS™ S3 SensorProcessing Platform Input/Output Multiplexor (IOMUX) User Guide• • • • • •IntroductionThis document provides a functional overview of the QuickLogic EOS S3 sensor processing platform IOMUX. It also describes how to program the IOMUX register block, which controls the 46 IOs.Functional OverviewThere are 46 IOs (or PADs) that can be multiplexed to/from various functions on the EOS S3 sensor processing platform. Each pad can be programmed independently as an input pad, output pad, or bidirectional pad. Programming the IOMUX register block (0x40004C00 – 0x40004DAC) controls the various functions that drive and sample the pad values. Refer to the Appendix – Table 12 for IOMUX register descriptions.NOTE: IOs and PADs are used interchangeably in this document. Both mean the same thing, which is an IO. For example IO_6 is the same as PAD 6.Figure 1 shows a block diagram of the implementation.•The red muxes are controlled by IOMUX_PAD_0_CTRL[1:0]. This function determines which output can drive to a pad. There is one red mux for each pad.•The blue muxes select the output pad control, which can come from:IOMUX_PAD_x_CTRL[12:5] – Register controlled (e.g., A0 register)Other – Controlled for bidirectional signals (e.g., Serial Wire Debugger (SWD) and I2C controllers)Fabric (FB) – I/O controlled. These muxes are for output and/or bidirectional signaling from the device to the system. •The yellow “AND” gate and mux allows the device to sample pad values to various functional blocks within the device. This logic is for input and bidirectional signaling to the device from the system.© 2020 QuickLogic Corporation2Figure 1: IOMUX Block DiagramWhen allocating pads in the system design for EOS S3, consider the following:• The Cortex ™ M4 processor, application processor (AP) (via SPI slave), and SWD can read/write the IOMUX registers. The IOMUX registers are located in the Always-On power domain. If the power is cycled or a device reset is asserted, the IOMUX register settings will default back to the reset state. The programmable logic (Fabric), which is a slave IP, cannot configure the IOMUX registers. The M4, AP, or SWD is required to set up the IOMUX settings for the Fabric to use. • Eight pads can be used as general purpose IOs (GPIOs), which the M4 can drive and sample, using the IOMUX_IO_REG_SEL (0x40004D60), MISC_IO_INPUT (0x40005100), and MISC_IO_OUTPUT (0x40005104) register controls. • The Fabric can control all 46 pads, assuming the M4 sets up the appropriate IOMUX programming.• Eight of the pads can be used as external interrupts to the system (e.g., sensor interrupt or GPIO interrupt), as interrupts to M4 or sensor interrupts to FFE. • The other pads can be used for serial interfaces such as SPI slave, multiple SPI masters, SWD, UART, IRDA, I 2C masters, audio microphone inputs (PDM or I 2S), and I2S output to the AP. • Eight of the pads can be used as debug monitoring pins (debug_mon). Some of PMU, CRU, Audio, and FFE internal signaling can be brought out to eight pads. For example, CRU can bring out clocks to a pad to monitor frequency. Refer to the Appendix – Table 13 for possible function/pad assignments. This is for system design, as it shows all the possible IO assignments.IMPORTANT: Determine functions for all 46 pads first as per the system design, then program the IOMUX register accordingly.Programming the IOMUX RegistersHow to Select the Output FunctionEach IO output can be driven from one of four different functional outputs, as shown by the red muxes in Figure 1. Only one function can drive to the pad as output.There are 46 IOMUX_PAD_x_CTRL registers, where ‘x’ is a register number from 0 to 45, one register per pad. Program the corresponding register IOMUX_PAD_x_CTRL bits [1:0] to select the function that drives the corresponding pad.Each IOMUX_PAD_x_CTRL register looks similar to the example shown in Table 1.© 2020 QuickLogic Corporation 3For pad 0, program IOMUX_PAD_0_CTRL[1:0] to select the function that outputs to pad 0. When looking at the register definition of IOMUX_PAD_0_CTRL, bit encoding is NOT listed in the highlighted bit field. Refer instead to the Appendix – Table 11 functional IOMUX descriptions.Table 2 is a partial list of pads 0 through 2 (from the Appendix – Table 11) that shows IOMUX output pad programming options.The following are programming examples based on the information in Table 2:•Example 1: To program IOMUX_PAD_0_CTRL[1:0]:Set to 0 for I2C0 CLK (SCL0) to drive pad 0Set to 1 for Fabric IO 0 (FBIO_0) to drive pad 02 and3 are not assigned and are reserved•Example 2: To program IOMUX_PAD_1_CTRL[1:0]:Set to 0 for I2C0 DAT (SDA0) to drive pad 1Set to 1 for Fabric IO 1 (FBIO_1) to drive pad 12 and3 are not assigned and are reserved.•Example 3: To program IOMUX_PAD_2_CTRL[1:0]:Set to 0 for Fabric IO 2 (FBIO_2) to drive PAD2Set to 1 for SPI sensor device select 2 (spi_sensor_ssn2) to drive PAD2© 2020 QuickLogic Corporation 4Set to 2 to bring out debug monitor point (debug_mon[0]) to drive PAD2Set to 3 to bring out battery monitor IO (batt_mon) to drive PAD2NOTE: If the pad is used as an input pad, then bits IOMUX_PAD_x_CTRL[1:0] can be ignored or left as is. PAD2 can also be an input pad assigned to a sensor interrupt.IOMUX_PAD_43_CTRL (0x40004CAC) is protected from accidental writes. To program this register, program MISC_LOCK_EN (0x40005310) to 0x1ACCES551 prior to writing IOMUX_PAD_43_CTRL. SeeTable 3 for details.The pad controls for the pad are controlled by IOMUX_PAD_x_CTRL[4:3]. See Table 4 for details. This is the blue-colored mux seen in Figure 1.© 2020 QuickLogic Corporation 5•Select 0 if the output enable from the pad is controlled by IOMUX_PAD_x_CTRL[5]. Since IOMUX is located in the A0 (Always-On) power domain, this is considered an A0 register.Program IOMUX_PAD_x_CTRL[5]–Set to 0 to be an output pad.–Set to 1 to be an input pad. Output driver within pad is disabled.•Select 1 if an alternate function controls the output enable dynamically. For example, I2C master(s) need bidirectional control of the output enable for the I2C DAT pin (SDAx). Another example, SWD needs bidirectional control of the output enable for SWD DATA pin (SW_DP_IO).IOMUX_PAD_x_CTRL[5] is ignored.•Select 2 if Fabric controls the output enable dynamically.IOMUX_PAD_x_CTRL[5] is ignored.How to Select an Input FunctionEach functional input can be selected from the eight IOs. See the yellow-colored “AND” gate and mux in Figure 1. To set up input pads:•Program IOMUX_PAD_x_CTRL[11] – Receive enable (yellow colored “AND” gate):Set to 1 to be an input pad.Set to 0 to IOMUX_PAD_x_CTRL[5] to disable as an output pad.•Program the input mux to route the pad signal to the functional block inside the device (yellow colored mux): Each functional input has IOMUX_<function>_SEL (0x40004d00 - 0x40004dac).© 2020 QuickLogic Corporation 6See the following examples:Example 1: I2C0 DAT pin (SDA0) can get its input from PAD1.•Program IOMUX_SDA0_SEL (0x40004D00) = 1.This enables the yellow mux between PAD1 to I2C0 master.•Program IOMUX_PAD_1_CTRL (0x40004C04) = 0x808.Bit[1:0] = 0, selects the SDA0 function.Bit[4:3] = 1, selects the Other function. This means the I2C0 master block controls the output enable.Bit[5] is ignored. Can write 0 for now.Bit[11]:1, sets the receive enable. This is required for the I2C0 master to detect the I2C0 DAT pin change, since this is a bidirectional pin.Example 2: I2C1 DAT pin (SDA1) can get its input from three possible pads: PAD15, PAD32, PAD44.Option 1 if PAD15 is selected:•Program IOMUX_SDA1_SEL (0x40004D04) = 1 for pad 15.•Program IOMUX_PAD_15_CTRL (0x40004C3C) = 0x80ABit[1:0] = 2, selects SDA_1 for PAD15. See Table 7.Bit[4:3] = 1, selects the Other function. This means I2C1 master controls the output enable.Bit[5] is ignored. Can write 0 for now.Bit[11] = 1, sets the receive enable. This is required for the I2C1 master to detect I2C1 DAT pin change, since this is a bidirectional pin.Option 2 if PAD32 is selected:•Program IOMUX_SDA1_SEL (0x40004D04) = 2 for pad 32.•Program IOMUX_PAD_32_CTRL (0x40004C80) = 0x80B.Bit[1:0] = 3, selects SDA_1 for PAD32. See Table 7.Bit[4:3] = 1, selects the Other function. This means I2C1 master controls the output enable.© 2020 QuickLogic Corporation 7Bit[5] is ignored. Can write 0 for now.Bit[11] = 1, sets the receive enable. This is required for the I2C1 master to detect the I2C1 DAT pin change, since this is a bidirectional pin.Option 3 if PAD44 is selected:•Program IOMUX_SDA1_SEL (0x40004D04) = 3 for pad 44.•Program IOMUX_PAD_44_CTRL (0x40004CB0) = 0x80A.Bit[1:0] = 2, selects SDA_1 for PAD44. See Table 7.Bit[4:3] = 1, selects the Other function. This means I2C1 master block will control the output enable.Bit[5] is ignored. Can write 0 for now.Bit[11] = 1, sets the receive enable. This is required for the I2C1 master to detect the I2C1 DAT pin change, since this is a bidirectional pin.© 2020 QuickLogic Corporation 8Table 7 shows a portion of the Appendix – Table 11.Table 7: IOMUX Assignment for Pads 15, 32, 44NOTE: Only one input pad can be selected for a functional block.How to use GPIOsIn EOS S3, eight pins can be used as GPIOs by the M4. Sixteen pads can be assigned to the eight IO functions. Once the eight pads are selected by IOMUX_IO_REG_SEL (0x40004D74) (see Table 8), the M4 can drive to the pad using MISC_IO_OUTPUT or sample the pads reading MISC_IO_INPUT (0x40005100) (see Table 9).© 2020 QuickLogic Corporation 9IOMUX_IO_REG_SEL (0x40004D74) is the register definition (see Table 8) that shows the possible pad assignments for GPIOs. •Pad 6 or 24 can be GPIO 0.•Pad 9 or 26 can be GPIO 1.•Pad 11 or 28 can be GPIO 2.•Pad 14 or 30 can be GPIO 3.•Pad 18 or 31 can be GPIO 4.•Pad 21 or 36 can be GPIO 5.•Pad 22 or 38 can be GPIO 6.•Pad 23 or 45 can be GPIO 7.© 2020 QuickLogic Corporation 10For example, set up all eight GPIOs to the following pads:1. Program IOMUX_IO_REG_SEL (0x40004D60) to 8’b11110000.•PAD6 as GPIO 0. Write bit[0] = 0.•PAD9 as GPIO 1. Write bit[1] = 0.•PAD11 as GPIO 2. Write bit[2] = 0.•PAD14 as GPIO 3. Write bit[3] = 0.•PAD31 as GPIO 4. Write bit[4] = 1.•PAD36 as GPIO 5. Write bit[5] = 1.•PAD38 as GPIO 6. Write bit[6] = 1.•PAD45 as GPIO 7. Write bit[7] = 1.2. Program the IOMUX pad controls, pad 6, 9, 11, and 14 as output pads.•Write 0x3 to IOMUX_PAD_6, 9, 11, and 14_CTRL registers.Bit[4:3] = 0, selects A0 register control (this must be programmed before bit[12:5] is programmed).Bit[1:0] = 3, selects the GPIO function for output (see the Appendix – Table 11).Bit[5] = 0, selects output driver enabled. Configures as an output pad.Bit[11] = 0, disables receive enable (input enable).Bit[7:6], Bit[9:8], Bit[12] are pad driver characteristics. Keep all 0 for now. Refer to Table 1 for details.3. Program the IOMUX pad controls, pad 31, 36, 38, and 45 as inputs pads.•Write 0x823 to IOMUX_PAD_31, 36, 38, and 45_CTRL registers.Bit[4:3] = 0, selects A0 register control (this must be programmed before bit[12:5] is programmed).Bit[1:0] = 3, selects the GPIO function for output (see the Appendix – Table 11).Bit[5] = 1, disables output driver enabled.Bit[11] = 1, enables receive enable (input enable). Configures as an input pad.Bit[7:6], Bit[9:8], Bit[12] are pad driver characteristics. Keep all 0 for now. Refer to Table 1for details.4. Drive all GPIO 0 through 3 to all ONES.•Write 4’b1111 to MISC_IO_OUTPUT.•Pads 6, 9, 11, and 14 go HIGH.5. Drive all GPIO 0 through 3 to all ZEROS.•Write 4’b0000 to MISC_IO_OUTPUT.•Pads 6, 9, 11, and 14 go LOW.6. Drive all GPIO 0 through 3 to all 4’b1000.•Write 4’b1000 to MISC_IO_OUTPUT.•Pad 14 goes HIGH and pads 6, 9, and 11 stay LOW.7. Sample GPIO 4 through 7.•Read MISC_IO_INPUT. The values present on PAD31, PAD36, PAD38, and PAD45 map to values MISC_IO_INPUT[4],[5], [6], and [7].Bootstrap Impacts in IOMUXSeveral of the pads (8, 9, 19, and 20) are used as bootstrap pins. Bootstrap pins are used to indicate device modes when the device is coming out of reset. Setting a bootstrap requires the IO to be asserted to a certain value (0 or 1) during the device reset assertion and de-assertion. The rising edge of the device reset latches the bootstrap value. These bootstraps can have an impact on the IOMUX function.The following example is for PAD14:•If bootstrap PAD8 is set to 0 when the device reset is released, PAD14 is a SWD Debug Clock pin.•If bootstrap PAD8 is set to 1 when the device reset is released, PAD14 is a Fabric IO pin. (This requires no programming and occurs in hardware.)The M4 processor can still program the IOMUX_PAD_14_CTRL to change the output mux select to 1, 2, and 3. But the 0 definition changes by bootstrap.The IOMUX_PAD_15_CTRL output mux select 0 is tied to the SWD Data pin, but only when bootstrap #8 = 0. When bootstrap #8 =1, the IOMUX_PAD15_CTRL defaults to 0, but the SWD is not active in this strap mode. This means thatIOMUX_PAD15_CTRL[1:0] must be reprogrammed to be non-zero. Refer to Table 10 for PAD 14 and PAD 15 output control.Bootstrap PAD 9 Impacts PAD 6If bootstrap PAD 9 is set to 1 when the device reset is released, PAD 6 becomes the FCLK input (fast clock input) which overrides the internal OSC output. This IOMUX selection can only be cleared by system reset, since this is a bootstrap function. Writing to IOMUX_PAD_6_CTRL register [1:0] has no impact when bootstrap PAD 9 is in effect.Similarly, pads 15, 16, 17, 18, 19, 34, 36, 38, 39, 44, and 45 are also impacted by different bootstrap modes. See the Appendix – Table 11 and look at the Comment column.How to Program Fabric IOThe on-device programmable logic (Fabric) can use all 46 IOs. The IOMUX must be programmed by the M4 processor first. Then the Fabric design can be loaded by the M4 processor, and the Fabric output isolation released. The following 46 IOs are configured by the M4 processor. A subset of the following C routine can be used to configure the Fabric IOs for your system design. Each Fabric IO is assigned to each IO respectively.AppendixTable 11 shows the EOS S3 IOMUX output assignments.Table 12 shows the IOMUX registers descriptions as reference. The IOMUX address base is at 0x40004C00. Add the register offset to the address base for the exact register address. The complete EOS S3 register map can be found in the QuickLogic EOS S3 Sensor Processing Platform Register Map Guide.。
