MBR20030CT中文资料

MBR10200CT ASEMI高压肖特基二极管
肖特基二极管MBR10200CT参数规格：
肖特基二极管MBR10200CT电流：10A；
肖特基二极管MBR10200CT电压：200V；
肖特基二极管MBR10200CT管装：50/管；盒装：1000PCS/盒。

肖特基二极管广泛应用于开关电源、变频器、驱动器等电路，作高频、低压、大电流整流二极管、续流二极管、保护二极管使用，或在微波通信等电路中作整流二极管、小信号检波二极管使用。

MBR10200CT ITO-220AB肖特基二极管PDF资料
MBR10200CT肖特基类型：高结温芯片，品牌：ASEMI，
应用市场：电源，小家电，LED电源，各式充电器，开关电源，LED显示屏等。

MBR10200CT肖特基相关参数如下：
MBR10200CT电压Vrrm:200V
MBR10200CT电流If平均：10A
MBR10200CT正向电压Vf最大：0.87V
MBR10200CT电流，Ifs最大：150A
MBR10200CT工作温度范围：-40°C to+150°C
MBR10200CT封装形式：TO-220/TO-220F/ITO-220
MBR10200CT反向恢复电流，Irrm:10UA
肖特基系列型号：
MBR1040CT,MBR1045CT,MBR1060CT,MBR1060FCT, MBR10100CT,MBR10100FCT,MBR10150FCT,MBR10150CT, MBR10200FCT,MBR10200CT
肖特基二极管封装：TO-251,TO-252,TO-263,
TO-220,TO-247,TO-3P。

MBR30H100CT , MBRF30H100CT & MBRB30H100CT SeriesVishay Semiconductorsformerly General SemiconductorDocument Number New ProductReverse Voltage 90 to 100VForward Current 30A Maximum T J 175°CMounting Pad Layout TO-263ABITO-220AB (MBRF30H90CT, MBRF30H100CT)(MBR30H90CT, MBR30H100CT)TO-263AB (MBRB30H90CT, MBRB30H100CT)Features• Plastic package has Underwriters Laboratory Flammability Classification 94V-0• Dual rectifier construction, positive center tap • Metal silicon junction, majority carrier conduction • Low power loss, high efficiency• Guardring for overvoltage protection• For use in low voltage, high frequency inverters, free wheeling, and polarity protection applicationsMechanical DataCase:JEDEC TO-220AB, ITO-220AB & TO-263AB molded plastic bodyTerminals:Plated leads, solderable per MIL-STD-750, Method 2026High temperature soldering guaranteed: 250°C/10 seconds, 0.25" (6.35mm) from case Polarity:As markedMounting Position: AnyMounting Torque:10 in-lbs maximum Weight:0.08oz., 2.24gMBR30H100CT , MBRF30H100CT & MBRB30H100CT SeriesVishay Semiconductorsformerly General Semiconductor Document Number 88791Maximum Ratings (TC= 25°C unless otherwise noted)ParameterSymbol MBR30H90CTMBR30H100CTUnit Maximum repetitive peak reverse voltage V RRM 90100V Working peak reverse voltage V RWM 90100V Maximum DC blocking voltageV DC 90100V Maximum average forward rectified current Total device 30(see fig. 1)Per leg I F(AV)15A Peak forward surge current8.3ms single half sine-wave superimposed I FSM 275A on rated load (JEDEC Method) per legPeak repetitive reverse current per leg at t p = 2µs, 1KH Z I RRM 1.0A Voltage rate of change (rated V R )dv/dt 10,000V/µs Operating junction and storage temperature range T J , T STG –65 to +175°C RMS Isolation voltage (MBRF type only) from terminals 4500(1)to heatsink with t = 1 second, RH ≤30%V ISOL3500(2)V1500(3)Electrical Characteristics (TC= 25°C unless otherwise noted)ParameterSymbolValue Unit at I F = 15A, T J = 25°C 0.82Maximum instantaneous at I F = 15A, T J = 125°C V F0.67Vforward voltage per leg (4)at I F = 30A, T J = 25°C 0.93at I F = 30A, T J = 125°C0.80Maximum reverse current per leg T J = 25°C 5.0µA at working peak reverse voltage (4)T J = 125°CI R6.0mAThermal Characteristics (TC= 25°C unless otherwise noted)ParameterSymbol MBR MBRF MBRB UnitTypical thermal resistance per legR θJC1.94.61.9OC/WNotes:(1) Clip mounting (on case), where lead does not overlap heatsink with 0.110” offset (2) Clip mounting (on case), where leads do overlap heatsink(3) Screw mounting with 4-40 screw, where washer diameter is ≤ 4.9 mm (0.19”)(4) Pulse test: 300µs pulse width, 1% duty cycleOrdering InformationProductCase Package CodePackage OptionMBR30H90CT - MBR30H100CT TO-220AB 45Anti-Static tube, 50/tube, 2K/carton MBRF30H90CT - MBRF30H100CT ITO-220AB 45Anti-Static tube, 50/tube, 2K/carton 3113” reel, 800/reel, 4.8K/cartonMBRB30H90CT - MBRB30H100CTTO-263AB45Anti-Static tube, 50/tube, 2K/carton81Anti-Static 13” reel, 800/reel, 4.8K/cartonMBR30H100CT , MBRF30H100CT & MBRB30H100CT SeriesVishay Semiconductorsformerly General SemiconductorDocument Number Ratings andCharacteristic Curves (T A = 25°C unless otherwise noted)100100.10.011.0J u n c t i o n C a p a c i t a n c e (p F )110100100100000.110Reverse Voltage (V)t, Pulse Duration (sec.)I F -- I n s t a n t a n e o u s F o r w a r d C u r r e n t (A )5101520253035Fig. 1 – Forward Derating CurvePer LegA v e r a g e F o r w a r d C u r r e n t (A )Fig. 2 – Maximum Non-Repetitive Peak Forward Surge Current Per Leg1000。

Intel® 80200 Processor based on Intel®XScale™ MicroarchitectureDatasheet - Commercial and Extended Temperature (80200T) Product FeaturesI High Performance Processor based onIntel® XScale™ Microarchitecture—7-8 stage Intel® SuperpipelinedTechnology—32-Entry Instruction MemoryManagement Unit—32-Entry Data Memory Management Unit—32 KByte, 32-way Set Associative Instruction Cache—32 KByte, 32-way Set Associative Data Cache—2 KByte, 2-way Set AssociativeMini-Data Cache—128-Entry Branch Target Buffer—8-Entry Write Buffer—4-Entry Fill and Pend BuffersI Intel® Dynamic V oltage Management—Core Voltage Range: 0.95 V to 1.55 V—Internal Clock Scalable by Software—Input Clock: 33-66 MHzI ARM* Version 5TE CompliantI Application-Code Compatible withIntel®StrongARM*SA-110I Power Management—Core Power is ~500mW at 600MHz—Core Voltage Operation Down to 0.95 V —Idle and Sleep ModesI Intel® Media Processing Technology—Multiply-Accumulate CoprocessorI High Performance External Bus—64- or 32-Bit Data Interface—Optional ECC Protection—Frequency up to 100 MHz—Asynchronous to Processor ClockI Performance Monitoring Unit—Two 32-Bit Event Counters—One 32-Bit Clock Counter—Monitors Occurrence and Duration EventsI Debug Unit—Accessible through JTAG Port—Hardware Breakpoints—256-Entry Trace BufferI80200T can operate at an ambienttemperature range of -40C to +85CIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHA TSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELA TING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.Intel products are not intended for use in medical, life saving, life sustaining applications.Intel may make changes to specifications and product descriptions at any time, without notice.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling1-800-548-4725 or by visiting Intel's website at .Copyright© Intel Corporation, 2003AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, iCat, iCOMP, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare, RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In, TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.*Other names and brands may be claimed as the property of others.Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureContents1.0About this Document (5)2.0Functional Overview (5)2.1Superpipeline (7)2.2Branch Target Buffer (BTB) (8)2.3Instruction Memory Management Unit (IMMU) (8)2.4Data Memory Management Unit (DMMU) (9)2.5Instruction Cache (I-Cache) (9)2.6Data Cache (D-Cache) (10)2.7Mini-Data Cache (10)2.8Fill Buffer (FB) and Pend Buffer (PB) (11)2.9Write Buffer (WB) (11)2.10Multiply-Accumulate Coprocessor (CP0) (11)2.11Clock and Power Management (12)2.12Performance Monitoring Unit (PMU) (12)2.13Debug Unit (12)2.14Extended Temperature (80200T) (12)3.0Package Information (13)3.1Package Introduction (13)3.1.1Functional Signal Definitions (13)3.1.1.1Signal Pin Descriptions (13)3.1.2241 Lead PBGA Package (17)3.2Package Thermal Specifications (22)3.3Package Thermal Resistance (22)4.0Electrical Specifications (24)4.1Absolute Maximum Ratings (24)4.2V CCA Pin Requirements (25)4.3Targeted DC Specifications (26)4.4Targeted AC Specifications (27)4.4.1Clock Signal Timings (27)4.4.2Bus Signal Timings (28)4.4.3Boundary Scan Test Signal Timings (29)4.5AC Timing Waveforms (30)4.6Power Sequence (32)4.7Reset Timing (34)4.8AC Test Conditions (34)4.9Typical Power Dissipation (35)Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureFigures1Intel® 80200 Processor Block Diagram (6)2241-Lead PBGA Package (17)3Case Temperature with No Air Flow (23)4Case Temperature at Nominal Power Dissipation (23)5V CCA Lowpass Filter (25)6CLK Waveform (30)7MCLK Waveform (30)8T OV Output Delay Waveform (31)9Correct Power Sequence for V CC, V CCP (32)10Another Correct Power Sequence for V CC, V CCP (32)11Incorrect Power Sequence for V CC, V CCP (32)12Preferred Power Sequence for VCC, VCCa (33)13Correct Power Sequence for VCC, VCCa (33)14Pins’ State at Reset (34)15AC Test Load (34)16Typical Pin Power Dissipation (35)17Typical Core Power Dissipation (35)Tables1Related Documentation (5)2Pin Description Nomenclature (13)4Signal Pin Description (14)3Power Pins (14)5JTAG Pins (16)6241-Lead PBGA Pinout — Ballpad Number Order (18)7241-Lead PBGA Pinout — Signal Name Order (20)8Package Thermal Resistance — °C/Watt (22)9Operating Conditions (24)10Voltage Range Requirements for Intel® 80200 Processor Product Options (24)11DC Characteristics (26)12I CC Characteristics (26)13Input Clock Timings (27)14Output Timings (28)15Input Timings (28)16Boundary Scan Test Signal Timings (29)Intel ® 80200 Processor based on Intel ® XScale ™ MicroarchitectureAbout this Document1.0About this DocumentThis is the Advance Information data sheet for the Intel ® 80200 processor based on Intel ® XScale ™ microarchitecture (ARM* architecture compliant). This data sheet contains a functional overview, mechanical data (package signal locations and simulated thermal characteristics), targeted electrical specifications (simulated), and bus functional waveforms. Detailed functional descriptions other than parametric performance is published in the Intel ® 80200 Processor based on Intel ® XScale ™ Microarchitecture Developer’s Manual .2.0Functional OverviewThe Intel ® 80200 processor technology is compliant with the ARM* Version 5TE instruction set architecture (ISA). The Intel ® 80200 processor is designed with Intel state-of-the-art 0.18micron production semiconductor process technology. This process technology, along with thecompactness of the ARM RISC ISA, enables the Intel ® 80200 processor to operate over a wide speed/power range, producing industry-leading mW/MIPS performance.•7-8 stage Superpipeline promotes high speed, efficient core performance•128-entry Branch Target Buffer keeps pipeline filled with statistically correct branch choices •32-entry Instruction Memory Management Unit for logical-to-physical address translation, access permissions, I-Cache attributes•32-entry Data Memory Management Unit for logical-to-physical address translation, access permissions, D-Cache attributes•32KB Instruction Cache can hold entire programs, preventing core stalls caused by multicyclememory accesses •32KB Data Cache reduces core stalls caused by multicycle memory accesses•2KB Minidata Cache for frequently changing data streams avoids “thrashing” of the D-Cache •4-entry Fill and Pend Buffers promote core efficiency by allowing “hit-under- miss” operation with Data Caches•Power Management Unit gives power savings via idle, and sleep modes•8-entry Write Buffer allows the core to continue execution while data is written to memory •Multiply-Accumulate Coprocessor can do two simultaneous 16-bit SIMD multiplies with 40-bit accumulation for efficient, high quality audioTable 1. Related Documentation Document Title Document #Intel ® 80200 Processor based on Intel ® XScale ™ Microarchitecture Developer ’s Manual 273411Intel ® 80200 Processor based on Intel ® XScale ™ Microarchitecture Specification Update 273415Intel ® 80310 I/O Processor Chipset Design Guide 273354Intel ® 80312 I/O Companion Chip Developer ’s Manual 273410Intel ® 80312 I/O Companion Chip Datasheet 273425Intel ® 80312 I/O Companion Chip Specification Update273416Intel® 80200 Processor based on Intel® XScale™ Microarchitecture ArrayFunctional Overview•Performance Monitoring Unit furnishes two 32-bit event counters and one 32-bit cycle counter for analysis of hit rates, etc.•JTAG Debug Unit uses Hardware Breakpoints and 256-entry Trace History Buffer (for flow change messages) to debug programs•Dynamic clocking allows optimized performanceFigure 1. Intel® 80200 Processor Block DiagramIntel® 80200 Processor based on Intel® XScale™ MicroarchitectureFunctional Overview2.1SuperpipelineThe Superpipeline is composed of Integer, Multiply-Accumulate (MAC), and memory pipes.The Integer pipe has seven stages:•Branch Target Buffer (BTB)/Fetch 1•Fetch 2•Decode•Register File/Shift•ALU Execute•State Execute•Integer WritebackThe Memory pipe has eight stages:•the first five stages of the Integer pipe (BTB/Fetch 1 through ALU Execute). . . then finish with Memory stages:•Data Cache 1•Data Cache 2•Data Cache WritebackThe MAC pipe has six to nine stages:•the first four stages of the Integer pipe (BTB/Fetch 1 through Register File/ Shift). . . then finish with MAC stages:•MAC1•MAC2•MAC3•MAC4•Register WritebackThe MAC pipe supports a data-dependent early terminate where stages MAC2, MAC3, and/orMAC4 are by-passed.Deep pipes promote high instruction execution rates only when a means exists to successfullypredict the outcome of branch instructions. The Branch Target Buffer provides such a means.Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureFunctional Overview2.2Branch Target Buffer (BTB)Each entry of the 128-entry BTB contains the address of a branch instruction, the target addressassociated with the branch instruction, and a previous history of the branch being taken or nottaken. The history is recorded as one of four states: strongly taken, weakly taken, weakly not-taken,or strongly not-taken. The BTB can be enabled or disabled via coprocessor 15, register 1.When the address of the branch instruction hits in the BTB and its history is strongly or weaklytaken, the instruction at the branch target address is fetched; when its history is strongly or weaklynot-taken, the next sequential instruction is fetched. In either case the history is updated.Data associated with a branch instruction enters the BTB the first time the branch is taken. Thisdata enters the BTB in a slot with a history of strongly not-taken (overwriting previous data whenpresent).Successfully predicted branches avoid any branch-latency penalties in the superpipeline.Unsuccessfully predicted branches result in a 4-5 cycle branch-latency penalty in the superpipeline.2.3Instruction Memory Management Unit (IMMU)For instruction prefetches the IMMU controls logical-to-physical address translation, memoryaccess permissions, memory domain identifications, and attributes (governing operation of theinstruction cache). The IMMU contains a 32-entry, fully associative Instruction TranslationLook-A-Side Buffer (ITLB) that has a round-robin replacement policy. ITLB entries 0-30 can belocked.When an instruction prefetch misses in the ITLB, the IMMU invokes an automatic table-walkmechanism that fetches an associated descriptor from memory and loads it into the ITLB. Thedescriptor contains information for logical-to-physical address translation, memory accesspermissions, memory domain identifications, and attributes governing operation of the i-cache.The IMMU then continues the instruction prefetch by using the address translation just entered intothe ITLB. When an instruction prefetch hits in the ITLB, the IMMU continues the prefetch usingthe address translation already resident in the ITLB.Access permissions for each of up to sixteen memory domains can be programmed. When aninstruction prefetch is attempted to an area of memory in violation of access permissions, then theattempt is aborted and a prefetch abort is sent to the core for exception processing. The IMMU andDMMU can be enabled or disabled together.Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureFunctional Overview2.4Data Memory Management Unit (DMMU)For data fetches, the DMMU controls logical-to-physical address translation, memory accesspermissions, memory domain identifications, and attributes (governing operation of the data cacheor mini-data cache and write buffer). The DMMU contains a 32-entry, fully associative datatranslation look-a-side buffer (DTLB) that has a round-robin replacement policy. DTLB entries0-30 can be locked.When a data fetch misses in the DTLB, the DMMU invokes an automatic table-walk mechanismthat fetches an associated descriptor from memory and loads it into the DTLB. The descriptorcontains information for logical-to-physical address translation, memory access permissions,memory domain identifications, and attributes (governing operation of the d-cache or mini-datacache and write buffer). The DMMU then continues the data fetch by using the address translationjust entered into the DTLB. When a data fetch hits in the DTLB, the DMMU continues the fetchusing the address translation already resident in the DTLB.Access permissions for each of up to sixteen memory domains can be programmed. When a datafetch is attempted to an area of memory in violation of access permissions, then the attempt isaborted and a data abort is sent to the core for exception processing. The IMMU and DMMU canbe enable or disable together.2.5Instruction Cache (I-Cache)The I-Cache can contain high-use multiple code segments or entire programs, allowing the coreaccess to instructions at core frequencies. This prevents core stalls caused by multicycle accesses toexternal memory.The 32KByte i-cache is 32-set/32-way associative, where each set contains 32-ways and each waycontains a tag address, a cache line (eight 32-bit words and one parity bit per word) of instructions,and a line-valid bit. For each of the 32sets, 0-28ways can be locked. Unlocked ways arereplaceable via a round robin policy.The i-cache can be enabled or disabled. Attribute bits within the descriptors contained in the ITLBof the IMMU provide some control over an enabled i-cache.When a needed line (eight 32-bit words) is not present in the i-cache, the line is fetched (criticalword first) from memory via a two-level-deep fetch queue.Intel® 80200 Processor based on Intel® XScale™ MicroarchitectureFunctional Overview2.6Data Cache (D-Cache)The D-Cache can contain high-use data such as lookup tables and filter coefficients, allowing thecore access to data at core frequencies. This prevents core stalls caused by multicycle accesses toexternal memory.The 32KByte d-cache is 32-set/32-way associative, where each set contains 32-ways and eachway contains a tag address, a cache line (32bytes with one parity bit per byte) of data, two dirtybits (one for each of two 8-byte groupings in a line), and one valid bit. For each of the 32sets,0-28ways can be locked, unlocked, or used as local SRAM. Unlocked ways are replaceable via around robin policy.The d-cache (together with the mini-data cache) can be enabled or disabled. Attribute bits withinthe descriptors contained in the DTLB of the DMMU provide significant control over an enabledd-cache. These bits specify cache operating modes such as read and write allocate, write-back,write-through, and d-cache versus mini-data cache targetingThe d-cache (and mini-data cache) work with the load buffer and pend buffer to provide“hit-under- miss” capability that allows the core to access other data in the cache after a “miss” isencountered (see Section 2.8, “Fill Buffer (FB) and Pend Buffer (PB)” on page11 for moreinformation). The d-cache (and mini-data cache) works in conjunction with the write buffer fordata that is to be stored to memory (see Section 2.9, “Write Buffer (WB)” on page11 for moreinformation).2.7Mini-Data CacheThe Mini-data Cache can contain frequently changing data streams such as MPEG video, allowingthe core access to data streams at core frequencies. This prevents core stalls caused by multicycleaccesses to external memory. The mini-data cache relieves the d-cache of data “thrashing” causedby frequently changing data streams.The 2KByte mini-data cache is 32-set/2-way associative, where each set contains 2-ways and eachway contains a tag address, a cache line (32 bytes with one parity bit per byte) of data, two dirtybits (one for each of two 8-byte groupings in a line), and a valid bit. The mini-data cache uses around robin replacement policy, and cannot be locked.The mini-data cache (together with the d-cache) can be enabled or disabled. Attribute bitscontained within a coprocessor register specify operating modes write and/or read allocate,write-back, and write-through.The mini-data cache (and d-cache) work with the load buffer and pend buffer to provide“hit-under-miss” capability that allows the core to access other data in the cache after a “miss” isencountered (see Section 2.8, “Fill Buffer (FB) and Pend Buffer (PB)” on page11 for moreinformation). The mini-data cache (and d-cache) works in conjunction with the write buffer fordata that is to be stored to memory (see Section 2.9, “Write Buffer (WB)” on page11 for moreinformation).Functional Overview2.8Fill Buffer (FB) and Pend Buffer (PB)The 4-entry Fill Buffer works with the core to hold loads until the bus controller can act on them.The FB and the 4-entry Pend Buffer work with the d-cache and mini-data cache to provide“hit-under-miss” capability, allowing the core to seek other data in the caches while “miss” data isbeing fetched from memory. The FB can contain up to four unique “miss” addresses (logical),allowing four “misses” before the core is stalled. The PB holds up to four addresses (logical) foradditional “misses” to those addresses that are already in the FB. A coprocessor register canspecify draining of the Fill and Pend (Write) Buffers.2.9Write Buffer (WB)The Write Buffer holds data for storage to memory until the bus controller can act on it. The WB is8-entries deep, where each entry holds 16bytes. The WB is constantly enabled, and accepts datafrom the core, d-cache, or mini-data cache.Coprocessor 15, register 1 specifies whether WB coalescing is enabled or disabled. Whencoalescing is disabled, stores to memory occur in program order regardless of the attribute bitswithin the descriptors located in the DTLB. When coalescing is enabled, the attribute bits withinthe descriptors located in the DTLB are examined to determine when coalescing is enabled for thedestination region of memory. When coalescing is enabled in both CP15, R1 and the DTLB, thendata entering the WB can coalesce with any of the 8-entries (16bytes) and then be stored to thedestination memory region, but possibly out of program order.Stores to a memory region specified to be non-cacheable and non-bufferable by the attribute bitswithin the descriptors located in the DTLB causes the Core to stall until the store completes. Acoprocessor register can specify draining of the write buffer.2.10Multiply-Accumulate Coprocessor (CP0)For efficient processing of high-quality audio algorithms, CP0 provides 40-bit accumulation of16x16, dual-16x16 (SIMD), and 32x32 signed multiplies. Special MAR and MRA instructions areimplemented to Move 40-bit Accumulator to Two Core General Registers (MAR) and Move TwoCore General Registers to 40-bit Accumulator (MRA). The 40-bit accumulator can be stored orloaded to or from d-cache, mini-data cache, or memory using two STC or LDC instructions.16x16 signed multiply-accumulates (MIAxy) multiply either the high/high, low/low, high/low, orlow/high 16bits of a 32-bit core general register (multiplier) and another 32-bit core generalregister (multiplicand) to produce a full 32-bit product which is sign-extended to 40bits and thenadded to the 40-bit accumulator.Dual signed 16x16 (SIMD) multiply-accumulates (MIAPH) multiply the high/high and low/low16-bits of a packed 32-bit core general register (multiplier) and another packed 32-bit core generalregister (multiplicand) to produce two 16-bits products which are both sign-extended to 40bits andthen both added to the 40-bit accumulator.32x32 signed multiply-accumulates (MIA) multiply a 32-bit core general register (multiplier) andanother 32-bit core general register (multiplicand) to produce a 64-bit product where the 40LSBsare added to the 40-bit accumulator. 16x32 versions of the multiply-accumulate instructionscomplete in a single cycle.Functional Overview2.11Clock and Power ManagementThe Intel® 80200 processor was designed with power saving techniques that power-up a functionalblock only when it is needed. Low power modes are selectable by programming CP 14, register 6.The Intel® 80200 processor was designed to allow dynamic clocking. The core clock frequency isset by programming CP14, Register7. This enables software to conserve power by matching thecore clock frequency to the current workload.2.12Performance Monitoring Unit (PMU)The Performance Monitoring Unit contains two 32-bit event counters and one 32-bit clock counter.The event counters can be programmed to monitor i-cache hit rate, data caches hit rate, ITLB hitrate, DTLB hit rate, pipeline stalls, BTB prediction hit rate, and instruction execution count. 2.13Debug UnitThe Debug Unit is accessed through the JTAG port. The industry-standard IEEE1149.1 JTAG portconsists of a Test Access Port (TAP) controller, Boundary-Scan register, instruction and dataregisters, and dedicated signals TDI, TDO, TCK, TMS, and TRST#. The debug unit, when usedwith debugger application code running on a host system outside of the Intel® 80200 processor,allows a program running on the Intel® 80200 processor to be debugged. It allows the debuggerapplication code or a debug exception to stop program execution and re-direct execution to a debughandling routine. Debug exceptions are instruction breakpoint, data breakpoint, softwarebreakpoint, external debug breakpoint, exception vector trap, and trace buffer full breakpoint. Onceexecution has stopped, the debugger application code can examine or modify the core’s state,co-processor state, or memory. The debugger application code can then restart program execution.The debug unit has two hardware instruction breakpoint registers, two hardware data breakpointregisters, and a hardware data breakpoint control register. The second data breakpoint register canbe alternatively used as a mask register for the first data breakpoint register. A 256-entry tracebuffer provides the ability to capture control flow messages or addresses. A JTAG instruction(LDIC) can be used to download a debug handler via the JTAG port to the mini-instruction cache(the i-cache has a 2KByte mini-instruction cache, like the mini-data cache, that is used only tohold a debug handler).2.14Extended Temperature (80200T)The 80200T processor (based on the high-performance, ultra-low power Intel Xscale™technology) operates at speeds up to 733MHz while consuming less than 1.3w and can operate attemperatures ranging from -40 to +85 degrees Celsius.The 80200T is functionally identical to the commercial temperature 80200 processor. Allinformation in this datasheet applies to the 80200T unless otherwise noted. See the 80200Specification Update for more information.Package Information 3.0Package Information3.1Package IntroductionThe Intel® 80200 processor is offered in a Plastic Ball Grid Array (PBGA) package. See Figure 2“241-Lead PBGA Package” on page17.3.1.1Functional Signal DefinitionsThis section defines the pins and signals in the following tables:•Table2 “Pin Description Nomenclature” on page13•Table3 “Power Pins” on page14•Table4 “Signal Pin Description” on page14•Table5 “JTAG Pins” on page163.1.1.1Signal Pin DescriptionsTable 2. Pin Description NomenclatureSymbol DescriptionI Input pin onlyO Output pin onlyI/O Pin can be either an input or output-Pin must be connected as describedN/C NO CONNECT. Do not make electrical connections to these balls.Rst(...)While the RESETOUT# pin is asserted, the pin:•Rst(1) Is driven to Vcc•Rst(0) Is driven to Vss•Rst(X) Is driven to unspecified state (1 or 0, buses may contain a mix of 1 and 0 signals)•Rst(H) Is pulled up to Vcc•Rst(L) Is pulled down to Vss•Rst(Z) Floats•Rst(Q) Is a valid outputSince RESET# is asynchronous, these are asynchronous events.Hld(...)While the Intel® 80200 processor is in HOLD mode (HOLD asserted and took effect), the pin:•Hld(Z) Floats•Hld(Q) is a valid output•Hld(1) is driven to VccNote: When both HLDA and RESETOUT# are asserted, then HOLD mode takes priority; theoutput pins assume the state specified by Hld(...). The HOLD pin is also honored during Idleand Sleep modes; the output pins assume the state specified by Hld(...).Slp(...)While the Intel® 80200 processor is in Idle or Sleep mode (software selected), pin:•Slp(1) Is driven to Vcc•Slp(0) Is driven to Vss•Slp(X) Is driven to unspecified state•Slp(Q) Is a valid outputPackage InformationTable 3. Power PinsName Count DescriptionV CC17Positive supply for the core.V SS70Ground.V CCP25Positive supply for the I/O pins.V CCA1Positive supply for the analog circuitry (PLL).Table 4. Signal Pin Description (Sheet 1 of 2)Name Count Type DescriptionA[15:0]16ORst(X)Hld(Z)Slp(X)Address Bus: Conveys either the upper or lower half of a 32-bitaddress during the issue phase of a bus transaction.ABORT 1I Abort Transaction: When asserted during the data phase of atransaction, this signal causes the remainder of that transaction tobe aborted.ADS#/LEN[2]1ORst(1)Hld(Z)Slp(1)Address Strobe/Length:During the first cycle of the issue phase, this signal indicates thestart of a bus request.During the second cycle of the issue phase, this signal is the MSBof a value which indicates the length of the transaction.BE[7:0]#8ORst(Z)Hld(Q)1Slp(Z)Byte Enable: Signifies which bytes are valid during a writetransaction. When not in use, this bus is floated (Z).CLK1I CLK: Clock input for the core logic.CWF/ DBusWidth (Config. Pin)1I Critical Word First: When active during a data read transaction, CWF informs the core of the data wrap order.DBusWidth: While RESET# is asserted, this pin is sampled by theIntel® 80200 processor to determine when the data bus is to beconfigured as 32-bits or 64-bits. When the pin is sampled as ‘0’during reset, the 80200 assumes a 64-bit bus. When the pin is ‘1’ atreset, a 32-bit bus is assumed.D[63:0]64I/ORst(Z)Hld(Q)1Slp(Z)Data Bus: Carries data to/from the processor during a bustransaction. When not in use, this bus is floated (Z).DCB[7:0]8I/ORst(Z)Hld(Q)1Slp(Z)Data Check Byte: Carries the optional ECC information associatedwith the data on the Data bus. When not in use, this bus is floated(Z).DVALID1I Data Valid: Asserted when the Data bus carries valid data.FIQ#1I Fast Interrupt Request: When FIQs are enabled, the processor responds to a low level on this input by taking the FIQ interruptexception.HLDA 1ORst(0)Hld(1)Slp(0)HLDA: This output is asserted when the 80200 has floated theshared bus signals in response to HOLD.。

编辑：GGASEMI肖特基二极管的型号众多，接下来所列型号主要以电流电压大小，分为大类，再以封装区分作为辅助分类。

ASEMI肖特基二极管型号大全，找找MBR4045PT属于哪一类1A~5A 20V~150V 肖特基二极管两者型号都在用SS封装：SS110 、SS14 。

10A 45V~200V 肖特基二极管采用TO-220AC封装的有：MBR10200AC、MBR10150AC、MBR10100AC、MBR1060AC、MBR1045AC、MBR1040AC采用TO-220封装的有：MBR1040FCT、MBR10200FCT、MBR10100FCT、MBR10150FCT、 MBR1040CT、MBR10200CT、MBR1040FCT、MBT1045FCT、 MBR1045CT、MBR1040CT、 MBR1045CT、MBR1060CT、MBR1060FCT、MBR10100CT、MBT10100FCT、MBR10150CT该封装有FCT和CT结尾的型号命名，区别于前者是塑封封装、后者是铁头封装。

采用TO-251封装的有：BD1045CT、BD1060CT、BD10100CT、BD10150CT、BD10200CT、BD1040CT采用TO-252封装的有：BD1040CS、BD1045CS、BD1060CS、BD10100CS、BD10150CS、 BD10200CS 采用TO-263封装的有：MBR10200DC、MBR1040DC、MBR1045DC、MBR1060DC、MBR10100DC、MBR10150DC20A 45V~200V肖特基二极管采用TO-220AC封装的有：MBR20200AC、MBR20150AC、MBR20100AC、MBR2060AC、 MR2045AC采用TO-251封装的有：BD2060CT、BD2045CT、BD20100CT、BD20150CT、BD20200CT、采用TO-252封装的有：BD20100CS、BD20150CS、BD20200CS、BD2045CS、BD2060CS采用TO-263封装的有：MBR2045DC、MBR2060DC、MBR20100DC、MBR20150DC、MBR20200DC采用TO-220封装的有：MBR2045CT、MBR2045FCT、MBR20200FCT、MBR2060CT、 MBR20100FCT、MBR2060FCT、MBR20100CT、MBR20100FCT、 MBR20150CT、MBR20150FCT、MBR20200CT、MBR20200FCT采用TO-247/3封装的有：MBR20200PT30A 45V~200V 肖特基二极管采用TO-247/3P封装的有：MBR3045PT、MBR3060PT、MBR30100PT、MBR30150PT、MBR30200PT采用TO-263封装的有：MBR30200DC、MBR3060DC、MBR30100DC、MBR30150DC、MBR3045DC采用TO-220封装的有：MBR3045CT、MBR3045FCT、MBR3060CT、MBR3060FCT、MBR30100CT、MBT30100FCT、MBR30150CT、MBR30150FCT、 MBR30200CT、MBR30200FCT 40A 45V~200V 肖特基二极管采用TO-263封装的有：MBR4045DC、MBR40200DC、MBR4060DC、MBR40100DC、MBR40150DC采用TO-247/3P封装的有：MBR40200PT、MBR4045PT、MBR4060PT、MBR40100PT、 MBR40150PT、采用TO-220封装的有：MBR4045FCT、MBR4045CT、MBR4060FCT、MB40100FCT、 MBR4060CT、MBR40100CT60A 45V~220V 肖特基二极管采用TO-247/3P封装的有：MBR6045PT、MBR6060PT、MBR60100PT、MBR60150PT、 MBR60200PT 10A~60A 20V~100V 肖特基二极管采用ITO-220AB封装的有：SBT10150UCT、SBT10100UCT、SBT1060UCT、SBT1045UCT、SBT10150VCT、SBT10100VCT、SBT1060VCT、SBT1045VCT、SBT30150UCT、SBT2045VCT、SBT2060VCT、SBT20100VCT、SBT20150VCT、SBT2045UCT、 SBT2060UCT、SBT20100UCT、 SBT20150UCT、SBT3045VCT、SBT3060VCT、SBT30100VCT、 SBT30150VCT、SBT3045UCT、SBT3060UCT、SBT30100UCT、SBT1045UFCT、SBT30100UFCT、SBT1060UFCT、SBT10150VFCT、SBT10100VFCT、SBT1060VFCT、SBT1045VFCT、SBT10100UFCT、SBT2045VFCT、SBT10150UFCT、 SBT2060VFCT、SBT20100VFCT、SBT20150VFCT、SBT2045UFCT、SBT2060UFCT、SBT20100UFCT、SBT20150UFCT、SBT3045VFCT、SBT3060VFCT、SBT30100VFCT、 SBT30150VFCT、SBT3045UFCT、SBT3060UFCT、SBT30150UFCT、SBT1045UFCT、 SB10100LCT、SB10150LCT、SB1045LFCT、SB1045LFCT、SB30100LFCT、 SB1060LFCT、SB30150LFCT、SB10100LFCT、SB2045LFCT、SB10150LFCT、SB2060LFCT、SB20100LFCT、SB3060LCT采用TO-220AB封装的有：SB1060LCT、SB30150LCT、SB30150LCT、SB10100LCT、SB2060LCT、SB10150LCT、SB20150LCT、SB3060LCT、SB30100LCT、SB1045LCT采用TO-277封装的有：10V45这款肖特基二极管型号是超低压降、贴片小封装的。

Document Number: 93445For technical questions, contact: diodes-tech@Schottky Rectifier, 2 x 10 AMBRB20...CTG, MBR20...CTG-1Vishay High Power ProductsFEATURES•150 °C T J operation•Center tap D 2PAK and TO-262 packages •Low forward voltage drop•High purity, high temperature epoxy encapsulation for enhanced mechanical strength and moisture resistance •High frequency operation•Guard ring enhanced ruggedness and long term reliability •Designed and qualified for AEC Q101 levelDESCRIPTIONThis center tap Schottky rectifier has been optimized for low reverse leakage at high temperature. The proprietary barrier technology allows for reliable operation up to 150 °C junction temperature. Typical applications are in switching power supplies, converters, freewheeling diodes, and reverse battery protection.PRODUCT SUMMARYI F(AV) 2 x 10 A V R80 to 100 VBase common cathodeBase common cathode2MAJOR RATINGS AND CHARACTERISTICSSYMBOL CHARACTERISTICS VALUESUNITS I FRM T C = 133 °C (per leg)20A V RRM 80 to 100V I FSM t p = 5 µs sine 850A V F 10 Apk, T J = 125 °C 0.70V T JRange- 65 to 150°CVOLTAGE RATINGSPARAMETERSYMBOLMBRB2080CTG MBR2080CTG-1MBRB2090CTG MBR2090CTG-1MBRB20100CTG MBR20100CTG-1UNITS Maximum DC reverse voltageV R 8090100VMaximum working peak reverse voltageV RWM元器件交易网For technical questions, contact: diodes-tech@Document Number: 93445MBRB20...CTG, MBR20...CTG-1Vishay High Power ProductsSchottky Rectifier,2 x 10 ANote(1)Pulse width < 300 µs, duty cycle < 2 %ABSOLUTE MAXIMUM RATINGSPARAMETER SYMBOL TEST CONDITIONSVALUES UNITSMaximum average forward currentper leg I F(AV)T C = 133 °C, rated V R10A per device20Peak repetitive forward current per legI FRMRated V R , square wave, 20 kHzT C = 133 °C 20Non-repetitive peak surge currentI FSM5 µs sine or 3 µs rect. pulseFollowing any rated load condition and with rated V RRM applied850Surge applied at rated load conditions half wave,single phase, 60 Hz 150Peak repetitive reverse surge current I RRM 2.0 µs, 1.0 kHz0.5Non-repetitive avalanche energy per legE AST J = 25 °C, I AS = 2 A, L = 12 mH24mJ ELECTRICAL SPECIFICATIONSPARAMETER SYMBOLTEST CONDITIONSVALUES UNITSMaximum forward voltage dropV FM (1)10 AT J = 25 °C 0.80V 20 A 0.9510 A T J = 125 °C 0.7020 A0.85Maximum instantaneous reverse current I RM (1)T J = 25 °C Rated DC voltage0.10mA T J = 125 °C 6Threshold voltage V F(TO)T J = T J maximum0.433V Forward slope resistance r t 15.8m ΩMaximum junction capacitance C T V R = 5 V DC (test signal range 100 kHz to 1 MHz) 25 °C 400pF Typical series inductance L S Measured from top of terminal to mounting plane 8.0nH Maximum voltage rate of change dV/dtRated V R10 000V/µs 元器件交易网MBRB20...CTG, MBR20...CTG-1Schottky Rectifier,2 x 10 AVishay High Power ProductsTHERMAL - MECHANICAL SPECIFICATIONSPARAMETER SYMBOL TESTCONDITIONS VALUES UNITSMaximum junction temperature range T J- 65 to 150°C Maximum storage temperature range T Stg- 65 to 175Maximum thermal resistance, junction to case per leg R thJCDC operation2.0°C/WMaximum thermal resistance,junction to ambientR thJA50Approximate weight2g 0.07oz.Mounting torqueminimumNon-lubricated threads6 (5)kgf · cm(lbf · in) maximum12 (10)Marking device Case style D2PAKMBRB2080CTGMBRB2090CTGMBRB20100CTG Case style TO-262MBR2080CTG-1MBR2090CTG-1MBR20100CTG-1元器件交易网Document Number: 93445For technical questions, contact: diodes-tech@ MBRB20...CTG, MBR20...CTG-1Vishay High Power Products Schottky Rectifier,2 x 10 AFig. 1 - Maximum Forward Voltage Drop Characteristics(Per Leg)Fig. 2 - Typical Values of Reverse Current vs.Reverse Voltage (Per Leg)Fig. 3 - Typical Junction Capacitance vs.Reverse Voltage (Per Leg)thJC元器件交易网 For technical questions, contact: diodes-tech@ Document Number: 93445Document Number: 93445For technical questions, contact: diodes-tech@MBRB20...CTG, MBR20...CTG-1Schottky Rectifier,2 x 10 AVishay High Power ProductsFig. 5 - Maximum Allowable Case Temperature vs. Average Forward Current (Per Leg)Fig. 6 - Forward Power Loss Characteristics(Per Leg)Fig. 7 - Maximum Non-Repetitive Surge Current (Per Leg)Note(1)Formula used: T C = T J - (Pd + Pd REV ) x R thJC ;Pd = Forward power loss = I F(AV) x V FM at (I F(AV)/D) (see fig. 6);Pd REV = Inverse power loss = V R1 x I R (1 - D); I R at V R1 = Rated V R元器件交易网元器件交易网MBRB20...CTG, MBR20...CTG-1Vishay High Power Products Schottky Rectifier,2 x 10 AORDERING INFORMATION TABLELINKS TO RELATED DOCUMENTSDimensions /doc?95014Part marking information /doc?95057Packaging information /doc?95032 For technical questions, contact: diodes-tech@ Document Number: 93445Disclaimer Legal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.元器件交易网Document Number: 。

MBR20H100CT , MBRF20H100CT & MBRB20H100CT SeriesVishay Semiconductorsformerly General SemiconductorDocument Number New ProductCase:JEDEC TO-220AB, ITO-220AB, TO-263AB & TO-262AA molded plastic bodyTerminals:Plated leads, solderable per MIL-STD-750, Method 2026High temperature soldering guaranteed:250°C/10 seconds, 0.25" (6.35mm) from case (TO-220AB,ITO-220AB & TO-252AA) at terminals (TO-236AB)Polarity:As marked Mounting Position: Any Mounting Torque:10 in-lbs maximum Weight:0.08 oz., 2.24 g• Plastic package has Underwriters Laboratory Flammability Classification 94V-0• Dual rectifier construction, positive center tap • Metal silicon junction, majority carrier conduction • Low power loss, high efficiency• Guardring for overvoltage protection• For use in low voltage, high frequency inverters, free wheeling, and polarity protection applicationsMBR20H100CT , MBRF20H100CT & MBRB20H100CT SeriesVishay Semiconductorsformerly General Semiconductor Document Number 88673Maximum Ratings (TC= 25°C unless otherwise noted)ParameterSymbol MBR20H90CTMBR20H100CTUnit Maximum repetitive peak reverse voltage V RRM 90100V Working peak reverse voltage V RWM 90100V Maximum DC blocking voltageV DC90100V Maximum average forward rectified current Total device20Per legI F(AV)10A Peak forward surge current8.3ms single half sine-wave superimposed I FSM 250A on rated load (JEDEC Method) per legPeak repetitive reverse current per leg at t p = 2µs, 1KH Z I RRM 1.0A Voltage rate of change (rated V R )dv/dt 10,000V/µs Operating junction and storage temperature range T J , T STG –65 to +175°C RMS Isolation voltage (MBRF type only) from terminals 4500(1)to heatsink with t = 1 second, RH ≤30%V ISOL3500(2)V1500 (3)Electrical Characteristics (TC= 25°C unless otherwise noted)ParameterSymbolValue UnitMaximum instantaneous I F = 10A,T C = 25°C 0.77forward voltage per leg at (4):I F = 10A,T C = 125°C 0.64I F = 20A,T C = 25°C V F 0.88V I F = 20A,T C = 125°C 0.73Maximum reverse current per leg T J = 25°C 4.5µA at working peak reverse voltageT J = 125°CI R6.0mAThermal Characteristics (TC= 25°C unless otherwise noted)ParameterSymbol MBR MBRF MBRB Unit Typical thermal resistance per legR ΘJC2.05.82.0°C/WNotes:(1) Clip mounting (on case), where lead does not overlap heatsink with 0.110” offset (2) Clip mounting (on case), where leads do overlap heatsink(3) Screw mounting with 4-40 screw, where washer diameter is ≤ 4.9 mm (0.19”)(4) Pulse test: 300µs pulse width, 1% duty cycleOrdering InformationProductCase Package CodePackage OptionMBR20H90CT - MBR20H100CT TO-220AB 45Anti-Static tube, 50/tube, 2K/carton MBRF20H90CT - MBRF20H100CT ITO-220AB 45Anti-Static tube, 50/tube, 2K/carton 3113” reel, 800/reel, 4.8K/cartonMBRB20H90CT - MBRB20H100CTTO-263AB45Anti-Static tube, 50/tube, 2K/carton81Anti-Static 13” reel, 800/reel, 4.8K/cartonMBR20H100CT , MBRF20H100CT & MBRB20H100CT SeriesVishay Semiconductorsformerly General SemiconductorDocument Number Ratings andCharacteristic Curves per leg (TA= 25°C unless otherwise noted)481220160.11101001000Fig. 1 — Forward Current Derating CurveFig. 2 — Maximum Non-Repetitive PeakForward Surge Current Per Leg0.010.1110。

MBR2535CT - MBR2560CTMBR2535CT - MBR2560CT, Rev. A©1999 Fairchild Semiconductor CorporationMBR2535CT - MBR2560CT, Rev. ATRADEMARKSACEx™CoolFET™CROSSVOLT™E 2CMOS TM FACT™FACT Quiet Series™FAST ®FASTr™GTO™HiSeC™The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.As used herein:ISOPLANAR™MICROWIRE™POP™PowerTrench™QS™Quiet Series™SuperSOT™-3SuperSOT™-6SuperSOT™-8TinyLogic™1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant intothe body, or (b) support or sustain life, or (c) whosefailure to perform when properly used in accordancewith instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.2. A critical component is any component of a lifesupport device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.PRODUCT STATUS DEFINITIONS Definition of TermsDatasheet Identification Product Status Definition Advance InformationPreliminary No Identification Needed Obsolete This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.This datasheet contains preliminary data, andsupplementary data will be published at a later date.Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only.Formative or In DesignFirst ProductionFull ProductionNot In ProductionDISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY , FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.。