Three-stage burst-mode transimpedance amplifier in deep-sub-_spl mu_m CMOS technology

Multi-Tap Photonic Microwave Filter Based on Two-PumpFiber Optical Parametric AmplifierJia Li, Kim K. Y. Cheung, Xing Xu, and Kenneth K. Y. Wong*Photonic Systems Research Laboratory, Department of Electrical and Electronic Engineering,The University of Hong Kong, Pokfulam Road, Hong Kong*Email: kywong@eee.hku.hkAbstract: A multi-tap photonic microwave filter based on two-pump fiber optical parametricamplifier (OPA) is proposed and an 8-tap filter is experimentally demonstrated. Tunability of thefilter is also investigated in the paper, which shows consistency between experimental andtheoretical results.©2009 Optical Society of AmericaOCIS codes: (190.4970) parametric oscillators and amplifiers; (060.5625) radio frequency photonics1. IntroductionPhotonic microwave filter attracts more interests recently in the broadband wireless access networks as well as radar and photonic beamsteering of phased-arrayed antennas because of its inherent advantages such as low loss, high bandwidth, immunity to electromagnetic interference (EMI) compared to the ordinary microwave filters [1].Basically, photonic microwave filters are implemented based on delay-line structure where multiple laser sources are usually used in order to achieve a linear relationship between the input and output radio-frequency (RF) signal and to enhance the Q-factor of the filter. Several approaches have been proposed [2-4]. However, in these approaches the number of laser sources required equals to the number of filter taps, which increases the cost of the system if multi-tap filter is implemented. Recently, a one-pump fiber OPA based photonic microwave filter is demonstrated which can reduce the number of laser sources, but requires a complex delay-line structure [5]. In this paper, we propose a novel method of using two-pump OPA to construct photonic microwave filter which has a much simpler delay-line structure providing flexible tuning ability, and to reduce the laser sources by almost half.2. PrincipleThe principle of two-pump OPA based photonic microwave filter is shown in Fig. 1 (a). Two strong continuous-wave (CW) pumps propagate along a spool of nonlinear fiber. The center wavelength of the two pumps is located around the zero-dispersion wavelength ν0 of the nonlinear fiber such that a wide range of signal wavelengths can meet the phase-matching conditions. The wavelengths and powers of the two pumps are carefully chosen to ensure the flatness of the gain spectrum [6]. Then if multiple signal wavelengths are launched into the nonlinear fiber with their wavelengths in the gain region, the pumps will transfer part of their energy to the signals and at the same time to generate another set of wavelengths which are called idlers as shown in Fig. 1 (b). The wavelengths of the signals and idlers are symmetric with respect to the center of the two pumps in terms of frequency. So it is possible to obtain the signals and idlers with equally-spaced wavelengths by careful selection of the signal wavelengths. Then all the signals and idlers are selected using a tunable bandpass filter (TBPF) and launched into a spool of dispersive fiber to introduce an equal amount of time delay between adjacent channels. Time-delayed optical signals are then detected and converted back into electrical signal in the photodetector (PD).fiberfiberTBPF PD Pump1Pump2Signalsp 2p 1i 4i 3i 2i 1s 1νs 2s 3s 4ν0νp : pump waves, νi : idler waves, νs : signal waves. 3. ExperimentThe experimental setup is shown in Fig. 2. Two tunable laser sources (TLSs) TLS1 and TLS2 serve as two pump waves with wavelength of 1535 nm and 1547 nm, respectively. They are then combined together using a 50/50 optical coupler (OC) and launched into a phase modulator (PM). The two pumps are phase modulated by 10-Gb/s 27-1 pseudo-random binary sequence (PRBS) to suppress stimulated Brillouin scattering (SBS). After phase dithering the two pumps are splitted into two paths by a wavelength-division multiplexing coupler (WDMC1) andamplified by two-stage erbium-doped fiber amplifiers (EDFAs) with TBPFs between them to suppress amplified spontaneous emission (ASE) noise. Each pump is amplified to a power of 22 dBm. Polarization controllers (PCs) PC7 and PC8 are used to adjust the state of polarization (SOP) of the two pumps to be orthogonal so that the cross-gain modulation (XGM) and four-wave mixing (FWM) effects can be reduced [7]. They are then combined using another WDMC2. As for the signalbranch, TLS1-4 corresponds to the four input signals. They are combined together using a 4-to-1 OC and launched into an amplitude modulator (AM). Optical power of each channel is -12 dBm before the nonlinear fiber. Then signals and pumps are combined together using a 10/90 OC. They are then launched into a spool of highly-nonlinear dispersion-shifted fiber (HNL-DSF) with the zero-dispersion wavelength of 1542 nm and the nonlinear coefficient of 10.4 W -1km -1. After parametric amplification, four signals and four idlers are selected by a bandwidth-variable tunable filter (BVF). Then they propagate along a spool of dispersion-compensating fiber (DCF) with dispersion of 850 ps/nm to introduce a relative time delay between eight channels. The frequency response of the filter is monitored by the vector network analyzer (VNA) after photodetection.Fig. 3 shows the experimental results. Firstly, the wavelengths of the four signals are set to be 1537.5 nm, 1538.5 nm, 1539.5 nm, and 1540.5nm, so the wavelength separation is 1 nm. As a result of dispersion induced time delay, the temporal separation of adjacent channels is 850 ps, corresponding to a free spectral range (FSR) of 1.18 GHz, which matches with the experimental result shown in the black solid line of Fig. 3. Then we change the wavelength separation from 1 nm to 0.8 nm and 0.6 nm, the frequency response curve is observed to shift to a higher frequency as shown in the red dashed line and blue dotted lines of Fig. 3. The FSR also changes from 1.18 GHz to 1.50 GHz and 2 GHz, respectively, which also agrees well with the theoretical value. A mainlobe-to-sidelobe ratio (MSR) of more than 10 dB is obtained in the experiment. The wavelength separation is changed by simply changing the four signals’ wavelengths without changing the other parameters of the system. So the proposed photonic microwave filter is tunable and a multi-tap configuration can be implemented using less laser sources.4. ConclusionsWe proposed and demonstrated a novel photonic microwave filter based on two-pump fiber OPA. In this scheme, only half of the laser sources are required to achieve a multi-tap operation. The filter is also tunable by simply tuning the wavelengths of the signals, which shows consistency between experimental and theoretical results.5. AcknowledgmentThe work described in this paper was partially supported by a grant from the Research Grants Council of the Hong Kong Special Administrative Region, China (Project No. HKU 7172/07E and HKU 7179/08E). The authors would also like to thank Alnair Labs for providing the BVF.6. References[1] R. A. Minasian, “Photonic signal processing of microwave signals,” IEEE Trans. Microw. Theory Tech. 54, 832-846 (2006).[2] J. Capmany, D. Pastor, and B. Ortega, “New and flexible fiber-optic delay-line filters using chirped Bragg grating and laser arrays,” IEEE Trans. Microwav. Theory Tech., 47, 1321-1326 (1999).[3] V. Polo, B. Vidal, J. L. Corral, and J. Marti, “Novel tunable photonic microwave filter based on laser arrays and N × N AWG-based delay lines,” IEEE Photon. Tech. Lett., 15, 584-586 (2003).[4] Q. Wang, and J. P. Yao, “Multitap photonic microwave filters with arbitrary positive and negative coefficients using a polarization modulator and an optical polarizer,” IEEE Photon. Technol. Lett. 20, 78-80 (2008)[5] J. Li, K. K. Y. Cheung, and K. K. Y. Wong, “Photonic microwave filter with negative coefficients using fiber optical parametric amplifier,” in Proc. OFC/NFOEC 2009, paper JWA53 (2009).[6] M. E. Marhic, Y. Park, F. S. Yang and L. G. Kazovsky, “Broadband fiber-optical parametric amplifiers and wavelength converters with low-ripple Chebyshev gain spectra,” Opt. Lett., 21, 1354-1356 (1996).[7] K. K. Y. Wong, G. W. Lu, and L. K. Chen, “Experimental studies of the WDM signal crosstalk in two-pump fiber optical parametric amplifiers,” Opt. Commun., 270, 429-432 (2007).Fig. 3 Frequency response of 8-tap filter. Black solid, red dashed, and blue dotted lines corresponds to wavelengthseparation of 1 nm, 0.8 nm, and 0.6 nm, respectively. VNA PD Fig. 2 Experimental setup for two-pump OPA-based photonicmicrowave filter. Refer to text for details.。

1、基尔霍夫定理的内容是什么？（仕兰微电子）2、平板电容公式(C=εS/4πkd)。

（未知）3、最基本的如三极管曲线特性。

（未知）4、描述反馈电路的概念，列举他们的应用。

（仕兰微电子）5、负反馈种类（电压并联反馈，电流串联反馈，电压串联反馈和电流并联反馈）；负反馈的优点（降低放大器的增益灵敏度，改变输入电阻和输出电阻，改善放大器的线性和非线性失真，有效地扩展放大器的通频带，自动调节作用）（未知）6、放大电路的频率补偿的目的是什么，有哪些方法？（仕兰微电子）7、频率响应，如：怎么才算是稳定的，如何改变频响曲线的几个方法。

（未知）8、给出一个查分运放，如何相位补偿，并画补偿后的波特图。

（凹凸）9、基本放大电路种类（电压放大器，电流放大器，互导放大器和互阻放大器），优缺点，特别是广泛采用差分结构的原因。

（未知）10、给出一差分电路，告诉其输出电压Y+和Y-,求共模分量和差模分量。

（未知）11、画差放的两个输入管。

（凹凸）12、画出由运放构成加法、减法、微分、积分运算的电路原理图。

并画出一个晶体管级的运放电路。

（仕兰微电子）13、用运算放大器组成一个10倍的放大器。

（未知）14、给出一个简单电路，让你分析输出电压的特性（就是个积分电路），并求输出端某点的 rise/fall时间。

(Infineon笔试试题) )15、电阻R和电容C串联，输入电压为R和C之间的电压，输出电压分别为C上电压和R 上电压，要求制这两种电路输入电压的频谱，判断这两种电路何为高通滤波器，何为低通滤波器。

当RC<<T时，给出输入电压波形图，绘制两种电路的输出波形图。

（未知）16、有源滤波器和无源滤波器的原理及区别?（新太硬件）17、有一时域信号S="V0sin"(2pif0t)+V1cos(2pif1t)+V2sin(2pif3t+90),当其通过低通、带通、高通滤波器后的信号表示方式。

（未知）18、选择电阻时要考虑什么？（东信笔试题）19、在CMOS电路中，要有一个单管作为开关管精确传递模拟低电平，这个单管你会用P 管还是N管，为什么？（仕兰微电子）20、给出多个mos管组成的电路求5个点的电压。

The information provided herein is believed to be reliable at press time. Stanford Microdevices assumes no responsibility for inaccuracies or omissions.Stanford Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Stanford Microdevices does not authorize or warrant any Stanford Microdevices product for use in life-support devices and/or systems.Copyright 2000 Stanford Microdevices, Inc. All worldwide rights reserved.Absolute Maximum Ratingsre t e m a r a P e u l a V t i n U t n e r r u C y l p p u S 61A m e g a t l o V e c i v e D 6V e r u t a r e p m e T g n i t a r e p O 58+o t 04-C ºr e w o P t u p n I m u m i x a M 4-m B d e g n a R e r u t a r e p m e T e g a r o t S 051+o t 04-C ºer u t a r e p m e T n o i t c n u J g n i t a r e p O 051+CºOperation of this device above any one of theseparameters may cause permanent damage.Bias Conditions should also satisfy the following expression: I D V D (max) < (T J - T OP )/R th ,j-lKey parameters, at typical operating frequencies:e c n e r ef e R ro t a n g i s e D n o i t c n u F z H M 005z H M 058z H M 0591z H M 00421b C g n i k c o l B C D F p 022F p 001F p 86F p 652b C g n i k c o l B C D F p 022F p 001F p 86F p 651d C g n i l p u o c e D F u 1F u 1F u 1F u 12d C g n i l p u o c e D F p 001F p 86F p 22F p 22ek o h c L gn i k c o l B C A Hn 86Hn 33Hn 22Hn 81Application Schematic#n i P n o i t c n u F n o i t p i r c s e D ci t a m e h c S e c i v e D 1D N G ts e b r o F .d n u o r g o t n o i t c e n n o C o t e s o l c s a (s e l o h a i v e s u e c n a m r o f r e p d a e l e c u d e r o t )e l b i s s o p s a s d a e l d n u o r g .e c n a t c u d n i 2D N G 1n i P s a e m a S 3N I F R na f o e s u e h t s e r i u q e r n i p s i h T .n i p t u p n i F R r o f n e s o h c r o t i c a p a c g n i k c o lb C D l a n r e t x e .n o i t a r e p o f o y c n e u q e r f e h t 4D N G 1n i P s a e m a S 5D N G 1n i P s a e m a S 6TU O F R eb d l u o h s s a i B .n i p s a i b d n a t u p t u o F R l a n r e t x e n a h g u o r h t n i p s i h t o t d e i l p p u s .r o t c u d n i e k o h c F R d n a r o t s i s e r s e i r e s a ,n i p s i h t n o t n e s e r p s i g n i s a i b C D e s u a c e B n i d e s u e b d l u o h s r o t i c a p a c g n i k c o l b C D no i t a c i l p p a e e s (s n o i t a c i l p p a t s o m s a i b s i h t f o e d i s y l p p u s e h T .)c i t a m e h c s .d e s s a p y b l l e w e b d l u o h s k r o w t e nd BCaution: ESD sensitiveAppropriate precautions in handling, packaging andtesting devices must be observed.Part Number Ordering Informationr e bmuNt r a P e z i S l e eR l e eR/s e c i v eD3610-AGS"70003 Package Dimensions Pad Layout Package MarkingNote: Pin 1 is on lower left when you canread package markingDIMENSIONS ARE IN INCHES [MM]。

第25卷第4期半　导　体　学　报V o l.25,N o.4　2004年4月CHIN ESE JOU R NA L O F SEM I CO N DU CT O RSA pr .,2004*电子预研资助项目(批准号:41308010402,415011005)　刘　飞　男,1974年出生,博士生,主要从事数模混合电路设计研究.　卢振庭　男,1979年出生,硕士生,研究方向为数模混合电路设计.　吉利久　男,教授,博士生导师,从事集成电路设计研究.　2003-02-10收到,2003-11-25定稿○c 2004中国电子学会带主从式T /H 电路的折叠插值A /D 转换器*刘　飞　贾　嵩　卢振庭　刘　凌　吉利久(北京大学微电子学研究所,北京　100871)摘要:提出了一种主从式T /H 电路,有效解决了折叠A DC 预处理器限制输入信号带宽的问题,使预处理电路速度及稳定性得到大幅度改善;同时该T /H 结构使用内部差分误差补偿技术,在高采样率情况下保持良好的精度,有效抑制了电荷注入、时钟馈通等问题.在1.2 m SPDM 标准数字CM O S 工艺条件下,实现6bit CM OS 折叠、电流插值A /D 转换器.仿真结果:采样频率为250M s /s 时,功耗小于300mW ,输入信号带宽约80M Hz ,输入模拟信号和二进制输出码输出之间延迟为2.5个时钟周期.关键词:A DC;CM OS;主从式T /H;折叠;电流插值EEACC :1265;1280;2570D中图分类号:T N 432 文献标识码:A 文章编号:0253-4177(2004)04-0462-061　引言目前高性能模数转换器(ADC)两大主要发展方向是高速、中低精度ADC 和低速、高精度ADC,而信号采样/保持电路是高性能ADC 中不可缺少的部件.在CMOS 数模混合电路中,高速、中低精度并行ADC 在磁盘读写驱动电路、医用图像仪器、通信设备、HDT V 等多种领域得到了广泛应用[1～3].高速并行ADC 具有高速度和最小转换延迟的优点,在高速读写、实时控制等领域具有不可替代的作用,然而它也有某些严重的缺点如功耗过大、与标准CMOS 工艺不兼容(主要指采用双极和BiCM OS 工艺的ADC )等.为符合目前So C 技术发展的需求,ADC 作为嵌入式IP 模块需要采用SPDM 的CMOS 工艺,以降低成本和增加可嵌入性.高速并行ADC 一般有两种基本结构:Flash 型ADC 和折叠插值ADC .Flash 型ADC 具有较大信号带宽和高功耗的特点;折叠插值ADC 功耗较低,但信号带宽由于信号预处理电路对输入信号折叠作用而下降 F /2倍(F 为折叠率),同时由于预处理电路本身对信号延迟影响及工艺偏差形成的不对称性,使输入信号带宽被进一步降低.为提高频率特性,二者可分别采用前置集总式采样/保持电路[4]和分布式采样/保持电路[5].这两种采样/保持电路均可以在一定程度上增大输入信号带宽、提高转换频率.但是受这两种ADC 基本结构所限,通常只能采用其中一种采样/保持电路,否则会引起噪声干扰、带宽下降等诸多不良影响.上述的前置采样/保持电路和分布式采样/保持电路存在以下问题:(1)由于CM OS 工艺很难设计高速高增益的运算放大器,导致只能采用简单的无源开关电容采样/保持电路,这使信号采样精度很低,难以超过6bit 分辨率;(2)在Flash 结构ADC 中为防止比较器噪声串扰和放大输入信号,通常在前置的采样/保持电路和比较器阵列之间插入一级或多级信号预放大器,而这造成比较器输入信号带宽受限,最终降低转换频率;(3)折叠插值结构ADC 内预处理电路的使用造成输入信号带宽下降,通过使用分布式采样/保持电路可以一定程度上改善预处理器的高频特性,但由于缺乏前置采样/保持电路,受内部放大器带宽有限的影响,导致在高频输入信号时ADC 有效分辨率下降.本文提出一种新型主从式T /H 结构,并作为折叠插值ADC 预处理器[6]的一部分,极大拓展了信号带宽.其中分布式主从T /H 电路的使用,使预处理电路的频率特性大为改善,进一步提高A DC 整体工作速度和信号稳定性.2　新型主从式T /H 工作原理在高速CM OS ADC 设计中,高速采样/保持电路设计非常困难,主要因为CM OS 工艺条件下,具有高增益带宽积的放大器设计困难,而采用简单的开关电容保持信号,会由于电荷注入和时钟馈通效应而引入非常大的误差[7].仿真结果表明,在1.2 m 工艺条件下,输入信号频率为100M Hz 、采样频率为200MHz 时,电荷注入形成的误差可达30m V 以上.2.1　前置T /H 电路采用全差分结构开关电容T /H 电路[8]可有效消除电荷注入和时钟馈通对T /H 电路造成的影响,在保持一定精度的前提下获得高采样频率和高输入信号带宽.但对于折叠插值ADC ,由于预处理电路的引入,使信号因折叠作用而带宽大为下降.2.2　折叠器内部分布式T /H 电路本设计在折叠单元[6]内部插入分布式T /H 电路,有效改善了预处理器的高频特性.预处理器由40个独立折叠放大器组成[7,9],其中每5个放大器组成一个4折叠率的折叠单元,共有8个折叠单元.信号的折叠和电流插值统一在放大器信号输出端进行,电流输出信号直接送入电流比较器以获得最大工作速度.从T /H 电路采用分布式结构,置于折叠放大器内部每个放大器的差分电压输出处,对差分信号进行采样保持,其所需精度原则上只需保存ze-ro -crossing 点相对位置不变,即保证相对精度.因此从T /H 电路精度要求很低,可以使用小开关管和小M OS 电容构成,不会对该节点频响特性造成大的负面影响.2.3　主从式T /H 电路前置T /H 电路可提高输入信号频率范围,而折叠器内部分布式T /H 电路可提高转换频率,因此二者结合可构成具有高输入信号带宽、高转换频率的主从式T /H 电路.置于折叠器前的前置T /H 电路作为主T /H 电路,同时为预处理器内部所有折叠单元提供稳定输入信号,而折叠器内部分布式T /H 电路使折叠器由原来的两级放大器变为事实上的两个单级放大器,显著增加了折叠器带宽,使整个ADC 能实现更高的转换频率.整个折叠插值ADC 的框架结构图如图1所示.图1　主从T/H 电路ADC 结构框图Fig.1　Diagr am of A DC w ith master -slav e T /H cir -cuit主从式T /H 电路结构如图2所示.主T /H 电路和从T /H 电路之间为信号预放大器,能够有效减小输入差分采样信号的误差,所以也称为误差补偿放大器,后面将做详细讨论.输入差分信号(V in 01、V in 02)经过主T /H 电路采样后,同时送入40个相同折叠单元内的误差补偿放大器,分别进行误差补偿,得到对应于参考电压V ref +和V ref -的输出差分电压;然后经过从T/H 电路采样后送入后续电路.主T /H 电路由M OS 开关和M OS 存储电容构成.为消除MOS 开关造成的电荷注入效应,增加一个伪开关管,尺寸约为M OS 开关的一半.M OS 电容为4pF.为使T /H 电路对高频输入信号具有足够快速的跟踪能力,开关M OS 管M 1,M 2的W /L 必463　4期刘　飞等:　带主从式T /H 电路的折叠插值A /D 转换器须足够大,而大的开关M OS 管必然会造成严重的电荷注入效应,伪开关管的加入能有效减少该效应.然而,由于输入信号快速变化造成的MOS 开关沟道电荷量变化,以及互补时钟信号事实上的不对称性,使采样精度远小于理论值.本设计使用差分误差补偿方式来消除电荷注入效应的影响,可大幅度增加采样精度.由于在许多实际情况下,并不存在具有良好对称关系的互补输入,因此本设计仍采用单端输入,同时取某一参考电平做补偿.下面具体讨论差分误差补偿放大器的工作原理.图2　主从式T /H 电路F ig.2　M aster -sla ve T /H circuit2.4　误差补偿放大器误差补偿放大器由图2中M 7,M 8,M 9,M 10及R 1,R 2组成.设输入差分电压为V in 和V 0,则可取参考电压为V +r ef=V ref ,V -ref=V 0.当考虑采样误差时,采样后的电压为V +in=V in + V in V -in =V 0+ V 0(1)则放大器输出为V d =R [g m (V +in-V +ref)-g m (V-in-V -r ef)]=R [g m (V in + V in -V r ef )-g m (V 0+ V 0-V 0)]=R [g m (V in -V r ef )+g m ( V in - V 0)](2) 只考虑一阶效应时,可认为采样误差与V in 大小无关,即 V in ≈ V 0,可得V d =Rg m (V in -V r ef )(3)由(3)式可知采样误差被消除.2.5　误差补偿放大器的误差分析(1)当考虑高阶效应时,由于输入信号电平和参考电平不等(V in ≠V 0)会导致两条支路的采样误差不完全相同,即 V in ≠ V 0,这表明(3)式有一定误差.(2)当输入高频V in 时,误差补偿放大器输出电压V d 通过C dg 反馈到采样电容,使采样电容变化量为C V d t .由于存在40个放大器电路,且每个放大器输入分别为V in ～V ref n ,使V in 不同时,累计到采样电容中得反馈电荷量不同,带来一定误差.然而累计电荷误差为一种平均效应,因此其影响有一定限度,而非单个放大器反馈量的简单叠加.464半　导　体　学　报25卷　(3)由于放大器本身存在非线性问题、电荷注入效应(电荷注入可由图示伪开关结构消除主要影响),会进一步降低T /H 精度.差分式T /H 中两条支路的采样电容所保持电压的相对精度可接近60dB ,但由于误差补偿放大器本身的非线性以及放大器电路中寄生电容C dg 的存在,使得高采样率下,补偿后的实际有效差分采样电压精度被降低到50dB 左右(此精度会随采样频率降低而明显提高).而高频输入信号时,ADC 的DNL 误差会明显增大.3　仿真结果设计使用贝岭1.2 m 工艺(SPDM ),通过Ca-dence Spectre 对几种采用不同T /H 电路的ADC 进行仿真验证.其中采用主从T /H 电路的6bit 折叠插值ADC 仿真结果(输入为1M Hz 正弦波,输入信号幅度为2.5～0.5V ,采样时钟频率为250M Hz)如图3所示.图3　带主从式T/H 的6bit 折叠插值ADC 仿真结果Fig.3　Simulatio n r esults for 6bit fo lding AD C w it h master -slav e T /H circuit图4为无独立T /H 电路的6bit 折叠插值ADC 在10M Hz 输入信号时的信号频谱图.图5为本文给出的带主从式T /H 电路的6bit 折叠插值ADC 在50M Hz 输入信号时的信号频谱图.二者电路结构基本相同,唯一区别在于是否采用独立的T /H 电路.从图4可明显看出,当无独立T /H 电路时,由于折叠插值ADC 的信号预处理器的倍频效应,使得输入信号带宽受到极大的限制.而从图5可看出,当采用本文给出的主从式T /H 电路时,ADC 信号带宽得到极大拓展,在50M Hz 输入信号情况下,ADC 仍能保持良好的动态性能.图4　信号频谱图　输入信号为10M Hz ,无独立T /H 电路Fig.4　T ypical output spect rum at 150M Hz/s f in =10M Hz ,w ithout T /H图5　信号频谱图　输入信号为50M Hz,带主从式T/H 电路F ig .5　O utput spectr um a t 250M Hz /s f in =50M Hz,w ith M -S T /H这里需要指出,在无独立T /H 电路的折叠插值ADC 中,由于信号预处理器对信号折叠作用会增加比较器阵列各个输入信号之间的时间不确定性,使得ADC 误码率随着转换频率增加而迅速增大,从而限制ADC 实际最大转换频率.而采用主从式T /H 电路后(特别是从T /H 电路),信号预处理器各个输出信号之间的同步性明显提高,从而增加了比较器阵列输入信号的稳定时间,降低了ADC 输出的误码率,最终使A DC 最大转换率得到提高.在1.2 m CMOS 工艺下,仿真结果表明,无独立T /H465　4期刘　飞等:　带主从式T /H 电路的折叠插值A /D 转换器电路和采用主从式T/H电路的6bit折叠插值ADC,最大转换率分别为150MHz/s和250MHz/s.图6(a)所示为无独立T/H电路的6bit折叠插值ADC版图照片,芯片面积为2.1m m×1.4mm,图6(b)所示为采用主从式T/H电路的6bit折叠插值ADC版图照片,芯片面积为2.5mm×1.5m m.二者对比可看出,采用主从式采样保持电路并不会大幅度增加ADC的芯片面积.ADC性能参数及对比总结如表1所示.表中采用主从式T/H电路的折叠插值ADC功耗增大的主要原因是ADC最大转换频率被提高,而在相同转换频率时,采用主从式T/H电路并不会明显增加电路功耗.图6　ADC版图照片F ig.6　M icr og raph of A DC表1　ADC仿真结果T able1　Simulated r esults o f AD CsADC类型Flash型ADC折叠插值ADC折叠插值ADC折叠插值ADC 分辨率4～5bit6b it6bit6b itT/H结构简单C M OS开关电容T/H无差分前置主T/H主从式T/H采样误差补偿放大器无无有有工艺 1.2 m标准数字CM OS 1.2 m标准数字CM OS 1.2 m标准数字CM OS 1.2 m标准数字CM OS 最大采样率≥200M S/s150M S/s200M S/s250M S/s 输入信号带宽>50M Hz≥0.5M Hz30M Hz80M Hz 输入信号V P-P 2.5V 2.5V2V2V 输入电容4pF4pF2×4pF2×4pFINL/DNL 0.5/0.5LSB(1M Hz in put)0.8/0.5LS B(0.5M Hz input)0.5/0.5L SB(1M H z in put)0.5/0.5LSB(1M Hz input)电源电压5V5V5V5V 最大功耗150～300m W185mW230m W300mW最大延迟时间2clock cycles≤1.5clock cycles2clock cycles 2.5clock cycles4　结论本文提出的主从式T/H电路结构,能够有效提高A DC的输入信号带宽,并一定程度增加转换频率.同时该T/H结构通过使用内部差分误差补偿技术来消除采样误差,保证高采样率情况下的采样精度.在1.2 m数字CM OS工艺下实现250M s/s采样率、6bit CM OS折叠、电流插值A/D转换器.仿真结果表明该设计中主从式T/H电路的实际采样精度约为50dB,ADC输入信号带宽可达到80MHz.此外,主从式T/H电路结构的应用范围并不仅仅局限于折叠插值A/D转换器,也可用于目前使用的高速Flash型ADC中.参考文献[1]　Van De Grift R,Rutten I W J M,Van Der Veen M.An8-bitvideo ADC incorporating folding and interp olation tech-niques.IEEE J Solid-State Cir cuits,1987,22(6):944[2]　Flynn M P,Allstot D J.CM OS folding A/D converters w ithcurren t-m ode interpolation.IEEE J Solid-State Circuits,1996,31(9):1248[3]　Van Valbur g J,Van de Plas sche R J.A n8-b650-M Hz foldingADC.IEEE J Solid-S tate Circuits,1992,27(12):1662[4]　Nauta B,Ven es A G W.A70-M S/s110mW8-b CM OS fold-ing and interpolating A/D converter.IEEE J Solid-State Cir-cu its,1995,30(12):1302[5]　Venes A G W,Van de Plas sche R J.An80-M Hz,80-mW,8b,CM OS foldin g and interpolating A/D converter w ith d is-tributed track-and-hold pr eprocess ing.IEE E J S olid-State466半　导　体　学　报25卷　Circu its ,1996,31(12):1846[6]　L iu Fei,Ji Lijiu.150-M s/s ,6b digital CM OS foldin g A/Dconverter with curr ent-mode interpolatin g.Chinese Journ al of Semiconductors,2002,23(9):988(in Chinese)[刘飞,吉利久.150-M s /s 、6b CM OS 数字工艺折叠、电流插值A /D 转换器.半导体学报,2002,23(9):988][7]　Razavi B.Design of analog CM OS integr ated circuits.NewYork :M cGraw -Hill Book ,2001:418[8]　Choi M ,Abid i A A.A 6-b 1.3Gsample/s A /D con verter in0.35- m CM OS.IEEE J S olid-State Circuits,2001,36(12):1847[9]　Flyn n M P ,Sh eahan B .A 400-M sample /s ,6-b CM OS foldingand inter polating ADC .IEE E J Solid -S tate C ircuits ,1998,33(12):1932A Folding and Interpolating A /D Converter with Master -Slave T /H Circuit*Liu Fei,Jia Song,Lu Zhenting,Liu Ling and Ji Lijiu(I nstitu te o f M icr oelectr onics ,P eking Univ er sity ,Be ij ing 100871,Ch ina )Abstract :A master -slave T /H circuit w ith the o ffset co mpensative amplifier s is pro po sed ,which can im pr ov e sample pr ecision and input bandw idth.A 250M s/s,6-bit CM O S fo lding and inter po lat ing A /D co nv ert er w ith M -S T /H is desig ned in a 1.2 m standar d digital CM O S pr ocess.T he simulatio n results demonstr ate that the po w er dissipation of the conv erter is less than 300mW for 5V supply and the signal bandw idth is about 80M Hz .T he latency betw een input and output is 2.5clock cycles .Key words :A DC;CM O S;m ast er-slav e T /H;fo lding ;int erpolating EEACC :1265;1280;2570DArticle ID :0253-4177(2004)04-0462-06*Project s upported by Electronic Pre -Research Found ation of China (Nos .41308010402,415011005)　Liu Fei male,w as born in 1974,PhD candidate.He is engaged in the research on m ixed A/D circuit des ign.　Lu Zh enting m ale,w as b or n in 1979,M S cand idate.He is engaged in the resear ch on m ixed A/D circuit des ign.　Ji Lijiu m ale,profes sor.He is engag ed in th e res earch on IC d esig n.　Received 10February 2003,r evised man uscr ipt received 25November 2003○c 2004Th e Chinese Ins titu te of Electronics 467　4期刘　飞等:　带主从式T /H 电路的折叠插值A /D 转换器。

一种高电源抑制比全工艺角低温漂CMOS基准电压源方圆;周凤星;张涛;张迪【摘要】A bandgap voltage reference circuit which has high PSRR and low temperature drift at all Process Corners was presented based on SMIC's0.35μm CMOS process. First, a high PSRR voltage reference is amplified bya voltage amplifier to get a stabilized voltage, which then is provided to bandgap core as power supply, so as to get high PSRR. Besides, set the key resistor tunable to adjust the positive voltage temperature coefficient, so as to meeting the negative voltage temperature coefficient change under different processes, and ultimately getting a bandgap voltage reference with low temperature coefficient at all processe. Cadence virtuoso simulation results showed that the circuit had a PSRR -109 dB (10 Hz)and --64 dB (10 kHz) at 27℃ and a temperature coefficient below 3.2×10^-6/℃ at all processes under 4 V supply voltage from-40-80℃.%基于SMIC0．35μm的CMOS工艺．设计了一种高电源抑制比，同时可在全工艺角下的得到低温漂的带隙基准电路。