EI1808NPOSS-1中文资料

物料编号CC1808JKNPOEBN100参数_易容网
MLCC即是多层陶瓷电容片式，是电子信息产品不可或缺的基本组件之一。

我国MLCC的生产起步在80年代初，行业早期主要是在外资企业的带动下发展起来的，近年来国内企业在技术上实现突破，行业国产化成效显著，并推动了MLCC产量迅速增长。

目前，MLCC的应用领域已从手机、电脑、电视机等消费电子领域，逐步拓展到新能源发电、新能源汽车、节能灯具、轨道交通、直流输变电、三网融合、高清电视、机顶盒、手机电视等多个行业。

对于这个悄悄活跃在人们生活中的元件你又知道多少呢.
本次易容网为大家推荐比较常用的MLCC国巨 | Yageo品牌的料号CC1808JKNPOEBN100相关参数
易
容网是深圳市易容信息技术有限公司独自研发的全球最大的MLCC搜索采购服务网站，2014年创立于深圳市南山区，全国首家电子元器件行业电容元件的搜索引擎及o2o商务服务平台。

易容网（）现已建成全球最大的MLCC电容搜索引擎数据库，包含全球25家电容生产厂商超过28万组MLCC产品数据，用户可根据行业应用、物料编号、规格参数等信息快速的找到所有相关的MLCC电容数据。

易容网在搜索服务的前提下还提供村田、TDK、国巨、太阳诱电、风华高科等常见品牌产品的o2o商务服务，让企业客户实现询价、报价、在线订单、出库、实时物流、签收、账期服务等在线一站式商务服务体验。

DS-K1808A系列读卡器用户手册法律声明版权所有©杭州海康威视数字技术股份有限公司2020。

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HCPL-0601中⽂资料CAUTION: The small device geometries inherent to the design of this bipolar component increase the component's susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.Small Outline, 5 Lead, High CMR, High Speed, Logic Gate Optocouplers Technical DataHCPL-M600HCPL-M601HCPL-M611DescriptionThese small outline high CMR,high speed, logic gate optocoup-lers are single channel devices in a five lead miniature footprint.They are electrically equivalent to the following Agilentoptocouplers (except there is no output enable feature):SO-5 Package Standard DIP SO-8 Package HCPL-M6006N137HCPL-0600HCPL-M601HCPL-2601HCPL-0601HCPL-M611HCPL-2611HCPL-0611The SO-5 JEDEC registered (MO-155) package outline does not require “through holes” in a PCB.This package occupies approximately one fourth the footprint area of the standard dual-in-line package. The lead profile is designed to be com-patible with standard surface mount processes.The HCPL-M600/01/11 optically coupled gates combine a GaAsP light emitting diode and an integrated high gain photon detector. The output of thedetector I.C. is an Open-collectorSchottky-clamped transistor. The internal shield provides a guaranteed common modetransient immunity specification of 5,000 V/µs for the HCPL-M601,and 10,000 V/µs for the HCPL-M611.This unique design provides maximum ac and dc circuit isolation while achieving TTL compatibility. The optocoupler ac and dc operational parameters are guaranteed from -40°C to 85°C allowing trouble free system performance.FeaturesSurface MountableVery Small, Low Profile JEDEC Registered Package OutlineCompatible with Infrared Vapor Phase Reflow and Wave Soldering Processes Internal Shield for High Common Mode Rejection (CMR)HCPL-M601: 10,000 V/µs at V CM = 50 VHCPL-M611: 15,000 V/µs at V CM = 1000 VHigh Speed: 10 Mbd LSTTL/TTL Compatible Low Input Current Capability: 5 mAGuaranteed ac and dc Performance overTemperature: -40°C to 85°C ? Recognized under theComponent Program of U.L.(File No. E55361) forDielectric Withstand Proof Test Voltage of 2500 Vac, 1MinuteThe HCPL-M600/01/11 are suitable for high speed logic interfacing, input/outputbuffering, as line receivers in environments that conventionalline receivers cannot tolerate, and are recommended for use inextremely high ground or induced noise environments.Outline Drawing (JEDEC MO-155)ApplicationsIsolated Line Receiver Simplex/Multiplex Data TransmissionComputer-Peripheral InterfaceMicroprocessor System InterfaceDigital Isolation for A/D, D/A ConversionSwitching Power Supply Instrument Input/Output IsolationGround Loop Elimination Pulse Transformer ReplacementPin Location (for reference only)SchematicUSE OF A 0.1 µF BYPASS CAPACITOR MUST BE CONNECTED BETWEEN PINS 6 AND 4 (SEE NOTE 1). V CC V OGNDTRUTH TABLE (POSITIVE LOGIC)LEDONOFFOUTPUT L H65431V CCV OUT GNDANODE 0.71 (0.028)UNDERSIDE OF THE PACKAGEDIMENSIONS IN MILLIMETERS (INCHES) * MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006) Recommended Operating ConditionsParameterSymbol Min.Max.Units Input Current, Low Level I FL *0250µA Input Current, High Level I FH 515m A Supply Voltage, Output V CC 4.55.5V Fan Out (R L = 1 k ?)N 5TTLLoads Output Pull-Up Resistor R L 3304,000?Operating TemperatureT A-4085°C* The off condition can also be guaranteed by ensuring that V F (off) ≤ 0.8 volts.Absolute Maximum Ratings(No Derating Required up to 85°C)Storage Temperature....................................................-55°C to +125°C Operating Temperature ..................................................-40°C to +85°C Forward Input Current - I F (see Note 2).......................................20 mA Reverse Input Voltage - V R .................................................................5 V Supply Voltage - V CC (1 Minute Maximum)........................................7 V Output Collector Current - I O ........................................................50 mA Output Collector Power Dissipation .. (85)mW Output Collector Voltage - V O ............................................................7 V (Selection for higher output voltages up to 20 V is available)Infrared and Vapor Phase Reflow Temperature.......................see belowMaximum Solder Reflow Thermal Profile.(Note: Use of Non-Chlorine Activated Fluxes is Recommended.)240TIME – MINUTEST E M P E R A T U R E – °C220200180160140120100806040200260Insulation Related SpecificationsParameter Symbol Value Units ConditionsMin. External Air Gap L(IO1)≥5mm Measured from input terminals (Clearance)to output terminalsMin. External Tracking Path L(IO2)≥5mm Measured from input terminals (Creepage)to output terminalsMin. Internal Plastic Gap0.08mm Through insulation distance (Clearance)conductor to conductor Tracking Resistance CTI175V DIN IEC 112/VDE 0303 Part 1 Isolation Group (per DIN VDE 0109)IIIa Material Group DIN VDE 0109 Electrical SpecificationsOver recommended temperature (T A = -40°C to 85°C) unless otherwise specified. (See note 1.)*All typicals at T A = 25°C, V CC = 5 V.Switching SpecificationsOver recommended temperature (T A = -40°C to 85°C), V CC = 5 V, I F = 7.5 mA unless otherwise specified.*All typicals at T A = 25°C, V CC = 5 V.Notes:1. Bypassing of the power supply line is required with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler. The total leadlength between both ends of the capacitor and the isolator pins should not exceed 10mm.2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 20mA.3. Device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together.4. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥3000 V RMS for 1 second(Leakage detection current limit, I I-O≤ 5 µA).5. The t PLH propagation delay is measured from 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the output pulse.6. The t PHL propagation delay is measured from 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the output pulse.7. CM H is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logicstate (i.e., V OUT > 2.0V).8. CM L is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., V OUT > 0.8 V).9. For sinusoidal voltages, (|dV CM|/dt)max = πf CM V CM(p-p).10. See application section; “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.11. t PSK is equal to the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature withinthe worst case operating condition range.Figure 5. Low Level Output Current vs. Temperature.Figure 4. Output Voltage vs.Forward Input current.Figure 1. High Level Output Current vs. Temperature.Figure 2. Low Level Output Voltage vs. Temperature.Figure 3. Input Diode Forward Characteristic.Figure 6. Test Circuit for t PHL and t PLH .I O H – H I G H L E V E L O U T P U T C U R R E N T – µAT A – TEMPERATURE – °C101550.4T A – TEMPERATURE – °C 0.30.1V O L – L O W L E V E L O U T P U T V O L T A G E – V0.2V F – FORWARD VOLTAGE – VOLTS10I F – F O R W A R D C U R R E N T – m A100I F – FORWARD INPUT CURRENT – mAV O – O U T P U TV O L T A G E – VI O L – L O W L E V E L O U T P U T C U R R E N T – m A T A – TEMPERATURE – °C60802040OUTPUT V O MONITORING NODEI FV F = 7.5 mAF = 3.75 mAFigure 12. Temperature Coefficient for Forward Voltage vs. Input Current.Figure 10. Rise and Fall Time vs.Temperature.Figure 9. Pulse Width Distortion vs.Temperature.Figure 8. Propagation Delay vs.Pulse Input Current.Figure 7. Propagation Delay vs.Temperature.Figure 11. Test Circuit for Common Mode Transient Immunity and Typical Waveforms.10080T A – TEMPERATURE – °C 600t P – P R O P A G A T I O N D E L A Y – n s402010590I F – PULSE INPUT CURRENT – mA7530t P – P R O P A G A T I O N D E L A Y – n s60454030T A – TEMPERATURE – °C20P W D – P U L S E W I D T H D I S T O R T I O N – n s10-10t r , t f– R I S E , F A L L T I M E – n sT A – TEMPERATURE – °Cd V F /d T – F O R W A R D V O L T A G E T E M P E R A T U R E C O E F F I C I E N T – m V /°C0.1110100I F – PULSE INPUT CURRENT – mA-1.4-2.2-2.0-1.8-1.6-1.2-2.4V O 0.5 VV O (MIN.)5 V0 V SWITCH AT A: I F = 0 mA SWITCH AT B: I F = 7.5 mAV CMCM HCM LV O (MAX.)V CM (PEAK)V O+5 VO GENERATOR Z O = 50 ?Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propaga-tion delay from low to high (t PLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (t PHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 7).Pulse-width distortion (PWD) results when t PLH and t PHL d iffer in value. PWD is defined as the difference between t PLH and t PHL and often determines the maxi-mum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232,RS422, T-1, etc.).Propagation delay skew, t PSK, is an important parameter to consider in parallel data appli-cations where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group ofoptocouplers, differences inpropagation delays will cause thedata to arrive at the outputs of theoptocouplers at different times. Ifthis difference in propagationdelays is large enough, it willdetermine the maximum rate atwhich parallel data can be sentthrough the optocouplers.Propagation delay skew is definedas the difference between theminimum and maximumpropagation delays, either t PLH ort PHL, for any given group ofoptocouplers which are operatingunder the same conditions (i.e.,the same drive current, supplyvoltage, output load, andoperating temperature). Asillustrated in Figure 15, if theinputs of a group of optocouplers are switched either ON or OFF at the same time, t PSK is the difference between the shortest propagation delay, either t PLH or t PHL, and the longest propagation delay, either t PLH or t PHL.As mentioned earlier, t PSK can determine the maximum parallel data transmission rate. Figure 11 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast.Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 16 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some ofthe data outputs may start tochange before the clock signalhas arrived. From theseconsiderations, the absoluteminimum pulse width that can besent through optocouplers in aparallel application is twice t PSK. Acautious design should use aslightly longer pulse width toensure that any additionaluncertainty in the rest of thecircuit does not cause a problem.The t PSK specified optocouplersoffer the advantages ofguaranteed specifications forpropagation delays, pulse-widthdistortion and propagation delayskew over the recommendedtemperature, and input current,and power supply ranges.Figure 15. Illustration ofPropagation Delay Skew – t PSK .Figure 13. Input Threshold Current vs. Temperature.Figure 14. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit. Figure 16. Parallel Data Transmission Example.I T H – I N P U T T H R E S H O L D C U R R E N T – m AT A – TEMPERATURE – °C452316V* DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT. CC 2I FV OI FV ODATAINPUTS CLOCKDATAOUTPUTSCLOCK/doc/9b0bff6d783e0912a2162a2e.html Data subject to change.Copyright ? 1999 Agilent Technologies Obsoletes 5091-9635E (10/93)5966-4942E (11/99)。

EPL-6200L产品基本介绍A U K L E T愛普生（中国）有限公司技術支援課　2003年10月Rev.A1概要 (4)1.1 上市时间 (4)1.2 市场参考价 (4)1.3 产品定位 (4)1.4 不同地区的名字 (4)2产品特点 (4)2.1 基本描述 (4)2.2 主要特点 (4)3产品比较 (4)3.1 与EPSON EPL-6100L的比较 (4)3.2 与EPSON EPL-6200的比较 (5)4基本规格 (6)4.1 纸张规格 (6)4.2 信赖性，可靠性和维护性 (6)4.2.1 信赖性 (6)4.2.2 可靠性 (6)4.2.3 维护性 (7)4.3 使用环境规格 (7)4.4 控制器基本规格 (7)5状态页说明 (8)6故障信息 (9)7特殊操作 (9)7.1 EEPROM初始化 (9)7.2 打印机调整（隐藏功能） (11)8耗材 (12)9维修信息 (12)9.1 维修服务 (12)9.2 保修期 (12)版本信息版本页项目描述原因---A ALL 首次发行 ---1 概要1.1 上市时间2003年9月1.2 市场参考价约RMB 2100 元1.3 产品定位经济型小型办公室A4幅面黑白激光打印机1.4 不同地区的名字名字地区EPL-6200L 日本之外的国家LP-1400 日本2 产品特点2.1 基本描述简洁轻巧的经济型A4幅面黑白激光打印机，适合小型办公或家庭使用。

2.2 主要特点1) 简洁轻巧的A4幅面黑白激光打印机。

2) 基于主机的打印机技术。

3) 数据压缩技术。

4) 20ppm高速打印。

5) 标配USB1.1接口。

6) 标配IEEE1284双向并行接口。

7) 硒鼓和碳粉既可分开又可以组装为一个整体的设计，既充分利用耗材又便于操作。

8) 碳粉盒有CSIC可自动识别碳粉容量和新碳粉。

9) 最高可达600dpi高清晰度。

10) 无分辨率增强模式。

11) 无300dpi模式。

376Surface Mount Fusesw w w.l i t t e l f u s e.c o mNANO 2®FUSE Very Fast-Acting 451/453 SeriesThe Nano 2SMF Fuse is a very small, square surface mount fuse that isalso available in a surface mount holder.• 451 Series RoHS Compliant version now available, use ordering suffix ‘L ’(see example on data sheet).ELECTRICAL CHARACTERISTICS:% of AmpereAmpereOpening Rating Rating Time 100%1/16–15 4 hours, Min imum 200%1/16–10 5 seconds, Max imum12–1520 seconds, Max imumAGENCY APPROVALS:Recognized under the Components Program of Underwriters Laboratories and Certified by CSA.Approved by METI from 1 through 5 amperes.UL Listed 0.062 - 5A.AGENCY FILE NUMBERS:UL E10480, CSA LR 29862.INTERRUPTING RATINGS:1/16 – 8A50 amperes at 125 VAC/VDC 300 amperes at 32 VDC10A 35 amperes at 125 VAC/50 amperes at 125 VDC300 amperes at 32 VDC12A – 15A 50 amperes at 65 VAC/VDC300 amperes at 24 VDCENVIRONMENTAL SPECIFICATIONS:Operating Temperature:–55°C to 125°C.Shock:MIL-STD-202, Method 213, Test Condition I(100 G’s peak for 6 milliseconds).Vibration:MIL-STD-202, Method 201 (10–55 Hz).Salt Spray:MIL-STD-202, Method 101, T est Condition B.Insulation Resistance (After Opening):MIL-STD-202, Method 302, Test Condition A, (10,000 ohms minimum).Resistance to Soldering Heat:MIL-STD-202, Method 210, Test Condition B (10 sec.at 260°C).Thermal Shock:MIL-STD-202, Method 107, T est Condition B (–65 to 125°C).Moisture Resistance:MIL-STD-202, Method 106, High Humidity (90-98 RH), Heat (65°C).(.077")(.057")Recommended pad layoutTin-LeadSilver Nominal Nominal Plated Plated Ampere Voltage Resistance Melting I 2t Catalog #Catalog #Rating Rating Cold Ohms A 2Sec.–0451.0620.062125 5.500.00019–0451.0800.080125 4.050.00033–0451.1000.100125 3.100.00138–0451.1250.125125 1.700.002860451.1600453.1600.160125 1.800.003060451.2000453.2000.200125 1.400.006520451.2500453.2500.250125 1.050.011260451.3150453.3150.3151250.780.02310451.3750453.3750.3751250.6100.04250451.4000453.4000.4001250.5600.04840451.5000453.5000.5001250.4200.07950451.6300453.6300.6301250.3050.1430451.7500453.7500.7501250.2450.1850451.8000453.8000.8001250.2120.2710451001.0453001. 1.01250.1530.45904511.2504531.25 1.251250.07800.664045101.5045301.5 1.51250.06300.853045101.6045301.6 1.61250.0580 1.0600451002.0453002.2.01250.03670.530045102.5045302.5 2.51250.0286 1.0290451003.0453003.3.01250.0227 1.65004513.1504533.15 3.151250.0215 1.920045103.5045303.53.51250.0200 2.4690451004.0453004.41250.0160 3.1520451005.0453005.51250.0125 5.566045106.3045306.3 6.31250.00969.170451007.0453007.71250.009010.320451008.0453008.81250.007720.230451010.0453010.101250.005626.460451012.0453012.12650.004947.970451015.0453015.15650.003797.82®Refer to pg.374 for SMF Omni-Blok ®Holder, Series 154 000.RoHSAverage Time Current CurvesMaterials:Body:CeramicTerminations:Tin-Lead AlloyRoHS Compliant Terminations:Gold over Nickel Plated Caps(451)Silver Plated Caps(453)Soldering Parameters(see page 3 for typical soldering profile):Wave Solder — 260°C, 10 seconds maximum Reflow Solder — 260°C, 30 seconds maximumSolderability:MIL-STD-202, Method 208.PACKAGING SPECIFICATIONS:12mm Tape and Reel perEIA-RS481-1 (IEC 286, part3);1,000 pieces per reel, add packaging suffix, MR;5,000 per reel, add packaging suffix NR.Options:For RoHS Compliant 451 series add the letter ‘L ’to end of packaging suffix.Example:0451001.MRL (RoHS Compliant 1A, 1,000 per reel).PATENTEDU L。