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Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claimsof infringement and any implied warranties of merchantability or fitness for a particular purpose.IntroductionThe LogiCORE™ Divider core creates a circuit for fixed-point or floating-point division based on radix-2non-restoring division, or division by repeated multi-plications, respectively. The Divider core supersedes the Serial Divider core version 3.0, which has been incorporated into this core and now forms the fixed-point solution.Features•Generates an arithmetic division algorithms for fixed-point or floating-point division with operands of up to 32 or 64 bits wide, respectively •Performs radix-2 integer division or division by repeated multiplications for floating-point numbers •Supports IEEE-754 format for floating-point numbers •Optional operand widths, synchronous controls, and selectable latency •For use with Xilinx CORE Generator™ tool v8.1i. •Incorporates Xilinx Smart-IP™ technology for maximum parameterization and optimum implementationDivider v1.0DS530 January 18, 2006Product SpecificationLogiCORE™ Facts Core SpecificsSupported Device FamilyVirtex™, Virtex-E, Virtex-II,Virtex-II Pro, Virtex-4, Spartan™-II,Spartan-IIE, Spartan-3, andSpartan-3E FPGAsResources UsedI/OLUTsFFsBlock RAMsFixed point See Table 5,Fixed-point Performance Characteristics Floating pointSee T able 9,Floating-point Performance CharacteristicsProvided with CoreDocumentation Data SheetDesign File Formats VHDL Constraints File noneVerificationVHDL Behavioral ModelVHDL Structural (UniSim)Model Verilog Structural (UniSim)ModelInstantiation TemplateVHDL Wrapper Verilog WrapperDesign Tool RequirementsXilinx Implementation Tools ISE 8.1i or later Verification ModelSim®PE 6.1a Simulation ModelSim PE 6.1a SynthesisXST v8.1i or higherSupportProvided by Xilinx, Inc. @ /support .OverviewThe Divider core selects an implementation depending on the algorithm_type parameter. Currently,the following two division implementations are supported:•Fixed-point. Radix-2, non-restoring integer division using fixed-point operands, allowing a remainder to be generated.•Floating-point. Division by repeated multiplications. Works on normalized operands; in effect, a floating-point implementation.A detailed explanation of each implementation is provided in a later section of this data sheet.ApplicationsDivision is the most complex of the four basic arithmetic operations. Because hardware solutions arecorrespondingly larger and more complex than the solutions for the other operations, it is best to min-imize the number of divisions in any algorithm. There are many forms of division implementation,which can be separated into two broad categories: fixed-point algorithms and floating-point algo-rithms. This core provides one example of each category.The radix-2 non-restoring algorithm solves one bit of the quotient per cycle using addition and subtrac-tion. For this reason, it can achieve very high clock speeds at the expense of relatively high latency.However, the design is fully pipelined, so can achieve a throughput of one division per clock cycle. Theresulting circuit is relatively large, however, so if the throughput is smaller, the divisions per clockparameter allows compromises of throughput and resource use. This algorithm naturally generates aremainder, so is the choice for applications requiring remainders or modulus results.The repeated multiplications algorithm is an iterative method using successive approximations to thereciprocal of the denominator. The number of bits of the quotient solved doubles per iteration, so thisalgorithm is well suited to applications requiring precise results. Also, because this core makes use ofembedded multipliers, the overall resource use is less than that for the radix-2 algorithm. Again, thedesign is fully pipelined to allow a throughput of one division per clock cycle. This algorithm does notnaturally yield a remainder.2DS530 January 18, 2006Generic XCO and VHDL ParametersThe descriptions below refer to generic VHDL parameters. Table2 defines the parameters, legal values,and meaning of the XCO parameters and VHDL generics, which are broadly equivalent.•c_family (string) and c_xdevicefamily (string): Together, these generics identify the specific FPGA device family the core is targeting. Table1 the values for each of the supported families.T able 1: Relationship between Target FPGA Family, c_family and c_xdevicefamilyTarget FPGA Family c_family c_xdevicefamily Virtex/Virtex-E"virtex""virtex"Spartan-II/Spartan-II E"virtex""spartan2"Virtex-II"virtex2""virtex2"Virtex-II Pro"virtex2p""virtex2p"Spartan-3"spartan3""spartan3"Spartan-3E"spartan3""spartan3e"Virtex-4"virtex4""virtex4"•algorithm_type (integer): Specifies the division algorithm to use. The choice is 1 for radix-2(fixed-point notation) or 2 for division by repeated multiplications (floating-point notation).•signed_b (integer): 0 for unsigned operands, 1 for signed (2’s complement) operands. Applies to fixed-point notation only.•fractional_b (integer): 0 (no remainder) or 1 (has remainder). Applies to fixed-point only.•dividend_width (integer): 2 to 32 (fixed). Specifies the width of both dividend and quotient.•fractional_width (integer): 2 to 32 (fixed-point only).•c_has_ce (integer): 0 (no ce), or 1 (has ce).•c_has_aclr (integer): 0 (no ce), or 1 (has ce).•c_has_sclr (integer): 0 (no ce), or 1 (has ce).•divclk_sel (integer): 1, 2, 4, or 8. Specifies the number of clocks between division results for the fixed-point case only. A higher number results in lower-circuit area at the cost of lower throughput.•latency (integer): 1 to 99(float only). Specifies the circuit latency in terms of enabled clock (ce) cycles.•divisor_width (integer):2 to 32 (fixed)•bias (integer): Specifies the bias on the exponent, according to IEEE-754 format. A value of -1 results in a bias value in the mid-point of the exponent range.•mantissa_width (integer): 2 to 64. Specifies the width of the mantissae of all operands (floating-point only).•exponent_width (integer): 2 to 16. Specifies the width of the exponents of all operands (floating-point only).4DS530 January 18, 2006T able 2: Common Generic Parameters XCO ParameterXCO ValuesGeneric VHDL Parameter Generic ValuesDescriptionCommon GenericsAlgorithm T ype Fixed, Float algorithm_type (1),21 = fixed-point division (radix-2)2 = floating-point division CE false, true c_has_ce (0),10 = no CE 1 = has CE ACLR false, true c_has_aclr (0),10 = no ACLR 1 = has ACLR SCLRfalse, true c_has_sclr(0),10 = no SCLR 1 = has SCLRSCLR/CE Priority SCLR_overrides _CE, CE_overrides_SCLRc_sync_enable (0),10 = SCLR overrides CE 1 = CE overrides SCLRSerial-divider Generics (Fixed-point)Dividend and Quotient width 2 to 32 (16)dividend_width 2 to 32(16)Width of dividend and quotient (fixed only)Divisor width 2 to 32 (16)divisor_width 2 to 32 (16)Width of divisor (fixed only)Remainder type remainder, fractional fractional_b 0,10 = remainder,1 = fractional Fractional width 2 to 32 (16)fractional_width 2 to 32 (16)Width of fraction (fractional only)Operand signunsigned, signedsigned_b0,10 = unsigned 1 = signedClocks per division 1,2,4,8divclk_sel (1),2,4,8Throughput (interval between input opportunities)Low-latency Generics (Floating-point)Mantissa width 2 to 64mantissa_width 2 to 64 (16)Width of mantissa Exponent width2 to 16exponent_width2 to 16 (8)Width of exponent Latency 1 to 99latency 1 to 99(1)Latency of division Bias-1 to 2^Exponent_width -1bias-1 to 2^exponent_width -1Exponent biasFeature Summary Fixed-point Solution•Divides dividend by divisor to provide the quotient with integer or fractional remainder •Pipelined architecture for increased throughput •Pipeline reduction for size versus throughput selections •Dividend width from 1 to 32 bits •Divisor width from 3 to 32 bits•Fractional remainder width from 3 to 32 bits•Independent dividend, divisor and fractional bit widths •Fully synchronous design using a single clock•Supports unsigned or two’s complement signed numbers •Can implement 1/X (reciprocal) function •Fully registered outputsOverview Fixed-point SolutionThis parameterized module divides an M-bit-wide variable dividend by an N-bit-wide variable divi-sor. The output consists of the quotient and either the integer remainder or the fractional result (quo-tient continued past the binary point). In the integer remainder case, the result of the division is an M-bit-wide quotient with an N-bit-wide integer remainder (Equation 1). In the fractional case, the result is an M-bit-wide quotient with an F-bit-wide fractional remainder (Equation 2). When both frac-tional and signed are selected, the top bit of the fractional result is a two’s complement sign bit, result-ing in one less bit of magnitude result (Equation 3). It is an efficient, high-speed, parallel implementation. The core can be configured for unsigned or signed data.Equation 1: Integer remainder case.Equation 2: F-bit-wide fractional remainder in the unsigned caseEquation 3: F-bit-wide fractional remainder in the signed caseNote that for signed mode with integer remainder, the sign of the quotient and remainder correspond exactly to Equation 1.Dividend = quotient * divisor + remainderFractRmd=IntRmd *2FDivisorFractRmd=IntRmd *2( F-1)DivisorThus6/-4 = -1 REMD 2whereas-6/4 = -1 REMD –2For signed mode with fractional remainder, the sign bit is present both in the quotient and the remain-der. For example, for a four-bit dividend, divisor and fractional remainder we have:-9/4 = 9/-4 = -(2 1/4)This corresponds to:(1)0111 / 0100 or 1001/1100Giving the result:Quotient = 1110 (= -2)Remainder = 1110 (= -1/4)For division by zero, the quotient, remainder, and fractional results are undefined.The design is highly pipelined. The amount of pipelining can be reduced to decrease the area of thedesign at the expense of throughput. In the fully pipelined mode the design outputs the result of onedivision operation per clock cycle after an initial latency. The design also supports the options of 2, 4,and 8 clock cycles per division after an initial latency, as shown in Table4.The dividend and divisor bit widths can be set independently. The bit width of the quotient is equal tothe bit width of the dividend. The bit width of the integer remainder is equal to the width of the divisor.For fractional output, the remainder bit width is also independent of the dividend and divisor. The corewill handle data ranges of 3 to 32 bits for the dividend, divisor and fractional output.The divider can be used to implement the 1/X function; that is, the reciprocal of the variable X. To dothis, the dividend bit width is set to 1 for unsigned or 2 for signed data and fractional mode is selected.The dividend input is tied high within the user’s design.6DS530 January 18, 2006Pinout of Fixed-point SolutionThe fixed-point core pinout and signal names are shown in Figure 1 and defined in Table 3.Figure 1: Core Pinout DiagramTable 3: Fixed-point Signal PinoutSignalDirectionDescriptionDIVIDEND[Dividend Width-1:0]Input Dividend (parallel data in). Data bit width determined by the Dividend width generic or XCO parameter.DIVISOR[Divisor Width -1:0]InputDivisor (parallel data in). Data bit width determined by the Divisor width generic or XCO parameter.CLK InputClock . With the exception of ACLR, control and data inputs are captured and new output data formed on rising clock transitions.ACLRInput (optional)Asynchronous Clear (ACLR). Optional input pin. All control signals are synchronous to the rising edge of CLK except ACLR. When ACLR is asserted (High), all the core flip-flops are asynchronously initialized. The core remain in this state until ACLR is negated.SCLRInput (optional)Synchronous Clear (SCLR). Optional input pin. When asserted (high), all the core flip-flops are synchronously initialized (synchronous to the clock). The core remains in this state until SCLR is deasserted. When both SCLR and CE exist, the sync_enable parameter determines whether SCLR is qualified by CE or whether SCLR overrides CE (that is, will clear the module on the clock edge even if CE is deasserted).CEInput (optional)Clock Enable (CE). Optional input pin. When deasserted (low), all the synchronous inputs are ignored and the core remains in its current state.8DS530 January 18, 2006Following a power-on reset, SCLR , or ACLR , the outputs QUOTIENT and REMAINDER output all zeroes until new results appear.Waveforms of Fixed-point SolutionThe total latency (number of clocks required to get the first output) is a function of the bit width of the dividend. If fractional output is required, the latency is also a function of the fractional bit width. If clock enable is selected, latency is in terms of enabled clock cycles.When ‘clocks per division’ is set to 2, 4, or 8, the RFD output indicates the cycle in which input data is sampled (Figure 2), and therefore from when latency is measured. Ready for data should be qualified by clock enable if used externally.In general:Latency is of the order M for integer remainder dividers Latency is of the order M + F for fractional remainder dividersRFDOutputReady for Data (RFD). An output that indicates the cycle in which input data is sampled by the core. This is only applicable to cores where divclk_sel is not 1. For the case of divclk_sel = 1 the core is fully pipelined and samples the inputs on every enabled clock rising edge; hence, RFD will always be high.When divclk_sel = 2, 4 or 8, the core only samples data on every 2nd, 4th or 8th enabled clock rising edge respectively. The cycle on which data is sampled isimportant for the definition of latency, as shown in figure3. RFD will only change on enabled (CE input) clock rising edges for a core that has CE input (has_ce = True).QUOTIENT[Dividend width-1:0]OutputQuotient . The result of the integer division of dividend by divisor (dividend DIV divisor). The bit width of the quotient is equal to the dividend. For signed operation, the quotient is in two’s complement form. Parallel data out. Data bit width determined by the dividend width generic or XCO parameter.REMAINDER[n:0]REMAINDER[f:0]OutputRemainder . The integer remainder of the integer division of dividend by divisor (dividend MOD divisor) when the core is not fractional. For a fractional core, this output is the fractional part of the division result.For either case, if the core is signed, the output is in two’s complement form.• Integer Remainder. Result data bit width determined by divisor width generic or XCO parameter.• Fractional Remainder. Result data bit width determined by Fractional Width generic or XCO parameter.Table 3: Fixed-point Signal Pinout (Continued)SignalDirectionDescriptionTable 4 provides a list of the latency formula for divider selections and Figure 2 illustrates how latency is defined. Latency is expressed in clock cycles for dividers with no clock enable input and otherwise in enabled clock cycles.The divclk_sel parameter allows a range of choices of throughput versus area. With divclk_sel = 1, the core is fully pipelined, so it will have maximal throughput of one division per clock cycle, but will occupy the most area. The divclk_sel selections of 2, 4 and 8 reduce the throughput by those respective factors for smaller core sizes.Figure 2: Latency Example (Clocks per Division = 4)T able 4: Latency of Fixed-point Solution Based on Divider ParametersSignedFractionalClks/DivLatencyFalse False 1M+2False False >1M+3False True 1M+F+2False True >1M+F+3True False 1M+4True False >1M+5True True 1M+F+4TrueTrue>1M+F+5Note: M=dividend width, F=fractional remainder width.clk dividend divisorrfd quot remda ba divb a rem blatencyce c div d c rem dc de f10DS530 January 18, 2006Performance Characteristics of Fixed-point SolutionTable 5 defines performance characteristics for cases run on a Virtex-4, speed grade 10 device, and are intended to provide an indication of resources used and achievable clock speed. Generics not specified are at their default values.T able 5: Fixed-point Performance CharacteristicsDivisor WidthDividend WidthDivclk_selSlices usedSpeed (MHz)DSP48s usedBlock Memories881129385008821002850088475322008886233000323211666203Feature Summary Floating-point Solution•Performs division by repeated multiplications for floating-point numbers•Supports IEEE-754 format for floating-point numbers•Optional operand widths, synchronous controls, selectable latencyOverview Floating-point SolutionThe floating-point implementation performs division by repeated multiplications. The design is fully pipelined for maximal throughput. The two operands, divisor and dividend, are entered in sign-man-tissa-exponent form. A single sign bit per operand determines the sign of the mantissa. The mantissa width is configurable, as is the exponent width. The bias of the exponent is also configurable. Following IEEE754, certain combinations of exponent and mantissa are interpreted as zero, infinity and NaN (not a number). The result is expressed in the same form as the inputs. Overflow and underflow outputs are given for those results whose magnitudes lie above or below (respectively) the range which can be expressed with the specified mantissa and exponent widths.The format of number representation follows IEEE754. The mantissas, both on input and output have an implicit leading ’1.’ The mantissa describes a number in the range 0.5(inclusive) to 1.0(not inclusive). For example, the number 0.75 is 0.11000... in binary. The mantissa to describe this would be 10000... (to the specified width). The leading 1 indicates the number is in the range 0.5 to just less than 1.0. Since the number representation requires this normalization the leading 1 is not required as an input since it car-ries no information.The underflow and overflow outputs are provided to show if the result of a calculation resulted in and exponent outside the range allowed by the width of the exponent, that is, <0 or >2^exponent_width. Table6 defines special values recognized by the core.T able 6: Special ValuesExponent Mantissa Special ValueAll ’1’s Not all ’0’s Not a Number (NaN)All ’1’s All ’0’s InfinityAll ’0’s All ’0’s ZeroTable7 defines division results involving any of the special values described in Table6.T able 7: Division Results Involving Special ValuesDividend Divisor QuotientNaN Any Value NaNAny Value NaN NaNInfinity Infinity NaNZero Zero NaNAny value Infinity Zero12DS530 January 18, 2006Pinout of Floating-point SolutionThe floating-point core pinout and signal names are displayed in Figure 3 and defined in Table 8.Any Value Zero Infinity Zero Any Value Zero InfinityAny ValueInfinityFigure 3: Floating-point Schematic SymbolTable 8: Pinout of Floating-point SolutionSignalDirectionDescriptionCLK Input Clock. Rising edge clock signal CE Input (optional)Clock Enable ACLR Input (optional)Asynchronous Clear SCLRInput (optional)Synchronous Clear DIVIDEND _MANTISSA [Mantissa Width-1:0]Input Dividend mantissa DIVISOR _MANTISSA [Mantissa Width-1:0]Input Divisor mantissaDIVISOR_SIGNInputSign of Divisor mantissa (0 for +ve, 1 for -ve)T able 7: Division Results Involving Special Values (Continued)DividendDivisorQuotientWaveforms of Floating-point SolutionThe functional timing characteristics of the floating-point solution are very simple. Because the design has a throughput of one division per clock cycle, no handshaking signals (Ready for Data, New Data,output Ready) are required. Latency is selectable and is defined in the same manner as for the fixed-point solution. For this reason, outputs occur following the n th enabled rising clock edge after the inputs, where n is the latency value.Performance Characteristics of Floating-point SolutionTable 9 defines performance characteristics for cases run on a Virtex-4, speed grade 10 device and are intended to provide an indication of resources used and achievable clock speed. Generics not specified are at their default values.Note that when the core does not have asynchronous clear nor synchronous clear, use can be made of SRL16 primitives, leading to a substantial reduction in circuit size. For this reason, the use of SCLR or ACLR is not recommended.DIVIDEND_SIGNInput Sign of Dividend mantissa (0 for +ve, 1 for -ve)DIVISOR _EXPONENT [Exponent Width-1:0]Input Exponent of Divisor DIVIDEND _EXPONENT [Exponent Width-1:0]Input Exponent of Dividend QUOTIENT _MANTISSA [Mantissa Width-1:0]Output Quotient mantissa QUOTIENT_SIGNOutput Sign of Quotient QUOTIENT _EXPONENT [Exponent Width-1:0]Output Exponent of Quotient OVERFLOW Output Float overflow indication UNDERFLOWOutputFloat underflow indicationNoteAll control inputs are Active High. If an Active Low input is required for a particular control pin, an inverter must be placed in the path to the pin. The inverter will be absorbed appropriately during synthesis and/or mapping.T able 9: Floating-point Performance CharacteristicsMantissa WidthExponent WidthLatencySlices usedSpeed (MHz)DSP48s usedBlock Memories1581842510115810231941011583027227610124826(no SCLR)399283101Table 8: Pinout of Floating-point Solution (Continued)SignalDirectionDescription14DS530 January 18, 2006Generating the CoreThe Divider core can be included in your design in two ways: Using the CORE Generator graphical user interface (GUI), or using direct instantiation.Method 1: GUIThe CORE Generator system produces several files when a core is generated. Instructions about how to instantiate a core using this method are automatically produced in the .vho file. An example of a section of a .vho file is provided below:-- The following code must appear in the VHDL architecture header:------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG component div_gen_v1_0 port (clk: IN std_logic;...(other ports));end component;-- COMP_TAG_END ------ End COMPONENT Declaration -- The following code must appear in the VHDL architecture -- body. Substitute your own instance name and net names.------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG your_instance_name : div_gen_v1_0 port map ( clk => clk, q => q);-- INST_TAG_END ------ End INSTANTIATION Template -- You must compile the wrapper file counter.vhd when simulating24826(with SCLR)720310101428157388821142845937211211T able 9: Floating-point Performance Characteristics (Continued)Mantissa WidthExponent WidthLatencySlices usedSpeed (MHz)DSP48s usedBlock Memories-- the core, counter. When compiling the wrapper file, be-- sure to reference the XilinxCoreLib VHDL simulation-- library. For detailed-- instructions, please see the CORE Generator User Guide.Method 2: Direct InstantiationThe CORE Generator now allows cores to be directly instantiated into user code. To do this, add the fol-lowing lines to the head of your VHDL file:Library Xilinxcorelib;Use Xilinxcorelib.div_gen_v1_0_comp.all;and instantiate the Divider core with appropriate values for the generics and your local signals:i_instance: div_gen_v1_0generic map(c_dividend_width => 16,c_has_ce => 1etc.);port map(clk => clk ,sclr => sclr ,quotient => output);Note that generics do not need to be specified if the default value suits your application.CORE Generator Parameter ScreensThe Divider core GUI provides three screens for selecting core parameters.•Main screen. Describes parameters common to both implementations, such as SCLR and CE, and allows the selection of the divider implementation.•Fixed-point implementation options. Provides configuration options for the fixed-point divider configuration. Note that this screen is displayed only if Fixed-point is selected on the main screen. •Floating-point implementation options. Provides configuration options for the floating-point divider configuration. Note that this screen is displayed only if Floating-point is selected on the main screen.16DS530 January 18, 2006Main Screen•Component Name. The base name of the output files generated for the core. Names must begin with a letter and be composed of any of the following characters: a to z, 0 to 9 and “_”.Figure 4: Main ScreenFixed-point Implementation OptionsFloating-point Implementation OptionsFigure 5: Fixed-point Implementation OptionsFigure 6: Floating-Point Implementation OptionsVerificationThe Divider core is supplied with a VHDL functional behavioral model, and the CORE Generator canalso produce a UniSim-based Verilog model if desired.SimulationWhen the Divider core is generated using the CORE Generator, a VHDL functional behavioral model is alsogenerated. The VHDL behavioral model is a pre-defined, parameterized model of the core, which is copiedto the project directory. A Verilog wrapper is also provided for the VHDL model for mixed-language simu-lation. If a Verilog model is selected, the CORE Generator produces a UniSim-based model of the core.Important Note: The VHDL Behavioral model provided for the floating-point solution does not exactlyreproduce the behavior of the synthesized core. The models quotients may differ by the least significant bitof the mantissa. For an exact match, the structural (UniSim) behavioral model must be used.References"Computer Arithmetic Algorithms and Hardware Designs," Behrooz Parhami. Oxford Press © 2000.LicensingThe Divider core does not require a license.Ordering InformationThis core may be downloaded from the Xilinx IP Center for use with the Xilinx CORE Generator systemv8.1i and higher. The Xilinx CORE Generator system is bundled with the ISE Foundation software at noadditional charge. To inquire about other Xilinx products, contact your local Xilinx sales representative.SupportXilinx provides technical support for this LogiCORE product when used as described in the productdocumentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented indevices not listed in the documentation, or if customized beyond that allowed in the productdocumentation, or if any changes are made in sections of design marked as DO NOT MODIFY.Related InformationXilinx products are not intended for use in life-support appliances, devices, or systems. Use of a Xilinxproduct in such application without the written consent of the appropriate Xilinx officer is prohibited.Revision HistoryDate Version Revision1/18/06 1.0Initial Xilinx release.18DS530 January 18, 2006。
