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DS090 (v2.5) June 28, 1Product Specification© 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at /legal.htm .All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.Features•Optimized for 1.8V systems-Industry’s fastest low power CPLD -Densities from 32 to 512 macrocells •Industry’s best 0.18 micron CMOS CPLD-Optimized architecture for effective logic synthesis -Multi-voltage I/O operation — 1.5V to 3.3V •Advanced system features-Fastest in system programming· 1.8V ISP using IEEE 1532 (JTAG) interface -On-The-Fly Reconfiguration (OTF)-IEEE1149.1 JTAG Boundary Scan Test -Optional Schmitt trigger input (per pin)-Multiple I/O banks on all devices-Unsurpassed low power management·DataGATE external signal control -Flexible clocking modes·Optional DualEDGE triggered registers ·Clock divider (÷ 2,4,6,8,10,12,14,16)·CoolCLOCK-Global signal options with macrocell control·Multiple global clocks with phase selection permacrocell ·Multiple global output enables ·Global set/reset-Abundant product term clocks, output enables andset/resets-Efficient control term clocks, output enables andset/resets for each macrocell and shared across function blocks-Advanced design security-Open-drain output option for Wired-OR and LEDdrive-Optional bus-hold, 3-state or weak pullup on selectI/O pins-Optional configurable grounds on unused I/Os-Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels on all parts -SSTL2_1,SSTL3_1, and HSTL_1 on 128macrocell and denser devices -Hot pluggable •PLA architecture-Superior pinout retention-100% product term routability across function block •Wide package availability including fine pitch:-Chip Scale Package (CSP) BGA, Fine Line BGA,TQFP , PQFP , VQFP , PLCC, and QFN packages -Pb-free available for all packages•Design entry/verification using Xilinx and industry standard CAE tools•Free software support for all densities using Xilinx WebPACK™•Industry leading nonvolatile 0.18 micron CMOS process-Guaranteed 1,000 program/erase cycles -Guaranteed 20 year data retention Family OverviewXilinx CoolRunner™-II CPLDs deliver the high speed and ease of use associated with the XC9500/XL/XV CPLD fam-ily with the extremely low power versatility of the XPLA3™family in a single CPLD. This means that the exact same parts can be used for high-speed data communications/computing systems and leading edge portable products,with the added benefit of In System Programming. Low power consumption and high-speed operation are com-bined into a single family that is easy to use and cost effec-tive. Clocking techniques and other power saving features extend the users’ power budget. The design features are supported starting with Xilinx ISE 4.1i ISE WebPACK. Addi-tional details can be found in Further Reading , page 13.Table 1 shows the macrocell capacity and key timing parameters for the CoolRunner-II CPLD family.CoolRunner-II CPLD FamilyDS090 (v2.5) June 28, 2005Product SpecificationTable 1: CoolRunner-II CPLD Family ParametersXC2C32AXC2C64AXC2C128XC2C256XC2C384XC2C512Macrocells 3264128256384512Max I/O 3364100184240270T PD (ns) 3.8 4.6 5.7 5.77.17.1T SU (ns) 1.9 2.0 2.4 2.4 2.9 2.6T CO (ns) 3.73.94.24.55.85.8F SYSTEM1 (MHz)323 263 244256 217 179元器件交易网2DS090 (v2.5) June 28, 2005Product SpecificationTable 2 shows key DC characteristics for the CoolRunner-II family.Table 3 shows the CoolRunner-II CPLD package offering with corresponding I/O count. All packages are surface mount, with over half of them being ball-grid technologies.The ultra tiny packages permit maximum functional capacity in the smallest possible area. The CMOS technology used in CoolRunner-II CPLDs generates minimal heat, allowing the use of tiny packages during high-speed operation.With the exception of the new Pb-free QF packages, there are at least two densities present in each package with three in the VQ100 (100-pin 1.0mm QFP) and TQ144(144-pin 1.4mm QFP), and in the FT256 (256-ball 1.0mm spacing FLBGA). The FT256 is particularly important for slim dimensioned portable products with mid- to high-den-sity logic requirements.Table 4 details the distribution of advanced features across the CoolRunner-II CPLD family. The family has uniform basic features with advanced features included in densities where they are most useful. For example, it is very unlikely that four I/O banks are needed on 32 and 64 macrocellparts, but very likely they are for 384 and 512 macrocell parts. The I/O banks are groupings of I/O pins using any one of a subset of compatible voltage standards that share the same V CCIO level. (See Table 5 for a summary of CoolRunner-II I/O standards.)Table 2: CoolRunner-II CPLD DC CharacteristicsXC2C32AXC2C64AXC2C128XC2C256XC2C384XC2C512I CC (µA), 0 MHz, 25°C (typical)161719212325I CC (mA), 50 MHz, 70°C (max)2.5510274555CC Table 3: CoolRunner-II CPLD Family Packages and I/O CountXC2C32XC2C32AXC2C64XC2C64AXC2C128XC2C256XC2C384XC2C512QFG32(1)21------PC4433333333----PCG44(1)3333----VQ4433333333----VQG44(1)3333----QFG48(1)---37----CP5633334545----CPG56(1)3345----VQ100--64648080--VQG100(1)--648080--CP132----100106--CPG132(1)----100106--TQ144----100118118-TQG144(1)----100118118-PQ208-----173173173PQG208(1)-----173173173FT256-----184212212FTG256(1)-----184212212FG324------240270FGG324(1)------240270Notes:1.The letter "G" as the third character indicates a Pb-free package.DS090 (v2.5) June 28, 3Product SpecificationArchitecture DescriptionCoolRunner-II CPLD is a highly uniform family of fast, lowpower CPLDs. The underlying architecture is a traditional CPLD architecture combining macrocells into Function Blocks (FBs) interconnected with a global routing matrix,the Xilinx Advanced Interconnect Matrix (AIM). The Func-tion Blocks use a Programmable Logic Array (PLA) config-uration which allows all product terms to be routed and shared among any of the macrocells of the FB. Design soft-ware can efficiently synthesize and optimize logic that is subsequently fit to the FBs and connected with the ability to utilize a very high percentage of device resources. Design changes are easily and automatically managed by the soft-ware, which exploits the 100% routability of the Program-mable Logic Array within each FB. This extremely robustbuilding block delivers the industry’s highest pinout reten-tion, under very broad design conditions. The architecture will be explained by expanding the detail as we discuss the underlying Function Blocks, logic and interconnect.The design software automatically manages these device resources so that users can express their designs using completely generic constructs without knowledge of these architectural details. More advanced users can take advan-tage of these details to more thoroughly understand the software’s choices and direct its results.Figure 1 shows the high-level architecture whereby Func-tion Blocks attach to pins and interconnect to each other within the internal interconnect matrix. Each FB contains 16macrocells. The BSC path is the JTAG Boundary Scan Con-Table 4: CoolRunner-II CPLD Family FeaturesXC2C32XC2C32AXC2C64 XC2C64AXC2C128XC2C256XC2C384XC2C512IEEE 1532✓✓✓✓✓✓✓✓I/O banks 12122244Clock division ----✓✓✓✓DualEDGE Registers ✓✓✓✓✓✓✓✓DataGATE ----✓✓✓✓LVTTL✓✓✓✓✓✓✓✓LVCMOS33, 25, 18, and 15(1)✓✓✓✓✓✓✓✓SSTL2_1----✓✓✓✓SSTL3_1----✓✓✓✓HSTL_1----✓✓✓✓Configurable ground ✓✓✓✓✓✓✓✓Quadruple data security✓✓✓✓✓✓✓✓Open drain outputs ✓✓✓✓✓✓✓✓Hot plugging ✓✓✓✓✓✓✓✓Schmitt Inputs✓✓✓✓✓✓✓✓4DS090 (v2.5) June 28, 2005Product Specificationtrol path. The BSC and ISP block has the JTAG controller and In-System Programming Circuits.Function BlockThe CoolRunner-II CPLD Function Blocks contain 16 mac-rocells, with 40 entry sites for signals to arrive for logic cre-ation and connection. The internal logic engine is a 56product term PLA. All Function Blocks, regardless of the number contained in the device, are identical. For a high-level view of the Function Block, see Figure 2.At the high level, it is seen that the product terms (p-terms)reside in a programmable logic array (PLA). This structureis extremely flexible, and very robust when compared to fixed or cascaded product term function blocks.Classic CPLDs typically have a few product terms available for a high-speed path to a given macrocell. They rely on capturing unused p-terms from neighboring macrocells to expand their product term tally, when needed. The result of this architecture is a variable timing model and the possibil-ity of stranding unusable logic within the FB.The PLA is different — and better. First, any product term can be attached to any OR gate inside the FB macrocell(s).Second, any logic function can have as many p-terms as needed attached to it within the FB, to an upper limit of 56.Third, product terms can be re-used at multiple macrocell OR functions so that within a FB, a particular logical product need only be created once, but can be re-used up to 16times within the FB. Naturally, this plays well with the fitting software, which identifies product terms that can be shared. The software places as many of those functions as it can into FBs, so it happens for free. There is no need to force macrocell functions to be adjacent or any other restriction save residing in the same FB, which is handled by the soft-ware. Functions need not share a common clock, common set/reset or common output enable to take full advantage of the PLA. Also, every product term arrives with the same time delay incurred. There are no cascade time adders for putting more product terms in the FB. When the FB product term budget is reached, there is a small interconnect timing penalty to route signals to another FB to continue creating logic. Xilinx design software handles all this automatically.Figure 1: CoolRunner-II CPLD ArchitectureFigure 2: CoolRunner-II CPLD Function BlockDS090 (v2.5) June 28, 5Product SpecificationMacrocellThe CoolRunner-II CPLD macrocell is extremely efficient and streamlined for logic creation. Users can develop sum of product (SOP) logic expressions that comprise up to 40inputs and span 56 product terms within a single function block. The macrocell can further combine the SOP expres-sion into an XOR gate with another single p-term expres-sion. The resulting logic expression’s polarity is also selectable. As well, the logic function can be pure combina-torial or registered, with the storage element operating selectably as a D or T flip-flop, or transparent latch. Avail-able at each macrocell are independent selections of glo-bal, function block level or local p-term derived clocks, sets,resets, and output enables. Each macrocell flip-flop is con-figurable for either single edge or DualEDGE clocking, pro-viding either double data rate capability or the ability to distribute a slower clock (thereby saving power). For single edge clocking or latching, either clock polarity may be selected per macrocell. CoolRunner-II macrocell details are shown in Figure 3. Note that in Figure 4, standard logic symbols are used except the trapezoidal multiplexers have input selection from statically programmed configuration select lines (not shown). Xilinx application note XAPP376gives a detailed explanation of how logic is created in the CoolRunner-II CPLD family.When configured as a D-type flip-flop, each macrocell has an optional clock enable signal permitting state hold while a clock runs freely. Note that Control Terms (CT) are available to be shared for key functions within the FB, and are gener-ally used whenever the exact same logic function would be repeatedly created at multiple macrocells. The CT product terms are available for FB clocking (CTC), FB asynchro-nous set (CTS), FB asynchronous reset (CTR), and FB out-put enable (CTE).Any macrocell flip-flop can be configured as an input regis-ter or latch, which takes in the signal from the macrocell’s I/O pin, and directly drives the AIM. The macrocell combina-tional functionality is retained for use as a buried logic node if needed. F Toggle is the maximum clock frequency to which a T flip-flop can reliably toggle.Advanced Interconnect Matrix (AIM)The Advanced Interconnect Matrix is a highly connected low power rapid switch. The AIM is directed by the software to deliver up to a set of 40 signals to each FB for the cre-ation of logic. Results from all FB macrocells, as well as, all pin inputs circulate back through the AIM for additional con-nection available to all other FBs as dictated by the designFigure 3: CoolRunner-II CPLD MacrocellDS090 (v2.5) June 28, 2005Product Specificationsoftware. The AIM minimizes both propagation delay and power as it makes attachments to the various FBs.I/O BlockI/O blocks are primarily transceivers. However, each I/O is either automatically compliant with standard voltage ranges or can be programmed to become so. See XAPP382 for detailed information on CoolRunner-II I/Os.In addition to voltage levels, each input can selectively arrive through Schmitt-trigger inputs. This adds a small time delay, but substantially reduces noise on that input pin.Approximately 500 mV of hysteresis will be added when Schmitt-trigger inputs are selected. All LVCMOS inputs can have hysteresis input. Hysteresis also allows easy genera-tion of external clock circuits. The Schmitt-trigger path is best seen in Figure 4. See Table 5 for Schmitt-trigger com-patibility with I/O standards.Outputs can be directly driven, 3-stated or open-drain con-figured. A choice of slow or fast slew rate output signal isalso available. Table 5 summarizes various supported volt-age standards associated with specific part capacities. All inputs and disabled outputs are voltage tolerant up to 3.3V.The CoolRunner-II family supports SSTL2-1, SSTL3-1 and HSTL-1 high-speed I/O standards in the 128-macrocell and larger devices. Figure 4 details the I/O pin, where it is noted that the inputs requiring comparison to an external refer-ence voltage are available. These I/O standards all require VREF pins for proper operation. The CoolRunner-II CPLD allows any I/O pin to act as a VREF pin, granting the board layout engineer extra freedom when laying out the pins.However, if VREF pin placement is not done properly,additional VREF pins may be required, resulting in a loss of potential I/O pins or board re-work. See XAPP399 for details regarding VREF pins and their placement.V REF has pin-range requirements that must be observed.The Xilinx software aids designers in remaining within the proper pin range.Table 5 summarizes the single ended I/O standard support and shows which standards require V REF values and board termination. V REF detail is given in specific data sheets.Figure 4: CoolRunner-II CPLD I/O Block DiagramTable 5: CoolRunner-II CPLD I/O Standard SummaryIOSTANDARD Attribute V CCIO Input V REFBoard Termination Voltage(V TT )Schmitt-trigger SupportLVTTL 3.3 N/A N/A Optional LVCMOS33 3.3 N/A N/A Optional LVCMOS25 2.5 N/A N/A Optional LVCMOS18 1.8 N/A N/A Optional LVCMOS15 1.5 N/A N/A Not optional HSTL_1 1.5 0.75 0.75Not optional SSTL2_1 2.5 1.25 1.25Not optional SSTL3_13.31.51.5Not optionalDS090 (v2.5) June 28, 7Product SpecificationOutput BankingCPLDs are widely used as voltage interface translators. To that end, the output pins are grouped in large banks. The XC2C32 and XC2C64 devices are not banked, but the new XC2C32A and XC2C64A devices have two banks. The medium parts (128 and 256 macrocell) support two output banks. With two, the outputs will switch to one of two selected output voltage levels, unless both banks are set to the same voltage. The larger parts (384 and 512 macrocell)support four output banks split evenly. They can support groupings of one, two, three or four separate output voltage levels. This kind of flexibility permits easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V in a single part.DataGATELow power is the hallmark of CMOS technology. Other CPLD families use a sense amplifier approach to creating product terms, which always has a residual current compo-nent being drawn. This residual current can be several hun-dred milliamps, making them unusable in portable systems.CoolRunner-II CPLDs use standard CMOS methods to cre-ate the CPLD architecture and deliver the corresponding low current consumption, without doing any special tricks.However, sometimes designers would like to reduce their system current even more by selectively disabling circuitry not being used.The patented DataGATE technology was developed to per-mit a straightforward approach to additional power reduc-tion. Each I/O pin has a series switch that can block the arrival of free running signals that are not of interest. Sig-nals that serve no use may increase power consumption,and can be disabled. Users are free to do their design, then choose sections to participate in the DataGATE function.DataGATE is a logic function that drives an assertion rail threaded through the medium and high-density CoolRunner-II CPLD parts. Designers can select inputs to be blocked under the control of the DataGATE function,effectively blocking controlled switching signals so they do not drive internal chip capacitances. Output signals that do not switch, are held by the bus hold feature. Any set of input pins can be chosen to participate in the DataGATE function.Figure 5 shows the familiar CMOS I CC versus switching fre-quency graph. With DataGATE, designers can approach zero power, should they choose to, in their designs Figure 6 shows how DataGATE basically works. One I/O pin drives the DataGATE Assertion Rail. It can have any desired logic function on it. It can be as simple as mapping an input pin to the DataGATE function or as complex as a counter or state machine output driving the DataGATE I/O pin through a macrocell. When the DataGATE rail is asserted high, any pass transistor switch attached to it is blocked. Note that each pin has the ability to attach to theAIM through a DataGATE pass transistor, and thus be blocked. A latch automatically captures the state of the pin when it becomes blocked. The DataGATE Assertion Rail threads throughout all possible I/Os, so each can participate if chosen. Note that one macrocell is singled out to drive the rail, and that macrocell is exposed to the outside world through a pin, for inspection. If DataGATE is not needed,this pin is an ordinary I/O.Figure 5: CMOS I CC vs. Switching Frequency CurveDS090 (v2.5) June 28, 2005Product SpecificationGlobal SignalsGlobal signals, clocks (GCK), sets/resets (GSR) and output enables (GTS), are designed to strongly resemble each other. This approach enables design software to make the best utilization of their capabilities. Each global capability is supplemented by a corresponding product term version.Figure 7 shows the common structure of the global signal trees. The pin input is buffered, then drives multiple internal global signal traces to deliver low skew and reduce loading delays. The DataGATE assertion rail is also a global signal.Additional Clock Options: Division, DualEDGE, and CoolCLOCKDivisionCircuitry has been included in the CoolRunner-II CPLD architecture to divide one externally supplied global clock by standard values. Division by 2,4,6,8,10, 12, 14 and 16are the options (see Figure 8). This capability is supplied on the GCK2 pin. The resulting clock produced will be 50%duty cycle for all possible divisions. Note that a Synchro-nous Reset (CDRST) is included to guarantee no runt clocks can get through to the global clock nets. Note that again, the signal is buffered and driven to multiple traces with minimal loading and skew.DualEDGEEach macrocell has the ability to double its input clock switching frequency. Figure 9 shows the macrocell flip-flop with the DualEDGE option (doubled clock) at each macro-cell. The source to double can be a control term clock, a product term clock or one of the available global clocks. The ability to switch on both clock edges is vital for a number of synchronous memory interface applications as well as cer-tain double data rate I/O applications.Figure 6: DataGATE Architecture (output drivers not shown)Figure 7: Global Clocks (GCK), Sets/Resets (GSR) andOutput Enables (GTS)DS090 (v2.5) June 28, 9Product SpecificationCoolCLOCKIn addition to the DualEDGE flip-flop, additional power sav-ings can be had by combining the clock division circuitry with the DualEDGE circuitry. This capability is called Cool-CLOCK and is designed to reduce clocking power within the CPLD. Because the clock net can be an appreciable powerdrain, the clock power can be reduced by driving the net at half frequency, then doubling the clock rate using DualEDGE triggering at the macrocells. Figure 10 shows how CoolCLOCK is created by internal clock cascading with the divider and DualEDGE flip-flop working together. See XAPP378 for more detail.Figure 8: Clock Division Circuitry for GCK2Figure 9: Macrocell Clock Chain with DualEDGE Option ShownFigure 10: CoolCLOCK Created by Cascading Clock Divider and DualEDGE OptionDS090 (v2.5) June 28, 2005Product SpecificationDesign SecurityDesigns can be secured during programming to prevent either accidental overwriting or pattern theft via readback.Four independent levels of security are provided on-chip,eliminating any electrical or visual detection of configuration patterns. These security bits can be reset only by erasing the entire device. See WP170 for more detail.Timing ModelFigure 11 shows the CoolRunner-II CPLD timing model. It represents one aspect of the overall architecture from a tim-ing viewpoint. Each little block is a time delay that a signal will incur if the signal passes through such a resource. Tim-ing reports are created by tallying the incremental signal delays as signals progress within the CPLD. Software cre-ates the timing reports after a design has been mapped onto the specific part, and knows the specific delay values for a given speed grade. Equations for the higher level tim-ing values (i.e., T PD and F SYSTEM ) are available. Table 6summarizes the individual parameters and provides a brief definition of their associated functions.Xilinx application note XAPP375 details the CoolRunner-II CPLD family tim-ing with several examples.Figure 11: CoolRunner-II CPLD Timing ModelTable 6: Timing Parameter Definitions Symbol ParameterBuffer DelaysT lN Input Buffer DelayT DIN Direct data register input delay T GCK Global clock (GCK) buffer delay T GSR Global set/reset (GSR) buffer delay T GTS Global output enable (GTS) buffer delay T OUT Output buffer delayT EN Output buffer enable/disable delay T SLEW Output buffer slew rate control delay P-term Delays T CT Control Term delay (single PT or FB-CT)T LOGI1Single P-term logic delay T LOGI2Multiple P-term logic delay adderMacrocell DelaysT PDI Macro cell input to output valid T SUI Macro register setup before clock T HI Macro register hold after clock T ECSU Macro register enable clock setup time T ECHO Macro register enable clock hold time T COI Macro register clock to output valid T AOI Macro register set/reset to output valid T HYS Hysteresis selection delay adder Feedback DelaysT F Feedback delayT OEMMacrocell to Global OE delayTable 6: Timing Parameter Definitions (Continued)Symbol ParameterProgrammingThe programming data sequence is delivered to the device using either Xilinx iMPACT software and a Xilinx download cable, a third-party JTAG development system, a JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. The iMPACT software also outputs serial vector format (SVF) files for use with any tools that accept SVF format, including automatic test equipment. See CoolRunner-II Application Notes for more information on how to program.In System ProgrammingAll CoolRunner-II CPLD parts are 1.8V in system program-mable. This means they derive their programming voltage and currents from the 1.8V V CC (internal supply voltage) pins on the part. The V CCIO pins do not participate in this operation, as they may assume another voltage ranging as high as 3.3V down to 1.5V. A 1.8V V CC is required to prop-erly operate the internal state machines and charge pumps that reside within the CPLD to do the nonvolatile program-ming operations. The JTAG interface buffers are powered by a dedicated power pin, V CCAUX, which is independent of all other supply pins. V CCAUX must be connected. Xilinx software is provided to deliver the bit-stream to the CPLD and drive the appropriate IEEE 1532 protocol. To that end, there is a set of IEEE 1532 commands that are supported in the CoolRunner-II CPLD parts. Programming times are less than one second for 32 to 256 macrocell parts. Program-ming times are less than four seconds for 384 and 512 mac-rocell parts. Programming of CoolRunner-II CPLDs is only guaranteed when operating in the commercial temperature and voltage ranges as defined in the device-specific data sheets.On-The-Fly Reconfiguration (OTF)Xilinx ISE 5.2i supports OTF for CoolRunner-II CPLDs. This permits programming a new nonvolatile pattern into the part while another pattern is currently in use. OTF has the same voltage and temperature specifications as system program-ming. During pattern transition I/O pins are in high imped-ance with weak pullup to V CCIO. Transition time typically lasts between 50 and 300 µs, depending on density. See XAPP388 for more information.JTAG InstructionsTable7 shows the commands available to users. These same commands may be used by third party ATE products,as well. The internal controllers can operate as fast as 66 MHz.Power-Up CharacteristicsCoolRunner-II CPLD parts must operate under the demands of both the high-speed and the portable market places, therefore, they must support hot plugging for the high-speed world and tolerate most any power sequence to its various voltage pins. They must also not draw excessive current during power-up initialization. To those ends, the general behavior is summarized as follows:1.I/O pins are disabled until the end of power-up.2.As supply rises, configuration bits transfer fromnonvolatile memory to SRAM cells.3.As power up completes, the outputs become asconfigured (input, output, or I/O).4.For specific configuration times and power uprequirements, see the device specific data sheet. CoolRunner-II CPLD I/O pins are well behaved under all operating conditions. During power-up, CoolRunner-II devices employ internal circuitry which keeps the devices in the quiescent state until the V CCINT supply voltage is at a safe level (approximately 1.3V). In the quiescent state, JTAG pins are disabled, and all device outputs are disabled with the pins weakly pulled high, as shown in Table8. When the supply voltage reaches a safe level, all user registers become initialized, and the device is immediately available for operation, as shown in Figure12. Best results are obtained with a smooth V CC rise in less than 4 ms. Final V CC value should occur within 1 second.If the device is in the erased state (before any user pattern is programmed), the device outputs remain disabled with a weak pull-up. The JTAG pins are enabled to allow the Table 7: JTAG InstructionsCode Instruction Description 00000000EXTEST Force boundary scan data ontooutputs00000011PRELOAD Latch macrocell data intoboundary scan cells11111111BYPASS Insert bypass register betweenTDI and TDO00000010INTEST Force boundary scan data ontoinputs and feedbacks 00000001IDCODE Read IDCODE11111101USERCODE Read USERCODE11111100HIGHZ Force output into highimpedance state11111010CLAMP Latch present output state。

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Siemens AGDigital Industries Postfach 48 4890026 NÜRNBERG C79000-G8952-C442-14Ⓟ 02/2023 本公司保留更改的权利Copyright © Siemens AG 2016 - 2023.保留所有权利目录1简介 (7)2安全须知 (15)3安全建议 (17)4设备描述 (25)4.1产品总览 (25)4.2设备视图 (31)4.2.1SCALANCE XC206-2 (ST/BFOC) (31)4.2.2SCALANCE XC206-2 (SC) (32)4.2.3SCALANCE XC206-2G PoE (33)4.2.4SCALANCE XC206-2SFP (34)4.2.5SCALANCE XC208 (35)4.2.6SCALANCE XC208G PoE (36)4.2.7SCALANCE XC216 (37)4.2.8SCALANCE XC216-3G PoE (38)4.2.9SCALANCE XC216-4C (38)4.2.10SCALANCE XC224 (40)4.2.11SCALANCE XC224-4C (41)4.3附件 (41)4.4SELECT/SET 按钮 (47)4.5LED 指示灯 (49)4.5.1总览 (49)4.5.2“RM”LED (50)4.5.3“SB”LED (50)4.5.4“F”LED (50)4.5.5LED“DM1”和“DM2” (51)4.5.6LED“L1”和“L2” (51)4.5.7端口 LED (52)4.6C-PLUG (54)4.6.1C-PLUG 的功能 (54)4.6.2更换 C-PLUG (56)4.7组合端口 (57)4.8以太网供电 (PoE) (58)4.8.1符合标准的电源和电压范围 (58)4.8.2设备的 PoE 属性 (59)4.8.3电源传输和引脚分配 (30 W) (61)SCALANCE XC-200目录4.8.4电源传输和引脚分配 (60 W) (62)4.8.5组态 (62)5组装和拆卸 (63)5.1安装的安全注意事项 (63)5.2关于 SFP 收发器的一般说明 (66)5.3安装类型 (66)5.4在 DIN 导轨上安装 (67)5.4.1基于固定板的凹顶导轨安装 (67)5.4.2无固定板时的凹顶导轨安装 (69)5.5在标准 S7-300 导轨上安装 (70)5.5.1在带有固定板的标准导轨 S7-300 上安装 (70)5.5.2在不带固定板的标准导轨 S7-300 上安装 (71)5.6在标准导轨 S7-1500 上安装 (72)5.6.1在带有固定板的标准导轨 S7-1500 上安装 (72)5.6.2在不带固定板的标准导轨 S7-1500 上安装 (74)5.7基于固定板的墙式安装 (75)5.8更改固定销的位置 (76)5.9拆卸 (77)6连接 (79)6.1不使用 PoE 的设备的安全注意事项 (79)6.2PoE 设备的安全注意事项 (80)6.3有关在危险场所使用的安全注意事项 (82)6.4附加说明 (85)6.5接线规则 (86)6.624 V DC 电源 (87)6.754 V DC 电源 (88)6.8信号触点 (90)6.9功能性接地 (91)6.10串口 (92)6.11工业以太网 (94)6.11.1电气 (94)6.11.2光纤 (95)SCALANCE XC-200目录7维护和清洁 (97)8故障排除 (99)8.1使用 TFTP 下载新固件（无需 WBM 和 CLI） (99)8.2恢复出厂设置 (100)9技术规范 (101)9.1SCALANCE XC206-2 (ST/BFOC) 的技术规范 (101)9.2SCALANCE XC206-2 (SC) 的技术规范 (104)9.3SCALANCE XC206-2G PoE 的技术规范 (107)9.4SCALANCE XC206-2G PoE (54 V) 的技术规范 (110)9.5SCALANCE XC206-2G PoE EEC (54 V) 的技术规范 (113)9.6SCALANCE XC206-2SFP 的技术规范 (116)9.7SCALANCE XC206-2SFP G 的技术规范 (119)9.8SCALANCE XC206-2SFP EEC 的技术规范 (122)9.9SCALANCE XC206-2SFP G EEC 的技术规范 (125)9.10SCALANCE XC208 的技术规范 (128)9.11SCALANCE XC208G 的技术规范 (130)9.12SCALANCE XC208G PoE 的技术规范 (132)9.13SCALANCE XC208G PoE (54 V) 的技术规范 (134)9.14SCALANCE XC208EEC 的技术规范 (136)9.15SCALANCE XC208G EEC 的技术规范 (138)9.16SCALANCE XC216 的技术规范 (140)9.17SCALANCE XC216EEC 的技术规范 (142)9.18SCALANCE XC216-3G PoE 的技术规范 (144)9.19SCALANCE XC216-3G PoE (54 V) 的技术规范 (146)9.20SCALANCE XC216-4C 的技术规范 (150)9.21SCALANCE XC216-4C G 的技术规范 (153)9.22SCALANCE XC216-4C G EEC 的技术规范 (156)9.23SCALANCE XC224 的技术规范 (159)9.24SCALANCE XC224-4C G 的技术规范 (161)9.25SCALANCE XC224-4C G EEC 的技术规范 (164)9.26机械稳定性（运行时） (167)SCALANCE XC-200目录9.27射频辐射符合 NAMUR NE21 标准 (167)9.28电缆长度 (167)9.29交换特性 (168)10尺寸图 (171)11证书和认证 (179)索引 (189)SCALANCE XC-200简介1操作说明的用途这些操作说明适用于 SCALANCE XC-200 系列产品的安装和连接。

TECHNOLOGY MOVES FAST. WE MOVE FASTER.* Under Construction / ** Authorized for ConstructionSUBMARINESUse of DoD visual information does not imply or constituent DoD endorsement.LOS ANGELES CLASS> SSN 717 Olympia > SSN 719 Providence > SSN 720 Pittsburgh > SSN 721 Chicago > SSN 722 Key West> SSN 723 Oklahoma City > SSN 724 Louisville > SSN 725 Helena> SSN 750 Newport News > SSN 751 San Juan > SSN 752 Pasadena > SSN 753 Albany > SSN 754 Topeka > SSN 756 Scranton > SSN 757 Alexandria > SSN 758 Asheville> SSN 759 Jefferson City > SSN 760 Annapolis > SSN 761 Springfield > SSN 762 Columbus > SSN 763 Santa Fe > SSN 764 Boise> SSN 765 Montpelier > SSN 766 Charlotte > SSN 767Hampton> SSN 768 Hartford > SSN 769 Toledo > SSN 770 Tucson > SSN 771 Columbia > SSN 772 Greeneville > SSN 773CheyenneVIRGINIA CLASS> SSN 774 Virginia > SSN 775 Texas > SSN 776 Hawaii> SSN 777 North Carolina > SSN 778 New Hampshire > SSN 779 New Mexico > SSN 780 Missouri > SSN 781 California > SSN 782 Mississippi > SSN 783 Minnesota > SSN 784 North Dakota > SSN 785 John Warner > SSN 786 Illinois> SSN 787 Washington > SSN 788 Colorado > SSN 789 Indiana> SSN 790 South Dakota > SSN 791Delaware> SSN 792 Vermont > SSN 793 Oregon*> SSN 794 Montana*> SSN 795 Hyman G Rickover*> SSN 796 New Jersey*> SSN 797 Iowa*> SSN 798 Massachusetts*> SSN 799 Idaho*> SSN 800 Arkansas*> SSN 801 Utah*> SSN 802 Oklahoma*> SSN 803 Arizona*> SSN 804 Barb*> SSN 805 Tang**> SSN 806 WAHOO**> SSN 807 (Unnamed)**> SSN 808 (Unnamed)**> SSN 809 (Unnamed)**> SSN 810(Unnamed)**FAST ATTACK (SSN)SEAWOLF CLASS> SSN 21 Seawolf > SSN 22 Connecticut > SSN 23Jimmy CarterGUIDED MISSILE (SSGN)OHIO CLASS> SSGN 726 Ohio > SSGN 727 Michigan > SSGN 728 Florida > SSGN 729GeorgiaBALLISTIC MISSILE (SSBN)OHIO CLASS> SSBN 730 Henry M Jackson > SSBN 731 Alabama > SSBN 732 Alaska > SSBN 733 Nevada > SSBN 734 Tennessee > SSBN 735 Pennsylvania > SSBN 736 West Virginia > SSBN 740 Rhode Island > SSBN 741 Maine > SSBN 742 Wyoming > SSBN 743 Louisiana > SSBN 737 Kentucky > SSBN 738 Maryland > SSBN 739 Nebraska> SSBN 826 USS Columbia**> SSBN 827USS Wisconsin**CAPABILITIES> Integrated C5ISR Systems - Integrated & AutomatedCommunications - Navigation & Management - Alarm & Announcing Systems - Bridge & Navigation Systems > Tactical Information Assurance Solutions> EW / SIGINT Systems > Ship Control & Propulsion Systems > Crypto, Key Management & Network Security Solutions > Automatic Information Systems> Defense & Security Unmanned Surface Vehicles (USV)> Commercial & Scientific USVs > Unmanned Vessel Conversion > Aluminum-Water Power Solutions > UUV Fuel Cell C5 SYSTEMS> Integrated Platform Management Systems > Nuclear Power Plant Simulators> Space Robotics Operations Training> Battle Damage Control System > Submarine Systems / Training > Visual Landing Aids / Naval Handling Systems > Mine Warfare Systems > Maritime EW / RF Mics > Electronic Systems & I ntegration> Underwater Communications > Multi-domain Situational Awareness> Hydrographic Systems> Defense & Security Unmanned Surface Vehicles (USV)> Commercial & Scientific USVs > Unmanned Vessel Conversion INTERNATIONALUse of DoD visual information does not imply or constituent DoD endorsement.CRUISERS (CG)TICONDEROGA CLASS> CG 52 Bunker Hill > CG 53 Mobile Bay > CG 54 Antietam > CG 55 Leyte Gulf > CG 56 San Jacinto> CG 57 Lake Champlain > CG 58 Philippine Sea > CG 59 Princeton > CG 60 Normandy > CG 61 Monterey> CG 62 Chancellorsville > CG 63 Cowpens > CG 64 Gettysburg > CG 65 Chosin > CG 66 Hue City > CG 67 Shiloh > CG 68 Anzio > CG 69 Vicksburg > CG 70 Lake Erie> CG 71 Cape St. George > CG 72 Vella Gulf > CG 73Port RoyalGUIDED MISSILE FRIGATE (FFG)FFG 62 Constellation**FFG 63 Congress**LITTORAL COMBAT SHIP (LCS)> LCS 1 Freedom> LCS 2 Independence > LCS 3 Fort Worth > LCS 4 Coronado > LCS 5 Milwaukee > LCS 6 Jackson > LCS 7 Detroit> LCS 8 Montgomery > LCS 9 Little Rock> LCS 10 Gabrielle Giffords > LCS 11 Sioux City > LCS 12 Omaha > LCS 13 Wichita > LCS 14 Manchester > LCS 15Billings> LCS 16 Tulsa> LCS 17 Indianapolis > LCS 18 Charleston > LCS 19 St Louis > LCS 20 Cincinnati > LCS 27 Nantucket*> LCS 28 Savannah*> LCS 29 Beloit*> LCS 30 Canberra*> LCS 31 Cleveland**> LCS 32 Santa Barbara**> LCS 34 Augusta*> LCS 36 Kingsville**> LCS 38 Pierre**DESTROYERS (DDG)ARLEIGH BURKE CLASS> DDG 51 Arleigh Burke > DDG 52 Barry> DDG 53 John Paul Jones > DDG 54 Curtis Wilbur > DDG 55 Stout> DDG 56 John S McCain > DDG 57 Mitscher > DDG 58 Laboon > DDG 59 Russell> DDG 60 Paul Hamilton > DDG 61 Ramage > DDG 62 Fitzgerald > DDG 63 Stethem > DDG 64 Carney > DDG 65 Benfold > DDG 66 Gonzalez > DDG 67 Cole> DDG 68 The Sullivans > DDG 69 Milius > DDG 70 Hopper > DDG 71 Ross > DDG 72 Mahan > DDG 73 Decatur > DDG 74 McFaul> DDG 75 Donald Cook > DDG 76 Higgins > DDG 77 O’kane > DDG 78 Porter> DDG 79 Oscar Austin > DDG 80 Roosevelt> DDG 81Winston S Churchill> DDG 82 Lassen > DDG 83 Howard > DDG 84 Bulkeley > DDG 85 McCampbell > DDG 86 Shoup > DDG 87 Mason > DDG 88 Preble > DDG 89 Mustin > DDG 90 Chafee > DDG 91 Pinckney > DDG 92 Momsen > DDG 93 Chung-hoon > DDG 94 Nitze> DDG 95 James E Williams > DDG 96 Bainbridge > DDG 97 Halsey> DDG 98 Forrest Sherman > DDG 99 Farragut > DDG 100 Kidd > DDG 101 Gridley > DDG 102 Sampson > DDG 103 Truxtun > DDG 104 Sterett > DDG 105 Dewey > DDG 106 Stockdale > DDG 107 Gravely> DDG 108 Wayne E Meyer > DDG 109 Jason Dunham> DDG 110 William P Lawrence > DDG 111 Spruance> DDG 112 Michael Murphy > DDG 113 John Finn> DDG 114 Ralph Johnson > DDG 115 Rafael Peralta > DDG 116 Thomas Hudner > DDG 117 Paul Ignatius > DDG 118 Daniel Inouye*> DDG 119 Delbert D Black*> DDG 120 Carl M Levin*> DDG 121 Frank E Petersen Jr*> DDG 122 John Basilone*> LCS 21 Minneapolis/St. Paul*> LCS 22 Kansas City > LCS 23 Cooperstown*> LCS 24 Oakland > LCS 25 Marinette*> LCS 26 Mobile*> DDG 128 Ted Stevens*> DDG 129 Jeramiah Denton**> DDG 130 William Charette**> DDG 131 George M Neal**> DDG 132 Quetin Walsk**> DDG 133 Sam Nunn**> DDG 134 John E Kilmer**> DDG 135 (Unnamed)**> DDG 136 (Unnamed)**> DDG 137 John F Lehman**> DDG 138 (Unnamed)**> DDG 139 (Unnamed)**DDG ZUMWALT CLASS> DDG 1000 Zumwalt> DDG 1001 Michael Monsoor > DDG 1002 Lyndon B Johnson*SURFACE COMBATANTSAIRCRAFT CARRIERSAIRCRAFT CARRIERS (CVN)NIMITZ CLASS> CVN 68 Nimitz> CVN 69 Dwight D Eisenhower > CVN 70 Carl Vinson> CVN 71 Theodore Roosevelt > CVN 72 Abraham Lincoln > CVN 73 George Washington > CVN 74 John C Stennis > CVN 75 Harry S Truman > CVN 76 Ronald Reagan > CVN 77George H W BushFORD CLASS> CVN 78 Gerald R Ford > CVN 79 John F Kennedy*> CVN 80 Enterprise*> CVN 81Doris Miller*** Under Construction / ** Authorized for ConstructionAMPHIBIOUS WARFARE SHIPS Use of DoD visual information does not imply or constituent DoD endorsement.COMMAND (LCC)BLUE RIDGE CLASS> LCC 19 Blue Ridge> LCC 20 Mount Whitney ASSAULT SHIPS (LHA, LHD)TARAWA CLASS> LHA 6 America> LHA 7 Tripoli> LHA 8 Bougainville* WASP CLASS> LHD 1 Wasp> LHD 2 Essex> LHD 3 Kearsarge> LHD 4 Boxer> LHD 5 Bataan> LHD 6 Bonhomme Richard > LHD 7 Iwo Jima> LHD 8 Makin Island SAN ANTONIO CLASS> LPD 17 San Antonio> LPD 18 New Orleans> LPD 19 Mesa Verde> LPD 20 Green Bay> LPD 21 New York> LPD 22 San Diego> LPD 23 Anchorage> LPD 24 Arlington> LPD 25 Somerset> LPD 26 John P Murtha> LPD 27 Portland> LPD 28 Ft. Lauderdale*> LPD 29 Richard M McCool Jr*> LPD 30 Harrisburg**> LPD 31 (Unnamed)**DOCK LANDING (LSD)WHIDBEY ISLAND CLASS> LSD 41 Whidbey Island> LSD 42 Germantown> LSD 43 Fort McHenry> LSD 44 Gunston Hall> LSD 45 Comstock> LSD 46 Tortuga> LSD 47 Rushmore> LSD 48 AshlandHARPERS FERRY CLASS> LSD 49 Harpers Ferry> LSD 50 Carter Hall> LSD 51 Oak Hall> LSD 52 Pearl HarborMINE COUNTER MEASURES (MCM)AVENGER CLASS> MCM 3 Sentry> MCM 6 Devastator> MCM 7 Patriot> MCM 9 Pioneer> MCM 10 Warrior> MCM 11 Gladiator> MCM 13 Dextrous> MCM 14 ChiefCAPABILITIES> Submarine, Imaging Systems & Consoles, and Radar> Surface Imaging Systems> Fleet Support Services / Marine Services> Dipping Sonar Systems> Towed Array Systems> Bottom Mounted Active & Passive Integrated Hydrophone System> Acoustic Systems> Maritime and Training and > Ocean Observatories> Underwater AcousticCommunications> Undersea Sensor Systems > Unmanned Underwater Vehicles (UUV)> Custom Payloads> Mission Planning Software > C2 Theater ASW Systems > Common Operational Picture Tools> C2 Systems and SystemsSENSORS> Electrical Auxiliary Propulsion> Specialty Submarine Products> Support Services > Power Conversion Modules- Advanced Degaussing- Automatic Bus Transfer- Frequency Converters- AC to DC Rectifiers- Fault Isolation> Circuit Breakers> Switchboards and Load Centers > Power Node Control Centers > Support ServicesSERVICES POWERUse of DoD visual information does not imply or constituent DoD endorsement.NATIONAL SECURITY CUTTERS (WMSL)418-FOOT-LEGEND CLASS > WMSL 750 Bertholf> WMSL 751 Waesche> WMSL 752 Stratton> WMSL 753 Hamilton> WMSL 754 James> WMSL 755 Munro> WMSL 756 Kimball> WMSL 757 Midgett> WMSL 758 Stone*> WMSL 759 Calhoun*> WMSL 760 Friedman* ICEBREAKERS (WAGB) 420-FOOT> WAGB 20 Healy399-FOOT> WAGB 10 Polar Star240-FOOT> WLBB 30 Mackinaw HIGH ENDURANCE CUTTERS (WHEC)378-FOOT-HAMILTON CLASS> WHEC 717 Mellon> WHEC 724 Munro> WHEC 726 Midgett MEDIUM ENDURANCE CUTTERS (WMEC)282-FOOT> WMEC 39 Alex Haley270-FOOT> WMEC 901 Bear> WMEC 902 Tampa> WMEC 903 Harriet Lane> WMEC 904 Northland > WMEC 905 Spencer> WMEC 906 Seneca> WMEC 907 Escanaba> WMEC 908 Tahoma> WMEC 909 Campbell> WMEC 910 Thetis> WMEC 911 Forward> WMEC 912 Legare> WMEC 913 Mohawk210-FOOT> WMEC 615 Reliance> WMEC 616 Diligence> WMEC 617 Vigilant> WMEC 618 Active> WMEC 619 Confidence> WMEC 620 Resolute> WMEC 621 Valiant> WMEC 623 Steadfast> WMEC 624 Dauntless> WMEC 625 Venturous> WMEC 626 Dependable> WMEC 627 Vigorous> WMEC 629 Decisive> WMEC 630 AlertSEAGOING BUOY TENDER(WLB)225-FOOT> WLB 201 Juniper> WLB 202 Willow> WLB 203 Kukui> WLB 204 Elm> WLB 205 Walnut> WLB 206 Spar> WLB 207 Maple> WLB 208 Aspen> WLB 209 Sycamore> WLB 210 Cypress> WLB 211 Oak> WLB 212 Hickory> WLB 213 Fir> WLB 214 Hollyhock> WLB 215 Sequoia> WLB 216 AlderCOASTAL BUOY TENDER(WLM)175-FOOT> WLM 551 Ida Lewis> WLM 552 Katherine Walker> WLM 553 Abbie Burgess> WLM 554 Marcus Hanna> WLM 555 James Rankin> WLM 556 Joshua Applebey> WLM 557 Frank Drew> WLM 558 Anthony Petit> WLM 559 Barbara Mabrity> WLM 560 William Tate> WLM 561 Harry Clairborne> WLM 562 Maria Bray> WLM 563 Henry Blake> WLM 564 George CobbINLAND CONSTRUCTIONTENDERS (WLIC)160-FOOT> WLIC 800 Pamlico> WLIC 801 Hudson> WLIC 802 Kennebec> WLIC 803 Saginaw100-FOOT> WLIC 315 SmilaxPATROL CUTTERS (WPC)154-FOOT-SENTINEL CLASS> WPC 1101 Bernard C Webber> WPC 1102 Richard Etheridge> WPC 1103 William Flores> WPC 1104 Robert Yered> WPC 1105 Margaret Norvell> WPC 1106 Paul Clark> WPC 1107 Charles David Jr> WPC 1108 Charles Sexton> WPC 1109 Kathleen Moore> WPC 1110 Raymond Evans> WPC 1111 William Trump> WPC 1112 Issac Mayo> WPC 1113 Richard Dixon> WPC 1114 Heriberto Hernandez> WPC 1115 Joseph Napier> WPC 1116 Winslow W Griesser> WPC 1117 Donald Horsley> WPC 1118 Joseph Tezanos> WPC 1119 Rollin A Fritch> WPC 1120 Lawrence O Lawson> WPC 1121 John F McCormick> WPC 1122 Bailey T Barco> WPC 1123 Benjamin B Dailey> WPC 1124 Oliver F Berry> WPC 1125 Jacob L.A. Poroo> WPC 1126 Joseph Gercezak> WPC 1127 Richard T Snyder> WPC 1128 Nathan Bruckenthal> WPC 1129 Forrest O Rednour> WPC 1130 Robert G Ward> WPC 1131 Terrell Horne III> WPC 1132 Benjamin A Bottoms> WPC 1133 Joseph O Doyle> WPC 1134 William C Hart> WPC 1135 Angela McShan> WPC 1136 Daniel Tarr> WPC 1137 Edgar Culbertson> WPC 1138 Harold Miller> WPC 1139 Myrtle Hazard> WPC 1140 Oliver Henry> WPC 1141 Charles Moulthrop> WPC 1142 Robert Goldman*> WPC 1143 Frederick Hatch*> WPC 1144 Glenn Harris*> WPC 1145 Emlen Tunnell*> WPC 1146 John Scheuerman*> WPC 1147 Clarence Sutphin*> WPC 1148 Pablo Valent*> WPC 1149 Douglas Denman*> WPC 1150 William Chadwick*> WPC 1151 Warren Deyampert*> WPC 1152 Maurice Jester*> WPC 1153 John Patterson*> WPC 1154 William Sparling*> WPC 1155 Melvin Bell*> WPC 1156 David Duren*> WPC 1157 Florence Finch**> WPC 1158 John Witherspoon**> WPC 1159 Earl Cunningham**> WPC 1160 Frederick Mann**COAST GUARD CUTTERSUse of DoD visual information does not imply or constituent DoD endorsement.ICEBREAKING TUG (WTGB)140-FOOT> WTGB 101 Katmai Bay> WTGB 102 Bristol Bay> WTGB 103 Mobile Bay> WTGB 104 Biscayne Bay> WTGB 105 Neah Bay> WTGB 106 Morro Bay> WTGB 107 Penobscot Bay > WTGB 108 Thunder Bay> WTGB 109 Sturgeon Bay PATROL BOAT (WPB) 110-FOOT> WPB 1304 Maui> WPB 1307 Ocracoke> WPB 1309 Aquidneck> WPB 1310 Mustang> WPB 1311 Naushon> WPB 1312 Sanibel> WPB 1313 Edisto> WPB 1318 Baranof> WPB 1319 Chandeleur> WPB 1322 Cuttyhunk> WPB 1324 Key Largo> WPB 1326 Monomoy> WPB 1327 Orcas> WPB 1329 Sitkinak> WPB 1330 Tybee> WPB 1331 Washington> WPB 1332 Wrangell> WPB 1333 Adak> WPB 1334 Liberty> WPB 1335 Anacapa> WPB 1336 Kiska> WPB 1349 Galveston Island INLAND BUOY TENDERS (WLI)100-FOOT> WLI 313 Bluebell> WLI 642 Buckthorn COASTAL PATROLBOATS (WPB)87-FOOT - MARINEPROTECTOR CLASS> WPB 87301 Barracuda> WPB 87302 Hammerhead> WPB 87303 Mako> WPB 87304 Marlin> WPB 87305 Stingray> WPB 87306 Dorado> WPB 87307 Osprey> WPB 87308 Chinook> WPB 87309 Albacore> WPB 87310 Tarpon> WPB 87311 Cobia> WPB 87312 Hawksbill> WPB 87313 Cormorant> WPB 87314 Finback> WPB 87315 Amberjack> WPB 87316 Kittiwake> WPB 87317 Blackfin> WPB 87318 Bluefin> WPB 87319 Yellowfin> WPB 87320 Manta> WPB 87321 Coho> WPB 87322 Kingfisher> WPB 87323 Seahawk> WPB 87324 Steelhead> WPB 87325 Beluga> WPB 87326 Blacktip> WPB 87327 Pelican> WPB 87328 Ridley> WPB 87329 Cochito> WPB 87330 Manowar> WPB 87331 Moray> WPB 87332 Razorbill> WPB 87333 Adelie> WPB 87334 Gannet> WPB 87335 Narwhal> WPB 87336 Sturgeon> WPB 87337 Sockeye> WPB 87338 Ibis> WPB 87339 Pompano> WPB 87340 Halibut> WPB 87341 Bonito> WPB 87342 Shrike> WPB 87343 Tern> WPB 87344 Heron> WPB 87345 Wahoo> WPB 87346 Flyingfish> WPB 87347 Haddock> WPB 87348 Brant> WPB 87349 Shearwater> WPB 87350 Petrel> WPB 87352 Sea Lion> WPB 87353 Skipjack> WPB 87354 Dolphin> WPB 87355 Hawk> WPB 87356 Sailfish> WPB 87357 Sawfish> WPB 87358 Swordfish> WPB 87359 Tiger Shark> WPB 87360 Blue Shark> WPB 87361 Sea Horse> WPB 87362 Sea Otter> WPB 87363 Manatee> WPB 87364 Ahi> WPB 87365 Pike> WPB 87366 Terrapin> WPB 87367 Sea Dragon> WPB 87368 Sea Devil> WPB 87369 Crocodile> WPB 87370 Diamondback> WPB 87371 Reef Shark> WPB 87372 Alligator> WPB 87373 Sea Dog> WPB 87374 Sea FoxARMY SHIPSLOGISTICS SUPPORT VESSEL– LSV 1 CLASS> LSV 1 GEN Frank S. Besson, Jr.> LSV2 CW3 Harold C. Clinger> LSV 3 GEN Brehon B.Sommervell> LSV 4 LTG William B. Bunker> LSV 5 MG Charles P. Gross> LSV 6 SP/ 4 James A. Loux> LSV 7 SSGT Robert T. Kuroda> LSV 8 MG Robert SmallsLANDING CRAFT UTILITY –LCU 2000 CLASS> LCU 2001 Runnymede> LCU 2002 Kennesaw Mountain> LCU 2003 Macon> LCU 2004 Aldie> LCU 2005 Brandy Station> LCU 2006 Bristoe Station> LCU 2007 Broad Run> LCU 2008 Buena Vista> LCU 2009 Calaboza> LCU 2010 Cedar Run> LCU 2011 Chickahominy> LCU 2012 Chickasaw Bayou> LCU 2013 Churubusco> LCU 2014 Coamo> LCU 2015 Contreras> LCU 2016 Corinth> LCU 2017 El Caney> LCU 2018 Five Forks> LCU 2019 Fort Donelson> LCU 2020 Fort McHenry> LCU 2021 Great Bridge> LCU 2022 Harpers Ferry> LCU 2023 Hobkirk> LCU 2024 Hormigueros> LCU 2025 Malvern Hill> LCU 2026 Matamoros> LCU 2027 Mechanicsville> LCU 2028 Missionary Ridge> LCU 2029 Molino Del Ray> LCU 2030 Monterrey> LCU 2031 New Orleans> LCU 2032 Palo Alto> LCU 2033 Paulus Hook> LCU 2034 Perryville> LCU 2035 Port HudsonMANEUVER SUPPORT VESSEL(LIGHT) – MSV(L) CLASS> MSV(L) 1 SSG Elroy F. Wells*COAST GUARD CUTTERSARMY SHIPSUse of DoD visual information does not imply or constituent DoD endorsement.AUXILIARY SHIPS SPEARHEAD CLASS JHSV > T-EPF1 Spearhead> T-EPF 2 Choctaw County> T-EPF 3 Millinocket> T-EPF 4 Fall River> T-EPF 5 Trenton> T-EPF 6 Brunswick> T-EPF 7 Carson City> T-EPF 8 Yuma> T-EPF 9 City Of Bismarck> T-EPF 10 Burlington> EPF 11 Puerto Rico> EPF 12 Newport> EPF 13 Apalachicola**> EPF 14 Cody**DRY CARGO/ AMMUNITION (T-AKE)> T-AKE 1 Lewis And Clark> T-AKE 2 Sacagawea> T-AKE 3 Alan Shepard> T-AKE 4 Richard E Byrd> T-AKE 5 Robert E Peary> T-AKE 6 Amelia Earhart> T-AKE 7 Carl Brashear> T-AKE 8 Wally Schirra> T-AKE 9 Matthew C Perry> T-AKE 10 Charles Drew> T-AKE 11 WashingtonChambers> T-AKE 12 William McLean> T-AKE 13 Medgar Evers> T-AKE 14 Cesar Chavez FAST COMBAT SUPPORT (T-AOE)> T-AOE 6 Supply> T-AOE 8 ArcticFLEET REPLENISHMENT OILERS (T-AO)> T-AO 187 Henry J Kaiser> T-AO 188 Joshua Humphreys > T-AO 189 John Lenthall > T-AO 193 Walter S Diehl> T-AO 194 John Ericsson> T-AO 195 Leroy Grumman> T-AO 196 Kanawha> T-AO 197 Pecos> T-AO 198 Big Horn> T-AO 199 Tippecanoe> T-AO 200 Guadalupe> T-AO 201 Patuxent> T-AO 202 Yukon> T-AO 203 Laramie> T-AO 204 Rappahannock> T-AO 205 John Lewis*> T-AO 206 Harvey Milk*> T-AO 207 Earl Warren**> T-AO 208 Robert F Kennedy**> T-AO 209 Lucy Stone**> T-AO 210 Sojourner Truth**PREPOSITIONINGSHIPSFLEET OCEAN TUGS (T-ATF)> T-ATF 168 Catawba> T-ATF 171 Sioux> T-ATF 172 ApacheHOSPITAL (T-AH)> T-AH 19 Mercy> T-AH 20 ComfortRESCUE AND SALVAGE(T-ARS)> T-ARS 51 Grasp> T-ARS 52 SalvorSGT MATEJ KOCAK CLASS> T-AK 3005 Sgt Matej Kocak> T-AK 3006 Pfc Eugene A Obregon> T-AK 3007 Maj Stephen W PlessAVIATION LOGISTICSSUPPORT (T-AVB)> T-AVB 3 Wright> T-AVB 4 CurtissMARINE CORPS CONTAINERAND RO/RO (T-AK) 2ND LTJOHN P BOBO CLASS> T-AK 3008 2nd Lt John P Bobo> T-AK 3009 Pfc Dewayne TWilliams> T-AK 3010 1st Lt BaldomeroLopez> T-AK 3011 1st Lt Jack Lummus> T-AK 3012 Sgt William R ButtonLT HARRY L. MARTIN CLASS> T-AK 3015 1st Lt Harry L Martin> T-AK 3016 LCPL Roy M Wheat> T-AK 3017 GySgt Fred WStockhamVEHICLE CARGO SHIP> T-AKR 10 Cape Island> T-AKR 11 Cape Intrepid> T-AKR 112 Cape Texas> T-AKR 113 Cape TaylorLARGE, MEDIUM-SPEED,RO/RO (T-AKR)> T-AKR 310 Watson> T-AKR 311 Sisler> T-AKR 312 Dahl> T-AKR 313 Red Cloud> T-AKR 314 Charlton> T-AKR 315 Watkins> T-AKR 316 Pomeroy> T-AKR 317 SodermanOPDS (T-AG)> T-AG 5001 Vadm K R WheelerAIR FORCE CONTAINER(T-AK)> T-AK 4396 Maj Bernard F FisherARMY CONTAINER (T-AK)> T-AK 4543 Ltc John U D Page> T-AK 4544 SSG Edward A Carter JrMODULAR CARGO (T-AK)> T-AK 5029 Cape Jacob> AK 5070 Cape Flattery> AK 4073 Cape FarewellHIGH SPEED VESSEL (HSV)> HSV 2 Swift> HSV 4676 Westpac ExpressMISSILE RANGEINSTRUMENTATION (T-AGM)> T-AGM 24 Invincible> T-AGM 25 Howard O LorenzenSPECIAL MISSION &SEALIFT SHIPSOCEAN SURVEILLANCE(T-AGOS)> T-AGOS 19 Victorious> T-AGOS 20 Able> T-AGOS 21 Effective> T-AGOS 22 Loyal> T-AGOS 23 ImpeccableSUBMARINE AND SPECIALWARFARE SUPPORT> MV C-Commando> MV C-Champion> MV Malama> MV Dolores Chouest> MV Hos DominatorSUBMARINE ESCORT SHIP> T-AGSE 1 Black Powder> T-AGSE 2 Westwind> T-AGSE 3 Eagleview> T-AGSE 4 ArrowheadMILITARY SEALIFT COMMANDUse of DoD visual information does not imply or constituent DoD endorsement.MILITARY SEALIFT COMMAND* Under Construction / ** Authorized for ConstructionOCEANOGRAPHIC SURVEY (T-AGS)> T-AGS 60 Pathfinder > T-AGS 62 Bowditch > T-AGS 63 Henson> T-AGS 64 Bruce C Heezen > T-AGS 65 Mary Sears > T-AGS 66MauryCABLE LAYING /REPAIR (T-ARC)> T-ARC 7ZeusNAVIGATION TEST SUPPORT (T-AGS)> T-AGS 45WatersSUBMARINE TENDER (AS)> AS 39 Emory S Land > AS 40Frank CableTANKERS (T-AOT)> T-AOT 1125Lawrence H GianellaDRY CARGO (T-AK)> T-AK 4729 American Tern > T-AK 9205VirginianLARGE, MEDIUM-SPEED RO/RO (T-AKR)> T-AKR 295 Shughart > T-AKR 296 Gordon > T-AKR 297 Yano > T-AKR 298 Gilliland > T-AKR 300 Bob Hope > T-AKR 301 Fisher > T-AKR 302 Seay> T-AKR 303 Mendonca > T-AKR 304Pililaau> T-AKR 305 Brittin > T-AKR 306 BenavidezEXPEDITIONARY TRANSFER DOCK (ESD)> T-ESD 1 Montford Point > T-ESD 2John GlennEXPEDITIONARY SEA BASE (ESB)> T-ESB 3 Lewis B Puller> T-ESB 4 Hershel “Woody” Williams > T-ESB 5 Miguel Keith*> T-ESB 6 (Unnamed)*> T-ESB 7(Unnamed)**L3Harris' solutions address customers' critical missions across air, land, sea, space and cyber domains. We empower people who serve from ocean to orbit and everywhere in between.As a full-spectrum systems integrator and network provider, L3Harris is among the world's leading integrators of C5ISR systems for customers around the globe. Our expertise delivers complete turnkey integration of whole-ship electrical, mechanical and electronic systems; powermanagement and distribution; undersea warfare systems; unmanned and autonomous surface and underwater vehicles; and airborne systems for maritime patrol and surveillance that enable secure, agile worldwide interoperability.In a world of ever-accelerating change, threat environments move fast. We move forward faster by delivering systems integrated solutions and。

Mellanox® MFA1A00-Exxx are QSFP28 VCSEL-based (Vertical Cavity Surface-Emitting Laser) activeoptical cables designed for use in InfiniBand 100Gb/s EDR systems. 100G EDR AOCs are the most popularinterconnect used in very high-speed InfiniBand High Performance Computing (HPC) environments as theyoffer predictable latency, very low power (2.2W) and enable increased air flow, tighter bend radii andsignificantly longer reach compared to DAC cables. Since the AOC is hot pluggable, it is easy to installand replace.MFA1A00-Exxx has a standard SFF-8665 compliant QSFP28 port on the electrical side towards the hostsystem. It contains four multi-mode fibers (MMF) optic transceivers per end, each operating at datarates of up to 26Gb/s.MFA1A00-Exxx offers selectable retiming per lane for both its optical transmitters and receivers forthe 25-26Gbp/s rates, but the AOC also supports lower bit rates without retiming. The transmittershave programmable input equalizers and input squelch function, while the receivers have programmableoutput amplitude and pre-emphasis.Mellanox’s unique, quality, active, fiber, cable solutions provide power-efficient connectivity for datacenter interconnects. They enable higher port bandwidth, density and configurability at a low cost andreduced power requirement in the data centers. Rigorous production testing ensures the best out-of-the-box installation experience, performance and durability.T able 1 - Absolute Maximum RatingsINTERCONNECTPRODUCT BRIEF100Gb/s QSFP28 MMF Active Optical CablesMFA1A00-Exxx†©2017 Mellanox Technologies. All rights reserved.350 Oakmead Parkway, Suite 100, Sunnyvale, CA 94085Tel: 408-970-3400 • Fax: © Copyright 2017. Mellanox Technologies. All rights reserved.Mellanox and Mellanox logo are registered trademarks of Mellanox Technologies, Ltd.LinkX is a trademark of Mellanox Technologies, Ltd. All other trademarks are property of their respective owners.Mellanox 100Gb/s QSFP28 MMF Active Optical Cablespage 2Warranty InformationMellanox LinkX AOC cables include a 1 year limited hardware warranty, which covers parts repair or replacement.53208PB Rev 1.81Figure 1.Cable LengthMechanical SchematicsTable 3 - Part Numbers and DescriptionsNote 1. See Figure 1 for the cable length definition. Note 2. LSZH is an abbreviation for Low Smoke, Zero Halogen jacket.。