北大众志系统芯片AHB总线的设计、优化和验证摘要：为了适配越来越复杂的系统架构，干扰消除和功耗优化，高效的总线处理架构变得十分必要。
在本文中，我们设计、优化并验证了北大众志系统芯片所采用的AHB总线架构。
主要工作包括：总线结构设计、干扰消除方案与电源管理优化。
经过验证，我们的设计成功地提高了总线处理的性能，同时优化了整体系统的功耗表现和抗干扰能力。
关键词：AHB总线；系统芯片；优化；电源管理；抗干扰能力一、引言近年来，随着人们对智能设备和大数据处理越来越依赖，各种计算资源需求越来越高。
而随之而来的是，系统的处理架构变得越来越复杂。
这些架构复杂性带来的问题包括功耗过高、器件干扰等。
AHB总线是一种高效处理系统复杂性的架构，能够提高数据传输速度并有效消除信号干扰，从而保证系统的表现性能。
本文描述了北大众志所采用的AHB 总线架构的设计、优化与验证过程。
二、总线结构设计为了设计出合适的AHB总线架构，我们考虑到总线结构、分频率设置和数据通信流程等多个方面。
在总线结构方面，我们将总线分为主总线和从总线两个部分，主总线上连接着所有处理器和存储器，从总线则连接着各种外设和设备。
分别设计不同的控制信号和数据传输通路。
在分频率设置方面，我们通过合理的频率设置来适应各个处理器之间的差异，实现数据传输。
最终，经过严谨的设计与验证，我们成功地开发出了一个可靠稳定的AHB总线架构。
三、干扰消除方案为了消除因信号干扰而导致的数据传输出错，我们采取了以下两种方案：一是采用流水线缓存技术，将每个处理器的数据分成多个部分并以序列化方式传输，从而消除信号的干扰影响；二是对所有相关部分进行电磁屏蔽，以保证信号传输的稳定性。
经过针对各种情况的测试，我们发现这两种方案能够有效地消除因干扰所导致的数据传输失败的危险，保证了系统的性能和可靠性。
四、电源管理优化为了优化系统功耗表现，我们采用了多项技术手段，包括：1.采用适当的电源降压技术，以确保在最小限度下保证系统正常工作，从而降低系统总功耗。
双向AHB-WISHBONE总线桥的设计与验证夏宏;郝春娥;闫江毓【期刊名称】《计算机工程与设计》【年(卷),期】2011(32)6【摘要】To make the connection convenient among different IP (intellectual property) cores, design of the bidirectional bus bridge is proposed in view of the universality of AHB and WISHBONE bus. Firstly, the characteristic and structure of the two buses is described,and then a conclusion of the designing and implementing technique of the bidirectional bus bridge is reached based on it. The special difficulties lie in the implementation of the burst transmission of the AHB bus, and the supporting of the mutual access between multiple AHB and multiple WISHBONE. Finally validation is implemented utilizing Verilog languadge under the environment of modelsim.Simulation result shows that design of this bus bridge conform to the requirements.%为了方便不同的IP(intellectual property)核的连接,针对AHB与WISHBONE这两种总线的广泛性,提出了一种双向AHB-WISHBONE总线桥的设计方法.介绍了这两种总线协议的特点和结构,阐述了AHB-WISHBONE总线桥的设计结构和实现方法.该方法难点在于AHB总线突发传输的实现,且支持多个AHB设备与多个WISHBONE设备之间的相互访问.使用Verilog语言在modelsim工具下进行了验证,仿真结果表明总线桥的设计符合要求.【总页数】4页(P2201-2204)【作者】夏宏;郝春娥;闫江毓【作者单位】华北电力大学控制与计算机工程学院,北京,102206;华北电力大学控制与计算机工程学院,北京,102206;华北电力大学控制与计算机工程学院,北京,102206【正文语种】中文【中图分类】TP336【相关文献】1.基于断言验证技术的Wishbone AHB协议总线桥设计研究 [J], 刘洋2.基于断言的AHB-Wishbone总线桥的功能验证 [J], 姜伟;王祖强3.一种低功耗高效率的双向AXI2AHB总线桥设计与实现 [J], 焦龙涛;高欣4.AHB-Wishbone总线桥的设计与实现 [J], 万静;王宏滨5.高效率PLB2AXI总线桥的设计与验证 [J], 张浩;魏敬和因版权原因，仅展示原文概要，查看原文内容请购买。
IGLOO2 HPMS AHB Bus Matrix ConfigurationIGLOO2 HPMS AHB Bus Matrix Configuration Table of ContentsIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Configuration Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4A Product Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7IntroductionThe IGLOO2 System Builder automatically configures the memory mapping for you based on your selections of the memory to be used in the design. No user configuration of memory mapping isnecessary.You can use the HPMS AHB Bus Matrix configurator to configure the arbitration schemes. To configure the AHB Bus Matrix access options, use the Security tab in the System Builder (as shown in Figure 1). The values entered in the configurator will be loaded in the SYSREG block at power up or when the DEVRST_N external pad is asserted/de-asserted.In this document we provide a brief description of these options. For more details please refer to the Microsemi IGLOO2 Silicon User’s Guides .Figure 1 •Security Tab in IGLOO2 System Builder1 – Configuration OptionsArbitrationEach of the slave devices on the AHB bus matrix contains an arbiter. Arbitration is done at two levels. Atthe first level, the fixed higher priority masters are evaluated for any access request to the slave. At thesecond level, the remaining busses are evaluated in round robin fashion for any access request to theslave.Note that you can override the arbitration scheme dynamically in their run-time code on the fly. Thefollowing slave arbitration configuration parameters are user programmable registers in the SYSREGblock.You can configure the following parameters from the HPMS AHB Bus Matrix tab of HPMS Options.•Programmable weight - MASTER_WEIGHT0_CR and MASTER_WEIGHT1_CR are 5-bit programmable registers located in the SYSREG block that define the number of consecutivetransfers the weighted master can perform without being interrupted by a fixed priority master, orbefore moving onto the next master in the WRR cycle. The Round Robin Weight for each of theMasters is user-configurable for values between 1 and 32. The Default is 1 (Figure1-1).Figure1-1 • Programmable Weight Configuration•Programmable slave maximum latency - Slave maximum latency, ESRAM_MAX_LAT are 3-bit programmable registers located in the SYSREG block that decides the peak wait time for a fixed priority master arbitrating for eSRAM access while the WRR master is accessing the slave. After the defined latency period, the WRR master must re-arbitrate for slave access. Slave maximum latency can be configurable from 1 to 8 clock cycles (8 by default). ESRAM_MAX_LAT is only supported for fixed priority masters addressing eSRAM slaves; it has no effect on WRR masters.The system designer can use this feature to ensure the processor latency for accesses to eSRAM is limited to a defined number of clock cycles. This is to facilitate limiting the ISR latency for real- time-critical functions (Figure1-2).Figure1-2 • Programmable Slave Maximum Latency ConfigurationA – Product SupportMicrosemi SoC Products Group backs its products with various support services, including CustomerService, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.This appendix contains information about contacting Microsemi SoC Products Group and using thesesupport services.Customer ServiceContact Customer Service for non-technical product support, such as product pricing, product upgrades,update information, order status, and authorization.From North America, call 800.262.1060From the rest of the world, call 650.318.4460Fax, from anywhere in the world, 408.643.6913Customer Technical Support CenterMicrosemi SoC Products Group staffs its Customer Technical Support Center with highly skilledengineers who can help answer your hardware, software, and design questions about Microsemi SoCProducts. The Customer Technical Support Center spends a great deal of time creating applicationnotes, answers to common design cycle questions, documentation of known issues, and various FAQs.So, before you contact us, please visit our online resources. It is very likely we have already answeredyour questions.Technical SupportVisit the Customer Support website (/soc/support/search/default.aspx) for moreinformation and support. Many answers available on the searchable web resource include diagrams,illustrations, and links to other resources on the website.WebsiteYou can browse a variety of technical and non-technical information on the SoC home page, at/soc.Contacting the Customer Technical Support CenterHighly skilled engineers staff the Technical Support Center. The Technical Support Center can becontacted by email or through the Microsemi SoC Products Group website.EmailYou can communicate your technical questions to our email address and receive answers back by email,fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.We constantly monitor the email account throughout the day. When sending your request to us, pleasebe sure to include your full name, company name, and your contact information for efficient processing ofyour request.The technical support email address is **********************.© 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at .Microsemi Corporate HeadquartersOne Enterprise, Aliso Viejo CA 92656 USAWithin the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996My CasesMicrosemi SoC Products Group customers may submit and track technical cases online by going to My Cases .Outside the U.S.Customers needing assistance outside the US time zones can either contact technical support via email (**********************) or contact a local sales office. Sales office listings can be found at /soc/company/contact/default.aspx.ITAR Technical SupportFor technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations (ITAR), contact us via ***************************. Alternatively, within My Cases , select Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the I TAR web page.。
