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PowerDC_DRC_Marking_in_Allegro

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©2014 Cadence Design Systems, Inc. All rights reserved.
Usage Flow: Step-2
If return “t”, the skill code is loaded successfully.
1. 2.
3.
Run runPDCBatch in the Skill Development window. The settings form shows. In the setting form, select Allegro Sigrity installation directory, Translator installation directory and PowerDC workspace file. Click OK. The program executes the translation and the simulation in the background. This process may take several mince Design Systems, Inc. All rights reserved.
Initial setup
Must be used with PowerDC version 7.1 or above The env file path and extracta.exe path in the Environment setting in SPDLinks must be set properly The PDCX file and the BRD file must be in the same directory Need the skill code “mark_powerdc_drc.cxt” If VRM and Sink are linked manually, they must be linked by pin names
Command > set telskill
Load the skill file
Skill > loadContext “mark_powerdc_drc.cxt” Skill > callInitProc “mark_powerdc_drc”
4.
If the skill file is not in the same directory as the brd file, the full path name needs to be provided, for example => loadContext “c:/skill_code/mark_powerdc_drc.cxt”
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©2014 Cadence Design Systems, Inc. All rights reserved.
Usage Flow: Step-3
After the simulation is finished, the PowerDC DRC form shows. Select drc type to mark.
Checking DRC Violations in Allegro with PowerDC
July 2014
Overview
SI analysis Layout design
Board translation
PowerDC PDCX
Integrated environment Electrical analysis for DRC Physical correlation
Usage Flow: Step-5

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Use show element command and turn on DRC errors to view the marked drc element Click Exit to stop the program
©2014 Cadence Design Systems, Inc. All rights reserved.
Net selection
DRC setup
Design update
This feature is available from PowerDC 7.1 version onwards. The PDCX file contains all the information needed for electrical analysis. This file can be reused for multiple designs that share same components and nets.
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©2014 Cadence Design Systems, Inc. All rights reserved.
Usage Flow: Step-4
Click here to bring up violation table Select the DRC types and click Mark to the mark DRC on the layout. Right-click for sorting Violation Table
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©2014 Cadence Design Systems, Inc. All rights reserved.
Usage Flow: Step-1
Skill Development window
1. 2. 3.
Start Allegro and open the mcm file or brd file Run set telskill command to show Skill Development window
Click here to clear the DRCs that were generated by PowerDC
Select a violation and click Zoom to zoom to the DRC in the layout
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©2014 Cadence Design Systems, Inc. All rights reserved.

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规03则管建理设器基设础置与创建 常见设置规则检查DRC报警含义及处理
深圳职业技术学院 物联网专业 王毅峰
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ALLEGRO中常见的DRC错误代码含义 常见设置规则检查DRC报警含义及处理 ALLEGRO中常见的DRC错误代码含义 ALLEGRO中常见的DRC错误代码含义 ALLEGRO中常见的DRC错误代码含义 ALLEGRO中常见的DRC错误代码含义 ALLEGRO中常见的DRC错误代码含义 ALLEGRO中常见的DRC错误代码含义 ALLEGRO中常见的DRC错误代码含义 ALLEGRO中常见的DRC错误代码含义 ALLEGRO中常见的DRC错误代码含义 ALLEGRO中常见的DRC错误代码含义 深圳职业技术学院 物联网专业 王毅峰 ALLEGRO中常见的DRC错误代码含义 ALLEGRO中常见的DRC错误代码含义 ALLEGRO中常见的DRC错误代码含义
ALLEGRO中常见的DRC错误代码意思

ALLEGRO中常见的DRC错误代码意思

W
Wire
与走线相关的错误
D
Design
与整个电路板相关的错误
M
Soldemask
与防焊层相关的错误
错ቤተ መጻሕፍቲ ባይዱ代码后置码说明
S
Shape/Stub
与走线层的Shape或分支相关的错误
N
Not Allowed
与不允许的设置相关的错误
W
Width
与宽度相关的错误
双字符错误代码
BB
Bondpad to Bondpad
EV
Max Via Count
已超过走线使用的VIA的最大数目
EX
Max Crosstalk
已超过Crosstalk值
Max Peak Crosstalk
已超过Peak Crosstalk值
HH
Hold to Hold Spacing
钻孔之间的距离太近
HW
Diagonal Wire to Hold Spacing
BBVia to Via Keepout Spacing
BBVia在Via Keepout之内
Test Via to Route Keepin Spacing
Test Via在Route Keepin之外
Test Via to Route Keepout Spacing
Test Via在Route Keepout之内
走线的等长错误
EL
Max Exposed Length
走线在外层（TOP&BOTTOM）的长度过长
EP
Max Net Parallelism Length-Distance Pair
已超过Net之间的平行长度
ES
Allegro中进行PowerPCB SI仿真

Allegro中进行PowerPCB SI仿真

第一章在Allegro 中准备好进行SI 仿真的PCB 板图1）在Cadence 中进行SI 分析可以通过几种方式得到结果：* Allegro 的PCB 画板界面，通过处理可以直接得到结果，或者直接以*.brd 存盘。

* 使用SpecctreQuest 打开*.brd，进行必要设置，通过处理直接得到结果。

这实际与上述方式类似，只不过是两个独立的模块，真正的仿真软件是下面的SigXplore 程序。

* 直接打开SigXplore 建立拓扑进行仿真。

2）从PowerPCB 转换到Allegro 格式在PowerPCb 中对已经完成的PCB 板，作如下操作：在文件菜单，选择Export 操作，出现File Export 窗口，选择ASCII 格式*.asc 文件格式，并指定文件名称和路径（图1.1）。

图1.1 在PowerPCB 中输出通用ASC 格式文件图1.2 PowerPCB 导出格式设置窗口点击图1.1 的保存按钮后出现图1.2 ASCII 输出定制窗口，在该窗口中，点击“Select All”项、在Expand Attributes 中选中Parts 和Nets 两项，尤其注意在Format 窗口只能选择PowerPCB V3.0 以下版本格式，否则Allegro 不能正确导入。

3）在Allegro 中导入*.ascPCB 板图在文件菜单，选择Import 操作，出现一个下拉菜单，在下拉菜单中选择PADS 项，出现PADS IN 设置窗口（图1.3），在该窗口中需要设置3 个必要参数：图1.3 转换阿三次文件参数设置窗口i. 在的一栏那填入源asc 文件的目录ii. 在第二栏指定转换必须的pads_in.ini 文件所在目录（也可将此文件拷入工作目录中，此例）iii. 指定转换后的文件存放目录然后运行“Run”，将在指定的目录中生成转换成功的.brd 文件。

注：pads_in.ini 所在目录路：.\Psd_14.2\Tools\PCB\bin 中。

ALLEGRO使用(V16.2)-DRC错误代码对照

ALLEGRO使用(V16.2)-DRC错误代码对照

ALLEGRO使用（V16.2）‐DRC错误代码对照代码相关对象 说明单一字符代码L Line 走线P Pin 元件脚V Via 贯穿孔K Keep in/out 允许区域/禁止区域C Component 元件层级E Electrical Constraint 电气约束J T‐Junction 呈现T形的走线I Island Form 被Pin或Via围成的负片孤铜 错误代码前置码说明W Wire 与走线相关的错误D Design 与整个电路板相关的错误M Soldemask 与防焊层相关的错误错误代码后置码说明S Shape/Stub 与走线层的Shape或分支相关的错误N NotAllowed与不允许的设置相关的错误W Width 与宽度相关的错误双字符错误代码BB Bondpad to Bondpad Bondpad之间的错误BL Bondpad to Line Bondpad与Line之间的错误 BS Bondpad to Shape Bondpad与Shape 之间的错误CC Package to Package Package之间的 Spacing 错误 Symbol Soldermask to SymbolSoldermask零件防焊层之间的Spacing 错误DF Differential Pair Length Tolerance 差分对走线的长度误差过长 Differential Pair Primary MaxSeparation差分对走线的主要距离太大 Differential Pair Secondary MaxSeparation差分对走线的次要距离太大 Differential Pair Secondary Max Length差分对走线的次要距离长度过长DI Design Constraint Negative PlaneIsland负片孤铜的错误ED Propagation‐Delay 走线的长度错误 Relative‐Propagation‐Delay 走线的等长错误EL Max Exposed Length 走线在外层（TOP&BOTTOM）的长度过长EP Max Net Parallelism Length‐DistancePair已超过Net之间的平行长度ES Max Stub Length 走线的分支过长ET Electrical Topology 走线连接方式的错误EV Max Via Count 已超过走线使用的VIA的最大数目EX Max Crosstalk 已超过Crosstalk值 Max Peak Crosstalk 已超过Peak Crosstalk值HH Hold to Hold Spacing 钻孔之间的距离太近HW Diagonal Wire to Hold Spacing 斜线与钻孔之间的距离太近Hold to Orthogonal Wire Spacing钻孔与垂直/水平线之间的距离太近IM Impedance Constraint 走线的阻抗值错误 JN T Junction Not Allowed 走线呈T形的错误KB Route Keepinto BondpadBondpad在Keepin之外 Route keepoutto BondpadBondpad在keepout之内 Via KeepouttoBondpadBondpad在Via Keepout之内KC Package to Place Keepin Spacing 元件在Place Keepin之外 Package to Place Keepout Spacing 元件在Place Keepout之内KL Line to Route Keepin Spacing 走线在Route Keepin之外 Line to Route Keepout Spacing 走线在Route Keepout之内KS Shape to Route Keepin Spacing Shape在Route Keepin之外 Shape to Route Keepout Spacing Shape在Route Keepout之内KV BBVia to Route Keepin Spacing BBVia在Route Keepin之外 BBVia to Route Keepout Spacing BBVia在Route Keepout之内 BBVia to Via Keepout Spacing BBVia在Via Keepout之内Test Via to Route Keepin Spacing Test Via在Route Keepin之外 Test Via to Route Keepout Spacing Test Via在Route Keepout之内 Test Via to Via Keepout Spacing Test Via在Via Keepout之内 Through Via to Route Keepin Spacing Through Via在Route Keepin之外 Through Via to Route Keepout Spacing Through Via在Route Keepout之内Through Via to Via Keepout Spacing Through Via在Via Keepout之内LB Min Self Crossing Loopback Length 无LL Line to Line Spacing 走线之间太近LS Line to Shape Spacing 走线与Shape 太近 LW Min Line Width 走线的宽度太细Min Neck Width 走线变细的宽度太细MASoldermask Alignment Error PadSoldermask Tolerance太小MC Pin/Via Soldermask to SymbolSoldermaskPad与Symbol Soldermask之间的错误MM Pin/Via Soldermask to Pin/ViaSoldermaskPadSoldermask之间的错误PB Pin to Bondpad Pin与Bondpad之间的错误PL Line to SMD Pin Spacing 走线与SMD元件脚太近 Line to Test Pin Spacing 走线与Test元件脚太近 Line to Through Pin Spacing 走线与Through元件脚太近PP SMD Pin to SMD Pin Spacing SMD元件脚与SMD元件脚太近 SMD Pin to Test Pin Spacing SMD元件脚与Test元件脚太近 Test Pin to Test Pin Spacing Test元件脚与Test元件脚太近 Test Pin to Through Pin Spacing Test元件脚与Through元件脚太近Through Pin to SMD Pin Spacing Through元件脚与SMD元件脚太近Through Pin to Through Pin SpacingThrough元件脚与Through元件脚太近PS Shape to SMD Pin Spacing Shape与SMD元件脚太近 Shape to Test Pin Spacing Shape与Test元件脚太近 Through Pin to Shape Spacing Through元件脚与Shape太近PV BBVia to SMD Pin Spacing BBVia与SMD元件脚太近 BBVia to Test Pin Spacing BBVia与Test元件脚太近 BBVia to Through Pin Spacing BBVia 与Through元件脚太近 SMD Pin to Test Via Spacing SMD Pin与Test Via太近SMD Pin to Through Via Spacing SMD Pin与Through Via太近 Test Pin to Test Via Spacing Test Pin与Test Via太近Test Pin to Through Via Spacing Test Pin与Through Via太近 Test Via to Through Pin Spacing Test Via与Through Pin太近 Through Pin to Through Via Spacing Through Pin与Through Via太近RC Package to Hard Room 元件在其他的Room之内RE Min Length Route End Segment at 135Degree无 Min Length Route End Segment at 45/90Degree无SB 135Degree Turn to Adjacent Crossing Distance无 90Degree Turn to Adjacent Crossing Distance无SL Min Length Wire Segment 无 Min Length Single Segment Wire 无SN Allow on Etch Subclass 允许在走线层上SO Segment Orientaion 无BB Bondpad to Bondpad Bondpad之间的错误SS Shape to Shape Shape之间的错误TA Max Turn Angle 无VB Via to Bondpad Via 与Bondpad之间的错误VG Max BB Via Stagger Distance 同一段线的BB Via之间的距离太长Min BB Via Gap BB Via之间太近Min BB Via Stagger Distance 同一段线的BB Via之间的距离太近Pad/Pad Direct Connect Pad 在另一个Pad 之上VL BB Via to Line Spacing BB Via与走线太近Line to Through Via Spacing 走线与Through Via太近 Line to Test Via Spacing 走线与Test Via太近VS BB Via to Shape Spacing BB Via与Shape太近 Shape to Test Via Spacing Shape 与Test Via太近 Shape to Through Via Spacing Shape与Through Via太近VV BB Via to BB ViaSpacingBB Via之间太近BB Via to Test Via Spacing BB Via与Test Via太近BB Via to Through Via Spacing BB Via与Through Via太近 Test Via to Test Via Spacing Test Via之间太近Test Via to Through Via Spacing Test Via与Through Via太近 Through Via to Through Via Spacing Through Via之间太近WA Min Bonding Wire Length Bonding Wire 长度太短WE Min End Segment Length 无 Min Length Wire End Segment at 135Degree无 Min Length Wire End Segment at 45/90Degree无WI Max Bonding Wire Length Bonding Wire 长度太长WW Diagonal Wire to Diagonal WireSpacing斜线之间太近Diagonal Wire to Orthogonal WireSpacing斜线与垂直/水平线之间的距离太近Orthogonal Wire to Orthogonal WireSpacing垂直/水平线之间的距离太近WX Max Number of Crossing 无 Min Distance between Crossing 无XB 135 Degree Turn to Adjacent Crossing Distance无 90 Degree Turn to Adjacent Crossing 无DistanceXD Externally Determined Violation 无XS Crossing to Adjacent Segment Distances无。